drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #include <rte_io.h>
  28
  29 #define HWRM_CMD_TIMEOUT                10000
  30 #define HWRM_VERSION_1_9_1              0x10901
  31
  32 struct bnxt_plcmodes_cfg {
  33         uint32_t        flags;
  34         uint16_t        jumbo_thresh;
  35         uint16_t        hds_offset;
  36         uint16_t        hds_threshold;
  37 };
  38
  39 static int page_getenum(size_t size)
  40 {
  41         if (size <= 1 << 4)
  42                 return 4;
  43         if (size <= 1 << 12)
  44                 return 12;
  45         if (size <= 1 << 13)
  46                 return 13;
  47         if (size <= 1 << 16)
  48                 return 16;
  49         if (size <= 1 << 21)
  50                 return 21;
  51         if (size <= 1 << 22)
  52                 return 22;
  53         if (size <= 1 << 30)
  54                 return 30;
  55         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  56         return sizeof(void *) * 8 - 1;
  57 }
  58
  59 static int page_roundup(size_t size)
  60 {
  61         return 1 << page_getenum(size);
  62 }
  63
  64 /*
  65  * HWRM Functions (sent to HWRM)
  66  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  67  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  68  * command was failed by the ChiMP.
  69  */
  70
  71 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  72                                         uint32_t msg_len)
  73 {
  74         unsigned int i;
  75         struct input *req = msg;
  76         struct output *resp = bp->hwrm_cmd_resp_addr;
  77         uint32_t *data = msg;
  78         uint8_t *bar;
  79         uint8_t *valid;
  80         uint16_t max_req_len = bp->max_req_len;
  81         struct hwrm_short_input short_input = { 0 };
  82
  83         if (bp->flags & BNXT_FLAG_SHORT_CMD) {
  84                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
  85
  86                 memset(short_cmd_req, 0, bp->max_req_len);
  87                 memcpy(short_cmd_req, req, msg_len);
  88
  89                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
  90                 short_input.signature = rte_cpu_to_le_16(
  91                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
  92                 short_input.size = rte_cpu_to_le_16(msg_len);
  93                 short_input.req_addr =
  94                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
  95
  96                 data = (uint32_t *)&short_input;
  97                 msg_len = sizeof(short_input);
  98
  99                 /* Sync memory write before updating doorbell */
 100                 rte_wmb();
 101
 102                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 103         }
 104
 105         /* Write request msg to hwrm channel */
 106         for (i = 0; i < msg_len; i += 4) {
 107                 bar = (uint8_t *)bp->bar0 + i;
 108                 rte_write32(*data, bar);
 109                 data++;
 110         }
 111
 112         /* Zero the rest of the request space */
 113         for (; i < max_req_len; i += 4) {
 114                 bar = (uint8_t *)bp->bar0 + i;
 115                 rte_write32(0, bar);
 116         }
 117
 118         /* Ring channel doorbell */
 119         bar = (uint8_t *)bp->bar0 + 0x100;
 120         rte_write32(1, bar);
 121
 122         /* Poll for the valid bit */
 123         for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
 124                 /* Sanity check on the resp->resp_len */
 125                 rte_rmb();
 126                 if (resp->resp_len && resp->resp_len <=
 127                                 bp->max_resp_len) {
 128                         /* Last byte of resp contains the valid key */
 129                         valid = (uint8_t *)resp + resp->resp_len - 1;
 130                         if (*valid == HWRM_RESP_VALID_KEY)
 131                                 break;
 132                 }
 133                 rte_delay_us(600);
 134         }
 135
 136         if (i >= HWRM_CMD_TIMEOUT) {
 137                 PMD_DRV_LOG(ERR, "Error sending msg 0x%04x\n",
 138                         req->req_type);
 139                 goto err_ret;
 140         }
 141         return 0;
 142
 143 err_ret:
 144         return -1;
 145 }
 146
 147 /*
 148  * HWRM_PREP() should be used to prepare *ALL* HWRM commands.  It grabs the
 149  * spinlock, and does initial processing.
 150  *
 151  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 152  * releases the spinlock only if it returns.  If the regular int return codes
 153  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 154  * directly, rather it should be copied and modified to suit the function.
 155  *
 156  * HWRM_UNLOCK() must be called after all response processing is completed.
 157  */
 158 #define HWRM_PREP(req, type) do { \
 159         rte_spinlock_lock(&bp->hwrm_lock); \
 160         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 161         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 162         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 163         req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 164         req.target_id = rte_cpu_to_le_16(0xffff); \
 165         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 166 } while (0)
 167
 168 #define HWRM_CHECK_RESULT() do {\
 169         if (rc) { \
 170                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 171                 rte_spinlock_unlock(&bp->hwrm_lock); \
 172                 return rc; \
 173         } \
 174         if (resp->error_code) { \
 175                 rc = rte_le_to_cpu_16(resp->error_code); \
 176                 if (resp->resp_len >= 16) { \
 177                         struct hwrm_err_output *tmp_hwrm_err_op = \
 178                                                 (void *)resp; \
 179                         PMD_DRV_LOG(ERR, \
 180                                 "error %d:%d:%08x:%04x\n", \
 181                                 rc, tmp_hwrm_err_op->cmd_err, \
 182                                 rte_le_to_cpu_32(\
 183                                         tmp_hwrm_err_op->opaque_0), \
 184                                 rte_le_to_cpu_16(\
 185                                         tmp_hwrm_err_op->opaque_1)); \
 186                 } else { \
 187                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 188                 } \
 189                 rte_spinlock_unlock(&bp->hwrm_lock); \
 190                 return rc; \
 191         } \
 192 } while (0)
 193
 194 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 195
 196 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 197 {
 198         int rc = 0;
 199         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 200         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 201
 202         HWRM_PREP(req, CFA_L2_SET_RX_MASK);
 203         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 204         req.mask = 0;
 205
 206         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 207
 208         HWRM_CHECK_RESULT();
 209         HWRM_UNLOCK();
 210
 211         return rc;
 212 }
 213
 214 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 215                                  struct bnxt_vnic_info *vnic,
 216                                  uint16_t vlan_count,
 217                                  struct bnxt_vlan_table_entry *vlan_table)
 218 {
 219         int rc = 0;
 220         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 221         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 222         uint32_t mask = 0;
 223
 224         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 225                 return rc;
 226
 227         HWRM_PREP(req, CFA_L2_SET_RX_MASK);
 228         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 229
 230         /* FIXME add multicast flag, when multicast adding options is supported
 231          * by ethtool.
 232          */
 233         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 234                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 235         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 236                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 237         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 238                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 239         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 240                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 241         if (vnic->flags & BNXT_VNIC_INFO_MCAST)
 242                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 243         if (vnic->mc_addr_cnt) {
 244                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 245                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 246                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 247         }
 248         if (vlan_table) {
 249                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 250                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 251                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 252                          rte_mem_virt2iova(vlan_table));
 253                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 254         }
 255         req.mask = rte_cpu_to_le_32(mask);
 256
 257         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 258
 259         HWRM_CHECK_RESULT();
 260         HWRM_UNLOCK();
 261
 262         return rc;
 263 }
 264
 265 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 266                         uint16_t vlan_count,
 267                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 268 {
 269         int rc = 0;
 270         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 271         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 272                                                 bp->hwrm_cmd_resp_addr;
 273
 274         /*
 275          * Older HWRM versions did not support this command, and the set_rx_mask
 276          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 277          * removed from set_rx_mask call, and this command was added.
 278          *
 279          * This command is also present from 1.7.8.11 and higher,
 280          * as well as 1.7.8.0
 281          */
 282         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 283                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 284                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 285                                         (11)))
 286                                 return 0;
 287                 }
 288         }
 289         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG);
 290         req.fid = rte_cpu_to_le_16(fid);
 291
 292         req.vlan_tag_mask_tbl_addr =
 293                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 294         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 295
 296         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 297
 298         HWRM_CHECK_RESULT();
 299         HWRM_UNLOCK();
 300
 301         return rc;
 302 }
 303
 304 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 305                            struct bnxt_filter_info *filter)
 306 {
 307         int rc = 0;
 308         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 309         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 310
 311         if (filter->fw_l2_filter_id == UINT64_MAX)
 312                 return 0;
 313
 314         HWRM_PREP(req, CFA_L2_FILTER_FREE);
 315
 316         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 317
 318         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 319
 320         HWRM_CHECK_RESULT();
 321         HWRM_UNLOCK();
 322
 323         filter->fw_l2_filter_id = UINT64_MAX;
 324
 325         return 0;
 326 }
 327
 328 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 329                          uint16_t dst_id,
 330                          struct bnxt_filter_info *filter)
 331 {
 332         int rc = 0;
 333         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 334         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 335         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 336         const struct rte_eth_vmdq_rx_conf *conf =
 337                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 338         uint32_t enables = 0;
 339         uint16_t j = dst_id - 1;
 340
 341         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 342         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 343             conf->pool_map[j].pools & (1UL << j)) {
 344                 PMD_DRV_LOG(DEBUG,
 345                         "Add vlan %u to vmdq pool %u\n",
 346                         conf->pool_map[j].vlan_id, j);
 347
 348                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 349                 filter->enables |=
 350                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 351                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 352         }
 353
 354         if (filter->fw_l2_filter_id != UINT64_MAX)
 355                 bnxt_hwrm_clear_l2_filter(bp, filter);
 356
 357         HWRM_PREP(req, CFA_L2_FILTER_ALLOC);
 358
 359         req.flags = rte_cpu_to_le_32(filter->flags);
 360
 361         enables = filter->enables |
 362               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 363         req.dst_id = rte_cpu_to_le_16(dst_id);
 364
 365         if (enables &
 366             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 367                 memcpy(req.l2_addr, filter->l2_addr,
 368                        ETHER_ADDR_LEN);
 369         if (enables &
 370             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 371                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 372                        ETHER_ADDR_LEN);
 373         if (enables &
 374             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 375                 req.l2_ovlan = filter->l2_ovlan;
 376         if (enables &
 377             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 378                 req.l2_ovlan = filter->l2_ivlan;
 379         if (enables &
 380             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 381                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 382         if (enables &
 383             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 384                 req.l2_ovlan_mask = filter->l2_ivlan_mask;
 385         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 386                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 387         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 388                 req.src_type = filter->src_type;
 389
 390         req.enables = rte_cpu_to_le_32(enables);
 391
 392         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 393
 394         HWRM_CHECK_RESULT();
 395
 396         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 397         HWRM_UNLOCK();
 398
 399         return rc;
 400 }
 401
 402 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 403 {
 404         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 405         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 406         uint32_t flags = 0;
 407         int rc;
 408
 409         if (!ptp)
 410                 return 0;
 411
 412         HWRM_PREP(req, PORT_MAC_CFG);
 413
 414         if (ptp->rx_filter)
 415                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 416         else
 417                 flags |=
 418                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 419         if (ptp->tx_tstamp_en)
 420                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 421         else
 422                 flags |=
 423                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 424         req.flags = rte_cpu_to_le_32(flags);
 425         req.enables = rte_cpu_to_le_32
 426                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 427         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 428
 429         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 430         HWRM_UNLOCK();
 431
 432         return rc;
 433 }
 434
 435 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 436 {
 437         int rc = 0;
 438         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 439         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 440         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 441
 442 /*      if (bp->hwrm_spec_code < 0x10801 || ptp)  TBD  */
 443         if (ptp)
 444                 return 0;
 445
 446         HWRM_PREP(req, PORT_MAC_PTP_QCFG);
 447
 448         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 449
 450         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 451
 452         HWRM_CHECK_RESULT();
 453
 454         if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 455                 return 0;
 456
 457         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 458         if (!ptp)
 459                 return -ENOMEM;
 460
 461         ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 462                 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 463         ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 464                 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 465         ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 466                 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 467         ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 468                 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 469         ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 470                 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 471         ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 472                 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 473         ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 474                 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 475         ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 476                 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 477         ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 478                 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 479
 480         ptp->bp = bp;
 481         bp->ptp_cfg = ptp;
 482
 483         return 0;
 484 }
 485
 486 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 487 {
 488         int rc = 0;
 489         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 490         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 491         uint16_t new_max_vfs;
 492         uint32_t flags;
 493         int i;
 494
 495         HWRM_PREP(req, FUNC_QCAPS);
 496
 497         req.fid = rte_cpu_to_le_16(0xffff);
 498
 499         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 500
 501         HWRM_CHECK_RESULT();
 502
 503         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 504         flags = rte_le_to_cpu_32(resp->flags);
 505         if (BNXT_PF(bp)) {
 506                 bp->pf.port_id = resp->port_id;
 507                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 508                 new_max_vfs = bp->pdev->max_vfs;
 509                 if (new_max_vfs != bp->pf.max_vfs) {
 510                         if (bp->pf.vf_info)
 511                                 rte_free(bp->pf.vf_info);
 512                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 513                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 514                         bp->pf.max_vfs = new_max_vfs;
 515                         for (i = 0; i < new_max_vfs; i++) {
 516                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 517                                 bp->pf.vf_info[i].vlan_table =
 518                                         rte_zmalloc("VF VLAN table",
 519                                                     getpagesize(),
 520                                                     getpagesize());
 521                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 522                                         PMD_DRV_LOG(ERR,
 523                                         "Fail to alloc VLAN table for VF %d\n",
 524                                         i);
 525                                 else
 526                                         rte_mem_lock_page(
 527                                                 bp->pf.vf_info[i].vlan_table);
 528                                 bp->pf.vf_info[i].vlan_as_table =
 529                                         rte_zmalloc("VF VLAN AS table",
 530                                                     getpagesize(),
 531                                                     getpagesize());
 532                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 533                                         PMD_DRV_LOG(ERR,
 534                                         "Alloc VLAN AS table for VF %d fail\n",
 535                                         i);
 536                                 else
 537                                         rte_mem_lock_page(
 538                                                bp->pf.vf_info[i].vlan_as_table);
 539                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 540                         }
 541                 }
 542         }
 543
 544         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 545         memcpy(bp->dflt_mac_addr, &resp->mac_address, ETHER_ADDR_LEN);
 546         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 547         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 548         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 549         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 550         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 551         /* TODO: For now, do not support VMDq/RFS on VFs. */
 552         if (BNXT_PF(bp)) {
 553                 if (bp->pf.max_vfs)
 554                         bp->max_vnics = 1;
 555                 else
 556                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 557         } else {
 558                 bp->max_vnics = 1;
 559         }
 560         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 561         if (BNXT_PF(bp)) {
 562                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 563                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 564                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 565                         PMD_DRV_LOG(INFO, "PTP SUPPORTED\n");
 566                         HWRM_UNLOCK();
 567                         bnxt_hwrm_ptp_qcfg(bp);
 568                 }
 569         }
 570
 571         HWRM_UNLOCK();
 572
 573         return rc;
 574 }
 575
 576 int bnxt_hwrm_func_reset(struct bnxt *bp)
 577 {
 578         int rc = 0;
 579         struct hwrm_func_reset_input req = {.req_type = 0 };
 580         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 581
 582         HWRM_PREP(req, FUNC_RESET);
 583
 584         req.enables = rte_cpu_to_le_32(0);
 585
 586         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 587
 588         HWRM_CHECK_RESULT();
 589         HWRM_UNLOCK();
 590
 591         return rc;
 592 }
 593
 594 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 595 {
 596         int rc;
 597         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 598         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 599
 600         if (bp->flags & BNXT_FLAG_REGISTERED)
 601                 return 0;
 602
 603         HWRM_PREP(req, FUNC_DRV_RGTR);
 604         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 605                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 606         req.ver_maj = RTE_VER_YEAR;
 607         req.ver_min = RTE_VER_MONTH;
 608         req.ver_upd = RTE_VER_MINOR;
 609
 610         if (BNXT_PF(bp)) {
 611                 req.enables |= rte_cpu_to_le_32(
 612                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 613                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 614                        RTE_MIN(sizeof(req.vf_req_fwd),
 615                                sizeof(bp->pf.vf_req_fwd)));
 616
 617                 /*
 618                  * PF can sniff HWRM API issued by VF. This can be set up by
 619                  * linux driver and inherited by the DPDK PF driver. Clear
 620                  * this HWRM sniffer list in FW because DPDK PF driver does
 621                  * not support this.
 622                  */
 623                 req.flags =
 624                 rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE);
 625         }
 626
 627         req.async_event_fwd[0] |=
 628                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 629                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 630                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE);
 631         req.async_event_fwd[1] |=
 632                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 633                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 634
 635         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 636
 637         HWRM_CHECK_RESULT();
 638         HWRM_UNLOCK();
 639
 640         bp->flags |= BNXT_FLAG_REGISTERED;
 641
 642         return rc;
 643 }
 644
 645 int bnxt_hwrm_ver_get(struct bnxt *bp)
 646 {
 647         int rc = 0;
 648         struct hwrm_ver_get_input req = {.req_type = 0 };
 649         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 650         uint32_t my_version;
 651         uint32_t fw_version;
 652         uint16_t max_resp_len;
 653         char type[RTE_MEMZONE_NAMESIZE];
 654         uint32_t dev_caps_cfg;
 655
 656         bp->max_req_len = HWRM_MAX_REQ_LEN;
 657         HWRM_PREP(req, VER_GET);
 658
 659         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 660         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 661         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 662
 663         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 664
 665         HWRM_CHECK_RESULT();
 666
 667         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 668                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 669                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 670                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 671         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 672                      (resp->hwrm_fw_min_8b << 16) |
 673                      (resp->hwrm_fw_bld_8b << 8) |
 674                      resp->hwrm_fw_rsvd_8b;
 675         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 676                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 677
 678         my_version = HWRM_VERSION_MAJOR << 16;
 679         my_version |= HWRM_VERSION_MINOR << 8;
 680         my_version |= HWRM_VERSION_UPDATE;
 681
 682         fw_version = resp->hwrm_intf_maj_8b << 16;
 683         fw_version |= resp->hwrm_intf_min_8b << 8;
 684         fw_version |= resp->hwrm_intf_upd_8b;
 685         bp->hwrm_spec_code = fw_version;
 686
 687         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
 688                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 689                 rc = -EINVAL;
 690                 goto error;
 691         }
 692
 693         if (my_version != fw_version) {
 694                 PMD_DRV_LOG(INFO, "BNXT Driver/HWRM API mismatch.\n");
 695                 if (my_version < fw_version) {
 696                         PMD_DRV_LOG(INFO,
 697                                 "Firmware API version is newer than driver.\n");
 698                         PMD_DRV_LOG(INFO,
 699                                 "The driver may be missing features.\n");
 700                 } else {
 701                         PMD_DRV_LOG(INFO,
 702                                 "Firmware API version is older than driver.\n");
 703                         PMD_DRV_LOG(INFO,
 704                                 "Not all driver features may be functional.\n");
 705                 }
 706         }
 707
 708         if (bp->max_req_len > resp->max_req_win_len) {
 709                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
 710                 rc = -EINVAL;
 711         }
 712         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 713         max_resp_len = resp->max_resp_len;
 714         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 715
 716         if (bp->max_resp_len != max_resp_len) {
 717                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 718                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 719                         bp->pdev->addr.devid, bp->pdev->addr.function);
 720
 721                 rte_free(bp->hwrm_cmd_resp_addr);
 722
 723                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 724                 if (bp->hwrm_cmd_resp_addr == NULL) {
 725                         rc = -ENOMEM;
 726                         goto error;
 727                 }
 728                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
 729                 bp->hwrm_cmd_resp_dma_addr =
 730                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
 731                 if (bp->hwrm_cmd_resp_dma_addr == 0) {
 732                         PMD_DRV_LOG(ERR,
 733                         "Unable to map response buffer to physical memory.\n");
 734                         rc = -ENOMEM;
 735                         goto error;
 736                 }
 737                 bp->max_resp_len = max_resp_len;
 738         }
 739
 740         if ((dev_caps_cfg &
 741                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 742             (dev_caps_cfg &
 743              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
 744                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
 745
 746                 rte_free(bp->hwrm_short_cmd_req_addr);
 747
 748                 bp->hwrm_short_cmd_req_addr = rte_malloc(type,
 749                                                         bp->max_req_len, 0);
 750                 if (bp->hwrm_short_cmd_req_addr == NULL) {
 751                         rc = -ENOMEM;
 752                         goto error;
 753                 }
 754                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
 755                 bp->hwrm_short_cmd_req_dma_addr =
 756                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
 757                 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
 758                         rte_free(bp->hwrm_short_cmd_req_addr);
 759                         PMD_DRV_LOG(ERR,
 760                                 "Unable to map buffer to physical memory.\n");
 761                         rc = -ENOMEM;
 762                         goto error;
 763                 }
 764
 765                 bp->flags |= BNXT_FLAG_SHORT_CMD;
 766         }
 767
 768 error:
 769         HWRM_UNLOCK();
 770         return rc;
 771 }
 772
 773 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
 774 {
 775         int rc;
 776         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
 777         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
 778
 779         if (!(bp->flags & BNXT_FLAG_REGISTERED))
 780                 return 0;
 781
 782         HWRM_PREP(req, FUNC_DRV_UNRGTR);
 783         req.flags = flags;
 784
 785         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 786
 787         HWRM_CHECK_RESULT();
 788         HWRM_UNLOCK();
 789
 790         bp->flags &= ~BNXT_FLAG_REGISTERED;
 791
 792         return rc;
 793 }
 794
 795 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
 796 {
 797         int rc = 0;
 798         struct hwrm_port_phy_cfg_input req = {0};
 799         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 800         uint32_t enables = 0;
 801
 802         HWRM_PREP(req, PORT_PHY_CFG);
 803
 804         if (conf->link_up) {
 805                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
 806                 if (bp->link_info.auto_mode && conf->link_speed) {
 807                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
 808                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
 809                 }
 810
 811                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
 812                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
 813                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
 814                 /*
 815                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
 816                  * any auto mode, even "none".
 817                  */
 818                 if (!conf->link_speed) {
 819                         /* No speeds specified. Enable AutoNeg - all speeds */
 820                         req.auto_mode =
 821                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
 822                 }
 823                 /* AutoNeg - Advertise speeds specified. */
 824                 if (conf->auto_link_speed_mask &&
 825                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
 826                         req.auto_mode =
 827                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
 828                         req.auto_link_speed_mask =
 829                                 conf->auto_link_speed_mask;
 830                         enables |=
 831                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
 832                 }
 833
 834                 req.auto_duplex = conf->duplex;
 835                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
 836                 req.auto_pause = conf->auto_pause;
 837                 req.force_pause = conf->force_pause;
 838                 /* Set force_pause if there is no auto or if there is a force */
 839                 if (req.auto_pause && !req.force_pause)
 840                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
 841                 else
 842                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
 843
 844                 req.enables = rte_cpu_to_le_32(enables);
 845         } else {
 846                 req.flags =
 847                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
 848                 PMD_DRV_LOG(INFO, "Force Link Down\n");
 849         }
 850
 851         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 852
 853         HWRM_CHECK_RESULT();
 854         HWRM_UNLOCK();
 855
 856         return rc;
 857 }
 858
 859 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
 860                                    struct bnxt_link_info *link_info)
 861 {
 862         int rc = 0;
 863         struct hwrm_port_phy_qcfg_input req = {0};
 864         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 865
 866         HWRM_PREP(req, PORT_PHY_QCFG);
 867
 868         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 869
 870         HWRM_CHECK_RESULT();
 871
 872         link_info->phy_link_status = resp->link;
 873         link_info->link_up =
 874                 (link_info->phy_link_status ==
 875                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
 876         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
 877         link_info->duplex = resp->duplex_cfg;
 878         link_info->pause = resp->pause;
 879         link_info->auto_pause = resp->auto_pause;
 880         link_info->force_pause = resp->force_pause;
 881         link_info->auto_mode = resp->auto_mode;
 882         link_info->phy_type = resp->phy_type;
 883         link_info->media_type = resp->media_type;
 884
 885         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
 886         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
 887         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
 888         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
 889         link_info->phy_ver[0] = resp->phy_maj;
 890         link_info->phy_ver[1] = resp->phy_min;
 891         link_info->phy_ver[2] = resp->phy_bld;
 892
 893         HWRM_UNLOCK();
 894
 895         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
 896         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
 897         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
 898         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
 899         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
 900                     link_info->auto_link_speed_mask);
 901         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
 902                     link_info->force_link_speed);
 903
 904         return rc;
 905 }
 906
 907 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
 908 {
 909         int rc = 0;
 910         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
 911         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
 912         int i;
 913
 914         HWRM_PREP(req, QUEUE_QPORTCFG);
 915
 916         req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
 917         /* HWRM Version >= 1.9.1 */
 918         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
 919                 req.drv_qmap_cap =
 920                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
 921         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 922
 923         HWRM_CHECK_RESULT();
 924
 925 #define GET_QUEUE_INFO(x) \
 926         bp->cos_queue[x].id = resp->queue_id##x; \
 927         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
 928
 929         GET_QUEUE_INFO(0);
 930         GET_QUEUE_INFO(1);
 931         GET_QUEUE_INFO(2);
 932         GET_QUEUE_INFO(3);
 933         GET_QUEUE_INFO(4);
 934         GET_QUEUE_INFO(5);
 935         GET_QUEUE_INFO(6);
 936         GET_QUEUE_INFO(7);
 937
 938         HWRM_UNLOCK();
 939
 940         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
 941                 bp->tx_cosq_id = bp->cos_queue[0].id;
 942         } else {
 943                 /* iterate and find the COSq profile to use for Tx */
 944                 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 945                         if (bp->cos_queue[i].profile ==
 946                                 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
 947                                 bp->tx_cosq_id = bp->cos_queue[i].id;
 948                                 break;
 949                         }
 950                 }
 951         }
 952         PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
 953
 954         return rc;
 955 }
 956
 957 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
 958                          struct bnxt_ring *ring,
 959                          uint32_t ring_type, uint32_t map_index,
 960                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
 961 {
 962         int rc = 0;
 963         uint32_t enables = 0;
 964         struct hwrm_ring_alloc_input req = {.req_type = 0 };
 965         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 966
 967         HWRM_PREP(req, RING_ALLOC);
 968
 969         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
 970         req.fbo = rte_cpu_to_le_32(0);
 971         /* Association of ring index with doorbell index */
 972         req.logical_id = rte_cpu_to_le_16(map_index);
 973         req.length = rte_cpu_to_le_32(ring->ring_size);
 974
 975         switch (ring_type) {
 976         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
 977                 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
 978                 /* FALLTHROUGH */
 979         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
 980                 req.ring_type = ring_type;
 981                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
 982                 req.stat_ctx_id = rte_cpu_to_le_16(stats_ctx_id);
 983                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
 984                         enables |=
 985                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
 986                 break;
 987         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
 988                 req.ring_type = ring_type;
 989                 /*
 990                  * TODO: Some HWRM versions crash with
 991                  * HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
 992                  */
 993                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
 994                 break;
 995         default:
 996                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
 997                         ring_type);
 998                 HWRM_UNLOCK();
 999                 return -1;
1000         }
1001         req.enables = rte_cpu_to_le_32(enables);
1002
1003         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1004
1005         if (rc || resp->error_code) {
1006                 if (rc == 0 && resp->error_code)
1007                         rc = rte_le_to_cpu_16(resp->error_code);
1008                 switch (ring_type) {
1009                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1010                         PMD_DRV_LOG(ERR,
1011                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1012                         HWRM_UNLOCK();
1013                         return rc;
1014                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1015                         PMD_DRV_LOG(ERR,
1016                                 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1017                         HWRM_UNLOCK();
1018                         return rc;
1019                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1020                         PMD_DRV_LOG(ERR,
1021                                 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1022                         HWRM_UNLOCK();
1023                         return rc;
1024                 default:
1025                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1026                         HWRM_UNLOCK();
1027                         return rc;
1028                 }
1029         }
1030
1031         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1032         HWRM_UNLOCK();
1033         return rc;
1034 }
1035
1036 int bnxt_hwrm_ring_free(struct bnxt *bp,
1037                         struct bnxt_ring *ring, uint32_t ring_type)
1038 {
1039         int rc;
1040         struct hwrm_ring_free_input req = {.req_type = 0 };
1041         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1042
1043         HWRM_PREP(req, RING_FREE);
1044
1045         req.ring_type = ring_type;
1046         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1047
1048         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1049
1050         if (rc || resp->error_code) {
1051                 if (rc == 0 && resp->error_code)
1052                         rc = rte_le_to_cpu_16(resp->error_code);
1053                 HWRM_UNLOCK();
1054
1055                 switch (ring_type) {
1056                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1057                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1058                                 rc);
1059                         return rc;
1060                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1061                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1062                                 rc);
1063                         return rc;
1064                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1065                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1066                                 rc);
1067                         return rc;
1068                 default:
1069                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1070                         return rc;
1071                 }
1072         }
1073         HWRM_UNLOCK();
1074         return 0;
1075 }
1076
1077 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1078 {
1079         int rc = 0;
1080         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1081         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1082
1083         HWRM_PREP(req, RING_GRP_ALLOC);
1084
1085         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1086         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1087         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1088         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1089
1090         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1091
1092         HWRM_CHECK_RESULT();
1093
1094         bp->grp_info[idx].fw_grp_id =
1095             rte_le_to_cpu_16(resp->ring_group_id);
1096
1097         HWRM_UNLOCK();
1098
1099         return rc;
1100 }
1101
1102 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1103 {
1104         int rc;
1105         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1106         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1107
1108         HWRM_PREP(req, RING_GRP_FREE);
1109
1110         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1111
1112         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1113
1114         HWRM_CHECK_RESULT();
1115         HWRM_UNLOCK();
1116
1117         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1118         return rc;
1119 }
1120
1121 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1122 {
1123         int rc = 0;
1124         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1125         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1126
1127         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1128                 return rc;
1129
1130         HWRM_PREP(req, STAT_CTX_CLR_STATS);
1131
1132         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1133
1134         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1135
1136         HWRM_CHECK_RESULT();
1137         HWRM_UNLOCK();
1138
1139         return rc;
1140 }
1141
1142 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1143                                 unsigned int idx __rte_unused)
1144 {
1145         int rc;
1146         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1147         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1148
1149         HWRM_PREP(req, STAT_CTX_ALLOC);
1150
1151         req.update_period_ms = rte_cpu_to_le_32(0);
1152
1153         req.stats_dma_addr =
1154             rte_cpu_to_le_64(cpr->hw_stats_map);
1155
1156         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1157
1158         HWRM_CHECK_RESULT();
1159
1160         cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
1161
1162         HWRM_UNLOCK();
1163
1164         return rc;
1165 }
1166
1167 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1168                                 unsigned int idx __rte_unused)
1169 {
1170         int rc;
1171         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1172         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1173
1174         HWRM_PREP(req, STAT_CTX_FREE);
1175
1176         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1177
1178         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1179
1180         HWRM_CHECK_RESULT();
1181         HWRM_UNLOCK();
1182
1183         return rc;
1184 }
1185
1186 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1187 {
1188         int rc = 0, i, j;
1189         struct hwrm_vnic_alloc_input req = { 0 };
1190         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1191
1192         /* map ring groups to this vnic */
1193         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1194                 vnic->start_grp_id, vnic->end_grp_id);
1195         for (i = vnic->start_grp_id, j = 0; i <= vnic->end_grp_id; i++, j++)
1196                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1197         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1198         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1199         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1200         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1201         vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1202                                 ETHER_CRC_LEN + VLAN_TAG_SIZE;
1203         HWRM_PREP(req, VNIC_ALLOC);
1204
1205         if (vnic->func_default)
1206                 req.flags =
1207                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1208         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1209
1210         HWRM_CHECK_RESULT();
1211
1212         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1213         HWRM_UNLOCK();
1214         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1215         return rc;
1216 }
1217
1218 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1219                                         struct bnxt_vnic_info *vnic,
1220                                         struct bnxt_plcmodes_cfg *pmode)
1221 {
1222         int rc = 0;
1223         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1224         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1225
1226         HWRM_PREP(req, VNIC_PLCMODES_QCFG);
1227
1228         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1229
1230         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1231
1232         HWRM_CHECK_RESULT();
1233
1234         pmode->flags = rte_le_to_cpu_32(resp->flags);
1235         /* dflt_vnic bit doesn't exist in the _cfg command */
1236         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1237         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1238         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1239         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1240
1241         HWRM_UNLOCK();
1242
1243         return rc;
1244 }
1245
1246 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1247                                        struct bnxt_vnic_info *vnic,
1248                                        struct bnxt_plcmodes_cfg *pmode)
1249 {
1250         int rc = 0;
1251         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1252         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1253
1254         HWRM_PREP(req, VNIC_PLCMODES_CFG);
1255
1256         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1257         req.flags = rte_cpu_to_le_32(pmode->flags);
1258         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1259         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1260         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1261         req.enables = rte_cpu_to_le_32(
1262             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1263             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1264             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1265         );
1266
1267         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1268
1269         HWRM_CHECK_RESULT();
1270         HWRM_UNLOCK();
1271
1272         return rc;
1273 }
1274
1275 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1276 {
1277         int rc = 0;
1278         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1279         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1280         uint32_t ctx_enable_flag = 0;
1281         struct bnxt_plcmodes_cfg pmodes;
1282
1283         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1284                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1285                 return rc;
1286         }
1287
1288         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1289         if (rc)
1290                 return rc;
1291
1292         HWRM_PREP(req, VNIC_CFG);
1293
1294         /* Only RSS support for now TBD: COS & LB */
1295         req.enables =
1296             rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP);
1297         if (vnic->lb_rule != 0xffff)
1298                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1299         if (vnic->cos_rule != 0xffff)
1300                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1301         if (vnic->rss_rule != 0xffff) {
1302                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1303                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1304         }
1305         req.enables |= rte_cpu_to_le_32(ctx_enable_flag);
1306         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1307         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1308         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1309         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1310         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1311         req.mru = rte_cpu_to_le_16(vnic->mru);
1312         if (vnic->func_default)
1313                 req.flags |=
1314                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1315         if (vnic->vlan_strip)
1316                 req.flags |=
1317                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1318         if (vnic->bd_stall)
1319                 req.flags |=
1320                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1321         if (vnic->roce_dual)
1322                 req.flags |= rte_cpu_to_le_32(
1323                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1324         if (vnic->roce_only)
1325                 req.flags |= rte_cpu_to_le_32(
1326                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1327         if (vnic->rss_dflt_cr)
1328                 req.flags |= rte_cpu_to_le_32(
1329                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1330
1331         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1332
1333         HWRM_CHECK_RESULT();
1334         HWRM_UNLOCK();
1335
1336         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1337
1338         return rc;
1339 }
1340
1341 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1342                 int16_t fw_vf_id)
1343 {
1344         int rc = 0;
1345         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1346         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1347
1348         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1349                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1350                 return rc;
1351         }
1352         HWRM_PREP(req, VNIC_QCFG);
1353
1354         req.enables =
1355                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1356         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1357         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1358
1359         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1360
1361         HWRM_CHECK_RESULT();
1362
1363         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1364         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1365         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1366         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1367         vnic->mru = rte_le_to_cpu_16(resp->mru);
1368         vnic->func_default = rte_le_to_cpu_32(
1369                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1370         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1371                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1372         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1373                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1374         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1375                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1376         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1377                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1378         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1379                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1380
1381         HWRM_UNLOCK();
1382
1383         return rc;
1384 }
1385
1386 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1387 {
1388         int rc = 0;
1389         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1390         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1391                                                 bp->hwrm_cmd_resp_addr;
1392
1393         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC);
1394
1395         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1396
1397         HWRM_CHECK_RESULT();
1398
1399         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1400         HWRM_UNLOCK();
1401         PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1402
1403         return rc;
1404 }
1405
1406 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1407 {
1408         int rc = 0;
1409         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1410         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1411                                                 bp->hwrm_cmd_resp_addr;
1412
1413         if (vnic->rss_rule == 0xffff) {
1414                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1415                 return rc;
1416         }
1417         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE);
1418
1419         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->rss_rule);
1420
1421         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1422
1423         HWRM_CHECK_RESULT();
1424         HWRM_UNLOCK();
1425
1426         vnic->rss_rule = INVALID_HW_RING_ID;
1427
1428         return rc;
1429 }
1430
1431 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1432 {
1433         int rc = 0;
1434         struct hwrm_vnic_free_input req = {.req_type = 0 };
1435         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1436
1437         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1438                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1439                 return rc;
1440         }
1441
1442         HWRM_PREP(req, VNIC_FREE);
1443
1444         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1445
1446         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1447
1448         HWRM_CHECK_RESULT();
1449         HWRM_UNLOCK();
1450
1451         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1452         return rc;
1453 }
1454
1455 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1456                            struct bnxt_vnic_info *vnic)
1457 {
1458         int rc = 0;
1459         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1460         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1461
1462         HWRM_PREP(req, VNIC_RSS_CFG);
1463
1464         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1465
1466         req.ring_grp_tbl_addr =
1467             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1468         req.hash_key_tbl_addr =
1469             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1470         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1471
1472         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1473
1474         HWRM_CHECK_RESULT();
1475         HWRM_UNLOCK();
1476
1477         return rc;
1478 }
1479
1480 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1481                         struct bnxt_vnic_info *vnic)
1482 {
1483         int rc = 0;
1484         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1485         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1486         uint16_t size;
1487
1488         HWRM_PREP(req, VNIC_PLCMODES_CFG);
1489
1490         req.flags = rte_cpu_to_le_32(
1491                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1492
1493         req.enables = rte_cpu_to_le_32(
1494                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1495
1496         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1497         size -= RTE_PKTMBUF_HEADROOM;
1498
1499         req.jumbo_thresh = rte_cpu_to_le_16(size);
1500         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1501
1502         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1503
1504         HWRM_CHECK_RESULT();
1505         HWRM_UNLOCK();
1506
1507         return rc;
1508 }
1509
1510 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1511                         struct bnxt_vnic_info *vnic, bool enable)
1512 {
1513         int rc = 0;
1514         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1515         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1516
1517         HWRM_PREP(req, VNIC_TPA_CFG);
1518
1519         if (enable) {
1520                 req.enables = rte_cpu_to_le_32(
1521                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1522                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1523                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1524                 req.flags = rte_cpu_to_le_32(
1525                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1526                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1527                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1528                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1529                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1530                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1531                 req.max_agg_segs = rte_cpu_to_le_16(5);
1532                 req.max_aggs =
1533                         rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1534                 req.min_agg_len = rte_cpu_to_le_32(512);
1535         }
1536         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1537
1538         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1539
1540         HWRM_CHECK_RESULT();
1541         HWRM_UNLOCK();
1542
1543         return rc;
1544 }
1545
1546 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1547 {
1548         struct hwrm_func_cfg_input req = {0};
1549         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1550         int rc;
1551
1552         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1553         req.enables = rte_cpu_to_le_32(
1554                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1555         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1556         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1557
1558         HWRM_PREP(req, FUNC_CFG);
1559
1560         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1561         HWRM_CHECK_RESULT();
1562         HWRM_UNLOCK();
1563
1564         bp->pf.vf_info[vf].random_mac = false;
1565
1566         return rc;
1567 }
1568
1569 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1570                                   uint64_t *dropped)
1571 {
1572         int rc = 0;
1573         struct hwrm_func_qstats_input req = {.req_type = 0};
1574         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1575
1576         HWRM_PREP(req, FUNC_QSTATS);
1577
1578         req.fid = rte_cpu_to_le_16(fid);
1579
1580         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1581
1582         HWRM_CHECK_RESULT();
1583
1584         if (dropped)
1585                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1586
1587         HWRM_UNLOCK();
1588
1589         return rc;
1590 }
1591
1592 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1593                           struct rte_eth_stats *stats)
1594 {
1595         int rc = 0;
1596         struct hwrm_func_qstats_input req = {.req_type = 0};
1597         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1598
1599         HWRM_PREP(req, FUNC_QSTATS);
1600
1601         req.fid = rte_cpu_to_le_16(fid);
1602
1603         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1604
1605         HWRM_CHECK_RESULT();
1606
1607         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1608         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1609         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1610         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1611         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1612         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1613
1614         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1615         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1616         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1617         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1618         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1619         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1620
1621         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
1622         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
1623         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
1624
1625         HWRM_UNLOCK();
1626
1627         return rc;
1628 }
1629
1630 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1631 {
1632         int rc = 0;
1633         struct hwrm_func_clr_stats_input req = {.req_type = 0};
1634         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1635
1636         HWRM_PREP(req, FUNC_CLR_STATS);
1637
1638         req.fid = rte_cpu_to_le_16(fid);
1639
1640         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1641
1642         HWRM_CHECK_RESULT();
1643         HWRM_UNLOCK();
1644
1645         return rc;
1646 }
1647
1648 /*
1649  * HWRM utility functions
1650  */
1651
1652 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1653 {
1654         unsigned int i;
1655         int rc = 0;
1656
1657         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1658                 struct bnxt_tx_queue *txq;
1659                 struct bnxt_rx_queue *rxq;
1660                 struct bnxt_cp_ring_info *cpr;
1661
1662                 if (i >= bp->rx_cp_nr_rings) {
1663                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1664                         cpr = txq->cp_ring;
1665                 } else {
1666                         rxq = bp->rx_queues[i];
1667                         cpr = rxq->cp_ring;
1668                 }
1669
1670                 rc = bnxt_hwrm_stat_clear(bp, cpr);
1671                 if (rc)
1672                         return rc;
1673         }
1674         return 0;
1675 }
1676
1677 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1678 {
1679         int rc;
1680         unsigned int i;
1681         struct bnxt_cp_ring_info *cpr;
1682
1683         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1684
1685                 if (i >= bp->rx_cp_nr_rings) {
1686                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
1687                 } else {
1688                         cpr = bp->rx_queues[i]->cp_ring;
1689                         bp->grp_info[i].fw_stats_ctx = -1;
1690                 }
1691                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
1692                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
1693                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1694                         if (rc)
1695                                 return rc;
1696                 }
1697         }
1698         return 0;
1699 }
1700
1701 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
1702 {
1703         unsigned int i;
1704         int rc = 0;
1705
1706         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1707                 struct bnxt_tx_queue *txq;
1708                 struct bnxt_rx_queue *rxq;
1709                 struct bnxt_cp_ring_info *cpr;
1710
1711                 if (i >= bp->rx_cp_nr_rings) {
1712                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1713                         cpr = txq->cp_ring;
1714                 } else {
1715                         rxq = bp->rx_queues[i];
1716                         cpr = rxq->cp_ring;
1717                 }
1718
1719                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
1720
1721                 if (rc)
1722                         return rc;
1723         }
1724         return rc;
1725 }
1726
1727 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
1728 {
1729         uint16_t idx;
1730         uint32_t rc = 0;
1731
1732         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
1733
1734                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
1735                         continue;
1736
1737                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
1738
1739                 if (rc)
1740                         return rc;
1741         }
1742         return rc;
1743 }
1744
1745 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1746                                 unsigned int idx __rte_unused)
1747 {
1748         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
1749
1750         bnxt_hwrm_ring_free(bp, cp_ring,
1751                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
1752         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
1753         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
1754                         sizeof(*cpr->cp_desc_ring));
1755         cpr->cp_raw_cons = 0;
1756 }
1757
1758 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
1759 {
1760         unsigned int i;
1761         int rc = 0;
1762
1763         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
1764                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
1765                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
1766                 struct bnxt_ring *ring = txr->tx_ring_struct;
1767                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
1768                 unsigned int idx = bp->rx_cp_nr_rings + i + 1;
1769
1770                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1771                         bnxt_hwrm_ring_free(bp, ring,
1772                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
1773                         ring->fw_ring_id = INVALID_HW_RING_ID;
1774                         memset(txr->tx_desc_ring, 0,
1775                                         txr->tx_ring_struct->ring_size *
1776                                         sizeof(*txr->tx_desc_ring));
1777                         memset(txr->tx_buf_ring, 0,
1778                                         txr->tx_ring_struct->ring_size *
1779                                         sizeof(*txr->tx_buf_ring));
1780                         txr->tx_prod = 0;
1781                         txr->tx_cons = 0;
1782                 }
1783                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1784                         bnxt_free_cp_ring(bp, cpr, idx);
1785                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1786                 }
1787         }
1788
1789         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1790                 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
1791                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1792                 struct bnxt_ring *ring = rxr->rx_ring_struct;
1793                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1794                 unsigned int idx = i + 1;
1795
1796                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1797                         bnxt_hwrm_ring_free(bp, ring,
1798                                         HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1799                         ring->fw_ring_id = INVALID_HW_RING_ID;
1800                         bp->grp_info[idx].rx_fw_ring_id = INVALID_HW_RING_ID;
1801                         memset(rxr->rx_desc_ring, 0,
1802                                         rxr->rx_ring_struct->ring_size *
1803                                         sizeof(*rxr->rx_desc_ring));
1804                         memset(rxr->rx_buf_ring, 0,
1805                                         rxr->rx_ring_struct->ring_size *
1806                                         sizeof(*rxr->rx_buf_ring));
1807                         rxr->rx_prod = 0;
1808                 }
1809                 ring = rxr->ag_ring_struct;
1810                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1811                         bnxt_hwrm_ring_free(bp, ring,
1812                                             HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1813                         ring->fw_ring_id = INVALID_HW_RING_ID;
1814                         memset(rxr->ag_buf_ring, 0,
1815                                rxr->ag_ring_struct->ring_size *
1816                                sizeof(*rxr->ag_buf_ring));
1817                         rxr->ag_prod = 0;
1818                         bp->grp_info[i].ag_fw_ring_id = INVALID_HW_RING_ID;
1819                 }
1820                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1821                         bnxt_free_cp_ring(bp, cpr, idx);
1822                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
1823                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1824                 }
1825         }
1826
1827         /* Default completion ring */
1828         {
1829                 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1830
1831                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1832                         bnxt_free_cp_ring(bp, cpr, 0);
1833                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1834                 }
1835         }
1836
1837         return rc;
1838 }
1839
1840 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
1841 {
1842         uint16_t i;
1843         uint32_t rc = 0;
1844
1845         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1846                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
1847                 if (rc)
1848                         return rc;
1849         }
1850         return rc;
1851 }
1852
1853 void bnxt_free_hwrm_resources(struct bnxt *bp)
1854 {
1855         /* Release memzone */
1856         rte_free(bp->hwrm_cmd_resp_addr);
1857         rte_free(bp->hwrm_short_cmd_req_addr);
1858         bp->hwrm_cmd_resp_addr = NULL;
1859         bp->hwrm_short_cmd_req_addr = NULL;
1860         bp->hwrm_cmd_resp_dma_addr = 0;
1861         bp->hwrm_short_cmd_req_dma_addr = 0;
1862 }
1863
1864 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
1865 {
1866         struct rte_pci_device *pdev = bp->pdev;
1867         char type[RTE_MEMZONE_NAMESIZE];
1868
1869         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
1870                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
1871         bp->max_resp_len = HWRM_MAX_RESP_LEN;
1872         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
1873         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1874         if (bp->hwrm_cmd_resp_addr == NULL)
1875                 return -ENOMEM;
1876         bp->hwrm_cmd_resp_dma_addr =
1877                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1878         if (bp->hwrm_cmd_resp_dma_addr == 0) {
1879                 PMD_DRV_LOG(ERR,
1880                         "unable to map response address to physical memory\n");
1881                 return -ENOMEM;
1882         }
1883         rte_spinlock_init(&bp->hwrm_lock);
1884
1885         return 0;
1886 }
1887
1888 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1889 {
1890         struct bnxt_filter_info *filter;
1891         int rc = 0;
1892
1893         STAILQ_FOREACH(filter, &vnic->filter, next) {
1894                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1895                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
1896                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1897                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
1898                 else
1899                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1900                 //if (rc)
1901                         //break;
1902         }
1903         return rc;
1904 }
1905
1906 static int
1907 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1908 {
1909         struct bnxt_filter_info *filter;
1910         struct rte_flow *flow;
1911         int rc = 0;
1912
1913         STAILQ_FOREACH(flow, &vnic->flow_list, next) {
1914                 filter = flow->filter;
1915                 PMD_DRV_LOG(ERR, "filter type %d\n", filter->filter_type);
1916                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1917                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
1918                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1919                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
1920                 else
1921                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1922
1923                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
1924                 rte_free(flow);
1925                 //if (rc)
1926                         //break;
1927         }
1928         return rc;
1929 }
1930
1931 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1932 {
1933         struct bnxt_filter_info *filter;
1934         int rc = 0;
1935
1936         STAILQ_FOREACH(filter, &vnic->filter, next) {
1937                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1938                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
1939                                                      filter);
1940                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1941                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
1942                                                          filter);
1943                 else
1944                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
1945                                                      filter);
1946                 if (rc)
1947                         break;
1948         }
1949         return rc;
1950 }
1951
1952 void bnxt_free_tunnel_ports(struct bnxt *bp)
1953 {
1954         if (bp->vxlan_port_cnt)
1955                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
1956                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
1957         bp->vxlan_port = 0;
1958         if (bp->geneve_port_cnt)
1959                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
1960                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
1961         bp->geneve_port = 0;
1962 }
1963
1964 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
1965 {
1966         int i;
1967
1968         if (bp->vnic_info == NULL)
1969                 return;
1970
1971         /*
1972          * Cleanup VNICs in reverse order, to make sure the L2 filter
1973          * from vnic0 is last to be cleaned up.
1974          */
1975         for (i = bp->nr_vnics - 1; i >= 0; i--) {
1976                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1977
1978                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
1979
1980                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
1981
1982                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
1983
1984                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
1985
1986                 bnxt_hwrm_vnic_free(bp, vnic);
1987         }
1988         /* Ring resources */
1989         bnxt_free_all_hwrm_rings(bp);
1990         bnxt_free_all_hwrm_ring_grps(bp);
1991         bnxt_free_all_hwrm_stat_ctxs(bp);
1992         bnxt_free_tunnel_ports(bp);
1993 }
1994
1995 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
1996 {
1997         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1998
1999         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2000                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2001
2002         switch (conf_link_speed) {
2003         case ETH_LINK_SPEED_10M_HD:
2004         case ETH_LINK_SPEED_100M_HD:
2005                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2006         }
2007         return hw_link_duplex;
2008 }
2009
2010 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2011 {
2012         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2013 }
2014
2015 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2016 {
2017         uint16_t eth_link_speed = 0;
2018
2019         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2020                 return ETH_LINK_SPEED_AUTONEG;
2021
2022         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2023         case ETH_LINK_SPEED_100M:
2024         case ETH_LINK_SPEED_100M_HD:
2025                 eth_link_speed =
2026                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2027                 break;
2028         case ETH_LINK_SPEED_1G:
2029                 eth_link_speed =
2030                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2031                 break;
2032         case ETH_LINK_SPEED_2_5G:
2033                 eth_link_speed =
2034                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2035                 break;
2036         case ETH_LINK_SPEED_10G:
2037                 eth_link_speed =
2038                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2039                 break;
2040         case ETH_LINK_SPEED_20G:
2041                 eth_link_speed =
2042                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2043                 break;
2044         case ETH_LINK_SPEED_25G:
2045                 eth_link_speed =
2046                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2047                 break;
2048         case ETH_LINK_SPEED_40G:
2049                 eth_link_speed =
2050                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2051                 break;
2052         case ETH_LINK_SPEED_50G:
2053                 eth_link_speed =
2054                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2055                 break;
2056         case ETH_LINK_SPEED_100G:
2057                 eth_link_speed =
2058                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2059                 break;
2060         default:
2061                 PMD_DRV_LOG(ERR,
2062                         "Unsupported link speed %d; default to AUTO\n",
2063                         conf_link_speed);
2064                 break;
2065         }
2066         return eth_link_speed;
2067 }
2068
2069 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2070                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2071                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2072                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2073
2074 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2075 {
2076         uint32_t one_speed;
2077
2078         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2079                 return 0;
2080
2081         if (link_speed & ETH_LINK_SPEED_FIXED) {
2082                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2083
2084                 if (one_speed & (one_speed - 1)) {
2085                         PMD_DRV_LOG(ERR,
2086                                 "Invalid advertised speeds (%u) for port %u\n",
2087                                 link_speed, port_id);
2088                         return -EINVAL;
2089                 }
2090                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2091                         PMD_DRV_LOG(ERR,
2092                                 "Unsupported advertised speed (%u) for port %u\n",
2093                                 link_speed, port_id);
2094                         return -EINVAL;
2095                 }
2096         } else {
2097                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2098                         PMD_DRV_LOG(ERR,
2099                                 "Unsupported advertised speeds (%u) for port %u\n",
2100                                 link_speed, port_id);
2101                         return -EINVAL;
2102                 }
2103         }
2104         return 0;
2105 }
2106
2107 static uint16_t
2108 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2109 {
2110         uint16_t ret = 0;
2111
2112         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2113                 if (bp->link_info.support_speeds)
2114                         return bp->link_info.support_speeds;
2115                 link_speed = BNXT_SUPPORTED_SPEEDS;
2116         }
2117
2118         if (link_speed & ETH_LINK_SPEED_100M)
2119                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2120         if (link_speed & ETH_LINK_SPEED_100M_HD)
2121                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2122         if (link_speed & ETH_LINK_SPEED_1G)
2123                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2124         if (link_speed & ETH_LINK_SPEED_2_5G)
2125                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2126         if (link_speed & ETH_LINK_SPEED_10G)
2127                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2128         if (link_speed & ETH_LINK_SPEED_20G)
2129                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2130         if (link_speed & ETH_LINK_SPEED_25G)
2131                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2132         if (link_speed & ETH_LINK_SPEED_40G)
2133                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2134         if (link_speed & ETH_LINK_SPEED_50G)
2135                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2136         if (link_speed & ETH_LINK_SPEED_100G)
2137                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2138         return ret;
2139 }
2140
2141 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2142 {
2143         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2144
2145         switch (hw_link_speed) {
2146         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2147                 eth_link_speed = ETH_SPEED_NUM_100M;
2148                 break;
2149         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2150                 eth_link_speed = ETH_SPEED_NUM_1G;
2151                 break;
2152         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2153                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2154                 break;
2155         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2156                 eth_link_speed = ETH_SPEED_NUM_10G;
2157                 break;
2158         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2159                 eth_link_speed = ETH_SPEED_NUM_20G;
2160                 break;
2161         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2162                 eth_link_speed = ETH_SPEED_NUM_25G;
2163                 break;
2164         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2165                 eth_link_speed = ETH_SPEED_NUM_40G;
2166                 break;
2167         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2168                 eth_link_speed = ETH_SPEED_NUM_50G;
2169                 break;
2170         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2171                 eth_link_speed = ETH_SPEED_NUM_100G;
2172                 break;
2173         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2174         default:
2175                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2176                         hw_link_speed);
2177                 break;
2178         }
2179         return eth_link_speed;
2180 }
2181
2182 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2183 {
2184         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2185
2186         switch (hw_link_duplex) {
2187         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2188         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2189                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2190                 break;
2191         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2192                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2193                 break;
2194         default:
2195                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2196                         hw_link_duplex);
2197                 break;
2198         }
2199         return eth_link_duplex;
2200 }
2201
2202 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2203 {
2204         int rc = 0;
2205         struct bnxt_link_info *link_info = &bp->link_info;
2206
2207         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2208         if (rc) {
2209                 PMD_DRV_LOG(ERR,
2210                         "Get link config failed with rc %d\n", rc);
2211                 goto exit;
2212         }
2213         if (link_info->link_speed)
2214                 link->link_speed =
2215                         bnxt_parse_hw_link_speed(link_info->link_speed);
2216         else
2217                 link->link_speed = ETH_SPEED_NUM_NONE;
2218         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2219         link->link_status = link_info->link_up;
2220         link->link_autoneg = link_info->auto_mode ==
2221                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2222                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2223 exit:
2224         return rc;
2225 }
2226
2227 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2228 {
2229         int rc = 0;
2230         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2231         struct bnxt_link_info link_req;
2232         uint16_t speed, autoneg;
2233
2234         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2235                 return 0;
2236
2237         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2238                         bp->eth_dev->data->port_id);
2239         if (rc)
2240                 goto error;
2241
2242         memset(&link_req, 0, sizeof(link_req));
2243         link_req.link_up = link_up;
2244         if (!link_up)
2245                 goto port_phy_cfg;
2246
2247         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2248         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2249         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2250         /* Autoneg can be done only when the FW allows */
2251         if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2252                                 bp->link_info.force_link_speed)) {
2253                 link_req.phy_flags |=
2254                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2255                 link_req.auto_link_speed_mask =
2256                         bnxt_parse_eth_link_speed_mask(bp,
2257                                                        dev_conf->link_speeds);
2258         } else {
2259                 if (bp->link_info.phy_type ==
2260                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2261                     bp->link_info.phy_type ==
2262                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2263                     bp->link_info.media_type ==
2264                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2265                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2266                         return -EINVAL;
2267                 }
2268
2269                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2270                 /* If user wants a particular speed try that first. */
2271                 if (speed)
2272                         link_req.link_speed = speed;
2273                 else if (bp->link_info.force_link_speed)
2274                         link_req.link_speed = bp->link_info.force_link_speed;
2275                 else
2276                         link_req.link_speed = bp->link_info.auto_link_speed;
2277         }
2278         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2279         link_req.auto_pause = bp->link_info.auto_pause;
2280         link_req.force_pause = bp->link_info.force_pause;
2281
2282 port_phy_cfg:
2283         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2284         if (rc) {
2285                 PMD_DRV_LOG(ERR,
2286                         "Set link config failed with rc %d\n", rc);
2287         }
2288
2289 error:
2290         return rc;
2291 }
2292
2293 /* JIRA 22088 */
2294 int bnxt_hwrm_func_qcfg(struct bnxt *bp)
2295 {
2296         struct hwrm_func_qcfg_input req = {0};
2297         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2298         uint16_t flags;
2299         int rc = 0;
2300
2301         HWRM_PREP(req, FUNC_QCFG);
2302         req.fid = rte_cpu_to_le_16(0xffff);
2303
2304         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2305
2306         HWRM_CHECK_RESULT();
2307
2308         /* Hard Coded.. 0xfff VLAN ID mask */
2309         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2310         flags = rte_le_to_cpu_16(resp->flags);
2311         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2312                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2313
2314         switch (resp->port_partition_type) {
2315         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2316         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2317         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2318                 bp->port_partition_type = resp->port_partition_type;
2319                 break;
2320         default:
2321                 bp->port_partition_type = 0;
2322                 break;
2323         }
2324
2325         HWRM_UNLOCK();
2326
2327         return rc;
2328 }
2329
2330 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2331                                    struct hwrm_func_qcaps_output *qcaps)
2332 {
2333         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2334         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2335                sizeof(qcaps->mac_address));
2336         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2337         qcaps->max_rx_rings = fcfg->num_rx_rings;
2338         qcaps->max_tx_rings = fcfg->num_tx_rings;
2339         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2340         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2341         qcaps->max_vfs = 0;
2342         qcaps->first_vf_id = 0;
2343         qcaps->max_vnics = fcfg->num_vnics;
2344         qcaps->max_decap_records = 0;
2345         qcaps->max_encap_records = 0;
2346         qcaps->max_tx_wm_flows = 0;
2347         qcaps->max_tx_em_flows = 0;
2348         qcaps->max_rx_wm_flows = 0;
2349         qcaps->max_rx_em_flows = 0;
2350         qcaps->max_flow_id = 0;
2351         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2352         qcaps->max_sp_tx_rings = 0;
2353         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2354 }
2355
2356 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2357 {
2358         struct hwrm_func_cfg_input req = {0};
2359         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2360         int rc;
2361
2362         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2363                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2364                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2365                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2366                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2367                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2368                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2369                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2370                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2371                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2372         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2373         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2374         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2375                                    ETHER_CRC_LEN + VLAN_TAG_SIZE *
2376                                    BNXT_NUM_VLANS);
2377         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2378         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2379         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2380         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2381         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2382         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2383         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2384         req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2385         req.fid = rte_cpu_to_le_16(0xffff);
2386
2387         HWRM_PREP(req, FUNC_CFG);
2388
2389         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2390
2391         HWRM_CHECK_RESULT();
2392         HWRM_UNLOCK();
2393
2394         return rc;
2395 }
2396
2397 static void populate_vf_func_cfg_req(struct bnxt *bp,
2398                                      struct hwrm_func_cfg_input *req,
2399                                      int num_vfs)
2400 {
2401         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2402                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2403                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2404                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2405                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2406                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2407                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2408                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2409                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2410                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2411
2412         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2413                                     ETHER_CRC_LEN + VLAN_TAG_SIZE *
2414                                     BNXT_NUM_VLANS);
2415         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2416                                     ETHER_CRC_LEN + VLAN_TAG_SIZE *
2417                                     BNXT_NUM_VLANS);
2418         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2419                                                 (num_vfs + 1));
2420         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2421         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2422                                                (num_vfs + 1));
2423         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2424         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2425         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2426         /* TODO: For now, do not support VMDq/RFS on VFs. */
2427         req->num_vnics = rte_cpu_to_le_16(1);
2428         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2429                                                  (num_vfs + 1));
2430 }
2431
2432 static void add_random_mac_if_needed(struct bnxt *bp,
2433                                      struct hwrm_func_cfg_input *cfg_req,
2434                                      int vf)
2435 {
2436         struct ether_addr mac;
2437
2438         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2439                 return;
2440
2441         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2442                 cfg_req->enables |=
2443                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2444                 eth_random_addr(cfg_req->dflt_mac_addr);
2445                 bp->pf.vf_info[vf].random_mac = true;
2446         } else {
2447                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes, ETHER_ADDR_LEN);
2448         }
2449 }
2450
2451 static void reserve_resources_from_vf(struct bnxt *bp,
2452                                       struct hwrm_func_cfg_input *cfg_req,
2453                                       int vf)
2454 {
2455         struct hwrm_func_qcaps_input req = {0};
2456         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2457         int rc;
2458
2459         /* Get the actual allocated values now */
2460         HWRM_PREP(req, FUNC_QCAPS);
2461         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2462         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2463
2464         if (rc) {
2465                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2466                 copy_func_cfg_to_qcaps(cfg_req, resp);
2467         } else if (resp->error_code) {
2468                 rc = rte_le_to_cpu_16(resp->error_code);
2469                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2470                 copy_func_cfg_to_qcaps(cfg_req, resp);
2471         }
2472
2473         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2474         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2475         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2476         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2477         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2478         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2479         /*
2480          * TODO: While not supporting VMDq with VFs, max_vnics is always
2481          * forced to 1 in this case
2482          */
2483         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2484         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2485
2486         HWRM_UNLOCK();
2487 }
2488
2489 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2490 {
2491         struct hwrm_func_qcfg_input req = {0};
2492         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2493         int rc;
2494
2495         /* Check for zero MAC address */
2496         HWRM_PREP(req, FUNC_QCFG);
2497         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2498         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2499         if (rc) {
2500                 PMD_DRV_LOG(ERR, "hwrm_func_qcfg failed rc:%d\n", rc);
2501                 return -1;
2502         } else if (resp->error_code) {
2503                 rc = rte_le_to_cpu_16(resp->error_code);
2504                 PMD_DRV_LOG(ERR, "hwrm_func_qcfg error %d\n", rc);
2505                 return -1;
2506         }
2507         rc = rte_le_to_cpu_16(resp->vlan);
2508
2509         HWRM_UNLOCK();
2510
2511         return rc;
2512 }
2513
2514 static int update_pf_resource_max(struct bnxt *bp)
2515 {
2516         struct hwrm_func_qcfg_input req = {0};
2517         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2518         int rc;
2519
2520         /* And copy the allocated numbers into the pf struct */
2521         HWRM_PREP(req, FUNC_QCFG);
2522         req.fid = rte_cpu_to_le_16(0xffff);
2523         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2524         HWRM_CHECK_RESULT();
2525
2526         /* Only TX ring value reflects actual allocation? TODO */
2527         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2528         bp->pf.evb_mode = resp->evb_mode;
2529
2530         HWRM_UNLOCK();
2531
2532         return rc;
2533 }
2534
2535 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2536 {
2537         int rc;
2538
2539         if (!BNXT_PF(bp)) {
2540                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2541                 return -1;
2542         }
2543
2544         rc = bnxt_hwrm_func_qcaps(bp);
2545         if (rc)
2546                 return rc;
2547
2548         bp->pf.func_cfg_flags &=
2549                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2550                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2551         bp->pf.func_cfg_flags |=
2552                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2553         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2554         return rc;
2555 }
2556
2557 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2558 {
2559         struct hwrm_func_cfg_input req = {0};
2560         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2561         int i;
2562         size_t sz;
2563         int rc = 0;
2564         size_t req_buf_sz;
2565
2566         if (!BNXT_PF(bp)) {
2567                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2568                 return -1;
2569         }
2570
2571         rc = bnxt_hwrm_func_qcaps(bp);
2572
2573         if (rc)
2574                 return rc;
2575
2576         bp->pf.active_vfs = num_vfs;
2577
2578         /*
2579          * First, configure the PF to only use one TX ring.  This ensures that
2580          * there are enough rings for all VFs.
2581          *
2582          * If we don't do this, when we call func_alloc() later, we will lock
2583          * extra rings to the PF that won't be available during func_cfg() of
2584          * the VFs.
2585          *
2586          * This has been fixed with firmware versions above 20.6.54
2587          */
2588         bp->pf.func_cfg_flags &=
2589                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2590                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2591         bp->pf.func_cfg_flags |=
2592                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2593         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2594         if (rc)
2595                 return rc;
2596
2597         /*
2598          * Now, create and register a buffer to hold forwarded VF requests
2599          */
2600         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2601         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2602                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2603         if (bp->pf.vf_req_buf == NULL) {
2604                 rc = -ENOMEM;
2605                 goto error_free;
2606         }
2607         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2608                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2609         for (i = 0; i < num_vfs; i++)
2610                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2611                                         (i * HWRM_MAX_REQ_LEN);
2612
2613         rc = bnxt_hwrm_func_buf_rgtr(bp);
2614         if (rc)
2615                 goto error_free;
2616
2617         populate_vf_func_cfg_req(bp, &req, num_vfs);
2618
2619         bp->pf.active_vfs = 0;
2620         for (i = 0; i < num_vfs; i++) {
2621                 add_random_mac_if_needed(bp, &req, i);
2622
2623                 HWRM_PREP(req, FUNC_CFG);
2624                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2625                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
2626                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2627
2628                 /* Clear enable flag for next pass */
2629                 req.enables &= ~rte_cpu_to_le_32(
2630                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2631
2632                 if (rc || resp->error_code) {
2633                         PMD_DRV_LOG(ERR,
2634                                 "Failed to initizlie VF %d\n", i);
2635                         PMD_DRV_LOG(ERR,
2636                                 "Not all VFs available. (%d, %d)\n",
2637                                 rc, resp->error_code);
2638                         HWRM_UNLOCK();
2639                         break;
2640                 }
2641
2642                 HWRM_UNLOCK();
2643
2644                 reserve_resources_from_vf(bp, &req, i);
2645                 bp->pf.active_vfs++;
2646                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
2647         }
2648
2649         /*
2650          * Now configure the PF to use "the rest" of the resources
2651          * We're using STD_TX_RING_MODE here though which will limit the TX
2652          * rings.  This will allow QoS to function properly.  Not setting this
2653          * will cause PF rings to break bandwidth settings.
2654          */
2655         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2656         if (rc)
2657                 goto error_free;
2658
2659         rc = update_pf_resource_max(bp);
2660         if (rc)
2661                 goto error_free;
2662
2663         return rc;
2664
2665 error_free:
2666         bnxt_hwrm_func_buf_unrgtr(bp);
2667         return rc;
2668 }
2669
2670 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
2671 {
2672         struct hwrm_func_cfg_input req = {0};
2673         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2674         int rc;
2675
2676         HWRM_PREP(req, FUNC_CFG);
2677
2678         req.fid = rte_cpu_to_le_16(0xffff);
2679         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
2680         req.evb_mode = bp->pf.evb_mode;
2681
2682         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2683         HWRM_CHECK_RESULT();
2684         HWRM_UNLOCK();
2685
2686         return rc;
2687 }
2688
2689 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
2690                                 uint8_t tunnel_type)
2691 {
2692         struct hwrm_tunnel_dst_port_alloc_input req = {0};
2693         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2694         int rc = 0;
2695
2696         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC);
2697         req.tunnel_type = tunnel_type;
2698         req.tunnel_dst_port_val = port;
2699         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2700         HWRM_CHECK_RESULT();
2701
2702         switch (tunnel_type) {
2703         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
2704                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2705                 bp->vxlan_port = port;
2706                 break;
2707         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
2708                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
2709                 bp->geneve_port = port;
2710                 break;
2711         default:
2712                 break;
2713         }
2714
2715         HWRM_UNLOCK();
2716
2717         return rc;
2718 }
2719
2720 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
2721                                 uint8_t tunnel_type)
2722 {
2723         struct hwrm_tunnel_dst_port_free_input req = {0};
2724         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
2725         int rc = 0;
2726
2727         HWRM_PREP(req, TUNNEL_DST_PORT_FREE);
2728
2729         req.tunnel_type = tunnel_type;
2730         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
2731         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2732
2733         HWRM_CHECK_RESULT();
2734         HWRM_UNLOCK();
2735
2736         return rc;
2737 }
2738
2739 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
2740                                         uint32_t flags)
2741 {
2742         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2743         struct hwrm_func_cfg_input req = {0};
2744         int rc;
2745
2746         HWRM_PREP(req, FUNC_CFG);
2747
2748         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2749         req.flags = rte_cpu_to_le_32(flags);
2750         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2751
2752         HWRM_CHECK_RESULT();
2753         HWRM_UNLOCK();
2754
2755         return rc;
2756 }
2757
2758 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
2759 {
2760         uint32_t *flag = flagp;
2761
2762         vnic->flags = *flag;
2763 }
2764
2765 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2766 {
2767         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2768 }
2769
2770 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
2771 {
2772         int rc = 0;
2773         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
2774         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
2775
2776         HWRM_PREP(req, FUNC_BUF_RGTR);
2777
2778         req.req_buf_num_pages = rte_cpu_to_le_16(1);
2779         req.req_buf_page_size = rte_cpu_to_le_16(
2780                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
2781         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
2782         req.req_buf_page_addr0 =
2783                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
2784         if (req.req_buf_page_addr0 == 0) {
2785                 PMD_DRV_LOG(ERR,
2786                         "unable to map buffer address to physical memory\n");
2787                 return -ENOMEM;
2788         }
2789
2790         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2791
2792         HWRM_CHECK_RESULT();
2793         HWRM_UNLOCK();
2794
2795         return rc;
2796 }
2797
2798 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
2799 {
2800         int rc = 0;
2801         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
2802         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
2803
2804         HWRM_PREP(req, FUNC_BUF_UNRGTR);
2805
2806         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2807
2808         HWRM_CHECK_RESULT();
2809         HWRM_UNLOCK();
2810
2811         return rc;
2812 }
2813
2814 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
2815 {
2816         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2817         struct hwrm_func_cfg_input req = {0};
2818         int rc;
2819
2820         HWRM_PREP(req, FUNC_CFG);
2821
2822         req.fid = rte_cpu_to_le_16(0xffff);
2823         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2824         req.enables = rte_cpu_to_le_32(
2825                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2826         req.async_event_cr = rte_cpu_to_le_16(
2827                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2828         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2829
2830         HWRM_CHECK_RESULT();
2831         HWRM_UNLOCK();
2832
2833         return rc;
2834 }
2835
2836 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
2837 {
2838         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2839         struct hwrm_func_vf_cfg_input req = {0};
2840         int rc;
2841
2842         HWRM_PREP(req, FUNC_VF_CFG);
2843
2844         req.enables = rte_cpu_to_le_32(
2845                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2846         req.async_event_cr = rte_cpu_to_le_16(
2847                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2848         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2849
2850         HWRM_CHECK_RESULT();
2851         HWRM_UNLOCK();
2852
2853         return rc;
2854 }
2855
2856 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
2857 {
2858         struct hwrm_func_cfg_input req = {0};
2859         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2860         uint16_t dflt_vlan, fid;
2861         uint32_t func_cfg_flags;
2862         int rc = 0;
2863
2864         HWRM_PREP(req, FUNC_CFG);
2865
2866         if (is_vf) {
2867                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
2868                 fid = bp->pf.vf_info[vf].fid;
2869                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
2870         } else {
2871                 fid = rte_cpu_to_le_16(0xffff);
2872                 func_cfg_flags = bp->pf.func_cfg_flags;
2873                 dflt_vlan = bp->vlan;
2874         }
2875
2876         req.flags = rte_cpu_to_le_32(func_cfg_flags);
2877         req.fid = rte_cpu_to_le_16(fid);
2878         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2879         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
2880
2881         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2882
2883         HWRM_CHECK_RESULT();
2884         HWRM_UNLOCK();
2885
2886         return rc;
2887 }
2888
2889 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
2890                         uint16_t max_bw, uint16_t enables)
2891 {
2892         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2893         struct hwrm_func_cfg_input req = {0};
2894         int rc;
2895
2896         HWRM_PREP(req, FUNC_CFG);
2897
2898         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2899         req.enables |= rte_cpu_to_le_32(enables);
2900         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2901         req.max_bw = rte_cpu_to_le_32(max_bw);
2902         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2903
2904         HWRM_CHECK_RESULT();
2905         HWRM_UNLOCK();
2906
2907         return rc;
2908 }
2909
2910 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
2911 {
2912         struct hwrm_func_cfg_input req = {0};
2913         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2914         int rc = 0;
2915
2916         HWRM_PREP(req, FUNC_CFG);
2917
2918         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2919         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2920         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2921         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
2922
2923         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2924
2925         HWRM_CHECK_RESULT();
2926         HWRM_UNLOCK();
2927
2928         return rc;
2929 }
2930
2931 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
2932                               void *encaped, size_t ec_size)
2933 {
2934         int rc = 0;
2935         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
2936         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2937
2938         if (ec_size > sizeof(req.encap_request))
2939                 return -1;
2940
2941         HWRM_PREP(req, REJECT_FWD_RESP);
2942
2943         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2944         memcpy(req.encap_request, encaped, ec_size);
2945
2946         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2947
2948         HWRM_CHECK_RESULT();
2949         HWRM_UNLOCK();
2950
2951         return rc;
2952 }
2953
2954 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
2955                                        struct ether_addr *mac)
2956 {
2957         struct hwrm_func_qcfg_input req = {0};
2958         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2959         int rc;
2960
2961         HWRM_PREP(req, FUNC_QCFG);
2962
2963         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2964         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2965
2966         HWRM_CHECK_RESULT();
2967
2968         memcpy(mac->addr_bytes, resp->mac_address, ETHER_ADDR_LEN);
2969
2970         HWRM_UNLOCK();
2971
2972         return rc;
2973 }
2974
2975 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
2976                             void *encaped, size_t ec_size)
2977 {
2978         int rc = 0;
2979         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
2980         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2981
2982         if (ec_size > sizeof(req.encap_request))
2983                 return -1;
2984
2985         HWRM_PREP(req, EXEC_FWD_RESP);
2986
2987         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2988         memcpy(req.encap_request, encaped, ec_size);
2989
2990         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2991
2992         HWRM_CHECK_RESULT();
2993         HWRM_UNLOCK();
2994
2995         return rc;
2996 }
2997
2998 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
2999                          struct rte_eth_stats *stats, uint8_t rx)
3000 {
3001         int rc = 0;
3002         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3003         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3004
3005         HWRM_PREP(req, STAT_CTX_QUERY);
3006
3007         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3008
3009         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3010
3011         HWRM_CHECK_RESULT();
3012
3013         if (rx) {
3014                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3015                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3016                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3017                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3018                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3019                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3020                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3021                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3022         } else {
3023                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3024                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3025                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3026                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3027                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3028                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3029                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->tx_err_pkts);
3030         }
3031
3032
3033         HWRM_UNLOCK();
3034
3035         return rc;
3036 }
3037
3038 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3039 {
3040         struct hwrm_port_qstats_input req = {0};
3041         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3042         struct bnxt_pf_info *pf = &bp->pf;
3043         int rc;
3044
3045         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
3046                 return 0;
3047
3048         HWRM_PREP(req, PORT_QSTATS);
3049
3050         req.port_id = rte_cpu_to_le_16(pf->port_id);
3051         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3052         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3053         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3054
3055         HWRM_CHECK_RESULT();
3056         HWRM_UNLOCK();
3057
3058         return rc;
3059 }
3060
3061 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3062 {
3063         struct hwrm_port_clr_stats_input req = {0};
3064         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3065         struct bnxt_pf_info *pf = &bp->pf;
3066         int rc;
3067
3068         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
3069                 return 0;
3070
3071         HWRM_PREP(req, PORT_CLR_STATS);
3072
3073         req.port_id = rte_cpu_to_le_16(pf->port_id);
3074         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3075
3076         HWRM_CHECK_RESULT();
3077         HWRM_UNLOCK();
3078
3079         return rc;
3080 }
3081
3082 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3083 {
3084         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3085         struct hwrm_port_led_qcaps_input req = {0};
3086         int rc;
3087
3088         if (BNXT_VF(bp))
3089                 return 0;
3090
3091         HWRM_PREP(req, PORT_LED_QCAPS);
3092         req.port_id = bp->pf.port_id;
3093         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3094
3095         HWRM_CHECK_RESULT();
3096
3097         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3098                 unsigned int i;
3099
3100                 bp->num_leds = resp->num_leds;
3101                 memcpy(bp->leds, &resp->led0_id,
3102                         sizeof(bp->leds[0]) * bp->num_leds);
3103                 for (i = 0; i < bp->num_leds; i++) {
3104                         struct bnxt_led_info *led = &bp->leds[i];
3105
3106                         uint16_t caps = led->led_state_caps;
3107
3108                         if (!led->led_group_id ||
3109                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3110                                 bp->num_leds = 0;
3111                                 break;
3112                         }
3113                 }
3114         }
3115
3116         HWRM_UNLOCK();
3117
3118         return rc;
3119 }
3120
3121 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3122 {
3123         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3124         struct hwrm_port_led_cfg_input req = {0};
3125         struct bnxt_led_cfg *led_cfg;
3126         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3127         uint16_t duration = 0;
3128         int rc, i;
3129
3130         if (!bp->num_leds || BNXT_VF(bp))
3131                 return -EOPNOTSUPP;
3132
3133         HWRM_PREP(req, PORT_LED_CFG);
3134
3135         if (led_on) {
3136                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3137                 duration = rte_cpu_to_le_16(500);
3138         }
3139         req.port_id = bp->pf.port_id;
3140         req.num_leds = bp->num_leds;
3141         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3142         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3143                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3144                 led_cfg->led_id = bp->leds[i].led_id;
3145                 led_cfg->led_state = led_state;
3146                 led_cfg->led_blink_on = duration;
3147                 led_cfg->led_blink_off = duration;
3148                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3149         }
3150
3151         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3152
3153         HWRM_CHECK_RESULT();
3154         HWRM_UNLOCK();
3155
3156         return rc;
3157 }
3158
3159 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3160                                uint32_t *length)
3161 {
3162         int rc;
3163         struct hwrm_nvm_get_dir_info_input req = {0};
3164         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3165
3166         HWRM_PREP(req, NVM_GET_DIR_INFO);
3167
3168         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3169
3170         HWRM_CHECK_RESULT();
3171         HWRM_UNLOCK();
3172
3173         if (!rc) {
3174                 *entries = rte_le_to_cpu_32(resp->entries);
3175                 *length = rte_le_to_cpu_32(resp->entry_length);
3176         }
3177         return rc;
3178 }
3179
3180 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3181 {
3182         int rc;
3183         uint32_t dir_entries;
3184         uint32_t entry_length;
3185         uint8_t *buf;
3186         size_t buflen;
3187         rte_iova_t dma_handle;
3188         struct hwrm_nvm_get_dir_entries_input req = {0};
3189         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3190
3191         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3192         if (rc != 0)
3193                 return rc;
3194
3195         *data++ = dir_entries;
3196         *data++ = entry_length;
3197         len -= 2;
3198         memset(data, 0xff, len);
3199
3200         buflen = dir_entries * entry_length;
3201         buf = rte_malloc("nvm_dir", buflen, 0);
3202         rte_mem_lock_page(buf);
3203         if (buf == NULL)
3204                 return -ENOMEM;
3205         dma_handle = rte_mem_virt2iova(buf);
3206         if (dma_handle == 0) {
3207                 PMD_DRV_LOG(ERR,
3208                         "unable to map response address to physical memory\n");
3209                 return -ENOMEM;
3210         }
3211         HWRM_PREP(req, NVM_GET_DIR_ENTRIES);
3212         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3213         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3214
3215         HWRM_CHECK_RESULT();
3216         HWRM_UNLOCK();
3217
3218         if (rc == 0)
3219                 memcpy(data, buf, len > buflen ? buflen : len);
3220
3221         rte_free(buf);
3222
3223         return rc;
3224 }
3225
3226 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3227                              uint32_t offset, uint32_t length,
3228                              uint8_t *data)
3229 {
3230         int rc;
3231         uint8_t *buf;
3232         rte_iova_t dma_handle;
3233         struct hwrm_nvm_read_input req = {0};
3234         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3235
3236         buf = rte_malloc("nvm_item", length, 0);
3237         rte_mem_lock_page(buf);
3238         if (!buf)
3239                 return -ENOMEM;
3240
3241         dma_handle = rte_mem_virt2iova(buf);
3242         if (dma_handle == 0) {
3243                 PMD_DRV_LOG(ERR,
3244                         "unable to map response address to physical memory\n");
3245                 return -ENOMEM;
3246         }
3247         HWRM_PREP(req, NVM_READ);
3248         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3249         req.dir_idx = rte_cpu_to_le_16(index);
3250         req.offset = rte_cpu_to_le_32(offset);
3251         req.len = rte_cpu_to_le_32(length);
3252         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3253         HWRM_CHECK_RESULT();
3254         HWRM_UNLOCK();
3255         if (rc == 0)
3256                 memcpy(data, buf, length);
3257
3258         rte_free(buf);
3259         return rc;
3260 }
3261
3262 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3263 {
3264         int rc;
3265         struct hwrm_nvm_erase_dir_entry_input req = {0};
3266         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3267
3268         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY);
3269         req.dir_idx = rte_cpu_to_le_16(index);
3270         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3271         HWRM_CHECK_RESULT();
3272         HWRM_UNLOCK();
3273
3274         return rc;
3275 }
3276
3277
3278 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3279                           uint16_t dir_ordinal, uint16_t dir_ext,
3280                           uint16_t dir_attr, const uint8_t *data,
3281                           size_t data_len)
3282 {
3283         int rc;
3284         struct hwrm_nvm_write_input req = {0};
3285         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3286         rte_iova_t dma_handle;
3287         uint8_t *buf;
3288
3289         HWRM_PREP(req, NVM_WRITE);
3290
3291         req.dir_type = rte_cpu_to_le_16(dir_type);
3292         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3293         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3294         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3295         req.dir_data_length = rte_cpu_to_le_32(data_len);
3296
3297         buf = rte_malloc("nvm_write", data_len, 0);
3298         rte_mem_lock_page(buf);
3299         if (!buf)
3300                 return -ENOMEM;
3301
3302         dma_handle = rte_mem_virt2iova(buf);
3303         if (dma_handle == 0) {
3304                 PMD_DRV_LOG(ERR,
3305                         "unable to map response address to physical memory\n");
3306                 return -ENOMEM;
3307         }
3308         memcpy(buf, data, data_len);
3309         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3310
3311         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3312
3313         HWRM_CHECK_RESULT();
3314         HWRM_UNLOCK();
3315
3316         rte_free(buf);
3317         return rc;
3318 }
3319
3320 static void
3321 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3322 {
3323         uint32_t *count = cbdata;
3324
3325         *count = *count + 1;
3326 }
3327
3328 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3329                                      struct bnxt_vnic_info *vnic __rte_unused)
3330 {
3331         return 0;
3332 }
3333
3334 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3335 {
3336         uint32_t count = 0;
3337
3338         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3339             &count, bnxt_vnic_count_hwrm_stub);
3340
3341         return count;
3342 }
3343
3344 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3345                                         uint16_t *vnic_ids)
3346 {
3347         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3348         struct hwrm_func_vf_vnic_ids_query_output *resp =
3349                                                 bp->hwrm_cmd_resp_addr;
3350         int rc;
3351
3352         /* First query all VNIC ids */
3353         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY);
3354
3355         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3356         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3357         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3358
3359         if (req.vnic_id_tbl_addr == 0) {
3360                 HWRM_UNLOCK();
3361                 PMD_DRV_LOG(ERR,
3362                 "unable to map VNIC ID table address to physical memory\n");
3363                 return -ENOMEM;
3364         }
3365         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3366         if (rc) {
3367                 HWRM_UNLOCK();
3368                 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
3369                 return -1;
3370         } else if (resp->error_code) {
3371                 rc = rte_le_to_cpu_16(resp->error_code);
3372                 HWRM_UNLOCK();
3373                 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query error %d\n", rc);
3374                 return -1;
3375         }
3376         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3377
3378         HWRM_UNLOCK();
3379
3380         return rc;
3381 }
3382
3383 /*
3384  * This function queries the VNIC IDs  for a specified VF. It then calls
3385  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3386  * Then it calls the hwrm_cb function to program this new vnic configuration.
3387  */
3388 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3389         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3390         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3391 {
3392         struct bnxt_vnic_info vnic;
3393         int rc = 0;
3394         int i, num_vnic_ids;
3395         uint16_t *vnic_ids;
3396         size_t vnic_id_sz;
3397         size_t sz;
3398
3399         /* First query all VNIC ids */
3400         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3401         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3402                         RTE_CACHE_LINE_SIZE);
3403         if (vnic_ids == NULL) {
3404                 rc = -ENOMEM;
3405                 return rc;
3406         }
3407         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3408                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3409
3410         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3411
3412         if (num_vnic_ids < 0)
3413                 return num_vnic_ids;
3414
3415         /* Retrieve VNIC, update bd_stall then update */
3416
3417         for (i = 0; i < num_vnic_ids; i++) {
3418                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3419                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3420                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3421                 if (rc)
3422                         break;
3423                 if (vnic.mru <= 4)      /* Indicates unallocated */
3424                         continue;
3425
3426                 vnic_cb(&vnic, cbdata);
3427
3428                 rc = hwrm_cb(bp, &vnic);
3429                 if (rc)
3430                         break;
3431         }
3432
3433         rte_free(vnic_ids);
3434
3435         return rc;
3436 }
3437
3438 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3439                                               bool on)
3440 {
3441         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3442         struct hwrm_func_cfg_input req = {0};
3443         int rc;
3444
3445         HWRM_PREP(req, FUNC_CFG);
3446
3447         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3448         req.enables |= rte_cpu_to_le_32(
3449                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3450         req.vlan_antispoof_mode = on ?
3451                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3452                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3453         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3454
3455         HWRM_CHECK_RESULT();
3456         HWRM_UNLOCK();
3457
3458         return rc;
3459 }
3460
3461 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3462 {
3463         struct bnxt_vnic_info vnic;
3464         uint16_t *vnic_ids;
3465         size_t vnic_id_sz;
3466         int num_vnic_ids, i;
3467         size_t sz;
3468         int rc;
3469
3470         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3471         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3472                         RTE_CACHE_LINE_SIZE);
3473         if (vnic_ids == NULL) {
3474                 rc = -ENOMEM;
3475                 return rc;
3476         }
3477
3478         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3479                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3480
3481         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3482         if (rc <= 0)
3483                 goto exit;
3484         num_vnic_ids = rc;
3485
3486         /*
3487          * Loop through to find the default VNIC ID.
3488          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3489          * by sending the hwrm_func_qcfg command to the firmware.
3490          */
3491         for (i = 0; i < num_vnic_ids; i++) {
3492                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3493                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3494                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3495                                         bp->pf.first_vf_id + vf);
3496                 if (rc)
3497                         goto exit;
3498                 if (vnic.func_default) {
3499                         rte_free(vnic_ids);
3500                         return vnic.fw_vnic_id;
3501                 }
3502         }
3503         /* Could not find a default VNIC. */
3504         PMD_DRV_LOG(ERR, "No default VNIC\n");
3505 exit:
3506         rte_free(vnic_ids);
3507         return -1;
3508 }
3509
3510 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3511                          uint16_t dst_id,
3512                          struct bnxt_filter_info *filter)
3513 {
3514         int rc = 0;
3515         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3516         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3517         uint32_t enables = 0;
3518
3519         if (filter->fw_em_filter_id != UINT64_MAX)
3520                 bnxt_hwrm_clear_em_filter(bp, filter);
3521
3522         HWRM_PREP(req, CFA_EM_FLOW_ALLOC);
3523
3524         req.flags = rte_cpu_to_le_32(filter->flags);
3525
3526         enables = filter->enables |
3527               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3528         req.dst_id = rte_cpu_to_le_16(dst_id);
3529
3530         if (filter->ip_addr_type) {
3531                 req.ip_addr_type = filter->ip_addr_type;
3532                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3533         }
3534         if (enables &
3535             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3536                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3537         if (enables &
3538             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3539                 memcpy(req.src_macaddr, filter->src_macaddr,
3540                        ETHER_ADDR_LEN);
3541         if (enables &
3542             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3543                 memcpy(req.dst_macaddr, filter->dst_macaddr,
3544                        ETHER_ADDR_LEN);
3545         if (enables &
3546             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3547                 req.ovlan_vid = filter->l2_ovlan;
3548         if (enables &
3549             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3550                 req.ivlan_vid = filter->l2_ivlan;
3551         if (enables &
3552             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3553                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3554         if (enables &
3555             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3556                 req.ip_protocol = filter->ip_protocol;
3557         if (enables &
3558             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3559                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3560         if (enables &
3561             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3562                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3563         if (enables &
3564             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3565                 req.src_port = rte_cpu_to_be_16(filter->src_port);
3566         if (enables &
3567             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3568                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3569         if (enables &
3570             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3571                 req.mirror_vnic_id = filter->mirror_vnic_id;
3572
3573         req.enables = rte_cpu_to_le_32(enables);
3574
3575         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3576
3577         HWRM_CHECK_RESULT();
3578
3579         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3580         HWRM_UNLOCK();
3581
3582         return rc;
3583 }
3584
3585 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3586 {
3587         int rc = 0;
3588         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3589         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3590
3591         if (filter->fw_em_filter_id == UINT64_MAX)
3592                 return 0;
3593
3594         PMD_DRV_LOG(ERR, "Clear EM filter\n");
3595         HWRM_PREP(req, CFA_EM_FLOW_FREE);
3596
3597         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
3598
3599         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3600
3601         HWRM_CHECK_RESULT();
3602         HWRM_UNLOCK();
3603
3604         filter->fw_em_filter_id = UINT64_MAX;
3605         filter->fw_l2_filter_id = UINT64_MAX;
3606
3607         return 0;
3608 }
3609
3610 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
3611                          uint16_t dst_id,
3612                          struct bnxt_filter_info *filter)
3613 {
3614         int rc = 0;
3615         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
3616         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3617                                                 bp->hwrm_cmd_resp_addr;
3618         uint32_t enables = 0;
3619
3620         if (filter->fw_ntuple_filter_id != UINT64_MAX)
3621                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
3622
3623         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC);
3624
3625         req.flags = rte_cpu_to_le_32(filter->flags);
3626
3627         enables = filter->enables |
3628               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
3629         req.dst_id = rte_cpu_to_le_16(dst_id);
3630
3631
3632         if (filter->ip_addr_type) {
3633                 req.ip_addr_type = filter->ip_addr_type;
3634                 enables |=
3635                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3636         }
3637         if (enables &
3638             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3639                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3640         if (enables &
3641             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3642                 memcpy(req.src_macaddr, filter->src_macaddr,
3643                        ETHER_ADDR_LEN);
3644         //if (enables &
3645             //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
3646                 //memcpy(req.dst_macaddr, filter->dst_macaddr,
3647                        //ETHER_ADDR_LEN);
3648         if (enables &
3649             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
3650                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3651         if (enables &
3652             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3653                 req.ip_protocol = filter->ip_protocol;
3654         if (enables &
3655             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3656                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
3657         if (enables &
3658             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
3659                 req.src_ipaddr_mask[0] =
3660                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
3661         if (enables &
3662             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
3663                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
3664         if (enables &
3665             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
3666                 req.dst_ipaddr_mask[0] =
3667                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
3668         if (enables &
3669             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
3670                 req.src_port = rte_cpu_to_le_16(filter->src_port);
3671         if (enables &
3672             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
3673                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
3674         if (enables &
3675             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
3676                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
3677         if (enables &
3678             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
3679                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
3680         if (enables &
3681             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3682                 req.mirror_vnic_id = filter->mirror_vnic_id;
3683
3684         req.enables = rte_cpu_to_le_32(enables);
3685
3686         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3687
3688         HWRM_CHECK_RESULT();
3689
3690         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
3691         HWRM_UNLOCK();
3692
3693         return rc;
3694 }
3695
3696 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
3697                                 struct bnxt_filter_info *filter)
3698 {
3699         int rc = 0;
3700         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
3701         struct hwrm_cfa_ntuple_filter_free_output *resp =
3702                                                 bp->hwrm_cmd_resp_addr;
3703
3704         if (filter->fw_ntuple_filter_id == UINT64_MAX)
3705                 return 0;
3706
3707         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE);
3708
3709         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
3710
3711         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3712
3713         HWRM_CHECK_RESULT();
3714         HWRM_UNLOCK();
3715
3716         filter->fw_ntuple_filter_id = UINT64_MAX;
3717         filter->fw_l2_filter_id = UINT64_MAX;
3718
3719         return 0;
3720 }
3721
3722 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3723 {
3724         unsigned int rss_idx, fw_idx, i;
3725
3726         if (vnic->rss_table && vnic->hash_type) {
3727                 /*
3728                  * Fill the RSS hash & redirection table with
3729                  * ring group ids for all VNICs
3730                  */
3731                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
3732                         rss_idx++, fw_idx++) {
3733                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
3734                                 fw_idx %= bp->rx_cp_nr_rings;
3735                                 if (vnic->fw_grp_ids[fw_idx] !=
3736                                     INVALID_HW_RING_ID)
3737                                         break;
3738                                 fw_idx++;
3739                         }
3740                         if (i == bp->rx_cp_nr_rings)
3741                                 return 0;
3742                         vnic->rss_table[rss_idx] =
3743                                 vnic->fw_grp_ids[fw_idx];
3744                 }
3745                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
3746         }
3747         return 0;
3748 }