drivers/net/bnxt/bnxt_hwrm.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) Broadcom Limited.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Broadcom Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <unistd.h>
  35
  36 #include <rte_byteorder.h>
  37 #include <rte_common.h>
  38 #include <rte_cycles.h>
  39 #include <rte_malloc.h>
  40 #include <rte_memzone.h>
  41 #include <rte_version.h>
  42
  43 #include "bnxt.h"
  44 #include "bnxt_cpr.h"
  45 #include "bnxt_filter.h"
  46 #include "bnxt_hwrm.h"
  47 #include "bnxt_rxq.h"
  48 #include "bnxt_rxr.h"
  49 #include "bnxt_ring.h"
  50 #include "bnxt_txq.h"
  51 #include "bnxt_txr.h"
  52 #include "bnxt_vnic.h"
  53 #include "hsi_struct_def_dpdk.h"
  54
  55 #include <rte_io.h>
  56
  57 #define HWRM_CMD_TIMEOUT                10000
  58
  59 struct bnxt_plcmodes_cfg {
  60         uint32_t        flags;
  61         uint16_t        jumbo_thresh;
  62         uint16_t        hds_offset;
  63         uint16_t        hds_threshold;
  64 };
  65
  66 static int page_getenum(size_t size)
  67 {
  68         if (size <= 1 << 4)
  69                 return 4;
  70         if (size <= 1 << 12)
  71                 return 12;
  72         if (size <= 1 << 13)
  73                 return 13;
  74         if (size <= 1 << 16)
  75                 return 16;
  76         if (size <= 1 << 21)
  77                 return 21;
  78         if (size <= 1 << 22)
  79                 return 22;
  80         if (size <= 1 << 30)
  81                 return 30;
  82         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  83         return sizeof(void *) * 8 - 1;
  84 }
  85
  86 static int page_roundup(size_t size)
  87 {
  88         return 1 << page_getenum(size);
  89 }
  90
  91 /*
  92  * HWRM Functions (sent to HWRM)
  93  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  94  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  95  * command was failed by the ChiMP.
  96  */
  97
  98 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  99                                         uint32_t msg_len)
 100 {
 101         unsigned int i;
 102         struct input *req = msg;
 103         struct output *resp = bp->hwrm_cmd_resp_addr;
 104         uint32_t *data = msg;
 105         uint8_t *bar;
 106         uint8_t *valid;
 107         uint16_t max_req_len = bp->max_req_len;
 108         struct hwrm_short_input short_input = { 0 };
 109
 110         if (bp->flags & BNXT_FLAG_SHORT_CMD) {
 111                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 112
 113                 memset(short_cmd_req, 0, bp->max_req_len);
 114                 memcpy(short_cmd_req, req, msg_len);
 115
 116                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 117                 short_input.signature = rte_cpu_to_le_16(
 118                                         HWRM_SHORT_REQ_SIGNATURE_SHORT_CMD);
 119                 short_input.size = rte_cpu_to_le_16(msg_len);
 120                 short_input.req_addr =
 121                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 122
 123                 data = (uint32_t *)&short_input;
 124                 msg_len = sizeof(short_input);
 125
 126                 /* Sync memory write before updating doorbell */
 127                 rte_wmb();
 128
 129                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 130         }
 131
 132         /* Write request msg to hwrm channel */
 133         for (i = 0; i < msg_len; i += 4) {
 134                 bar = (uint8_t *)bp->bar0 + i;
 135                 rte_write32(*data, bar);
 136                 data++;
 137         }
 138
 139         /* Zero the rest of the request space */
 140         for (; i < max_req_len; i += 4) {
 141                 bar = (uint8_t *)bp->bar0 + i;
 142                 rte_write32(0, bar);
 143         }
 144
 145         /* Ring channel doorbell */
 146         bar = (uint8_t *)bp->bar0 + 0x100;
 147         rte_write32(1, bar);
 148
 149         /* Poll for the valid bit */
 150         for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
 151                 /* Sanity check on the resp->resp_len */
 152                 rte_rmb();
 153                 if (resp->resp_len && resp->resp_len <=
 154                                 bp->max_resp_len) {
 155                         /* Last byte of resp contains the valid key */
 156                         valid = (uint8_t *)resp + resp->resp_len - 1;
 157                         if (*valid == HWRM_RESP_VALID_KEY)
 158                                 break;
 159                 }
 160                 rte_delay_us(600);
 161         }
 162
 163         if (i >= HWRM_CMD_TIMEOUT) {
 164                 PMD_DRV_LOG(ERR, "Error sending msg 0x%04x\n",
 165                         req->req_type);
 166                 goto err_ret;
 167         }
 168         return 0;
 169
 170 err_ret:
 171         return -1;
 172 }
 173
 174 /*
 175  * HWRM_PREP() should be used to prepare *ALL* HWRM commands.  It grabs the
 176  * spinlock, and does initial processing.
 177  *
 178  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 179  * releases the spinlock only if it returns.  If the regular int return codes
 180  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 181  * directly, rather it should be copied and modified to suit the function.
 182  *
 183  * HWRM_UNLOCK() must be called after all response processing is completed.
 184  */
 185 #define HWRM_PREP(req, type) do { \
 186         rte_spinlock_lock(&bp->hwrm_lock); \
 187         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 188         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 189         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 190         req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 191         req.target_id = rte_cpu_to_le_16(0xffff); \
 192         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 193 } while (0)
 194
 195 #define HWRM_CHECK_RESULT() do {\
 196         if (rc) { \
 197                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 198                 rte_spinlock_unlock(&bp->hwrm_lock); \
 199                 return rc; \
 200         } \
 201         if (resp->error_code) { \
 202                 rc = rte_le_to_cpu_16(resp->error_code); \
 203                 if (resp->resp_len >= 16) { \
 204                         struct hwrm_err_output *tmp_hwrm_err_op = \
 205                                                 (void *)resp; \
 206                         PMD_DRV_LOG(ERR, \
 207                                 "error %d:%d:%08x:%04x\n", \
 208                                 rc, tmp_hwrm_err_op->cmd_err, \
 209                                 rte_le_to_cpu_32(\
 210                                         tmp_hwrm_err_op->opaque_0), \
 211                                 rte_le_to_cpu_16(\
 212                                         tmp_hwrm_err_op->opaque_1)); \
 213                 } else { \
 214                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 215                 } \
 216                 rte_spinlock_unlock(&bp->hwrm_lock); \
 217                 return rc; \
 218         } \
 219 } while (0)
 220
 221 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 222
 223 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 224 {
 225         int rc = 0;
 226         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 227         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 228
 229         HWRM_PREP(req, CFA_L2_SET_RX_MASK);
 230         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 231         req.mask = 0;
 232
 233         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 234
 235         HWRM_CHECK_RESULT();
 236         HWRM_UNLOCK();
 237
 238         return rc;
 239 }
 240
 241 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 242                                  struct bnxt_vnic_info *vnic,
 243                                  uint16_t vlan_count,
 244                                  struct bnxt_vlan_table_entry *vlan_table)
 245 {
 246         int rc = 0;
 247         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 248         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 249         uint32_t mask = 0;
 250
 251         HWRM_PREP(req, CFA_L2_SET_RX_MASK);
 252         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 253
 254         /* FIXME add multicast flag, when multicast adding options is supported
 255          * by ethtool.
 256          */
 257         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 258                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 259         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 260                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 261         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 262                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 263         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 264                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 265         if (vnic->flags & BNXT_VNIC_INFO_MCAST)
 266                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 267         if (vnic->mc_addr_cnt) {
 268                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 269                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 270                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 271         }
 272         if (vlan_table) {
 273                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 274                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 275                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 276                          rte_mem_virt2iova(vlan_table));
 277                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 278         }
 279         req.mask = rte_cpu_to_le_32(mask);
 280
 281         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 282
 283         HWRM_CHECK_RESULT();
 284         HWRM_UNLOCK();
 285
 286         return rc;
 287 }
 288
 289 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 290                         uint16_t vlan_count,
 291                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 292 {
 293         int rc = 0;
 294         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 295         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 296                                                 bp->hwrm_cmd_resp_addr;
 297
 298         /*
 299          * Older HWRM versions did not support this command, and the set_rx_mask
 300          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 301          * removed from set_rx_mask call, and this command was added.
 302          *
 303          * This command is also present from 1.7.8.11 and higher,
 304          * as well as 1.7.8.0
 305          */
 306         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 307                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 308                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 309                                         (11)))
 310                                 return 0;
 311                 }
 312         }
 313         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG);
 314         req.fid = rte_cpu_to_le_16(fid);
 315
 316         req.vlan_tag_mask_tbl_addr =
 317                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 318         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 319
 320         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 321
 322         HWRM_CHECK_RESULT();
 323         HWRM_UNLOCK();
 324
 325         return rc;
 326 }
 327
 328 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 329                            struct bnxt_filter_info *filter)
 330 {
 331         int rc = 0;
 332         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 333         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 334
 335         if (filter->fw_l2_filter_id == UINT64_MAX)
 336                 return 0;
 337
 338         HWRM_PREP(req, CFA_L2_FILTER_FREE);
 339
 340         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 341
 342         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 343
 344         HWRM_CHECK_RESULT();
 345         HWRM_UNLOCK();
 346
 347         filter->fw_l2_filter_id = -1;
 348
 349         return 0;
 350 }
 351
 352 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 353                          uint16_t dst_id,
 354                          struct bnxt_filter_info *filter)
 355 {
 356         int rc = 0;
 357         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 358         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 359         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 360         const struct rte_eth_vmdq_rx_conf *conf =
 361                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 362         uint32_t enables = 0;
 363         uint16_t j = dst_id - 1;
 364
 365         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 366         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 367             conf->pool_map[j].pools & (1UL << j)) {
 368                 PMD_DRV_LOG(DEBUG,
 369                         "Add vlan %u to vmdq pool %u\n",
 370                         conf->pool_map[j].vlan_id, j);
 371
 372                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 373                 filter->enables |=
 374                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 375                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 376         }
 377
 378         if (filter->fw_l2_filter_id != UINT64_MAX)
 379                 bnxt_hwrm_clear_l2_filter(bp, filter);
 380
 381         HWRM_PREP(req, CFA_L2_FILTER_ALLOC);
 382
 383         req.flags = rte_cpu_to_le_32(filter->flags);
 384
 385         enables = filter->enables |
 386               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 387         req.dst_id = rte_cpu_to_le_16(dst_id);
 388
 389         if (enables &
 390             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 391                 memcpy(req.l2_addr, filter->l2_addr,
 392                        ETHER_ADDR_LEN);
 393         if (enables &
 394             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 395                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 396                        ETHER_ADDR_LEN);
 397         if (enables &
 398             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 399                 req.l2_ovlan = filter->l2_ovlan;
 400         if (enables &
 401             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 402                 req.l2_ovlan = filter->l2_ivlan;
 403         if (enables &
 404             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 405                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 406         if (enables &
 407             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 408                 req.l2_ovlan_mask = filter->l2_ivlan_mask;
 409         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 410                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 411         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 412                 req.src_type = filter->src_type;
 413
 414         req.enables = rte_cpu_to_le_32(enables);
 415
 416         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 417
 418         HWRM_CHECK_RESULT();
 419
 420         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 421         HWRM_UNLOCK();
 422
 423         return rc;
 424 }
 425
 426 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 427 {
 428         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 429         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 430         uint32_t flags = 0;
 431         int rc;
 432
 433         if (!ptp)
 434                 return 0;
 435
 436         HWRM_PREP(req, PORT_MAC_CFG);
 437
 438         if (ptp->rx_filter)
 439                 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 440         else
 441                 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 442         if (ptp->tx_tstamp_en)
 443                 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 444         else
 445                 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 446         req.flags = rte_cpu_to_le_32(flags);
 447         req.enables =
 448         rte_cpu_to_le_32(PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 449         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 450
 451         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 452         HWRM_UNLOCK();
 453
 454         return rc;
 455 }
 456
 457 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 458 {
 459         int rc = 0;
 460         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 461         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 462         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 463
 464 /*      if (bp->hwrm_spec_code < 0x10801 || ptp)  TBD  */
 465         if (ptp)
 466                 return 0;
 467
 468         HWRM_PREP(req, PORT_MAC_PTP_QCFG);
 469
 470         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 471
 472         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 473
 474         HWRM_CHECK_RESULT();
 475
 476         if (!(resp->flags & PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS))
 477                 return 0;
 478
 479         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 480         if (!ptp)
 481                 return -ENOMEM;
 482
 483         ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 484                 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 485         ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 486                 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 487         ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 488                 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 489         ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 490                 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 491         ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 492                 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 493         ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 494                 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 495         ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 496                 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 497         ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 498                 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 499         ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 500                 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 501
 502         ptp->bp = bp;
 503         bp->ptp_cfg = ptp;
 504
 505         return 0;
 506 }
 507
 508 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 509 {
 510         int rc = 0;
 511         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 512         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 513         uint16_t new_max_vfs;
 514         uint32_t flags;
 515         int i;
 516
 517         HWRM_PREP(req, FUNC_QCAPS);
 518
 519         req.fid = rte_cpu_to_le_16(0xffff);
 520
 521         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 522
 523         HWRM_CHECK_RESULT();
 524
 525         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 526         flags = rte_le_to_cpu_32(resp->flags);
 527         if (BNXT_PF(bp)) {
 528                 bp->pf.port_id = resp->port_id;
 529                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 530                 new_max_vfs = bp->pdev->max_vfs;
 531                 if (new_max_vfs != bp->pf.max_vfs) {
 532                         if (bp->pf.vf_info)
 533                                 rte_free(bp->pf.vf_info);
 534                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 535                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 536                         bp->pf.max_vfs = new_max_vfs;
 537                         for (i = 0; i < new_max_vfs; i++) {
 538                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 539                                 bp->pf.vf_info[i].vlan_table =
 540                                         rte_zmalloc("VF VLAN table",
 541                                                     getpagesize(),
 542                                                     getpagesize());
 543                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 544                                         PMD_DRV_LOG(ERR,
 545                                         "Fail to alloc VLAN table for VF %d\n",
 546                                         i);
 547                                 else
 548                                         rte_mem_lock_page(
 549                                                 bp->pf.vf_info[i].vlan_table);
 550                                 bp->pf.vf_info[i].vlan_as_table =
 551                                         rte_zmalloc("VF VLAN AS table",
 552                                                     getpagesize(),
 553                                                     getpagesize());
 554                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 555                                         PMD_DRV_LOG(ERR,
 556                                         "Alloc VLAN AS table for VF %d fail\n",
 557                                         i);
 558                                 else
 559                                         rte_mem_lock_page(
 560                                                bp->pf.vf_info[i].vlan_as_table);
 561                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 562                         }
 563                 }
 564         }
 565
 566         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 567         memcpy(bp->dflt_mac_addr, &resp->mac_address, ETHER_ADDR_LEN);
 568         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 569         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 570         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 571         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 572         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 573         /* TODO: For now, do not support VMDq/RFS on VFs. */
 574         if (BNXT_PF(bp)) {
 575                 if (bp->pf.max_vfs)
 576                         bp->max_vnics = 1;
 577                 else
 578                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 579         } else {
 580                 bp->max_vnics = 1;
 581         }
 582         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 583         if (BNXT_PF(bp)) {
 584                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 585                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 586                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 587                         PMD_DRV_LOG(INFO, "PTP SUPPORTED\n");
 588                         HWRM_UNLOCK();
 589                         bnxt_hwrm_ptp_qcfg(bp);
 590                 }
 591         }
 592
 593         HWRM_UNLOCK();
 594
 595         return rc;
 596 }
 597
 598 int bnxt_hwrm_func_reset(struct bnxt *bp)
 599 {
 600         int rc = 0;
 601         struct hwrm_func_reset_input req = {.req_type = 0 };
 602         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 603
 604         HWRM_PREP(req, FUNC_RESET);
 605
 606         req.enables = rte_cpu_to_le_32(0);
 607
 608         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 609
 610         HWRM_CHECK_RESULT();
 611         HWRM_UNLOCK();
 612
 613         return rc;
 614 }
 615
 616 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 617 {
 618         int rc;
 619         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 620         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 621
 622         if (bp->flags & BNXT_FLAG_REGISTERED)
 623                 return 0;
 624
 625         HWRM_PREP(req, FUNC_DRV_RGTR);
 626         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 627                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 628         req.ver_maj = RTE_VER_YEAR;
 629         req.ver_min = RTE_VER_MONTH;
 630         req.ver_upd = RTE_VER_MINOR;
 631
 632         if (BNXT_PF(bp)) {
 633                 req.enables |= rte_cpu_to_le_32(
 634                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_INPUT_FWD);
 635                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 636                        RTE_MIN(sizeof(req.vf_req_fwd),
 637                                sizeof(bp->pf.vf_req_fwd)));
 638         }
 639
 640         req.async_event_fwd[0] |=
 641                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 642                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 643                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE);
 644         req.async_event_fwd[1] |=
 645                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 646                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 647
 648         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 649
 650         HWRM_CHECK_RESULT();
 651         HWRM_UNLOCK();
 652
 653         bp->flags |= BNXT_FLAG_REGISTERED;
 654
 655         return rc;
 656 }
 657
 658 int bnxt_hwrm_ver_get(struct bnxt *bp)
 659 {
 660         int rc = 0;
 661         struct hwrm_ver_get_input req = {.req_type = 0 };
 662         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 663         uint32_t my_version;
 664         uint32_t fw_version;
 665         uint16_t max_resp_len;
 666         char type[RTE_MEMZONE_NAMESIZE];
 667         uint32_t dev_caps_cfg;
 668
 669         bp->max_req_len = HWRM_MAX_REQ_LEN;
 670         HWRM_PREP(req, VER_GET);
 671
 672         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 673         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 674         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 675
 676         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 677
 678         HWRM_CHECK_RESULT();
 679
 680         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 681                 resp->hwrm_intf_maj, resp->hwrm_intf_min,
 682                 resp->hwrm_intf_upd,
 683                 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
 684         bp->fw_ver = (resp->hwrm_fw_maj << 24) | (resp->hwrm_fw_min << 16) |
 685                         (resp->hwrm_fw_bld << 8) | resp->hwrm_fw_rsvd;
 686         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 687                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 688
 689         my_version = HWRM_VERSION_MAJOR << 16;
 690         my_version |= HWRM_VERSION_MINOR << 8;
 691         my_version |= HWRM_VERSION_UPDATE;
 692
 693         fw_version = resp->hwrm_intf_maj << 16;
 694         fw_version |= resp->hwrm_intf_min << 8;
 695         fw_version |= resp->hwrm_intf_upd;
 696
 697         if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
 698                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 699                 rc = -EINVAL;
 700                 goto error;
 701         }
 702
 703         if (my_version != fw_version) {
 704                 PMD_DRV_LOG(INFO, "BNXT Driver/HWRM API mismatch.\n");
 705                 if (my_version < fw_version) {
 706                         PMD_DRV_LOG(INFO,
 707                                 "Firmware API version is newer than driver.\n");
 708                         PMD_DRV_LOG(INFO,
 709                                 "The driver may be missing features.\n");
 710                 } else {
 711                         PMD_DRV_LOG(INFO,
 712                                 "Firmware API version is older than driver.\n");
 713                         PMD_DRV_LOG(INFO,
 714                                 "Not all driver features may be functional.\n");
 715                 }
 716         }
 717
 718         if (bp->max_req_len > resp->max_req_win_len) {
 719                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
 720                 rc = -EINVAL;
 721         }
 722         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 723         max_resp_len = resp->max_resp_len;
 724         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 725
 726         if (bp->max_resp_len != max_resp_len) {
 727                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 728                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 729                         bp->pdev->addr.devid, bp->pdev->addr.function);
 730
 731                 rte_free(bp->hwrm_cmd_resp_addr);
 732
 733                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 734                 if (bp->hwrm_cmd_resp_addr == NULL) {
 735                         rc = -ENOMEM;
 736                         goto error;
 737                 }
 738                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
 739                 bp->hwrm_cmd_resp_dma_addr =
 740                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
 741                 if (bp->hwrm_cmd_resp_dma_addr == 0) {
 742                         PMD_DRV_LOG(ERR,
 743                         "Unable to map response buffer to physical memory.\n");
 744                         rc = -ENOMEM;
 745                         goto error;
 746                 }
 747                 bp->max_resp_len = max_resp_len;
 748         }
 749
 750         if ((dev_caps_cfg &
 751                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 752             (dev_caps_cfg &
 753              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_INPUTUIRED)) {
 754                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
 755
 756                 rte_free(bp->hwrm_short_cmd_req_addr);
 757
 758                 bp->hwrm_short_cmd_req_addr = rte_malloc(type,
 759                                                         bp->max_req_len, 0);
 760                 if (bp->hwrm_short_cmd_req_addr == NULL) {
 761                         rc = -ENOMEM;
 762                         goto error;
 763                 }
 764                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
 765                 bp->hwrm_short_cmd_req_dma_addr =
 766                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
 767                 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
 768                         rte_free(bp->hwrm_short_cmd_req_addr);
 769                         PMD_DRV_LOG(ERR,
 770                                 "Unable to map buffer to physical memory.\n");
 771                         rc = -ENOMEM;
 772                         goto error;
 773                 }
 774
 775                 bp->flags |= BNXT_FLAG_SHORT_CMD;
 776         }
 777
 778 error:
 779         HWRM_UNLOCK();
 780         return rc;
 781 }
 782
 783 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
 784 {
 785         int rc;
 786         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
 787         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
 788
 789         if (!(bp->flags & BNXT_FLAG_REGISTERED))
 790                 return 0;
 791
 792         HWRM_PREP(req, FUNC_DRV_UNRGTR);
 793         req.flags = flags;
 794
 795         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 796
 797         HWRM_CHECK_RESULT();
 798         HWRM_UNLOCK();
 799
 800         bp->flags &= ~BNXT_FLAG_REGISTERED;
 801
 802         return rc;
 803 }
 804
 805 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
 806 {
 807         int rc = 0;
 808         struct hwrm_port_phy_cfg_input req = {0};
 809         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 810         uint32_t enables = 0;
 811
 812         HWRM_PREP(req, PORT_PHY_CFG);
 813
 814         if (conf->link_up) {
 815                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
 816                 if (bp->link_info.auto_mode && conf->link_speed) {
 817                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
 818                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
 819                 }
 820
 821                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
 822                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
 823                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
 824                 /*
 825                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
 826                  * any auto mode, even "none".
 827                  */
 828                 if (!conf->link_speed) {
 829                         /* No speeds specified. Enable AutoNeg - all speeds */
 830                         req.auto_mode =
 831                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
 832                 }
 833                 /* AutoNeg - Advertise speeds specified. */
 834                 if (conf->auto_link_speed_mask) {
 835                         req.auto_mode =
 836                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
 837                         req.auto_link_speed_mask =
 838                                 conf->auto_link_speed_mask;
 839                         enables |=
 840                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
 841                 }
 842
 843                 req.auto_duplex = conf->duplex;
 844                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
 845                 req.auto_pause = conf->auto_pause;
 846                 req.force_pause = conf->force_pause;
 847                 /* Set force_pause if there is no auto or if there is a force */
 848                 if (req.auto_pause && !req.force_pause)
 849                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
 850                 else
 851                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
 852
 853                 req.enables = rte_cpu_to_le_32(enables);
 854         } else {
 855                 req.flags =
 856                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
 857                 PMD_DRV_LOG(INFO, "Force Link Down\n");
 858         }
 859
 860         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 861
 862         HWRM_CHECK_RESULT();
 863         HWRM_UNLOCK();
 864
 865         return rc;
 866 }
 867
 868 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
 869                                    struct bnxt_link_info *link_info)
 870 {
 871         int rc = 0;
 872         struct hwrm_port_phy_qcfg_input req = {0};
 873         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 874
 875         HWRM_PREP(req, PORT_PHY_QCFG);
 876
 877         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 878
 879         HWRM_CHECK_RESULT();
 880
 881         link_info->phy_link_status = resp->link;
 882         link_info->link_up =
 883                 (link_info->phy_link_status ==
 884                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
 885         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
 886         link_info->duplex = resp->duplex_cfg;
 887         link_info->pause = resp->pause;
 888         link_info->auto_pause = resp->auto_pause;
 889         link_info->force_pause = resp->force_pause;
 890         link_info->auto_mode = resp->auto_mode;
 891         link_info->phy_type = resp->phy_type;
 892         link_info->media_type = resp->media_type;
 893
 894         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
 895         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
 896         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
 897         link_info->phy_ver[0] = resp->phy_maj;
 898         link_info->phy_ver[1] = resp->phy_min;
 899         link_info->phy_ver[2] = resp->phy_bld;
 900
 901         HWRM_UNLOCK();
 902
 903         return rc;
 904 }
 905
 906 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
 907 {
 908         int rc = 0;
 909         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
 910         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
 911
 912         HWRM_PREP(req, QUEUE_QPORTCFG);
 913
 914         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 915
 916         HWRM_CHECK_RESULT();
 917
 918 #define GET_QUEUE_INFO(x) \
 919         bp->cos_queue[x].id = resp->queue_id##x; \
 920         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
 921
 922         GET_QUEUE_INFO(0);
 923         GET_QUEUE_INFO(1);
 924         GET_QUEUE_INFO(2);
 925         GET_QUEUE_INFO(3);
 926         GET_QUEUE_INFO(4);
 927         GET_QUEUE_INFO(5);
 928         GET_QUEUE_INFO(6);
 929         GET_QUEUE_INFO(7);
 930
 931         HWRM_UNLOCK();
 932
 933         return rc;
 934 }
 935
 936 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
 937                          struct bnxt_ring *ring,
 938                          uint32_t ring_type, uint32_t map_index,
 939                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
 940 {
 941         int rc = 0;
 942         uint32_t enables = 0;
 943         struct hwrm_ring_alloc_input req = {.req_type = 0 };
 944         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 945
 946         HWRM_PREP(req, RING_ALLOC);
 947
 948         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
 949         req.fbo = rte_cpu_to_le_32(0);
 950         /* Association of ring index with doorbell index */
 951         req.logical_id = rte_cpu_to_le_16(map_index);
 952         req.length = rte_cpu_to_le_32(ring->ring_size);
 953
 954         switch (ring_type) {
 955         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
 956                 req.queue_id = bp->cos_queue[0].id;
 957                 /* FALLTHROUGH */
 958         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
 959                 req.ring_type = ring_type;
 960                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
 961                 req.stat_ctx_id = rte_cpu_to_le_16(stats_ctx_id);
 962                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
 963                         enables |=
 964                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
 965                 break;
 966         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
 967                 req.ring_type = ring_type;
 968                 /*
 969                  * TODO: Some HWRM versions crash with
 970                  * HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
 971                  */
 972                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
 973                 break;
 974         default:
 975                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
 976                         ring_type);
 977                 HWRM_UNLOCK();
 978                 return -1;
 979         }
 980         req.enables = rte_cpu_to_le_32(enables);
 981
 982         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 983
 984         if (rc || resp->error_code) {
 985                 if (rc == 0 && resp->error_code)
 986                         rc = rte_le_to_cpu_16(resp->error_code);
 987                 switch (ring_type) {
 988                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
 989                         PMD_DRV_LOG(ERR,
 990                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
 991                         HWRM_UNLOCK();
 992                         return rc;
 993                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
 994                         PMD_DRV_LOG(ERR,
 995                                 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
 996                         HWRM_UNLOCK();
 997                         return rc;
 998                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
 999                         PMD_DRV_LOG(ERR,
1000                                 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1001                         HWRM_UNLOCK();
1002                         return rc;
1003                 default:
1004                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1005                         HWRM_UNLOCK();
1006                         return rc;
1007                 }
1008         }
1009
1010         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1011         HWRM_UNLOCK();
1012         return rc;
1013 }
1014
1015 int bnxt_hwrm_ring_free(struct bnxt *bp,
1016                         struct bnxt_ring *ring, uint32_t ring_type)
1017 {
1018         int rc;
1019         struct hwrm_ring_free_input req = {.req_type = 0 };
1020         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1021
1022         HWRM_PREP(req, RING_FREE);
1023
1024         req.ring_type = ring_type;
1025         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1026
1027         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1028
1029         if (rc || resp->error_code) {
1030                 if (rc == 0 && resp->error_code)
1031                         rc = rte_le_to_cpu_16(resp->error_code);
1032                 HWRM_UNLOCK();
1033
1034                 switch (ring_type) {
1035                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1036                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1037                                 rc);
1038                         return rc;
1039                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1040                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1041                                 rc);
1042                         return rc;
1043                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1044                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1045                                 rc);
1046                         return rc;
1047                 default:
1048                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1049                         return rc;
1050                 }
1051         }
1052         HWRM_UNLOCK();
1053         return 0;
1054 }
1055
1056 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1057 {
1058         int rc = 0;
1059         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1060         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1061
1062         HWRM_PREP(req, RING_GRP_ALLOC);
1063
1064         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1065         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1066         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1067         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1068
1069         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1070
1071         HWRM_CHECK_RESULT();
1072
1073         bp->grp_info[idx].fw_grp_id =
1074             rte_le_to_cpu_16(resp->ring_group_id);
1075
1076         HWRM_UNLOCK();
1077
1078         return rc;
1079 }
1080
1081 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1082 {
1083         int rc;
1084         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1085         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1086
1087         HWRM_PREP(req, RING_GRP_FREE);
1088
1089         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1090
1091         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1092
1093         HWRM_CHECK_RESULT();
1094         HWRM_UNLOCK();
1095
1096         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1097         return rc;
1098 }
1099
1100 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1101 {
1102         int rc = 0;
1103         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1104         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1105
1106         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1107                 return rc;
1108
1109         HWRM_PREP(req, STAT_CTX_CLR_STATS);
1110
1111         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1112
1113         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1114
1115         HWRM_CHECK_RESULT();
1116         HWRM_UNLOCK();
1117
1118         return rc;
1119 }
1120
1121 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1122                                 unsigned int idx __rte_unused)
1123 {
1124         int rc;
1125         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1126         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1127
1128         HWRM_PREP(req, STAT_CTX_ALLOC);
1129
1130         req.update_period_ms = rte_cpu_to_le_32(0);
1131
1132         req.stats_dma_addr =
1133             rte_cpu_to_le_64(cpr->hw_stats_map);
1134
1135         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1136
1137         HWRM_CHECK_RESULT();
1138
1139         cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
1140
1141         HWRM_UNLOCK();
1142
1143         return rc;
1144 }
1145
1146 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1147                                 unsigned int idx __rte_unused)
1148 {
1149         int rc;
1150         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1151         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1152
1153         HWRM_PREP(req, STAT_CTX_FREE);
1154
1155         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1156
1157         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1158
1159         HWRM_CHECK_RESULT();
1160         HWRM_UNLOCK();
1161
1162         return rc;
1163 }
1164
1165 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1166 {
1167         int rc = 0, i, j;
1168         struct hwrm_vnic_alloc_input req = { 0 };
1169         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1170
1171         /* map ring groups to this vnic */
1172         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1173                 vnic->start_grp_id, vnic->end_grp_id);
1174         for (i = vnic->start_grp_id, j = 0; i <= vnic->end_grp_id; i++, j++)
1175                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1176         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1177         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1178         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1179         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1180         vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1181                                 ETHER_CRC_LEN + VLAN_TAG_SIZE;
1182         HWRM_PREP(req, VNIC_ALLOC);
1183
1184         if (vnic->func_default)
1185                 req.flags = HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT;
1186         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1187
1188         HWRM_CHECK_RESULT();
1189
1190         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1191         HWRM_UNLOCK();
1192         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1193         return rc;
1194 }
1195
1196 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1197                                         struct bnxt_vnic_info *vnic,
1198                                         struct bnxt_plcmodes_cfg *pmode)
1199 {
1200         int rc = 0;
1201         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1202         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1203
1204         HWRM_PREP(req, VNIC_PLCMODES_QCFG);
1205
1206         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1207
1208         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1209
1210         HWRM_CHECK_RESULT();
1211
1212         pmode->flags = rte_le_to_cpu_32(resp->flags);
1213         /* dflt_vnic bit doesn't exist in the _cfg command */
1214         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1215         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1216         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1217         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1218
1219         HWRM_UNLOCK();
1220
1221         return rc;
1222 }
1223
1224 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1225                                        struct bnxt_vnic_info *vnic,
1226                                        struct bnxt_plcmodes_cfg *pmode)
1227 {
1228         int rc = 0;
1229         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1230         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1231
1232         HWRM_PREP(req, VNIC_PLCMODES_CFG);
1233
1234         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1235         req.flags = rte_cpu_to_le_32(pmode->flags);
1236         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1237         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1238         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1239         req.enables = rte_cpu_to_le_32(
1240             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1241             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1242             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1243         );
1244
1245         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1246
1247         HWRM_CHECK_RESULT();
1248         HWRM_UNLOCK();
1249
1250         return rc;
1251 }
1252
1253 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1254 {
1255         int rc = 0;
1256         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1257         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1258         uint32_t ctx_enable_flag = 0;
1259         struct bnxt_plcmodes_cfg pmodes;
1260
1261         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1262                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1263                 return rc;
1264         }
1265
1266         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1267         if (rc)
1268                 return rc;
1269
1270         HWRM_PREP(req, VNIC_CFG);
1271
1272         /* Only RSS support for now TBD: COS & LB */
1273         req.enables =
1274             rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP);
1275         if (vnic->lb_rule != 0xffff)
1276                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1277         if (vnic->cos_rule != 0xffff)
1278                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1279         if (vnic->rss_rule != 0xffff) {
1280                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1281                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1282         }
1283         req.enables |= rte_cpu_to_le_32(ctx_enable_flag);
1284         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1285         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1286         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1287         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1288         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1289         req.mru = rte_cpu_to_le_16(vnic->mru);
1290         if (vnic->func_default)
1291                 req.flags |=
1292                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1293         if (vnic->vlan_strip)
1294                 req.flags |=
1295                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1296         if (vnic->bd_stall)
1297                 req.flags |=
1298                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1299         if (vnic->roce_dual)
1300                 req.flags |= rte_cpu_to_le_32(
1301                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1302         if (vnic->roce_only)
1303                 req.flags |= rte_cpu_to_le_32(
1304                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1305         if (vnic->rss_dflt_cr)
1306                 req.flags |= rte_cpu_to_le_32(
1307                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1308
1309         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1310
1311         HWRM_CHECK_RESULT();
1312         HWRM_UNLOCK();
1313
1314         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1315
1316         return rc;
1317 }
1318
1319 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1320                 int16_t fw_vf_id)
1321 {
1322         int rc = 0;
1323         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1324         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1325
1326         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1327                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1328                 return rc;
1329         }
1330         HWRM_PREP(req, VNIC_QCFG);
1331
1332         req.enables =
1333                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1334         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1335         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1336
1337         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1338
1339         HWRM_CHECK_RESULT();
1340
1341         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1342         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1343         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1344         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1345         vnic->mru = rte_le_to_cpu_16(resp->mru);
1346         vnic->func_default = rte_le_to_cpu_32(
1347                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1348         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1349                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1350         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1351                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1352         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1353                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1354         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1355                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1356         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1357                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1358
1359         HWRM_UNLOCK();
1360
1361         return rc;
1362 }
1363
1364 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1365 {
1366         int rc = 0;
1367         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1368         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1369                                                 bp->hwrm_cmd_resp_addr;
1370
1371         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC);
1372
1373         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1374
1375         HWRM_CHECK_RESULT();
1376
1377         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1378         HWRM_UNLOCK();
1379         PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1380
1381         return rc;
1382 }
1383
1384 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1385 {
1386         int rc = 0;
1387         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1388         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1389                                                 bp->hwrm_cmd_resp_addr;
1390
1391         if (vnic->rss_rule == 0xffff) {
1392                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1393                 return rc;
1394         }
1395         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE);
1396
1397         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->rss_rule);
1398
1399         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1400
1401         HWRM_CHECK_RESULT();
1402         HWRM_UNLOCK();
1403
1404         vnic->rss_rule = INVALID_HW_RING_ID;
1405
1406         return rc;
1407 }
1408
1409 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1410 {
1411         int rc = 0;
1412         struct hwrm_vnic_free_input req = {.req_type = 0 };
1413         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1414
1415         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1416                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1417                 return rc;
1418         }
1419
1420         HWRM_PREP(req, VNIC_FREE);
1421
1422         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1423
1424         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1425
1426         HWRM_CHECK_RESULT();
1427         HWRM_UNLOCK();
1428
1429         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1430         return rc;
1431 }
1432
1433 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1434                            struct bnxt_vnic_info *vnic)
1435 {
1436         int rc = 0;
1437         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1438         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1439
1440         HWRM_PREP(req, VNIC_RSS_CFG);
1441
1442         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1443
1444         req.ring_grp_tbl_addr =
1445             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1446         req.hash_key_tbl_addr =
1447             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1448         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1449
1450         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1451
1452         HWRM_CHECK_RESULT();
1453         HWRM_UNLOCK();
1454
1455         return rc;
1456 }
1457
1458 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1459                         struct bnxt_vnic_info *vnic)
1460 {
1461         int rc = 0;
1462         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1463         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1464         uint16_t size;
1465
1466         HWRM_PREP(req, VNIC_PLCMODES_CFG);
1467
1468         req.flags = rte_cpu_to_le_32(
1469                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1470
1471         req.enables = rte_cpu_to_le_32(
1472                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1473
1474         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1475         size -= RTE_PKTMBUF_HEADROOM;
1476
1477         req.jumbo_thresh = rte_cpu_to_le_16(size);
1478         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1479
1480         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1481
1482         HWRM_CHECK_RESULT();
1483         HWRM_UNLOCK();
1484
1485         return rc;
1486 }
1487
1488 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1489                         struct bnxt_vnic_info *vnic, bool enable)
1490 {
1491         int rc = 0;
1492         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1493         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1494
1495         HWRM_PREP(req, VNIC_TPA_CFG);
1496
1497         if (enable) {
1498                 req.enables = rte_cpu_to_le_32(
1499                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1500                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1501                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1502                 req.flags = rte_cpu_to_le_32(
1503                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1504                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1505                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1506                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1507                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1508                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1509                 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1510                 req.max_agg_segs = rte_cpu_to_le_16(5);
1511                 req.max_aggs =
1512                         rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1513                 req.min_agg_len = rte_cpu_to_le_32(512);
1514         }
1515
1516         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1517
1518         HWRM_CHECK_RESULT();
1519         HWRM_UNLOCK();
1520
1521         return rc;
1522 }
1523
1524 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1525 {
1526         struct hwrm_func_cfg_input req = {0};
1527         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1528         int rc;
1529
1530         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1531         req.enables = rte_cpu_to_le_32(
1532                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1533         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1534         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1535
1536         HWRM_PREP(req, FUNC_CFG);
1537
1538         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1539         HWRM_CHECK_RESULT();
1540         HWRM_UNLOCK();
1541
1542         bp->pf.vf_info[vf].random_mac = false;
1543
1544         return rc;
1545 }
1546
1547 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1548                                   uint64_t *dropped)
1549 {
1550         int rc = 0;
1551         struct hwrm_func_qstats_input req = {.req_type = 0};
1552         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1553
1554         HWRM_PREP(req, FUNC_QSTATS);
1555
1556         req.fid = rte_cpu_to_le_16(fid);
1557
1558         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1559
1560         HWRM_CHECK_RESULT();
1561
1562         if (dropped)
1563                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1564
1565         HWRM_UNLOCK();
1566
1567         return rc;
1568 }
1569
1570 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1571                           struct rte_eth_stats *stats)
1572 {
1573         int rc = 0;
1574         struct hwrm_func_qstats_input req = {.req_type = 0};
1575         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1576
1577         HWRM_PREP(req, FUNC_QSTATS);
1578
1579         req.fid = rte_cpu_to_le_16(fid);
1580
1581         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1582
1583         HWRM_CHECK_RESULT();
1584
1585         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1586         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1587         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1588         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1589         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1590         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1591
1592         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1593         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1594         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1595         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1596         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1597         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1598
1599         stats->ierrors = rte_le_to_cpu_64(resp->rx_err_pkts);
1600         stats->oerrors = rte_le_to_cpu_64(resp->tx_err_pkts);
1601
1602         stats->imissed = rte_le_to_cpu_64(resp->rx_drop_pkts);
1603
1604         HWRM_UNLOCK();
1605
1606         return rc;
1607 }
1608
1609 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1610 {
1611         int rc = 0;
1612         struct hwrm_func_clr_stats_input req = {.req_type = 0};
1613         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1614
1615         HWRM_PREP(req, FUNC_CLR_STATS);
1616
1617         req.fid = rte_cpu_to_le_16(fid);
1618
1619         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1620
1621         HWRM_CHECK_RESULT();
1622         HWRM_UNLOCK();
1623
1624         return rc;
1625 }
1626
1627 /*
1628  * HWRM utility functions
1629  */
1630
1631 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1632 {
1633         unsigned int i;
1634         int rc = 0;
1635
1636         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1637                 struct bnxt_tx_queue *txq;
1638                 struct bnxt_rx_queue *rxq;
1639                 struct bnxt_cp_ring_info *cpr;
1640
1641                 if (i >= bp->rx_cp_nr_rings) {
1642                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1643                         cpr = txq->cp_ring;
1644                 } else {
1645                         rxq = bp->rx_queues[i];
1646                         cpr = rxq->cp_ring;
1647                 }
1648
1649                 rc = bnxt_hwrm_stat_clear(bp, cpr);
1650                 if (rc)
1651                         return rc;
1652         }
1653         return 0;
1654 }
1655
1656 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1657 {
1658         int rc;
1659         unsigned int i;
1660         struct bnxt_cp_ring_info *cpr;
1661
1662         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1663
1664                 if (i >= bp->rx_cp_nr_rings) {
1665                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
1666                 } else {
1667                         cpr = bp->rx_queues[i]->cp_ring;
1668                         bp->grp_info[i].fw_stats_ctx = -1;
1669                 }
1670                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
1671                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
1672                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1673                         if (rc)
1674                                 return rc;
1675                 }
1676         }
1677         return 0;
1678 }
1679
1680 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
1681 {
1682         unsigned int i;
1683         int rc = 0;
1684
1685         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1686                 struct bnxt_tx_queue *txq;
1687                 struct bnxt_rx_queue *rxq;
1688                 struct bnxt_cp_ring_info *cpr;
1689
1690                 if (i >= bp->rx_cp_nr_rings) {
1691                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1692                         cpr = txq->cp_ring;
1693                 } else {
1694                         rxq = bp->rx_queues[i];
1695                         cpr = rxq->cp_ring;
1696                 }
1697
1698                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
1699
1700                 if (rc)
1701                         return rc;
1702         }
1703         return rc;
1704 }
1705
1706 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
1707 {
1708         uint16_t idx;
1709         uint32_t rc = 0;
1710
1711         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
1712
1713                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
1714                         continue;
1715
1716                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
1717
1718                 if (rc)
1719                         return rc;
1720         }
1721         return rc;
1722 }
1723
1724 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1725                                 unsigned int idx __rte_unused)
1726 {
1727         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
1728
1729         bnxt_hwrm_ring_free(bp, cp_ring,
1730                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
1731         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
1732         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
1733                         sizeof(*cpr->cp_desc_ring));
1734         cpr->cp_raw_cons = 0;
1735 }
1736
1737 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
1738 {
1739         unsigned int i;
1740         int rc = 0;
1741
1742         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
1743                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
1744                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
1745                 struct bnxt_ring *ring = txr->tx_ring_struct;
1746                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
1747                 unsigned int idx = bp->rx_cp_nr_rings + i + 1;
1748
1749                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1750                         bnxt_hwrm_ring_free(bp, ring,
1751                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
1752                         ring->fw_ring_id = INVALID_HW_RING_ID;
1753                         memset(txr->tx_desc_ring, 0,
1754                                         txr->tx_ring_struct->ring_size *
1755                                         sizeof(*txr->tx_desc_ring));
1756                         memset(txr->tx_buf_ring, 0,
1757                                         txr->tx_ring_struct->ring_size *
1758                                         sizeof(*txr->tx_buf_ring));
1759                         txr->tx_prod = 0;
1760                         txr->tx_cons = 0;
1761                 }
1762                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1763                         bnxt_free_cp_ring(bp, cpr, idx);
1764                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1765                 }
1766         }
1767
1768         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1769                 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
1770                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1771                 struct bnxt_ring *ring = rxr->rx_ring_struct;
1772                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1773                 unsigned int idx = i + 1;
1774
1775                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1776                         bnxt_hwrm_ring_free(bp, ring,
1777                                         HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1778                         ring->fw_ring_id = INVALID_HW_RING_ID;
1779                         bp->grp_info[idx].rx_fw_ring_id = INVALID_HW_RING_ID;
1780                         memset(rxr->rx_desc_ring, 0,
1781                                         rxr->rx_ring_struct->ring_size *
1782                                         sizeof(*rxr->rx_desc_ring));
1783                         memset(rxr->rx_buf_ring, 0,
1784                                         rxr->rx_ring_struct->ring_size *
1785                                         sizeof(*rxr->rx_buf_ring));
1786                         rxr->rx_prod = 0;
1787                 }
1788                 ring = rxr->ag_ring_struct;
1789                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1790                         bnxt_hwrm_ring_free(bp, ring,
1791                                             HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1792                         ring->fw_ring_id = INVALID_HW_RING_ID;
1793                         memset(rxr->ag_buf_ring, 0,
1794                                rxr->ag_ring_struct->ring_size *
1795                                sizeof(*rxr->ag_buf_ring));
1796                         rxr->ag_prod = 0;
1797                         bp->grp_info[i].ag_fw_ring_id = INVALID_HW_RING_ID;
1798                 }
1799                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1800                         bnxt_free_cp_ring(bp, cpr, idx);
1801                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
1802                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1803                 }
1804         }
1805
1806         /* Default completion ring */
1807         {
1808                 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1809
1810                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1811                         bnxt_free_cp_ring(bp, cpr, 0);
1812                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1813                 }
1814         }
1815
1816         return rc;
1817 }
1818
1819 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
1820 {
1821         uint16_t i;
1822         uint32_t rc = 0;
1823
1824         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1825                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
1826                 if (rc)
1827                         return rc;
1828         }
1829         return rc;
1830 }
1831
1832 void bnxt_free_hwrm_resources(struct bnxt *bp)
1833 {
1834         /* Release memzone */
1835         rte_free(bp->hwrm_cmd_resp_addr);
1836         rte_free(bp->hwrm_short_cmd_req_addr);
1837         bp->hwrm_cmd_resp_addr = NULL;
1838         bp->hwrm_short_cmd_req_addr = NULL;
1839         bp->hwrm_cmd_resp_dma_addr = 0;
1840         bp->hwrm_short_cmd_req_dma_addr = 0;
1841 }
1842
1843 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
1844 {
1845         struct rte_pci_device *pdev = bp->pdev;
1846         char type[RTE_MEMZONE_NAMESIZE];
1847
1848         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
1849                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
1850         bp->max_resp_len = HWRM_MAX_RESP_LEN;
1851         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
1852         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1853         if (bp->hwrm_cmd_resp_addr == NULL)
1854                 return -ENOMEM;
1855         bp->hwrm_cmd_resp_dma_addr =
1856                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1857         if (bp->hwrm_cmd_resp_dma_addr == 0) {
1858                 PMD_DRV_LOG(ERR,
1859                         "unable to map response address to physical memory\n");
1860                 return -ENOMEM;
1861         }
1862         rte_spinlock_init(&bp->hwrm_lock);
1863
1864         return 0;
1865 }
1866
1867 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1868 {
1869         struct bnxt_filter_info *filter;
1870         int rc = 0;
1871
1872         STAILQ_FOREACH(filter, &vnic->filter, next) {
1873                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1874                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
1875                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1876                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
1877                 else
1878                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1879                 //if (rc)
1880                         //break;
1881         }
1882         return rc;
1883 }
1884
1885 static int
1886 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1887 {
1888         struct bnxt_filter_info *filter;
1889         struct rte_flow *flow;
1890         int rc = 0;
1891
1892         STAILQ_FOREACH(flow, &vnic->flow_list, next) {
1893                 filter = flow->filter;
1894                 PMD_DRV_LOG(ERR, "filter type %d\n", filter->filter_type);
1895                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1896                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
1897                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1898                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
1899                 else
1900                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1901
1902                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
1903                 rte_free(flow);
1904                 //if (rc)
1905                         //break;
1906         }
1907         return rc;
1908 }
1909
1910 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1911 {
1912         struct bnxt_filter_info *filter;
1913         int rc = 0;
1914
1915         STAILQ_FOREACH(filter, &vnic->filter, next) {
1916                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1917                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
1918                                                      filter);
1919                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1920                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
1921                                                          filter);
1922                 else
1923                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
1924                                                      filter);
1925                 if (rc)
1926                         break;
1927         }
1928         return rc;
1929 }
1930
1931 void bnxt_free_tunnel_ports(struct bnxt *bp)
1932 {
1933         if (bp->vxlan_port_cnt)
1934                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
1935                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
1936         bp->vxlan_port = 0;
1937         if (bp->geneve_port_cnt)
1938                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
1939                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
1940         bp->geneve_port = 0;
1941 }
1942
1943 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
1944 {
1945         int i;
1946
1947         if (bp->vnic_info == NULL)
1948                 return;
1949
1950         /*
1951          * Cleanup VNICs in reverse order, to make sure the L2 filter
1952          * from vnic0 is last to be cleaned up.
1953          */
1954         for (i = bp->nr_vnics - 1; i >= 0; i--) {
1955                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1956
1957                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
1958
1959                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
1960
1961                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
1962
1963                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
1964
1965                 bnxt_hwrm_vnic_free(bp, vnic);
1966         }
1967         /* Ring resources */
1968         bnxt_free_all_hwrm_rings(bp);
1969         bnxt_free_all_hwrm_ring_grps(bp);
1970         bnxt_free_all_hwrm_stat_ctxs(bp);
1971         bnxt_free_tunnel_ports(bp);
1972 }
1973
1974 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
1975 {
1976         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1977
1978         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
1979                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1980
1981         switch (conf_link_speed) {
1982         case ETH_LINK_SPEED_10M_HD:
1983         case ETH_LINK_SPEED_100M_HD:
1984                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
1985         }
1986         return hw_link_duplex;
1987 }
1988
1989 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
1990 {
1991         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
1992 }
1993
1994 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
1995 {
1996         uint16_t eth_link_speed = 0;
1997
1998         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
1999                 return ETH_LINK_SPEED_AUTONEG;
2000
2001         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2002         case ETH_LINK_SPEED_100M:
2003         case ETH_LINK_SPEED_100M_HD:
2004                 eth_link_speed =
2005                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2006                 break;
2007         case ETH_LINK_SPEED_1G:
2008                 eth_link_speed =
2009                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2010                 break;
2011         case ETH_LINK_SPEED_2_5G:
2012                 eth_link_speed =
2013                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2014                 break;
2015         case ETH_LINK_SPEED_10G:
2016                 eth_link_speed =
2017                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2018                 break;
2019         case ETH_LINK_SPEED_20G:
2020                 eth_link_speed =
2021                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2022                 break;
2023         case ETH_LINK_SPEED_25G:
2024                 eth_link_speed =
2025                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2026                 break;
2027         case ETH_LINK_SPEED_40G:
2028                 eth_link_speed =
2029                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2030                 break;
2031         case ETH_LINK_SPEED_50G:
2032                 eth_link_speed =
2033                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2034                 break;
2035         default:
2036                 PMD_DRV_LOG(ERR,
2037                         "Unsupported link speed %d; default to AUTO\n",
2038                         conf_link_speed);
2039                 break;
2040         }
2041         return eth_link_speed;
2042 }
2043
2044 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2045                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2046                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2047                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G)
2048
2049 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2050 {
2051         uint32_t one_speed;
2052
2053         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2054                 return 0;
2055
2056         if (link_speed & ETH_LINK_SPEED_FIXED) {
2057                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2058
2059                 if (one_speed & (one_speed - 1)) {
2060                         PMD_DRV_LOG(ERR,
2061                                 "Invalid advertised speeds (%u) for port %u\n",
2062                                 link_speed, port_id);
2063                         return -EINVAL;
2064                 }
2065                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2066                         PMD_DRV_LOG(ERR,
2067                                 "Unsupported advertised speed (%u) for port %u\n",
2068                                 link_speed, port_id);
2069                         return -EINVAL;
2070                 }
2071         } else {
2072                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2073                         PMD_DRV_LOG(ERR,
2074                                 "Unsupported advertised speeds (%u) for port %u\n",
2075                                 link_speed, port_id);
2076                         return -EINVAL;
2077                 }
2078         }
2079         return 0;
2080 }
2081
2082 static uint16_t
2083 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2084 {
2085         uint16_t ret = 0;
2086
2087         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2088                 if (bp->link_info.support_speeds)
2089                         return bp->link_info.support_speeds;
2090                 link_speed = BNXT_SUPPORTED_SPEEDS;
2091         }
2092
2093         if (link_speed & ETH_LINK_SPEED_100M)
2094                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2095         if (link_speed & ETH_LINK_SPEED_100M_HD)
2096                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2097         if (link_speed & ETH_LINK_SPEED_1G)
2098                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2099         if (link_speed & ETH_LINK_SPEED_2_5G)
2100                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2101         if (link_speed & ETH_LINK_SPEED_10G)
2102                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2103         if (link_speed & ETH_LINK_SPEED_20G)
2104                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2105         if (link_speed & ETH_LINK_SPEED_25G)
2106                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2107         if (link_speed & ETH_LINK_SPEED_40G)
2108                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2109         if (link_speed & ETH_LINK_SPEED_50G)
2110                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2111         return ret;
2112 }
2113
2114 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2115 {
2116         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2117
2118         switch (hw_link_speed) {
2119         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2120                 eth_link_speed = ETH_SPEED_NUM_100M;
2121                 break;
2122         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2123                 eth_link_speed = ETH_SPEED_NUM_1G;
2124                 break;
2125         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2126                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2127                 break;
2128         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2129                 eth_link_speed = ETH_SPEED_NUM_10G;
2130                 break;
2131         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2132                 eth_link_speed = ETH_SPEED_NUM_20G;
2133                 break;
2134         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2135                 eth_link_speed = ETH_SPEED_NUM_25G;
2136                 break;
2137         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2138                 eth_link_speed = ETH_SPEED_NUM_40G;
2139                 break;
2140         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2141                 eth_link_speed = ETH_SPEED_NUM_50G;
2142                 break;
2143         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2144         default:
2145                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2146                         hw_link_speed);
2147                 break;
2148         }
2149         return eth_link_speed;
2150 }
2151
2152 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2153 {
2154         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2155
2156         switch (hw_link_duplex) {
2157         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2158         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2159                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2160                 break;
2161         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2162                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2163                 break;
2164         default:
2165                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2166                         hw_link_duplex);
2167                 break;
2168         }
2169         return eth_link_duplex;
2170 }
2171
2172 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2173 {
2174         int rc = 0;
2175         struct bnxt_link_info *link_info = &bp->link_info;
2176
2177         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2178         if (rc) {
2179                 PMD_DRV_LOG(ERR,
2180                         "Get link config failed with rc %d\n", rc);
2181                 goto exit;
2182         }
2183         if (link_info->link_speed)
2184                 link->link_speed =
2185                         bnxt_parse_hw_link_speed(link_info->link_speed);
2186         else
2187                 link->link_speed = ETH_SPEED_NUM_NONE;
2188         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2189         link->link_status = link_info->link_up;
2190         link->link_autoneg = link_info->auto_mode ==
2191                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2192                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2193 exit:
2194         return rc;
2195 }
2196
2197 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2198 {
2199         int rc = 0;
2200         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2201         struct bnxt_link_info link_req;
2202         uint16_t speed, autoneg;
2203
2204         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2205                 return 0;
2206
2207         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2208                         bp->eth_dev->data->port_id);
2209         if (rc)
2210                 goto error;
2211
2212         memset(&link_req, 0, sizeof(link_req));
2213         link_req.link_up = link_up;
2214         if (!link_up)
2215                 goto port_phy_cfg;
2216
2217         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2218         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2219         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2220         if (autoneg == 1) {
2221                 link_req.phy_flags |=
2222                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2223                 link_req.auto_link_speed_mask =
2224                         bnxt_parse_eth_link_speed_mask(bp,
2225                                                        dev_conf->link_speeds);
2226         } else {
2227                 if (bp->link_info.phy_type ==
2228                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2229                     bp->link_info.phy_type ==
2230                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2231                     bp->link_info.media_type ==
2232                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2233                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2234                         return -EINVAL;
2235                 }
2236
2237                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2238                 link_req.link_speed = speed;
2239         }
2240         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2241         link_req.auto_pause = bp->link_info.auto_pause;
2242         link_req.force_pause = bp->link_info.force_pause;
2243
2244 port_phy_cfg:
2245         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2246         if (rc) {
2247                 PMD_DRV_LOG(ERR,
2248                         "Set link config failed with rc %d\n", rc);
2249         }
2250
2251 error:
2252         return rc;
2253 }
2254
2255 /* JIRA 22088 */
2256 int bnxt_hwrm_func_qcfg(struct bnxt *bp)
2257 {
2258         struct hwrm_func_qcfg_input req = {0};
2259         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2260         uint16_t flags;
2261         int rc = 0;
2262
2263         HWRM_PREP(req, FUNC_QCFG);
2264         req.fid = rte_cpu_to_le_16(0xffff);
2265
2266         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2267
2268         HWRM_CHECK_RESULT();
2269
2270         /* Hard Coded.. 0xfff VLAN ID mask */
2271         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2272         flags = rte_le_to_cpu_16(resp->flags);
2273         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2274                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2275
2276         switch (resp->port_partition_type) {
2277         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2278         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2279         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2280                 bp->port_partition_type = resp->port_partition_type;
2281                 break;
2282         default:
2283                 bp->port_partition_type = 0;
2284                 break;
2285         }
2286
2287         HWRM_UNLOCK();
2288
2289         return rc;
2290 }
2291
2292 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2293                                    struct hwrm_func_qcaps_output *qcaps)
2294 {
2295         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2296         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2297                sizeof(qcaps->mac_address));
2298         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2299         qcaps->max_rx_rings = fcfg->num_rx_rings;
2300         qcaps->max_tx_rings = fcfg->num_tx_rings;
2301         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2302         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2303         qcaps->max_vfs = 0;
2304         qcaps->first_vf_id = 0;
2305         qcaps->max_vnics = fcfg->num_vnics;
2306         qcaps->max_decap_records = 0;
2307         qcaps->max_encap_records = 0;
2308         qcaps->max_tx_wm_flows = 0;
2309         qcaps->max_tx_em_flows = 0;
2310         qcaps->max_rx_wm_flows = 0;
2311         qcaps->max_rx_em_flows = 0;
2312         qcaps->max_flow_id = 0;
2313         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2314         qcaps->max_sp_tx_rings = 0;
2315         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2316 }
2317
2318 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2319 {
2320         struct hwrm_func_cfg_input req = {0};
2321         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2322         int rc;
2323
2324         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2325                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2326                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2327                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2328                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2329                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2330                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2331                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2332                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2333                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2334         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2335         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2336         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2337                                    ETHER_CRC_LEN + VLAN_TAG_SIZE);
2338         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2339         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2340         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2341         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2342         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2343         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2344         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2345         req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2346         req.fid = rte_cpu_to_le_16(0xffff);
2347
2348         HWRM_PREP(req, FUNC_CFG);
2349
2350         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2351
2352         HWRM_CHECK_RESULT();
2353         HWRM_UNLOCK();
2354
2355         return rc;
2356 }
2357
2358 static void populate_vf_func_cfg_req(struct bnxt *bp,
2359                                      struct hwrm_func_cfg_input *req,
2360                                      int num_vfs)
2361 {
2362         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2363                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2364                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2365                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2366                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2367                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2368                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2369                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2370                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2371                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2372
2373         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2374                                     ETHER_CRC_LEN + VLAN_TAG_SIZE);
2375         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2376                                     ETHER_CRC_LEN + VLAN_TAG_SIZE);
2377         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2378                                                 (num_vfs + 1));
2379         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2380         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2381                                                (num_vfs + 1));
2382         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2383         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2384         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2385         /* TODO: For now, do not support VMDq/RFS on VFs. */
2386         req->num_vnics = rte_cpu_to_le_16(1);
2387         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2388                                                  (num_vfs + 1));
2389 }
2390
2391 static void add_random_mac_if_needed(struct bnxt *bp,
2392                                      struct hwrm_func_cfg_input *cfg_req,
2393                                      int vf)
2394 {
2395         struct ether_addr mac;
2396
2397         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2398                 return;
2399
2400         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2401                 cfg_req->enables |=
2402                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2403                 eth_random_addr(cfg_req->dflt_mac_addr);
2404                 bp->pf.vf_info[vf].random_mac = true;
2405         } else {
2406                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes, ETHER_ADDR_LEN);
2407         }
2408 }
2409
2410 static void reserve_resources_from_vf(struct bnxt *bp,
2411                                       struct hwrm_func_cfg_input *cfg_req,
2412                                       int vf)
2413 {
2414         struct hwrm_func_qcaps_input req = {0};
2415         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2416         int rc;
2417
2418         /* Get the actual allocated values now */
2419         HWRM_PREP(req, FUNC_QCAPS);
2420         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2421         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2422
2423         if (rc) {
2424                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2425                 copy_func_cfg_to_qcaps(cfg_req, resp);
2426         } else if (resp->error_code) {
2427                 rc = rte_le_to_cpu_16(resp->error_code);
2428                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2429                 copy_func_cfg_to_qcaps(cfg_req, resp);
2430         }
2431
2432         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2433         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2434         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2435         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2436         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2437         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2438         /*
2439          * TODO: While not supporting VMDq with VFs, max_vnics is always
2440          * forced to 1 in this case
2441          */
2442         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2443         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2444
2445         HWRM_UNLOCK();
2446 }
2447
2448 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2449 {
2450         struct hwrm_func_qcfg_input req = {0};
2451         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2452         int rc;
2453
2454         /* Check for zero MAC address */
2455         HWRM_PREP(req, FUNC_QCFG);
2456         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2457         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2458         if (rc) {
2459                 PMD_DRV_LOG(ERR, "hwrm_func_qcfg failed rc:%d\n", rc);
2460                 return -1;
2461         } else if (resp->error_code) {
2462                 rc = rte_le_to_cpu_16(resp->error_code);
2463                 PMD_DRV_LOG(ERR, "hwrm_func_qcfg error %d\n", rc);
2464                 return -1;
2465         }
2466         rc = rte_le_to_cpu_16(resp->vlan);
2467
2468         HWRM_UNLOCK();
2469
2470         return rc;
2471 }
2472
2473 static int update_pf_resource_max(struct bnxt *bp)
2474 {
2475         struct hwrm_func_qcfg_input req = {0};
2476         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2477         int rc;
2478
2479         /* And copy the allocated numbers into the pf struct */
2480         HWRM_PREP(req, FUNC_QCFG);
2481         req.fid = rte_cpu_to_le_16(0xffff);
2482         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2483         HWRM_CHECK_RESULT();
2484
2485         /* Only TX ring value reflects actual allocation? TODO */
2486         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2487         bp->pf.evb_mode = resp->evb_mode;
2488
2489         HWRM_UNLOCK();
2490
2491         return rc;
2492 }
2493
2494 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2495 {
2496         int rc;
2497
2498         if (!BNXT_PF(bp)) {
2499                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2500                 return -1;
2501         }
2502
2503         rc = bnxt_hwrm_func_qcaps(bp);
2504         if (rc)
2505                 return rc;
2506
2507         bp->pf.func_cfg_flags &=
2508                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2509                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2510         bp->pf.func_cfg_flags |=
2511                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2512         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2513         return rc;
2514 }
2515
2516 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2517 {
2518         struct hwrm_func_cfg_input req = {0};
2519         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2520         int i;
2521         size_t sz;
2522         int rc = 0;
2523         size_t req_buf_sz;
2524
2525         if (!BNXT_PF(bp)) {
2526                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2527                 return -1;
2528         }
2529
2530         rc = bnxt_hwrm_func_qcaps(bp);
2531
2532         if (rc)
2533                 return rc;
2534
2535         bp->pf.active_vfs = num_vfs;
2536
2537         /*
2538          * First, configure the PF to only use one TX ring.  This ensures that
2539          * there are enough rings for all VFs.
2540          *
2541          * If we don't do this, when we call func_alloc() later, we will lock
2542          * extra rings to the PF that won't be available during func_cfg() of
2543          * the VFs.
2544          *
2545          * This has been fixed with firmware versions above 20.6.54
2546          */
2547         bp->pf.func_cfg_flags &=
2548                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2549                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2550         bp->pf.func_cfg_flags |=
2551                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2552         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2553         if (rc)
2554                 return rc;
2555
2556         /*
2557          * Now, create and register a buffer to hold forwarded VF requests
2558          */
2559         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2560         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2561                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2562         if (bp->pf.vf_req_buf == NULL) {
2563                 rc = -ENOMEM;
2564                 goto error_free;
2565         }
2566         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2567                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2568         for (i = 0; i < num_vfs; i++)
2569                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2570                                         (i * HWRM_MAX_REQ_LEN);
2571
2572         rc = bnxt_hwrm_func_buf_rgtr(bp);
2573         if (rc)
2574                 goto error_free;
2575
2576         populate_vf_func_cfg_req(bp, &req, num_vfs);
2577
2578         bp->pf.active_vfs = 0;
2579         for (i = 0; i < num_vfs; i++) {
2580                 add_random_mac_if_needed(bp, &req, i);
2581
2582                 HWRM_PREP(req, FUNC_CFG);
2583                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2584                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
2585                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2586
2587                 /* Clear enable flag for next pass */
2588                 req.enables &= ~rte_cpu_to_le_32(
2589                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2590
2591                 if (rc || resp->error_code) {
2592                         PMD_DRV_LOG(ERR,
2593                                 "Failed to initizlie VF %d\n", i);
2594                         PMD_DRV_LOG(ERR,
2595                                 "Not all VFs available. (%d, %d)\n",
2596                                 rc, resp->error_code);
2597                         HWRM_UNLOCK();
2598                         break;
2599                 }
2600
2601                 HWRM_UNLOCK();
2602
2603                 reserve_resources_from_vf(bp, &req, i);
2604                 bp->pf.active_vfs++;
2605                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
2606         }
2607
2608         /*
2609          * Now configure the PF to use "the rest" of the resources
2610          * We're using STD_TX_RING_MODE here though which will limit the TX
2611          * rings.  This will allow QoS to function properly.  Not setting this
2612          * will cause PF rings to break bandwidth settings.
2613          */
2614         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2615         if (rc)
2616                 goto error_free;
2617
2618         rc = update_pf_resource_max(bp);
2619         if (rc)
2620                 goto error_free;
2621
2622         return rc;
2623
2624 error_free:
2625         bnxt_hwrm_func_buf_unrgtr(bp);
2626         return rc;
2627 }
2628
2629 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
2630 {
2631         struct hwrm_func_cfg_input req = {0};
2632         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2633         int rc;
2634
2635         HWRM_PREP(req, FUNC_CFG);
2636
2637         req.fid = rte_cpu_to_le_16(0xffff);
2638         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
2639         req.evb_mode = bp->pf.evb_mode;
2640
2641         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2642         HWRM_CHECK_RESULT();
2643         HWRM_UNLOCK();
2644
2645         return rc;
2646 }
2647
2648 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
2649                                 uint8_t tunnel_type)
2650 {
2651         struct hwrm_tunnel_dst_port_alloc_input req = {0};
2652         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2653         int rc = 0;
2654
2655         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC);
2656         req.tunnel_type = tunnel_type;
2657         req.tunnel_dst_port_val = port;
2658         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2659         HWRM_CHECK_RESULT();
2660
2661         switch (tunnel_type) {
2662         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
2663                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2664                 bp->vxlan_port = port;
2665                 break;
2666         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
2667                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
2668                 bp->geneve_port = port;
2669                 break;
2670         default:
2671                 break;
2672         }
2673
2674         HWRM_UNLOCK();
2675
2676         return rc;
2677 }
2678
2679 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
2680                                 uint8_t tunnel_type)
2681 {
2682         struct hwrm_tunnel_dst_port_free_input req = {0};
2683         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
2684         int rc = 0;
2685
2686         HWRM_PREP(req, TUNNEL_DST_PORT_FREE);
2687
2688         req.tunnel_type = tunnel_type;
2689         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
2690         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2691
2692         HWRM_CHECK_RESULT();
2693         HWRM_UNLOCK();
2694
2695         return rc;
2696 }
2697
2698 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
2699                                         uint32_t flags)
2700 {
2701         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2702         struct hwrm_func_cfg_input req = {0};
2703         int rc;
2704
2705         HWRM_PREP(req, FUNC_CFG);
2706
2707         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2708         req.flags = rte_cpu_to_le_32(flags);
2709         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2710
2711         HWRM_CHECK_RESULT();
2712         HWRM_UNLOCK();
2713
2714         return rc;
2715 }
2716
2717 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
2718 {
2719         uint32_t *flag = flagp;
2720
2721         vnic->flags = *flag;
2722 }
2723
2724 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2725 {
2726         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2727 }
2728
2729 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
2730 {
2731         int rc = 0;
2732         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
2733         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
2734
2735         HWRM_PREP(req, FUNC_BUF_RGTR);
2736
2737         req.req_buf_num_pages = rte_cpu_to_le_16(1);
2738         req.req_buf_page_size = rte_cpu_to_le_16(
2739                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
2740         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
2741         req.req_buf_page_addr[0] =
2742                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
2743         if (req.req_buf_page_addr[0] == 0) {
2744                 PMD_DRV_LOG(ERR,
2745                         "unable to map buffer address to physical memory\n");
2746                 return -ENOMEM;
2747         }
2748
2749         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2750
2751         HWRM_CHECK_RESULT();
2752         HWRM_UNLOCK();
2753
2754         return rc;
2755 }
2756
2757 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
2758 {
2759         int rc = 0;
2760         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
2761         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
2762
2763         HWRM_PREP(req, FUNC_BUF_UNRGTR);
2764
2765         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2766
2767         HWRM_CHECK_RESULT();
2768         HWRM_UNLOCK();
2769
2770         return rc;
2771 }
2772
2773 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
2774 {
2775         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2776         struct hwrm_func_cfg_input req = {0};
2777         int rc;
2778
2779         HWRM_PREP(req, FUNC_CFG);
2780
2781         req.fid = rte_cpu_to_le_16(0xffff);
2782         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2783         req.enables = rte_cpu_to_le_32(
2784                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2785         req.async_event_cr = rte_cpu_to_le_16(
2786                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2787         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2788
2789         HWRM_CHECK_RESULT();
2790         HWRM_UNLOCK();
2791
2792         return rc;
2793 }
2794
2795 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
2796 {
2797         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2798         struct hwrm_func_vf_cfg_input req = {0};
2799         int rc;
2800
2801         HWRM_PREP(req, FUNC_VF_CFG);
2802
2803         req.enables = rte_cpu_to_le_32(
2804                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2805         req.async_event_cr = rte_cpu_to_le_16(
2806                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2807         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2808
2809         HWRM_CHECK_RESULT();
2810         HWRM_UNLOCK();
2811
2812         return rc;
2813 }
2814
2815 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
2816 {
2817         struct hwrm_func_cfg_input req = {0};
2818         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2819         uint16_t dflt_vlan, fid;
2820         uint32_t func_cfg_flags;
2821         int rc = 0;
2822
2823         HWRM_PREP(req, FUNC_CFG);
2824
2825         if (is_vf) {
2826                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
2827                 fid = bp->pf.vf_info[vf].fid;
2828                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
2829         } else {
2830                 fid = rte_cpu_to_le_16(0xffff);
2831                 func_cfg_flags = bp->pf.func_cfg_flags;
2832                 dflt_vlan = bp->vlan;
2833         }
2834
2835         req.flags = rte_cpu_to_le_32(func_cfg_flags);
2836         req.fid = rte_cpu_to_le_16(fid);
2837         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2838         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
2839
2840         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2841
2842         HWRM_CHECK_RESULT();
2843         HWRM_UNLOCK();
2844
2845         return rc;
2846 }
2847
2848 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
2849                         uint16_t max_bw, uint16_t enables)
2850 {
2851         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2852         struct hwrm_func_cfg_input req = {0};
2853         int rc;
2854
2855         HWRM_PREP(req, FUNC_CFG);
2856
2857         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2858         req.enables |= rte_cpu_to_le_32(enables);
2859         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2860         req.max_bw = rte_cpu_to_le_32(max_bw);
2861         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2862
2863         HWRM_CHECK_RESULT();
2864         HWRM_UNLOCK();
2865
2866         return rc;
2867 }
2868
2869 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
2870 {
2871         struct hwrm_func_cfg_input req = {0};
2872         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2873         int rc = 0;
2874
2875         HWRM_PREP(req, FUNC_CFG);
2876
2877         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2878         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2879         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2880         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
2881
2882         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2883
2884         HWRM_CHECK_RESULT();
2885         HWRM_UNLOCK();
2886
2887         return rc;
2888 }
2889
2890 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
2891                               void *encaped, size_t ec_size)
2892 {
2893         int rc = 0;
2894         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
2895         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2896
2897         if (ec_size > sizeof(req.encap_request))
2898                 return -1;
2899
2900         HWRM_PREP(req, REJECT_FWD_RESP);
2901
2902         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2903         memcpy(req.encap_request, encaped, ec_size);
2904
2905         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2906
2907         HWRM_CHECK_RESULT();
2908         HWRM_UNLOCK();
2909
2910         return rc;
2911 }
2912
2913 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
2914                                        struct ether_addr *mac)
2915 {
2916         struct hwrm_func_qcfg_input req = {0};
2917         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2918         int rc;
2919
2920         HWRM_PREP(req, FUNC_QCFG);
2921
2922         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2923         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2924
2925         HWRM_CHECK_RESULT();
2926
2927         memcpy(mac->addr_bytes, resp->mac_address, ETHER_ADDR_LEN);
2928
2929         HWRM_UNLOCK();
2930
2931         return rc;
2932 }
2933
2934 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
2935                             void *encaped, size_t ec_size)
2936 {
2937         int rc = 0;
2938         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
2939         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2940
2941         if (ec_size > sizeof(req.encap_request))
2942                 return -1;
2943
2944         HWRM_PREP(req, EXEC_FWD_RESP);
2945
2946         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2947         memcpy(req.encap_request, encaped, ec_size);
2948
2949         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2950
2951         HWRM_CHECK_RESULT();
2952         HWRM_UNLOCK();
2953
2954         return rc;
2955 }
2956
2957 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
2958                          struct rte_eth_stats *stats, uint8_t rx)
2959 {
2960         int rc = 0;
2961         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
2962         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
2963
2964         HWRM_PREP(req, STAT_CTX_QUERY);
2965
2966         req.stat_ctx_id = rte_cpu_to_le_32(cid);
2967
2968         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2969
2970         HWRM_CHECK_RESULT();
2971
2972         if (rx) {
2973                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2974                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2975                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2976                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2977                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2978                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2979                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
2980                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
2981         } else {
2982                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2983                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2984                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2985                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2986                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2987                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2988                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->tx_err_pkts);
2989         }
2990
2991
2992         HWRM_UNLOCK();
2993
2994         return rc;
2995 }
2996
2997 int bnxt_hwrm_port_qstats(struct bnxt *bp)
2998 {
2999         struct hwrm_port_qstats_input req = {0};
3000         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3001         struct bnxt_pf_info *pf = &bp->pf;
3002         int rc;
3003
3004         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
3005                 return 0;
3006
3007         HWRM_PREP(req, PORT_QSTATS);
3008
3009         req.port_id = rte_cpu_to_le_16(pf->port_id);
3010         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3011         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3012         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3013
3014         HWRM_CHECK_RESULT();
3015         HWRM_UNLOCK();
3016
3017         return rc;
3018 }
3019
3020 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3021 {
3022         struct hwrm_port_clr_stats_input req = {0};
3023         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3024         struct bnxt_pf_info *pf = &bp->pf;
3025         int rc;
3026
3027         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
3028                 return 0;
3029
3030         HWRM_PREP(req, PORT_CLR_STATS);
3031
3032         req.port_id = rte_cpu_to_le_16(pf->port_id);
3033         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3034
3035         HWRM_CHECK_RESULT();
3036         HWRM_UNLOCK();
3037
3038         return rc;
3039 }
3040
3041 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3042 {
3043         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3044         struct hwrm_port_led_qcaps_input req = {0};
3045         int rc;
3046
3047         if (BNXT_VF(bp))
3048                 return 0;
3049
3050         HWRM_PREP(req, PORT_LED_QCAPS);
3051         req.port_id = bp->pf.port_id;
3052         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3053
3054         HWRM_CHECK_RESULT();
3055
3056         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3057                 unsigned int i;
3058
3059                 bp->num_leds = resp->num_leds;
3060                 memcpy(bp->leds, &resp->led0_id,
3061                         sizeof(bp->leds[0]) * bp->num_leds);
3062                 for (i = 0; i < bp->num_leds; i++) {
3063                         struct bnxt_led_info *led = &bp->leds[i];
3064
3065                         uint16_t caps = led->led_state_caps;
3066
3067                         if (!led->led_group_id ||
3068                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3069                                 bp->num_leds = 0;
3070                                 break;
3071                         }
3072                 }
3073         }
3074
3075         HWRM_UNLOCK();
3076
3077         return rc;
3078 }
3079
3080 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3081 {
3082         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3083         struct hwrm_port_led_cfg_input req = {0};
3084         struct bnxt_led_cfg *led_cfg;
3085         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3086         uint16_t duration = 0;
3087         int rc, i;
3088
3089         if (!bp->num_leds || BNXT_VF(bp))
3090                 return -EOPNOTSUPP;
3091
3092         HWRM_PREP(req, PORT_LED_CFG);
3093
3094         if (led_on) {
3095                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3096                 duration = rte_cpu_to_le_16(500);
3097         }
3098         req.port_id = bp->pf.port_id;
3099         req.num_leds = bp->num_leds;
3100         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3101         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3102                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3103                 led_cfg->led_id = bp->leds[i].led_id;
3104                 led_cfg->led_state = led_state;
3105                 led_cfg->led_blink_on = duration;
3106                 led_cfg->led_blink_off = duration;
3107                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3108         }
3109
3110         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3111
3112         HWRM_CHECK_RESULT();
3113         HWRM_UNLOCK();
3114
3115         return rc;
3116 }
3117
3118 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3119                                uint32_t *length)
3120 {
3121         int rc;
3122         struct hwrm_nvm_get_dir_info_input req = {0};
3123         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3124
3125         HWRM_PREP(req, NVM_GET_DIR_INFO);
3126
3127         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3128
3129         HWRM_CHECK_RESULT();
3130         HWRM_UNLOCK();
3131
3132         if (!rc) {
3133                 *entries = rte_le_to_cpu_32(resp->entries);
3134                 *length = rte_le_to_cpu_32(resp->entry_length);
3135         }
3136         return rc;
3137 }
3138
3139 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3140 {
3141         int rc;
3142         uint32_t dir_entries;
3143         uint32_t entry_length;
3144         uint8_t *buf;
3145         size_t buflen;
3146         rte_iova_t dma_handle;
3147         struct hwrm_nvm_get_dir_entries_input req = {0};
3148         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3149
3150         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3151         if (rc != 0)
3152                 return rc;
3153
3154         *data++ = dir_entries;
3155         *data++ = entry_length;
3156         len -= 2;
3157         memset(data, 0xff, len);
3158
3159         buflen = dir_entries * entry_length;
3160         buf = rte_malloc("nvm_dir", buflen, 0);
3161         rte_mem_lock_page(buf);
3162         if (buf == NULL)
3163                 return -ENOMEM;
3164         dma_handle = rte_mem_virt2iova(buf);
3165         if (dma_handle == 0) {
3166                 PMD_DRV_LOG(ERR,
3167                         "unable to map response address to physical memory\n");
3168                 return -ENOMEM;
3169         }
3170         HWRM_PREP(req, NVM_GET_DIR_ENTRIES);
3171         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3172         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3173
3174         HWRM_CHECK_RESULT();
3175         HWRM_UNLOCK();
3176
3177         if (rc == 0)
3178                 memcpy(data, buf, len > buflen ? buflen : len);
3179
3180         rte_free(buf);
3181
3182         return rc;
3183 }
3184
3185 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3186                              uint32_t offset, uint32_t length,
3187                              uint8_t *data)
3188 {
3189         int rc;
3190         uint8_t *buf;
3191         rte_iova_t dma_handle;
3192         struct hwrm_nvm_read_input req = {0};
3193         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3194
3195         buf = rte_malloc("nvm_item", length, 0);
3196         rte_mem_lock_page(buf);
3197         if (!buf)
3198                 return -ENOMEM;
3199
3200         dma_handle = rte_mem_virt2iova(buf);
3201         if (dma_handle == 0) {
3202                 PMD_DRV_LOG(ERR,
3203                         "unable to map response address to physical memory\n");
3204                 return -ENOMEM;
3205         }
3206         HWRM_PREP(req, NVM_READ);
3207         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3208         req.dir_idx = rte_cpu_to_le_16(index);
3209         req.offset = rte_cpu_to_le_32(offset);
3210         req.len = rte_cpu_to_le_32(length);
3211         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3212         HWRM_CHECK_RESULT();
3213         HWRM_UNLOCK();
3214         if (rc == 0)
3215                 memcpy(data, buf, length);
3216
3217         rte_free(buf);
3218         return rc;
3219 }
3220
3221 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3222 {
3223         int rc;
3224         struct hwrm_nvm_erase_dir_entry_input req = {0};
3225         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3226
3227         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY);
3228         req.dir_idx = rte_cpu_to_le_16(index);
3229         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3230         HWRM_CHECK_RESULT();
3231         HWRM_UNLOCK();
3232
3233         return rc;
3234 }
3235
3236
3237 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3238                           uint16_t dir_ordinal, uint16_t dir_ext,
3239                           uint16_t dir_attr, const uint8_t *data,
3240                           size_t data_len)
3241 {
3242         int rc;
3243         struct hwrm_nvm_write_input req = {0};
3244         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3245         rte_iova_t dma_handle;
3246         uint8_t *buf;
3247
3248         HWRM_PREP(req, NVM_WRITE);
3249
3250         req.dir_type = rte_cpu_to_le_16(dir_type);
3251         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3252         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3253         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3254         req.dir_data_length = rte_cpu_to_le_32(data_len);
3255
3256         buf = rte_malloc("nvm_write", data_len, 0);
3257         rte_mem_lock_page(buf);
3258         if (!buf)
3259                 return -ENOMEM;
3260
3261         dma_handle = rte_mem_virt2iova(buf);
3262         if (dma_handle == 0) {
3263                 PMD_DRV_LOG(ERR,
3264                         "unable to map response address to physical memory\n");
3265                 return -ENOMEM;
3266         }
3267         memcpy(buf, data, data_len);
3268         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3269
3270         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3271
3272         HWRM_CHECK_RESULT();
3273         HWRM_UNLOCK();
3274
3275         rte_free(buf);
3276         return rc;
3277 }
3278
3279 static void
3280 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3281 {
3282         uint32_t *count = cbdata;
3283
3284         *count = *count + 1;
3285 }
3286
3287 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3288                                      struct bnxt_vnic_info *vnic __rte_unused)
3289 {
3290         return 0;
3291 }
3292
3293 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3294 {
3295         uint32_t count = 0;
3296
3297         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3298             &count, bnxt_vnic_count_hwrm_stub);
3299
3300         return count;
3301 }
3302
3303 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3304                                         uint16_t *vnic_ids)
3305 {
3306         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3307         struct hwrm_func_vf_vnic_ids_query_output *resp =
3308                                                 bp->hwrm_cmd_resp_addr;
3309         int rc;
3310
3311         /* First query all VNIC ids */
3312         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY);
3313
3314         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3315         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3316         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3317
3318         if (req.vnic_id_tbl_addr == 0) {
3319                 HWRM_UNLOCK();
3320                 PMD_DRV_LOG(ERR,
3321                 "unable to map VNIC ID table address to physical memory\n");
3322                 return -ENOMEM;
3323         }
3324         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3325         if (rc) {
3326                 HWRM_UNLOCK();
3327                 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
3328                 return -1;
3329         } else if (resp->error_code) {
3330                 rc = rte_le_to_cpu_16(resp->error_code);
3331                 HWRM_UNLOCK();
3332                 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query error %d\n", rc);
3333                 return -1;
3334         }
3335         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3336
3337         HWRM_UNLOCK();
3338
3339         return rc;
3340 }
3341
3342 /*
3343  * This function queries the VNIC IDs  for a specified VF. It then calls
3344  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3345  * Then it calls the hwrm_cb function to program this new vnic configuration.
3346  */
3347 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3348         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3349         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3350 {
3351         struct bnxt_vnic_info vnic;
3352         int rc = 0;
3353         int i, num_vnic_ids;
3354         uint16_t *vnic_ids;
3355         size_t vnic_id_sz;
3356         size_t sz;
3357
3358         /* First query all VNIC ids */
3359         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3360         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3361                         RTE_CACHE_LINE_SIZE);
3362         if (vnic_ids == NULL) {
3363                 rc = -ENOMEM;
3364                 return rc;
3365         }
3366         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3367                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3368
3369         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3370
3371         if (num_vnic_ids < 0)
3372                 return num_vnic_ids;
3373
3374         /* Retrieve VNIC, update bd_stall then update */
3375
3376         for (i = 0; i < num_vnic_ids; i++) {
3377                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3378                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3379                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3380                 if (rc)
3381                         break;
3382                 if (vnic.mru <= 4)      /* Indicates unallocated */
3383                         continue;
3384
3385                 vnic_cb(&vnic, cbdata);
3386
3387                 rc = hwrm_cb(bp, &vnic);
3388                 if (rc)
3389                         break;
3390         }
3391
3392         rte_free(vnic_ids);
3393
3394         return rc;
3395 }
3396
3397 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3398                                               bool on)
3399 {
3400         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3401         struct hwrm_func_cfg_input req = {0};
3402         int rc;
3403
3404         HWRM_PREP(req, FUNC_CFG);
3405
3406         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3407         req.enables |= rte_cpu_to_le_32(
3408                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3409         req.vlan_antispoof_mode = on ?
3410                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3411                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3412         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3413
3414         HWRM_CHECK_RESULT();
3415         HWRM_UNLOCK();
3416
3417         return rc;
3418 }
3419
3420 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3421 {
3422         struct bnxt_vnic_info vnic;
3423         uint16_t *vnic_ids;
3424         size_t vnic_id_sz;
3425         int num_vnic_ids, i;
3426         size_t sz;
3427         int rc;
3428
3429         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3430         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3431                         RTE_CACHE_LINE_SIZE);
3432         if (vnic_ids == NULL) {
3433                 rc = -ENOMEM;
3434                 return rc;
3435         }
3436
3437         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3438                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3439
3440         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3441         if (rc <= 0)
3442                 goto exit;
3443         num_vnic_ids = rc;
3444
3445         /*
3446          * Loop through to find the default VNIC ID.
3447          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3448          * by sending the hwrm_func_qcfg command to the firmware.
3449          */
3450         for (i = 0; i < num_vnic_ids; i++) {
3451                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3452                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3453                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3454                                         bp->pf.first_vf_id + vf);
3455                 if (rc)
3456                         goto exit;
3457                 if (vnic.func_default) {
3458                         rte_free(vnic_ids);
3459                         return vnic.fw_vnic_id;
3460                 }
3461         }
3462         /* Could not find a default VNIC. */
3463         PMD_DRV_LOG(ERR, "No default VNIC\n");
3464 exit:
3465         rte_free(vnic_ids);
3466         return -1;
3467 }
3468
3469 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3470                          uint16_t dst_id,
3471                          struct bnxt_filter_info *filter)
3472 {
3473         int rc = 0;
3474         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3475         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3476         uint32_t enables = 0;
3477
3478         if (filter->fw_em_filter_id != UINT64_MAX)
3479                 bnxt_hwrm_clear_em_filter(bp, filter);
3480
3481         HWRM_PREP(req, CFA_EM_FLOW_ALLOC);
3482
3483         req.flags = rte_cpu_to_le_32(filter->flags);
3484
3485         enables = filter->enables |
3486               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3487         req.dst_id = rte_cpu_to_le_16(dst_id);
3488
3489         if (filter->ip_addr_type) {
3490                 req.ip_addr_type = filter->ip_addr_type;
3491                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3492         }
3493         if (enables &
3494             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3495                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3496         if (enables &
3497             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3498                 memcpy(req.src_macaddr, filter->src_macaddr,
3499                        ETHER_ADDR_LEN);
3500         if (enables &
3501             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3502                 memcpy(req.dst_macaddr, filter->dst_macaddr,
3503                        ETHER_ADDR_LEN);
3504         if (enables &
3505             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3506                 req.ovlan_vid = filter->l2_ovlan;
3507         if (enables &
3508             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3509                 req.ivlan_vid = filter->l2_ivlan;
3510         if (enables &
3511             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3512                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3513         if (enables &
3514             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3515                 req.ip_protocol = filter->ip_protocol;
3516         if (enables &
3517             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3518                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3519         if (enables &
3520             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3521                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3522         if (enables &
3523             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3524                 req.src_port = rte_cpu_to_be_16(filter->src_port);
3525         if (enables &
3526             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3527                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3528         if (enables &
3529             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3530                 req.mirror_vnic_id = filter->mirror_vnic_id;
3531
3532         req.enables = rte_cpu_to_le_32(enables);
3533
3534         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3535
3536         HWRM_CHECK_RESULT();
3537
3538         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3539         HWRM_UNLOCK();
3540
3541         return rc;
3542 }
3543
3544 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3545 {
3546         int rc = 0;
3547         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3548         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3549
3550         if (filter->fw_em_filter_id == UINT64_MAX)
3551                 return 0;
3552
3553         PMD_DRV_LOG(ERR, "Clear EM filter\n");
3554         HWRM_PREP(req, CFA_EM_FLOW_FREE);
3555
3556         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
3557
3558         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3559
3560         HWRM_CHECK_RESULT();
3561         HWRM_UNLOCK();
3562
3563         filter->fw_em_filter_id = -1;
3564         filter->fw_l2_filter_id = -1;
3565
3566         return 0;
3567 }
3568
3569 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
3570                          uint16_t dst_id,
3571                          struct bnxt_filter_info *filter)
3572 {
3573         int rc = 0;
3574         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
3575         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3576                                                 bp->hwrm_cmd_resp_addr;
3577         uint32_t enables = 0;
3578
3579         if (filter->fw_ntuple_filter_id != UINT64_MAX)
3580                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
3581
3582         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC);
3583
3584         req.flags = rte_cpu_to_le_32(filter->flags);
3585
3586         enables = filter->enables |
3587               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
3588         req.dst_id = rte_cpu_to_le_16(dst_id);
3589
3590
3591         if (filter->ip_addr_type) {
3592                 req.ip_addr_type = filter->ip_addr_type;
3593                 enables |=
3594                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3595         }
3596         if (enables &
3597             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3598                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3599         if (enables &
3600             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3601                 memcpy(req.src_macaddr, filter->src_macaddr,
3602                        ETHER_ADDR_LEN);
3603         //if (enables &
3604             //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
3605                 //memcpy(req.dst_macaddr, filter->dst_macaddr,
3606                        //ETHER_ADDR_LEN);
3607         if (enables &
3608             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
3609                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3610         if (enables &
3611             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3612                 req.ip_protocol = filter->ip_protocol;
3613         if (enables &
3614             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3615                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
3616         if (enables &
3617             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
3618                 req.src_ipaddr_mask[0] =
3619                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
3620         if (enables &
3621             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
3622                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
3623         if (enables &
3624             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
3625                 req.dst_ipaddr_mask[0] =
3626                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
3627         if (enables &
3628             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
3629                 req.src_port = rte_cpu_to_le_16(filter->src_port);
3630         if (enables &
3631             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
3632                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
3633         if (enables &
3634             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
3635                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
3636         if (enables &
3637             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
3638                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
3639         if (enables &
3640             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3641                 req.mirror_vnic_id = filter->mirror_vnic_id;
3642
3643         req.enables = rte_cpu_to_le_32(enables);
3644
3645         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3646
3647         HWRM_CHECK_RESULT();
3648
3649         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
3650         HWRM_UNLOCK();
3651
3652         return rc;
3653 }
3654
3655 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
3656                                 struct bnxt_filter_info *filter)
3657 {
3658         int rc = 0;
3659         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
3660         struct hwrm_cfa_ntuple_filter_free_output *resp =
3661                                                 bp->hwrm_cmd_resp_addr;
3662
3663         if (filter->fw_ntuple_filter_id == UINT64_MAX)
3664                 return 0;
3665
3666         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE);
3667
3668         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
3669
3670         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3671
3672         HWRM_CHECK_RESULT();
3673         HWRM_UNLOCK();
3674
3675         filter->fw_ntuple_filter_id = -1;
3676
3677         return 0;
3678 }
3679
3680 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3681 {
3682         unsigned int rss_idx, fw_idx, i;
3683
3684         if (vnic->rss_table && vnic->hash_type) {
3685                 /*
3686                  * Fill the RSS hash & redirection table with
3687                  * ring group ids for all VNICs
3688                  */
3689                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
3690                         rss_idx++, fw_idx++) {
3691                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
3692                                 fw_idx %= bp->rx_cp_nr_rings;
3693                                 if (vnic->fw_grp_ids[fw_idx] !=
3694                                     INVALID_HW_RING_ID)
3695                                         break;
3696                                 fw_idx++;
3697                         }
3698                         if (i == bp->rx_cp_nr_rings)
3699                                 return 0;
3700                         vnic->rss_table[rss_idx] =
3701                                 vnic->fw_grp_ids[fw_idx];
3702                 }
3703                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
3704         }
3705         return 0;
3706 }