drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #include <rte_io.h>
  28
  29 #define HWRM_CMD_TIMEOUT                6000000
  30 #define HWRM_SHORT_CMD_TIMEOUT          50000
  31 #define HWRM_SPEC_CODE_1_8_3            0x10803
  32 #define HWRM_VERSION_1_9_1              0x10901
  33 #define HWRM_VERSION_1_9_2              0x10903
  34
  35 struct bnxt_plcmodes_cfg {
  36         uint32_t        flags;
  37         uint16_t        jumbo_thresh;
  38         uint16_t        hds_offset;
  39         uint16_t        hds_threshold;
  40 };
  41
  42 static int page_getenum(size_t size)
  43 {
  44         if (size <= 1 << 4)
  45                 return 4;
  46         if (size <= 1 << 12)
  47                 return 12;
  48         if (size <= 1 << 13)
  49                 return 13;
  50         if (size <= 1 << 16)
  51                 return 16;
  52         if (size <= 1 << 21)
  53                 return 21;
  54         if (size <= 1 << 22)
  55                 return 22;
  56         if (size <= 1 << 30)
  57                 return 30;
  58         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  59         return sizeof(void *) * 8 - 1;
  60 }
  61
  62 static int page_roundup(size_t size)
  63 {
  64         return 1 << page_getenum(size);
  65 }
  66
  67 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  68                                   uint8_t *pg_attr,
  69                                   uint64_t *pg_dir)
  70 {
  71         if (rmem->nr_pages > 1) {
  72                 *pg_attr = 1;
  73                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  74         } else {
  75                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  76         }
  77 }
  78
  79 /*
  80  * HWRM Functions (sent to HWRM)
  81  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  82  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  83  * command was failed by the ChiMP.
  84  */
  85
  86 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  87                                   uint32_t msg_len, bool use_kong_mb)
  88 {
  89         unsigned int i;
  90         struct input *req = msg;
  91         struct output *resp = bp->hwrm_cmd_resp_addr;
  92         uint32_t *data = msg;
  93         uint8_t *bar;
  94         uint8_t *valid;
  95         uint16_t max_req_len = bp->max_req_len;
  96         struct hwrm_short_input short_input = { 0 };
  97         uint16_t bar_offset = use_kong_mb ?
  98                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  99         uint16_t mb_trigger_offset = use_kong_mb ?
 100                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 101         uint32_t timeout;
 102
 103         /* Do not send HWRM commands to firmware in error state */
 104         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 105                 return 0;
 106
 107         /* For VER_GET command, set timeout as 50ms */
 108         if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 109                 timeout = HWRM_SHORT_CMD_TIMEOUT;
 110         else
 111                 timeout = HWRM_CMD_TIMEOUT;
 112
 113         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 114             msg_len > bp->max_req_len) {
 115                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 116
 117                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 118                 memcpy(short_cmd_req, req, msg_len);
 119
 120                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 121                 short_input.signature = rte_cpu_to_le_16(
 122                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 123                 short_input.size = rte_cpu_to_le_16(msg_len);
 124                 short_input.req_addr =
 125                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 126
 127                 data = (uint32_t *)&short_input;
 128                 msg_len = sizeof(short_input);
 129
 130                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 131         }
 132
 133         /* Write request msg to hwrm channel */
 134         for (i = 0; i < msg_len; i += 4) {
 135                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 136                 rte_write32(*data, bar);
 137                 data++;
 138         }
 139
 140         /* Zero the rest of the request space */
 141         for (; i < max_req_len; i += 4) {
 142                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 143                 rte_write32(0, bar);
 144         }
 145
 146         /* Ring channel doorbell */
 147         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 148         rte_write32(1, bar);
 149         /*
 150          * Make sure the channel doorbell ring command complete before
 151          * reading the response to avoid getting stale or invalid
 152          * responses.
 153          */
 154         rte_io_mb();
 155
 156         /* Poll for the valid bit */
 157         for (i = 0; i < timeout; i++) {
 158                 /* Sanity check on the resp->resp_len */
 159                 rte_cio_rmb();
 160                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 161                         /* Last byte of resp contains the valid key */
 162                         valid = (uint8_t *)resp + resp->resp_len - 1;
 163                         if (*valid == HWRM_RESP_VALID_KEY)
 164                                 break;
 165                 }
 166                 rte_delay_us(1);
 167         }
 168
 169         if (i >= timeout) {
 170                 /* Suppress VER_GET timeout messages during reset recovery */
 171                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 172                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 173                         return -ETIMEDOUT;
 174
 175                 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
 176                             req->req_type);
 177                 return -ETIMEDOUT;
 178         }
 179         return 0;
 180 }
 181
 182 /*
 183  * HWRM_PREP() should be used to prepare *ALL* HWRM commands.  It grabs the
 184  * spinlock, and does initial processing.
 185  *
 186  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 187  * releases the spinlock only if it returns.  If the regular int return codes
 188  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 189  * directly, rather it should be copied and modified to suit the function.
 190  *
 191  * HWRM_UNLOCK() must be called after all response processing is completed.
 192  */
 193 #define HWRM_PREP(req, type, kong) do { \
 194         rte_spinlock_lock(&bp->hwrm_lock); \
 195         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 196         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 197         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 198         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 199                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 200         req.target_id = rte_cpu_to_le_16(0xffff); \
 201         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 202 } while (0)
 203
 204 #define HWRM_CHECK_RESULT_SILENT() do {\
 205         if (rc) { \
 206                 rte_spinlock_unlock(&bp->hwrm_lock); \
 207                 return rc; \
 208         } \
 209         if (resp->error_code) { \
 210                 rc = rte_le_to_cpu_16(resp->error_code); \
 211                 rte_spinlock_unlock(&bp->hwrm_lock); \
 212                 return rc; \
 213         } \
 214 } while (0)
 215
 216 #define HWRM_CHECK_RESULT() do {\
 217         if (rc) { \
 218                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 219                 rte_spinlock_unlock(&bp->hwrm_lock); \
 220                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 221                         rc = -EACCES; \
 222                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 223                         rc = -ENOSPC; \
 224                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 225                         rc = -EINVAL; \
 226                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 227                         rc = -ENOTSUP; \
 228                 else if (rc > 0) \
 229                         rc = -EIO; \
 230                 return rc; \
 231         } \
 232         if (resp->error_code) { \
 233                 rc = rte_le_to_cpu_16(resp->error_code); \
 234                 if (resp->resp_len >= 16) { \
 235                         struct hwrm_err_output *tmp_hwrm_err_op = \
 236                                                 (void *)resp; \
 237                         PMD_DRV_LOG(ERR, \
 238                                 "error %d:%d:%08x:%04x\n", \
 239                                 rc, tmp_hwrm_err_op->cmd_err, \
 240                                 rte_le_to_cpu_32(\
 241                                         tmp_hwrm_err_op->opaque_0), \
 242                                 rte_le_to_cpu_16(\
 243                                         tmp_hwrm_err_op->opaque_1)); \
 244                 } else { \
 245                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 246                 } \
 247                 rte_spinlock_unlock(&bp->hwrm_lock); \
 248                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 249                         rc = -EACCES; \
 250                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 251                         rc = -ENOSPC; \
 252                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 253                         rc = -EINVAL; \
 254                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 255                         rc = -ENOTSUP; \
 256                 else if (rc > 0) \
 257                         rc = -EIO; \
 258                 return rc; \
 259         } \
 260 } while (0)
 261
 262 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 263
 264 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 265 {
 266         int rc = 0;
 267         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 268         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 269
 270         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 271         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 272         req.mask = 0;
 273
 274         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 275
 276         HWRM_CHECK_RESULT();
 277         HWRM_UNLOCK();
 278
 279         return rc;
 280 }
 281
 282 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 283                                  struct bnxt_vnic_info *vnic,
 284                                  uint16_t vlan_count,
 285                                  struct bnxt_vlan_table_entry *vlan_table)
 286 {
 287         int rc = 0;
 288         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 289         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 290         uint32_t mask = 0;
 291
 292         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 293                 return rc;
 294
 295         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 296         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 297
 298         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 299                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 300         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 301                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 302
 303         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 304                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 305
 306         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 307                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 308         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 309                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 310                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 311                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 312         }
 313         if (vlan_table) {
 314                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 315                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 316                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 317                          rte_mem_virt2iova(vlan_table));
 318                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 319         }
 320         req.mask = rte_cpu_to_le_32(mask);
 321
 322         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 323
 324         HWRM_CHECK_RESULT();
 325         HWRM_UNLOCK();
 326
 327         return rc;
 328 }
 329
 330 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 331                         uint16_t vlan_count,
 332                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 333 {
 334         int rc = 0;
 335         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 336         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 337                                                 bp->hwrm_cmd_resp_addr;
 338
 339         /*
 340          * Older HWRM versions did not support this command, and the set_rx_mask
 341          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 342          * removed from set_rx_mask call, and this command was added.
 343          *
 344          * This command is also present from 1.7.8.11 and higher,
 345          * as well as 1.7.8.0
 346          */
 347         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 348                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 349                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 350                                         (11)))
 351                                 return 0;
 352                 }
 353         }
 354         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 355         req.fid = rte_cpu_to_le_16(fid);
 356
 357         req.vlan_tag_mask_tbl_addr =
 358                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 359         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 360
 361         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 362
 363         HWRM_CHECK_RESULT();
 364         HWRM_UNLOCK();
 365
 366         return rc;
 367 }
 368
 369 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 370                            struct bnxt_filter_info *filter)
 371 {
 372         int rc = 0;
 373         struct bnxt_filter_info *l2_filter = filter;
 374         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 375         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 376
 377         if (filter->fw_l2_filter_id == UINT64_MAX)
 378                 return 0;
 379
 380         if (filter->matching_l2_fltr_ptr)
 381                 l2_filter = filter->matching_l2_fltr_ptr;
 382
 383         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 384                     filter, l2_filter, l2_filter->l2_ref_cnt);
 385
 386         if (l2_filter->l2_ref_cnt > 0)
 387                 l2_filter->l2_ref_cnt--;
 388
 389         if (l2_filter->l2_ref_cnt > 0)
 390                 return 0;
 391
 392         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 393
 394         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 395
 396         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 397
 398         HWRM_CHECK_RESULT();
 399         HWRM_UNLOCK();
 400
 401         filter->fw_l2_filter_id = UINT64_MAX;
 402
 403         return 0;
 404 }
 405
 406 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 407                          uint16_t dst_id,
 408                          struct bnxt_filter_info *filter)
 409 {
 410         int rc = 0;
 411         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 412         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 413         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 414         const struct rte_eth_vmdq_rx_conf *conf =
 415                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 416         uint32_t enables = 0;
 417         uint16_t j = dst_id - 1;
 418
 419         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 420         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 421             conf->pool_map[j].pools & (1UL << j)) {
 422                 PMD_DRV_LOG(DEBUG,
 423                         "Add vlan %u to vmdq pool %u\n",
 424                         conf->pool_map[j].vlan_id, j);
 425
 426                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 427                 filter->enables |=
 428                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 429                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 430         }
 431
 432         if (filter->fw_l2_filter_id != UINT64_MAX)
 433                 bnxt_hwrm_clear_l2_filter(bp, filter);
 434
 435         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 436
 437         req.flags = rte_cpu_to_le_32(filter->flags);
 438
 439         enables = filter->enables |
 440               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 441         req.dst_id = rte_cpu_to_le_16(dst_id);
 442
 443         if (enables &
 444             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 445                 memcpy(req.l2_addr, filter->l2_addr,
 446                        RTE_ETHER_ADDR_LEN);
 447         if (enables &
 448             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 449                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 450                        RTE_ETHER_ADDR_LEN);
 451         if (enables &
 452             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 453                 req.l2_ovlan = filter->l2_ovlan;
 454         if (enables &
 455             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 456                 req.l2_ivlan = filter->l2_ivlan;
 457         if (enables &
 458             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 459                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 460         if (enables &
 461             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 462                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 463         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 464                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 465         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 466                 req.src_type = filter->src_type;
 467         if (filter->pri_hint) {
 468                 req.pri_hint = filter->pri_hint;
 469                 req.l2_filter_id_hint =
 470                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 471         }
 472
 473         req.enables = rte_cpu_to_le_32(enables);
 474
 475         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 476
 477         HWRM_CHECK_RESULT();
 478
 479         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 480         HWRM_UNLOCK();
 481
 482         return rc;
 483 }
 484
 485 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 486 {
 487         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 488         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 489         uint32_t flags = 0;
 490         int rc;
 491
 492         if (!ptp)
 493                 return 0;
 494
 495         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 496
 497         if (ptp->rx_filter)
 498                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 499         else
 500                 flags |=
 501                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 502         if (ptp->tx_tstamp_en)
 503                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 504         else
 505                 flags |=
 506                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 507         req.flags = rte_cpu_to_le_32(flags);
 508         req.enables = rte_cpu_to_le_32
 509                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 510         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 511
 512         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 513         HWRM_UNLOCK();
 514
 515         return rc;
 516 }
 517
 518 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 519 {
 520         int rc = 0;
 521         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 522         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 523         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 524
 525 /*      if (bp->hwrm_spec_code < 0x10801 || ptp)  TBD  */
 526         if (ptp)
 527                 return 0;
 528
 529         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 530
 531         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 532
 533         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 534
 535         HWRM_CHECK_RESULT();
 536
 537         if (!BNXT_CHIP_THOR(bp) &&
 538             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 539                 return 0;
 540
 541         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 542                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 543
 544         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 545         if (!ptp)
 546                 return -ENOMEM;
 547
 548         if (!BNXT_CHIP_THOR(bp)) {
 549                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 550                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 551                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 552                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 553                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 554                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 555                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 556                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 557                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 558                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 559                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 560                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 561                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 562                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 563                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 564                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 565                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 566                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 567         }
 568
 569         ptp->bp = bp;
 570         bp->ptp_cfg = ptp;
 571
 572         return 0;
 573 }
 574
 575 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 576 {
 577         int rc = 0;
 578         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 579         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 580         uint16_t new_max_vfs;
 581         uint32_t flags;
 582         int i;
 583
 584         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 585
 586         req.fid = rte_cpu_to_le_16(0xffff);
 587
 588         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 589
 590         HWRM_CHECK_RESULT();
 591
 592         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 593         flags = rte_le_to_cpu_32(resp->flags);
 594         if (BNXT_PF(bp)) {
 595                 bp->pf.port_id = resp->port_id;
 596                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 597                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 598                 new_max_vfs = bp->pdev->max_vfs;
 599                 if (new_max_vfs != bp->pf.max_vfs) {
 600                         if (bp->pf.vf_info)
 601                                 rte_free(bp->pf.vf_info);
 602                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 603                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 604                         bp->pf.max_vfs = new_max_vfs;
 605                         for (i = 0; i < new_max_vfs; i++) {
 606                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 607                                 bp->pf.vf_info[i].vlan_table =
 608                                         rte_zmalloc("VF VLAN table",
 609                                                     getpagesize(),
 610                                                     getpagesize());
 611                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 612                                         PMD_DRV_LOG(ERR,
 613                                         "Fail to alloc VLAN table for VF %d\n",
 614                                         i);
 615                                 else
 616                                         rte_mem_lock_page(
 617                                                 bp->pf.vf_info[i].vlan_table);
 618                                 bp->pf.vf_info[i].vlan_as_table =
 619                                         rte_zmalloc("VF VLAN AS table",
 620                                                     getpagesize(),
 621                                                     getpagesize());
 622                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 623                                         PMD_DRV_LOG(ERR,
 624                                         "Alloc VLAN AS table for VF %d fail\n",
 625                                         i);
 626                                 else
 627                                         rte_mem_lock_page(
 628                                                bp->pf.vf_info[i].vlan_as_table);
 629                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 630                         }
 631                 }
 632         }
 633
 634         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 635         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 636         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 637         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 638         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 639         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 640         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 641         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 642         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 643         if (!BNXT_CHIP_THOR(bp))
 644                 bp->max_l2_ctx += bp->max_rx_em_flows;
 645         /* TODO: For now, do not support VMDq/RFS on VFs. */
 646         if (BNXT_PF(bp)) {
 647                 if (bp->pf.max_vfs)
 648                         bp->max_vnics = 1;
 649                 else
 650                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 651         } else {
 652                 bp->max_vnics = 1;
 653         }
 654         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 655         if (BNXT_PF(bp)) {
 656                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 657                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 658                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 659                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 660                         HWRM_UNLOCK();
 661                         bnxt_hwrm_ptp_qcfg(bp);
 662                 }
 663         }
 664
 665         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 666                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 667
 668         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 669                 bp->flags |= BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
 670                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 671         } else {
 672                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
 673         }
 674
 675         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 676                 bp->flags |= BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
 677         else
 678                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
 679
 680         HWRM_UNLOCK();
 681
 682         return rc;
 683 }
 684
 685 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 686 {
 687         int rc;
 688
 689         rc = __bnxt_hwrm_func_qcaps(bp);
 690         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 691                 rc = bnxt_alloc_ctx_mem(bp);
 692                 if (rc)
 693                         return rc;
 694
 695                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 696                 if (!rc)
 697                         bp->flags |= BNXT_FLAG_NEW_RM;
 698         }
 699
 700         return rc;
 701 }
 702
 703 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 704 {
 705         int rc = 0;
 706         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 707         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 708
 709         HWRM_PREP(req, VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 710
 711         req.target_id = rte_cpu_to_le_16(0xffff);
 712
 713         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 714
 715         HWRM_CHECK_RESULT();
 716
 717         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 718
 719         HWRM_UNLOCK();
 720
 721         return rc;
 722 }
 723
 724 int bnxt_hwrm_func_reset(struct bnxt *bp)
 725 {
 726         int rc = 0;
 727         struct hwrm_func_reset_input req = {.req_type = 0 };
 728         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 729
 730         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 731
 732         req.enables = rte_cpu_to_le_32(0);
 733
 734         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 735
 736         HWRM_CHECK_RESULT();
 737         HWRM_UNLOCK();
 738
 739         return rc;
 740 }
 741
 742 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 743 {
 744         int rc;
 745         uint32_t flags = 0;
 746         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 747         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 748
 749         if (bp->flags & BNXT_FLAG_REGISTERED)
 750                 return 0;
 751
 752         flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 753         if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
 754                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 755
 756         /* PFs and trusted VFs should indicate the support of the
 757          * Master capability on non Stingray platform
 758          */
 759         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 760                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 761
 762         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 763         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 764                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 765         req.ver_maj = RTE_VER_YEAR;
 766         req.ver_min = RTE_VER_MONTH;
 767         req.ver_upd = RTE_VER_MINOR;
 768
 769         if (BNXT_PF(bp)) {
 770                 req.enables |= rte_cpu_to_le_32(
 771                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 772                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 773                        RTE_MIN(sizeof(req.vf_req_fwd),
 774                                sizeof(bp->pf.vf_req_fwd)));
 775
 776                 /*
 777                  * PF can sniff HWRM API issued by VF. This can be set up by
 778                  * linux driver and inherited by the DPDK PF driver. Clear
 779                  * this HWRM sniffer list in FW because DPDK PF driver does
 780                  * not support this.
 781                  */
 782                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 783         }
 784
 785         req.flags = rte_cpu_to_le_32(flags);
 786
 787         req.async_event_fwd[0] |=
 788                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 789                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 790                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 791                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 792                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 793         if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
 794                 req.async_event_fwd[0] |=
 795                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 796         req.async_event_fwd[1] |=
 797                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 798                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 799
 800         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 801
 802         HWRM_CHECK_RESULT();
 803
 804         flags = rte_le_to_cpu_32(resp->flags);
 805         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 806                 bp->flags |= BNXT_FLAG_FW_CAP_IF_CHANGE;
 807
 808         HWRM_UNLOCK();
 809
 810         bp->flags |= BNXT_FLAG_REGISTERED;
 811
 812         return rc;
 813 }
 814
 815 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 816 {
 817         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 818                 return 0;
 819
 820         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 821 }
 822
 823 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 824 {
 825         int rc;
 826         uint32_t flags = 0;
 827         uint32_t enables;
 828         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 829         struct hwrm_func_vf_cfg_input req = {0};
 830
 831         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 832
 833         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 834                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 835                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 836                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 837                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 838
 839         if (BNXT_HAS_RING_GRPS(bp)) {
 840                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 841                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 842         }
 843
 844         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 845         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 846                                             AGG_RING_MULTIPLIER);
 847         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings +
 848                                              bp->tx_nr_rings +
 849                                              BNXT_NUM_ASYNC_CPR(bp));
 850         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 851                                               bp->tx_nr_rings +
 852                                               BNXT_NUM_ASYNC_CPR(bp));
 853         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 854         if (bp->vf_resv_strategy ==
 855             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 856                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 857                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 858                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 859                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 860                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 861                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 862         }
 863
 864         if (test)
 865                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 866                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 867                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 868                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 869                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 870                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 871
 872         if (test && BNXT_HAS_RING_GRPS(bp))
 873                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 874
 875         req.flags = rte_cpu_to_le_32(flags);
 876         req.enables |= rte_cpu_to_le_32(enables);
 877
 878         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 879
 880         if (test)
 881                 HWRM_CHECK_RESULT_SILENT();
 882         else
 883                 HWRM_CHECK_RESULT();
 884
 885         HWRM_UNLOCK();
 886         return rc;
 887 }
 888
 889 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 890 {
 891         int rc;
 892         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 893         struct hwrm_func_resource_qcaps_input req = {0};
 894
 895         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 896         req.fid = rte_cpu_to_le_16(0xffff);
 897
 898         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 899
 900         HWRM_CHECK_RESULT();
 901
 902         if (BNXT_VF(bp)) {
 903                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 904                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 905                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 906                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 907                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 908                 /* func_resource_qcaps does not return max_rx_em_flows.
 909                  * So use the value provided by func_qcaps.
 910                  */
 911                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 912                 if (!BNXT_CHIP_THOR(bp))
 913                         bp->max_l2_ctx += bp->max_rx_em_flows;
 914                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 915                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 916         }
 917         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 918         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 919         if (bp->vf_resv_strategy >
 920             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 921                 bp->vf_resv_strategy =
 922                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 923
 924         HWRM_UNLOCK();
 925         return rc;
 926 }
 927
 928 int bnxt_hwrm_ver_get(struct bnxt *bp)
 929 {
 930         int rc = 0;
 931         struct hwrm_ver_get_input req = {.req_type = 0 };
 932         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 933         uint32_t fw_version;
 934         uint16_t max_resp_len;
 935         char type[RTE_MEMZONE_NAMESIZE];
 936         uint32_t dev_caps_cfg;
 937
 938         bp->max_req_len = HWRM_MAX_REQ_LEN;
 939         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 940
 941         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 942         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 943         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 944
 945         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 946
 947         if (bp->flags & BNXT_FLAG_FW_RESET)
 948                 HWRM_CHECK_RESULT_SILENT();
 949         else
 950                 HWRM_CHECK_RESULT();
 951
 952         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 953                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 954                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 955                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 956         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 957                      (resp->hwrm_fw_min_8b << 16) |
 958                      (resp->hwrm_fw_bld_8b << 8) |
 959                      resp->hwrm_fw_rsvd_8b;
 960         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 961                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 962
 963         fw_version = resp->hwrm_intf_maj_8b << 16;
 964         fw_version |= resp->hwrm_intf_min_8b << 8;
 965         fw_version |= resp->hwrm_intf_upd_8b;
 966         bp->hwrm_spec_code = fw_version;
 967
 968         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
 969                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 970                 rc = -EINVAL;
 971                 goto error;
 972         }
 973
 974         if (bp->max_req_len > resp->max_req_win_len) {
 975                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
 976                 rc = -EINVAL;
 977         }
 978         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 979         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
 980         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
 981                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
 982
 983         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
 984         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 985
 986         if (bp->max_resp_len != max_resp_len) {
 987                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 988                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 989                         bp->pdev->addr.devid, bp->pdev->addr.function);
 990
 991                 rte_free(bp->hwrm_cmd_resp_addr);
 992
 993                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 994                 if (bp->hwrm_cmd_resp_addr == NULL) {
 995                         rc = -ENOMEM;
 996                         goto error;
 997                 }
 998                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
 999                 bp->hwrm_cmd_resp_dma_addr =
1000                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1001                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1002                         PMD_DRV_LOG(ERR,
1003                         "Unable to map response buffer to physical memory.\n");
1004                         rc = -ENOMEM;
1005                         goto error;
1006                 }
1007                 bp->max_resp_len = max_resp_len;
1008         }
1009
1010         if ((dev_caps_cfg &
1011                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1012             (dev_caps_cfg &
1013              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1014                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1015                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1016         }
1017
1018         if (((dev_caps_cfg &
1019               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1020              (dev_caps_cfg &
1021               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1022             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1023                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
1024                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1025                         bp->pdev->addr.devid, bp->pdev->addr.function);
1026
1027                 rte_free(bp->hwrm_short_cmd_req_addr);
1028
1029                 bp->hwrm_short_cmd_req_addr =
1030                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1031                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1032                         rc = -ENOMEM;
1033                         goto error;
1034                 }
1035                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
1036                 bp->hwrm_short_cmd_req_dma_addr =
1037                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
1038                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1039                         rte_free(bp->hwrm_short_cmd_req_addr);
1040                         PMD_DRV_LOG(ERR,
1041                                 "Unable to map buffer to physical memory.\n");
1042                         rc = -ENOMEM;
1043                         goto error;
1044                 }
1045         }
1046         if (dev_caps_cfg &
1047             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1048                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1049                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1050         }
1051         if (dev_caps_cfg &
1052             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1053                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1054         if (dev_caps_cfg &
1055             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1056                 bp->flags |= BNXT_FLAG_ADV_FLOW_MGMT;
1057                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1058         }
1059
1060 error:
1061         HWRM_UNLOCK();
1062         return rc;
1063 }
1064
1065 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1066 {
1067         int rc;
1068         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1069         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1070
1071         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1072                 return 0;
1073
1074         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1075         req.flags = flags;
1076
1077         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1078
1079         HWRM_CHECK_RESULT();
1080         HWRM_UNLOCK();
1081
1082         return rc;
1083 }
1084
1085 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1086 {
1087         int rc = 0;
1088         struct hwrm_port_phy_cfg_input req = {0};
1089         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1090         uint32_t enables = 0;
1091
1092         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1093
1094         if (conf->link_up) {
1095                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1096                 if (bp->link_info.auto_mode && conf->link_speed) {
1097                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1098                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1099                 }
1100
1101                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1102                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1103                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1104                 /*
1105                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1106                  * any auto mode, even "none".
1107                  */
1108                 if (!conf->link_speed) {
1109                         /* No speeds specified. Enable AutoNeg - all speeds */
1110                         req.auto_mode =
1111                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1112                 }
1113                 /* AutoNeg - Advertise speeds specified. */
1114                 if (conf->auto_link_speed_mask &&
1115                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1116                         req.auto_mode =
1117                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1118                         req.auto_link_speed_mask =
1119                                 conf->auto_link_speed_mask;
1120                         enables |=
1121                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1122                 }
1123
1124                 req.auto_duplex = conf->duplex;
1125                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1126                 req.auto_pause = conf->auto_pause;
1127                 req.force_pause = conf->force_pause;
1128                 /* Set force_pause if there is no auto or if there is a force */
1129                 if (req.auto_pause && !req.force_pause)
1130                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1131                 else
1132                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1133
1134                 req.enables = rte_cpu_to_le_32(enables);
1135         } else {
1136                 req.flags =
1137                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1138                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1139         }
1140
1141         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1142
1143         HWRM_CHECK_RESULT();
1144         HWRM_UNLOCK();
1145
1146         return rc;
1147 }
1148
1149 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1150                                    struct bnxt_link_info *link_info)
1151 {
1152         int rc = 0;
1153         struct hwrm_port_phy_qcfg_input req = {0};
1154         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1155
1156         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1157
1158         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1159
1160         HWRM_CHECK_RESULT();
1161
1162         link_info->phy_link_status = resp->link;
1163         link_info->link_up =
1164                 (link_info->phy_link_status ==
1165                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1166         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1167         link_info->duplex = resp->duplex_cfg;
1168         link_info->pause = resp->pause;
1169         link_info->auto_pause = resp->auto_pause;
1170         link_info->force_pause = resp->force_pause;
1171         link_info->auto_mode = resp->auto_mode;
1172         link_info->phy_type = resp->phy_type;
1173         link_info->media_type = resp->media_type;
1174
1175         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1176         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1177         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1178         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1179         link_info->phy_ver[0] = resp->phy_maj;
1180         link_info->phy_ver[1] = resp->phy_min;
1181         link_info->phy_ver[2] = resp->phy_bld;
1182
1183         HWRM_UNLOCK();
1184
1185         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1186         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1187         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1188         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1189         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1190                     link_info->auto_link_speed_mask);
1191         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1192                     link_info->force_link_speed);
1193
1194         return rc;
1195 }
1196
1197 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1198 {
1199         int rc = 0;
1200         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1201         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1202         int i;
1203
1204         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1205
1206         req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1207         /* HWRM Version >= 1.9.1 */
1208         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1209                 req.drv_qmap_cap =
1210                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1211         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1212
1213         HWRM_CHECK_RESULT();
1214
1215 #define GET_QUEUE_INFO(x) \
1216         bp->cos_queue[x].id = resp->queue_id##x; \
1217         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1218
1219         GET_QUEUE_INFO(0);
1220         GET_QUEUE_INFO(1);
1221         GET_QUEUE_INFO(2);
1222         GET_QUEUE_INFO(3);
1223         GET_QUEUE_INFO(4);
1224         GET_QUEUE_INFO(5);
1225         GET_QUEUE_INFO(6);
1226         GET_QUEUE_INFO(7);
1227
1228         HWRM_UNLOCK();
1229
1230         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1231                 bp->tx_cosq_id = bp->cos_queue[0].id;
1232         } else {
1233                 /* iterate and find the COSq profile to use for Tx */
1234                 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1235                         if (bp->cos_queue[i].profile ==
1236                                 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1237                                 bp->tx_cosq_id = bp->cos_queue[i].id;
1238                                 break;
1239                         }
1240                 }
1241         }
1242
1243         bp->max_tc = resp->max_configurable_queues;
1244         bp->max_lltc = resp->max_configurable_lossless_queues;
1245         if (bp->max_tc > BNXT_MAX_QUEUE)
1246                 bp->max_tc = BNXT_MAX_QUEUE;
1247         bp->max_q = bp->max_tc;
1248
1249         PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1250
1251         return rc;
1252 }
1253
1254 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1255                          struct bnxt_ring *ring,
1256                          uint32_t ring_type, uint32_t map_index,
1257                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1258 {
1259         int rc = 0;
1260         uint32_t enables = 0;
1261         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1262         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1263         struct rte_mempool *mb_pool;
1264         uint16_t rx_buf_size;
1265
1266         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1267
1268         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1269         req.fbo = rte_cpu_to_le_32(0);
1270         /* Association of ring index with doorbell index */
1271         req.logical_id = rte_cpu_to_le_16(map_index);
1272         req.length = rte_cpu_to_le_32(ring->ring_size);
1273
1274         switch (ring_type) {
1275         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1276                 req.ring_type = ring_type;
1277                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1278                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1279                 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1280                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1281                         enables |=
1282                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1283                 break;
1284         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1285                 req.ring_type = ring_type;
1286                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1287                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1288                 if (BNXT_CHIP_THOR(bp)) {
1289                         mb_pool = bp->rx_queues[0]->mb_pool;
1290                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1291                                       RTE_PKTMBUF_HEADROOM;
1292                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1293                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1294                         enables |=
1295                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1296                 }
1297                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1298                         enables |=
1299                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1300                 break;
1301         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1302                 req.ring_type = ring_type;
1303                 if (BNXT_HAS_NQ(bp)) {
1304                         /* Association of cp ring with nq */
1305                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1306                         enables |=
1307                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1308                 }
1309                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1310                 break;
1311         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1312                 req.ring_type = ring_type;
1313                 req.page_size = BNXT_PAGE_SHFT;
1314                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1315                 break;
1316         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1317                 req.ring_type = ring_type;
1318                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1319
1320                 mb_pool = bp->rx_queues[0]->mb_pool;
1321                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1322                               RTE_PKTMBUF_HEADROOM;
1323                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1324                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1325
1326                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1327                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1328                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1329                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1330                 break;
1331         default:
1332                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1333                         ring_type);
1334                 HWRM_UNLOCK();
1335                 return -EINVAL;
1336         }
1337         req.enables = rte_cpu_to_le_32(enables);
1338
1339         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1340
1341         if (rc || resp->error_code) {
1342                 if (rc == 0 && resp->error_code)
1343                         rc = rte_le_to_cpu_16(resp->error_code);
1344                 switch (ring_type) {
1345                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1346                         PMD_DRV_LOG(ERR,
1347                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1348                         HWRM_UNLOCK();
1349                         return rc;
1350                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1351                         PMD_DRV_LOG(ERR,
1352                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1353                         HWRM_UNLOCK();
1354                         return rc;
1355                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1356                         PMD_DRV_LOG(ERR,
1357                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1358                                     rc);
1359                         HWRM_UNLOCK();
1360                         return rc;
1361                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1362                         PMD_DRV_LOG(ERR,
1363                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1364                         HWRM_UNLOCK();
1365                         return rc;
1366                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1367                         PMD_DRV_LOG(ERR,
1368                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1369                         HWRM_UNLOCK();
1370                         return rc;
1371                 default:
1372                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1373                         HWRM_UNLOCK();
1374                         return rc;
1375                 }
1376         }
1377
1378         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1379         HWRM_UNLOCK();
1380         return rc;
1381 }
1382
1383 int bnxt_hwrm_ring_free(struct bnxt *bp,
1384                         struct bnxt_ring *ring, uint32_t ring_type)
1385 {
1386         int rc;
1387         struct hwrm_ring_free_input req = {.req_type = 0 };
1388         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1389
1390         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1391
1392         req.ring_type = ring_type;
1393         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1394
1395         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1396
1397         if (rc || resp->error_code) {
1398                 if (rc == 0 && resp->error_code)
1399                         rc = rte_le_to_cpu_16(resp->error_code);
1400                 HWRM_UNLOCK();
1401
1402                 switch (ring_type) {
1403                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1404                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1405                                 rc);
1406                         return rc;
1407                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1408                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1409                                 rc);
1410                         return rc;
1411                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1412                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1413                                 rc);
1414                         return rc;
1415                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1416                         PMD_DRV_LOG(ERR,
1417                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1418                         return rc;
1419                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1420                         PMD_DRV_LOG(ERR,
1421                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1422                         return rc;
1423                 default:
1424                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1425                         return rc;
1426                 }
1427         }
1428         HWRM_UNLOCK();
1429         return 0;
1430 }
1431
1432 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1433 {
1434         int rc = 0;
1435         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1436         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1437
1438         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1439
1440         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1441         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1442         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1443         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1444
1445         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1446
1447         HWRM_CHECK_RESULT();
1448
1449         bp->grp_info[idx].fw_grp_id =
1450             rte_le_to_cpu_16(resp->ring_group_id);
1451
1452         HWRM_UNLOCK();
1453
1454         return rc;
1455 }
1456
1457 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1458 {
1459         int rc;
1460         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1461         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1462
1463         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1464
1465         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1466
1467         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1468
1469         HWRM_CHECK_RESULT();
1470         HWRM_UNLOCK();
1471
1472         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1473         return rc;
1474 }
1475
1476 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1477 {
1478         int rc = 0;
1479         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1480         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1481
1482         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1483                 return rc;
1484
1485         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1486
1487         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1488
1489         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1490
1491         HWRM_CHECK_RESULT();
1492         HWRM_UNLOCK();
1493
1494         return rc;
1495 }
1496
1497 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1498                                 unsigned int idx __rte_unused)
1499 {
1500         int rc;
1501         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1502         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1503
1504         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1505
1506         req.update_period_ms = rte_cpu_to_le_32(0);
1507
1508         req.stats_dma_addr =
1509             rte_cpu_to_le_64(cpr->hw_stats_map);
1510
1511         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1512
1513         HWRM_CHECK_RESULT();
1514
1515         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1516
1517         HWRM_UNLOCK();
1518
1519         return rc;
1520 }
1521
1522 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1523                                 unsigned int idx __rte_unused)
1524 {
1525         int rc;
1526         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1527         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1528
1529         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1530
1531         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1532
1533         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1534
1535         HWRM_CHECK_RESULT();
1536         HWRM_UNLOCK();
1537
1538         return rc;
1539 }
1540
1541 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1542 {
1543         int rc = 0, i, j;
1544         struct hwrm_vnic_alloc_input req = { 0 };
1545         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1546
1547         if (!BNXT_HAS_RING_GRPS(bp))
1548                 goto skip_ring_grps;
1549
1550         /* map ring groups to this vnic */
1551         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1552                 vnic->start_grp_id, vnic->end_grp_id);
1553         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1554                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1555
1556         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1557         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1558         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1559         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1560
1561 skip_ring_grps:
1562         vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1563                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1564         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1565
1566         if (vnic->func_default)
1567                 req.flags =
1568                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1569         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1570
1571         HWRM_CHECK_RESULT();
1572
1573         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1574         HWRM_UNLOCK();
1575         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1576         return rc;
1577 }
1578
1579 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1580                                         struct bnxt_vnic_info *vnic,
1581                                         struct bnxt_plcmodes_cfg *pmode)
1582 {
1583         int rc = 0;
1584         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1585         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1586
1587         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1588
1589         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1590
1591         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1592
1593         HWRM_CHECK_RESULT();
1594
1595         pmode->flags = rte_le_to_cpu_32(resp->flags);
1596         /* dflt_vnic bit doesn't exist in the _cfg command */
1597         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1598         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1599         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1600         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1601
1602         HWRM_UNLOCK();
1603
1604         return rc;
1605 }
1606
1607 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1608                                        struct bnxt_vnic_info *vnic,
1609                                        struct bnxt_plcmodes_cfg *pmode)
1610 {
1611         int rc = 0;
1612         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1613         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1614
1615         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1616                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1617                 return rc;
1618         }
1619
1620         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1621
1622         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1623         req.flags = rte_cpu_to_le_32(pmode->flags);
1624         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1625         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1626         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1627         req.enables = rte_cpu_to_le_32(
1628             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1629             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1630             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1631         );
1632
1633         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1634
1635         HWRM_CHECK_RESULT();
1636         HWRM_UNLOCK();
1637
1638         return rc;
1639 }
1640
1641 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1642 {
1643         int rc = 0;
1644         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1645         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1646         struct bnxt_plcmodes_cfg pmodes = { 0 };
1647         uint32_t ctx_enable_flag = 0;
1648         uint32_t enables = 0;
1649
1650         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1651                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1652                 return rc;
1653         }
1654
1655         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1656         if (rc)
1657                 return rc;
1658
1659         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1660
1661         if (BNXT_CHIP_THOR(bp)) {
1662                 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1663                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1664                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1665
1666                 req.default_rx_ring_id =
1667                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1668                 req.default_cmpl_ring_id =
1669                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1670                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1671                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1672                 goto config_mru;
1673         }
1674
1675         /* Only RSS support for now TBD: COS & LB */
1676         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1677         if (vnic->lb_rule != 0xffff)
1678                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1679         if (vnic->cos_rule != 0xffff)
1680                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1681         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1682                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1683                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1684         }
1685         enables |= ctx_enable_flag;
1686         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1687         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1688         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1689         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1690
1691 config_mru:
1692         req.enables = rte_cpu_to_le_32(enables);
1693         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1694         req.mru = rte_cpu_to_le_16(vnic->mru);
1695         /* Configure default VNIC only once. */
1696         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1697                 req.flags |=
1698                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1699                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1700         }
1701         if (vnic->vlan_strip)
1702                 req.flags |=
1703                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1704         if (vnic->bd_stall)
1705                 req.flags |=
1706                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1707         if (vnic->roce_dual)
1708                 req.flags |= rte_cpu_to_le_32(
1709                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1710         if (vnic->roce_only)
1711                 req.flags |= rte_cpu_to_le_32(
1712                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1713         if (vnic->rss_dflt_cr)
1714                 req.flags |= rte_cpu_to_le_32(
1715                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1716
1717         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1718
1719         HWRM_CHECK_RESULT();
1720         HWRM_UNLOCK();
1721
1722         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1723
1724         return rc;
1725 }
1726
1727 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1728                 int16_t fw_vf_id)
1729 {
1730         int rc = 0;
1731         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1732         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1733
1734         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1735                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1736                 return rc;
1737         }
1738         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1739
1740         req.enables =
1741                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1742         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1743         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1744
1745         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1746
1747         HWRM_CHECK_RESULT();
1748
1749         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1750         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1751         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1752         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1753         vnic->mru = rte_le_to_cpu_16(resp->mru);
1754         vnic->func_default = rte_le_to_cpu_32(
1755                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1756         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1757                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1758         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1759                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1760         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1761                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1762         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1763                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1764         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1765                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1766
1767         HWRM_UNLOCK();
1768
1769         return rc;
1770 }
1771
1772 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1773                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1774 {
1775         int rc = 0;
1776         uint16_t ctx_id;
1777         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1778         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1779                                                 bp->hwrm_cmd_resp_addr;
1780
1781         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1782
1783         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1784         HWRM_CHECK_RESULT();
1785
1786         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1787         if (!BNXT_HAS_RING_GRPS(bp))
1788                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1789         else if (ctx_idx == 0)
1790                 vnic->rss_rule = ctx_id;
1791
1792         HWRM_UNLOCK();
1793
1794         return rc;
1795 }
1796
1797 static
1798 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1799                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1800 {
1801         int rc = 0;
1802         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1803         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1804                                                 bp->hwrm_cmd_resp_addr;
1805
1806         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1807                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1808                 return rc;
1809         }
1810         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1811
1812         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1813
1814         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1815
1816         HWRM_CHECK_RESULT();
1817         HWRM_UNLOCK();
1818
1819         return rc;
1820 }
1821
1822 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1823 {
1824         int rc = 0;
1825
1826         if (BNXT_CHIP_THOR(bp)) {
1827                 int j;
1828
1829                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
1830                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
1831                                                       vnic,
1832                                                       vnic->fw_grp_ids[j]);
1833                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
1834                 }
1835                 vnic->num_lb_ctxts = 0;
1836         } else {
1837                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
1838                 vnic->rss_rule = INVALID_HW_RING_ID;
1839         }
1840
1841         return rc;
1842 }
1843
1844 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1845 {
1846         int rc = 0;
1847         struct hwrm_vnic_free_input req = {.req_type = 0 };
1848         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1849
1850         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1851                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1852                 return rc;
1853         }
1854
1855         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1856
1857         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1858
1859         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1860
1861         HWRM_CHECK_RESULT();
1862         HWRM_UNLOCK();
1863
1864         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1865         /* Configure default VNIC again if necessary. */
1866         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1867                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1868
1869         return rc;
1870 }
1871
1872 static int
1873 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1874 {
1875         int i;
1876         int rc = 0;
1877         int nr_ctxs = vnic->num_lb_ctxts;
1878         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1879         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1880
1881         for (i = 0; i < nr_ctxs; i++) {
1882                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1883
1884                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1885                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1886                 req.hash_mode_flags = vnic->hash_mode;
1887
1888                 req.hash_key_tbl_addr =
1889                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1890
1891                 req.ring_grp_tbl_addr =
1892                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1893                                          i * HW_HASH_INDEX_SIZE);
1894                 req.ring_table_pair_index = i;
1895                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1896
1897                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1898                                             BNXT_USE_CHIMP_MB);
1899
1900                 HWRM_CHECK_RESULT();
1901                 HWRM_UNLOCK();
1902         }
1903
1904         return rc;
1905 }
1906
1907 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1908                            struct bnxt_vnic_info *vnic)
1909 {
1910         int rc = 0;
1911         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1912         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1913
1914         if (!vnic->rss_table)
1915                 return 0;
1916
1917         if (BNXT_CHIP_THOR(bp))
1918                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1919
1920         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1921
1922         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1923         req.hash_mode_flags = vnic->hash_mode;
1924
1925         req.ring_grp_tbl_addr =
1926             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1927         req.hash_key_tbl_addr =
1928             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1929         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1930         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1931
1932         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1933
1934         HWRM_CHECK_RESULT();
1935         HWRM_UNLOCK();
1936
1937         return rc;
1938 }
1939
1940 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1941                         struct bnxt_vnic_info *vnic)
1942 {
1943         int rc = 0;
1944         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1945         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1946         uint16_t size;
1947
1948         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1949                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1950                 return rc;
1951         }
1952
1953         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1954
1955         req.flags = rte_cpu_to_le_32(
1956                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1957
1958         req.enables = rte_cpu_to_le_32(
1959                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1960
1961         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1962         size -= RTE_PKTMBUF_HEADROOM;
1963         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
1964
1965         req.jumbo_thresh = rte_cpu_to_le_16(size);
1966         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1967
1968         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1969
1970         HWRM_CHECK_RESULT();
1971         HWRM_UNLOCK();
1972
1973         return rc;
1974 }
1975
1976 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1977                         struct bnxt_vnic_info *vnic, bool enable)
1978 {
1979         int rc = 0;
1980         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1981         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1982
1983         if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
1984                 if (enable)
1985                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
1986                 return -ENOTSUP;
1987         }
1988
1989         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1990                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
1991                 return 0;
1992         }
1993
1994         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1995
1996         if (enable) {
1997                 req.enables = rte_cpu_to_le_32(
1998                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1999                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2000                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2001                 req.flags = rte_cpu_to_le_32(
2002                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2003                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2004                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2005                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2006                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2007                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2008                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2009                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2010                 req.min_agg_len = rte_cpu_to_le_32(512);
2011         }
2012         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2013
2014         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2015
2016         HWRM_CHECK_RESULT();
2017         HWRM_UNLOCK();
2018
2019         return rc;
2020 }
2021
2022 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2023 {
2024         struct hwrm_func_cfg_input req = {0};
2025         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2026         int rc;
2027
2028         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2029         req.enables = rte_cpu_to_le_32(
2030                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2031         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2032         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2033
2034         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2035
2036         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2037         HWRM_CHECK_RESULT();
2038         HWRM_UNLOCK();
2039
2040         bp->pf.vf_info[vf].random_mac = false;
2041
2042         return rc;
2043 }
2044
2045 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2046                                   uint64_t *dropped)
2047 {
2048         int rc = 0;
2049         struct hwrm_func_qstats_input req = {.req_type = 0};
2050         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2051
2052         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2053
2054         req.fid = rte_cpu_to_le_16(fid);
2055
2056         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2057
2058         HWRM_CHECK_RESULT();
2059
2060         if (dropped)
2061                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2062
2063         HWRM_UNLOCK();
2064
2065         return rc;
2066 }
2067
2068 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2069                           struct rte_eth_stats *stats)
2070 {
2071         int rc = 0;
2072         struct hwrm_func_qstats_input req = {.req_type = 0};
2073         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2074
2075         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2076
2077         req.fid = rte_cpu_to_le_16(fid);
2078
2079         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2080
2081         HWRM_CHECK_RESULT();
2082
2083         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2084         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2085         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2086         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2087         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2088         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2089
2090         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2091         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2092         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2093         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2094         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2095         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2096
2097         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2098         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2099         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2100
2101         HWRM_UNLOCK();
2102
2103         return rc;
2104 }
2105
2106 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2107 {
2108         int rc = 0;
2109         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2110         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2111
2112         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2113
2114         req.fid = rte_cpu_to_le_16(fid);
2115
2116         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2117
2118         HWRM_CHECK_RESULT();
2119         HWRM_UNLOCK();
2120
2121         return rc;
2122 }
2123
2124 /*
2125  * HWRM utility functions
2126  */
2127
2128 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2129 {
2130         unsigned int i;
2131         int rc = 0;
2132
2133         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2134                 struct bnxt_tx_queue *txq;
2135                 struct bnxt_rx_queue *rxq;
2136                 struct bnxt_cp_ring_info *cpr;
2137
2138                 if (i >= bp->rx_cp_nr_rings) {
2139                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2140                         cpr = txq->cp_ring;
2141                 } else {
2142                         rxq = bp->rx_queues[i];
2143                         cpr = rxq->cp_ring;
2144                 }
2145
2146                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2147                 if (rc)
2148                         return rc;
2149         }
2150         return 0;
2151 }
2152
2153 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2154 {
2155         int rc;
2156         unsigned int i;
2157         struct bnxt_cp_ring_info *cpr;
2158
2159         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2160
2161                 if (i >= bp->rx_cp_nr_rings) {
2162                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2163                 } else {
2164                         cpr = bp->rx_queues[i]->cp_ring;
2165                         if (BNXT_HAS_RING_GRPS(bp))
2166                                 bp->grp_info[i].fw_stats_ctx = -1;
2167                 }
2168                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2169                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2170                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2171                         if (rc)
2172                                 return rc;
2173                 }
2174         }
2175         return 0;
2176 }
2177
2178 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2179 {
2180         unsigned int i;
2181         int rc = 0;
2182
2183         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2184                 struct bnxt_tx_queue *txq;
2185                 struct bnxt_rx_queue *rxq;
2186                 struct bnxt_cp_ring_info *cpr;
2187
2188                 if (i >= bp->rx_cp_nr_rings) {
2189                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2190                         cpr = txq->cp_ring;
2191                 } else {
2192                         rxq = bp->rx_queues[i];
2193                         cpr = rxq->cp_ring;
2194                 }
2195
2196                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2197
2198                 if (rc)
2199                         return rc;
2200         }
2201         return rc;
2202 }
2203
2204 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2205 {
2206         uint16_t idx;
2207         uint32_t rc = 0;
2208
2209         if (!BNXT_HAS_RING_GRPS(bp))
2210                 return 0;
2211
2212         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2213
2214                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2215                         continue;
2216
2217                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2218
2219                 if (rc)
2220                         return rc;
2221         }
2222         return rc;
2223 }
2224
2225 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2226 {
2227         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2228
2229         bnxt_hwrm_ring_free(bp, cp_ring,
2230                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2231         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2232         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2233                                      sizeof(*cpr->cp_desc_ring));
2234         cpr->cp_raw_cons = 0;
2235         cpr->valid = 0;
2236 }
2237
2238 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2239 {
2240         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2241
2242         bnxt_hwrm_ring_free(bp, cp_ring,
2243                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2244         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2245         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2246                         sizeof(*cpr->cp_desc_ring));
2247         cpr->cp_raw_cons = 0;
2248         cpr->valid = 0;
2249 }
2250
2251 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2252 {
2253         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2254         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2255         struct bnxt_ring *ring = rxr->rx_ring_struct;
2256         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2257
2258         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2259                 bnxt_hwrm_ring_free(bp, ring,
2260                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2261                 ring->fw_ring_id = INVALID_HW_RING_ID;
2262                 if (BNXT_HAS_RING_GRPS(bp))
2263                         bp->grp_info[queue_index].rx_fw_ring_id =
2264                                                         INVALID_HW_RING_ID;
2265                 memset(rxr->rx_desc_ring, 0,
2266                        rxr->rx_ring_struct->ring_size *
2267                        sizeof(*rxr->rx_desc_ring));
2268                 memset(rxr->rx_buf_ring, 0,
2269                        rxr->rx_ring_struct->ring_size *
2270                        sizeof(*rxr->rx_buf_ring));
2271                 rxr->rx_prod = 0;
2272         }
2273         ring = rxr->ag_ring_struct;
2274         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2275                 bnxt_hwrm_ring_free(bp, ring,
2276                                     BNXT_CHIP_THOR(bp) ?
2277                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2278                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2279                 ring->fw_ring_id = INVALID_HW_RING_ID;
2280                 memset(rxr->ag_buf_ring, 0,
2281                        rxr->ag_ring_struct->ring_size *
2282                        sizeof(*rxr->ag_buf_ring));
2283                 rxr->ag_prod = 0;
2284                 if (BNXT_HAS_RING_GRPS(bp))
2285                         bp->grp_info[queue_index].ag_fw_ring_id =
2286                                                         INVALID_HW_RING_ID;
2287         }
2288         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2289                 bnxt_free_cp_ring(bp, cpr);
2290                 if (rxq->nq_ring)
2291                         bnxt_free_nq_ring(bp, rxq->nq_ring);
2292         }
2293
2294         if (BNXT_HAS_RING_GRPS(bp))
2295                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2296 }
2297
2298 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2299 {
2300         unsigned int i;
2301
2302         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2303                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2304                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2305                 struct bnxt_ring *ring = txr->tx_ring_struct;
2306                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2307
2308                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2309                         bnxt_hwrm_ring_free(bp, ring,
2310                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2311                         ring->fw_ring_id = INVALID_HW_RING_ID;
2312                         memset(txr->tx_desc_ring, 0,
2313                                         txr->tx_ring_struct->ring_size *
2314                                         sizeof(*txr->tx_desc_ring));
2315                         memset(txr->tx_buf_ring, 0,
2316                                         txr->tx_ring_struct->ring_size *
2317                                         sizeof(*txr->tx_buf_ring));
2318                         txr->tx_prod = 0;
2319                         txr->tx_cons = 0;
2320                 }
2321                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2322                         bnxt_free_cp_ring(bp, cpr);
2323                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2324                         if (txq->nq_ring)
2325                                 bnxt_free_nq_ring(bp, txq->nq_ring);
2326                 }
2327         }
2328
2329         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2330                 bnxt_free_hwrm_rx_ring(bp, i);
2331
2332         return 0;
2333 }
2334
2335 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2336 {
2337         uint16_t i;
2338         uint32_t rc = 0;
2339
2340         if (!BNXT_HAS_RING_GRPS(bp))
2341                 return 0;
2342
2343         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2344                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2345                 if (rc)
2346                         return rc;
2347         }
2348         return rc;
2349 }
2350
2351 void bnxt_free_hwrm_resources(struct bnxt *bp)
2352 {
2353         /* Release memzone */
2354         rte_free(bp->hwrm_cmd_resp_addr);
2355         rte_free(bp->hwrm_short_cmd_req_addr);
2356         bp->hwrm_cmd_resp_addr = NULL;
2357         bp->hwrm_short_cmd_req_addr = NULL;
2358         bp->hwrm_cmd_resp_dma_addr = 0;
2359         bp->hwrm_short_cmd_req_dma_addr = 0;
2360 }
2361
2362 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2363 {
2364         struct rte_pci_device *pdev = bp->pdev;
2365         char type[RTE_MEMZONE_NAMESIZE];
2366
2367         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2368                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2369         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2370         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2371         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2372         if (bp->hwrm_cmd_resp_addr == NULL)
2373                 return -ENOMEM;
2374         bp->hwrm_cmd_resp_dma_addr =
2375                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2376         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2377                 PMD_DRV_LOG(ERR,
2378                         "unable to map response address to physical memory\n");
2379                 return -ENOMEM;
2380         }
2381         rte_spinlock_init(&bp->hwrm_lock);
2382
2383         return 0;
2384 }
2385
2386 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2387 {
2388         struct bnxt_filter_info *filter;
2389         int rc = 0;
2390
2391         STAILQ_FOREACH(filter, &vnic->filter, next) {
2392                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2393                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2394                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2395                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2396                 else
2397                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2398                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2399                 bnxt_free_filter(bp, filter);
2400                 //if (rc)
2401                         //break;
2402         }
2403         return rc;
2404 }
2405
2406 static int
2407 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2408 {
2409         struct bnxt_filter_info *filter;
2410         struct rte_flow *flow;
2411         int rc = 0;
2412
2413         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2414                 flow = STAILQ_FIRST(&vnic->flow_list);
2415                 filter = flow->filter;
2416                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2417                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2418                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2419                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2420                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2421                 else
2422                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2423
2424                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2425                 rte_free(flow);
2426                 //if (rc)
2427                         //break;
2428         }
2429         return rc;
2430 }
2431
2432 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2433 {
2434         struct bnxt_filter_info *filter;
2435         int rc = 0;
2436
2437         STAILQ_FOREACH(filter, &vnic->filter, next) {
2438                 if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2439                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2440                                                      filter);
2441                 } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2442                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2443                                                          filter);
2444                 } else {
2445                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2446                                                      filter);
2447                         if (!rc)
2448                                 filter->dflt = 1;
2449                 }
2450                 if (rc)
2451                         break;
2452         }
2453         return rc;
2454 }
2455
2456 void bnxt_free_tunnel_ports(struct bnxt *bp)
2457 {
2458         if (bp->vxlan_port_cnt)
2459                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2460                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2461         bp->vxlan_port = 0;
2462         if (bp->geneve_port_cnt)
2463                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2464                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2465         bp->geneve_port = 0;
2466 }
2467
2468 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2469 {
2470         int i;
2471
2472         if (bp->vnic_info == NULL)
2473                 return;
2474
2475         /*
2476          * Cleanup VNICs in reverse order, to make sure the L2 filter
2477          * from vnic0 is last to be cleaned up.
2478          */
2479         for (i = bp->max_vnics - 1; i >= 0; i--) {
2480                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2481
2482                 // If the VNIC ID is invalid we are not currently using the VNIC
2483                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2484                         continue;
2485
2486                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2487
2488                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2489
2490                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2491
2492                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2493
2494                 bnxt_hwrm_vnic_free(bp, vnic);
2495
2496                 rte_free(vnic->fw_grp_ids);
2497         }
2498         /* Ring resources */
2499         bnxt_free_all_hwrm_rings(bp);
2500         bnxt_free_all_hwrm_ring_grps(bp);
2501         bnxt_free_all_hwrm_stat_ctxs(bp);
2502         bnxt_free_tunnel_ports(bp);
2503 }
2504
2505 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2506 {
2507         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2508
2509         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2510                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2511
2512         switch (conf_link_speed) {
2513         case ETH_LINK_SPEED_10M_HD:
2514         case ETH_LINK_SPEED_100M_HD:
2515                 /* FALLTHROUGH */
2516                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2517         }
2518         return hw_link_duplex;
2519 }
2520
2521 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2522 {
2523         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2524 }
2525
2526 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2527 {
2528         uint16_t eth_link_speed = 0;
2529
2530         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2531                 return ETH_LINK_SPEED_AUTONEG;
2532
2533         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2534         case ETH_LINK_SPEED_100M:
2535         case ETH_LINK_SPEED_100M_HD:
2536                 /* FALLTHROUGH */
2537                 eth_link_speed =
2538                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2539                 break;
2540         case ETH_LINK_SPEED_1G:
2541                 eth_link_speed =
2542                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2543                 break;
2544         case ETH_LINK_SPEED_2_5G:
2545                 eth_link_speed =
2546                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2547                 break;
2548         case ETH_LINK_SPEED_10G:
2549                 eth_link_speed =
2550                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2551                 break;
2552         case ETH_LINK_SPEED_20G:
2553                 eth_link_speed =
2554                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2555                 break;
2556         case ETH_LINK_SPEED_25G:
2557                 eth_link_speed =
2558                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2559                 break;
2560         case ETH_LINK_SPEED_40G:
2561                 eth_link_speed =
2562                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2563                 break;
2564         case ETH_LINK_SPEED_50G:
2565                 eth_link_speed =
2566                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2567                 break;
2568         case ETH_LINK_SPEED_100G:
2569                 eth_link_speed =
2570                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2571                 break;
2572         default:
2573                 PMD_DRV_LOG(ERR,
2574                         "Unsupported link speed %d; default to AUTO\n",
2575                         conf_link_speed);
2576                 break;
2577         }
2578         return eth_link_speed;
2579 }
2580
2581 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2582                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2583                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2584                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2585
2586 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2587 {
2588         uint32_t one_speed;
2589
2590         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2591                 return 0;
2592
2593         if (link_speed & ETH_LINK_SPEED_FIXED) {
2594                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2595
2596                 if (one_speed & (one_speed - 1)) {
2597                         PMD_DRV_LOG(ERR,
2598                                 "Invalid advertised speeds (%u) for port %u\n",
2599                                 link_speed, port_id);
2600                         return -EINVAL;
2601                 }
2602                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2603                         PMD_DRV_LOG(ERR,
2604                                 "Unsupported advertised speed (%u) for port %u\n",
2605                                 link_speed, port_id);
2606                         return -EINVAL;
2607                 }
2608         } else {
2609                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2610                         PMD_DRV_LOG(ERR,
2611                                 "Unsupported advertised speeds (%u) for port %u\n",
2612                                 link_speed, port_id);
2613                         return -EINVAL;
2614                 }
2615         }
2616         return 0;
2617 }
2618
2619 static uint16_t
2620 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2621 {
2622         uint16_t ret = 0;
2623
2624         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2625                 if (bp->link_info.support_speeds)
2626                         return bp->link_info.support_speeds;
2627                 link_speed = BNXT_SUPPORTED_SPEEDS;
2628         }
2629
2630         if (link_speed & ETH_LINK_SPEED_100M)
2631                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2632         if (link_speed & ETH_LINK_SPEED_100M_HD)
2633                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2634         if (link_speed & ETH_LINK_SPEED_1G)
2635                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2636         if (link_speed & ETH_LINK_SPEED_2_5G)
2637                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2638         if (link_speed & ETH_LINK_SPEED_10G)
2639                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2640         if (link_speed & ETH_LINK_SPEED_20G)
2641                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2642         if (link_speed & ETH_LINK_SPEED_25G)
2643                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2644         if (link_speed & ETH_LINK_SPEED_40G)
2645                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2646         if (link_speed & ETH_LINK_SPEED_50G)
2647                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2648         if (link_speed & ETH_LINK_SPEED_100G)
2649                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2650         return ret;
2651 }
2652
2653 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2654 {
2655         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2656
2657         switch (hw_link_speed) {
2658         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2659                 eth_link_speed = ETH_SPEED_NUM_100M;
2660                 break;
2661         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2662                 eth_link_speed = ETH_SPEED_NUM_1G;
2663                 break;
2664         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2665                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2666                 break;
2667         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2668                 eth_link_speed = ETH_SPEED_NUM_10G;
2669                 break;
2670         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2671                 eth_link_speed = ETH_SPEED_NUM_20G;
2672                 break;
2673         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2674                 eth_link_speed = ETH_SPEED_NUM_25G;
2675                 break;
2676         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2677                 eth_link_speed = ETH_SPEED_NUM_40G;
2678                 break;
2679         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2680                 eth_link_speed = ETH_SPEED_NUM_50G;
2681                 break;
2682         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2683                 eth_link_speed = ETH_SPEED_NUM_100G;
2684                 break;
2685         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2686         default:
2687                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2688                         hw_link_speed);
2689                 break;
2690         }
2691         return eth_link_speed;
2692 }
2693
2694 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2695 {
2696         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2697
2698         switch (hw_link_duplex) {
2699         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2700         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2701                 /* FALLTHROUGH */
2702                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2703                 break;
2704         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2705                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2706                 break;
2707         default:
2708                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2709                         hw_link_duplex);
2710                 break;
2711         }
2712         return eth_link_duplex;
2713 }
2714
2715 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2716 {
2717         int rc = 0;
2718         struct bnxt_link_info *link_info = &bp->link_info;
2719
2720         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2721         if (rc) {
2722                 PMD_DRV_LOG(ERR,
2723                         "Get link config failed with rc %d\n", rc);
2724                 goto exit;
2725         }
2726         if (link_info->link_speed)
2727                 link->link_speed =
2728                         bnxt_parse_hw_link_speed(link_info->link_speed);
2729         else
2730                 link->link_speed = ETH_SPEED_NUM_NONE;
2731         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2732         link->link_status = link_info->link_up;
2733         link->link_autoneg = link_info->auto_mode ==
2734                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2735                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2736 exit:
2737         return rc;
2738 }
2739
2740 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2741 {
2742         int rc = 0;
2743         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2744         struct bnxt_link_info link_req;
2745         uint16_t speed, autoneg;
2746
2747         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2748                 return 0;
2749
2750         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2751                         bp->eth_dev->data->port_id);
2752         if (rc)
2753                 goto error;
2754
2755         memset(&link_req, 0, sizeof(link_req));
2756         link_req.link_up = link_up;
2757         if (!link_up)
2758                 goto port_phy_cfg;
2759
2760         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2761         if (BNXT_CHIP_THOR(bp) &&
2762             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2763                 /* 40G is not supported as part of media auto detect.
2764                  * The speed should be forced and autoneg disabled
2765                  * to configure 40G speed.
2766                  */
2767                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2768                 autoneg = 0;
2769         }
2770
2771         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2772         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2773         /* Autoneg can be done only when the FW allows.
2774          * When user configures fixed speed of 40G and later changes to
2775          * any other speed, auto_link_speed/force_link_speed is still set
2776          * to 40G until link comes up at new speed.
2777          */
2778         if (autoneg == 1 &&
2779             !(!BNXT_CHIP_THOR(bp) &&
2780               (bp->link_info.auto_link_speed ||
2781                bp->link_info.force_link_speed))) {
2782                 link_req.phy_flags |=
2783                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2784                 link_req.auto_link_speed_mask =
2785                         bnxt_parse_eth_link_speed_mask(bp,
2786                                                        dev_conf->link_speeds);
2787         } else {
2788                 if (bp->link_info.phy_type ==
2789                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2790                     bp->link_info.phy_type ==
2791                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2792                     bp->link_info.media_type ==
2793                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2794                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2795                         return -EINVAL;
2796                 }
2797
2798                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2799                 /* If user wants a particular speed try that first. */
2800                 if (speed)
2801                         link_req.link_speed = speed;
2802                 else if (bp->link_info.force_link_speed)
2803                         link_req.link_speed = bp->link_info.force_link_speed;
2804                 else
2805                         link_req.link_speed = bp->link_info.auto_link_speed;
2806         }
2807         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2808         link_req.auto_pause = bp->link_info.auto_pause;
2809         link_req.force_pause = bp->link_info.force_pause;
2810
2811 port_phy_cfg:
2812         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2813         if (rc) {
2814                 PMD_DRV_LOG(ERR,
2815                         "Set link config failed with rc %d\n", rc);
2816         }
2817
2818 error:
2819         return rc;
2820 }
2821
2822 /* JIRA 22088 */
2823 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2824 {
2825         struct hwrm_func_qcfg_input req = {0};
2826         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2827         uint16_t flags;
2828         int rc = 0;
2829
2830         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2831         req.fid = rte_cpu_to_le_16(0xffff);
2832
2833         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2834
2835         HWRM_CHECK_RESULT();
2836
2837         /* Hard Coded.. 0xfff VLAN ID mask */
2838         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2839         flags = rte_le_to_cpu_16(resp->flags);
2840         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2841                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2842
2843         if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2844                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2845                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2846         } else if (BNXT_VF(bp) &&
2847                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2848                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2849                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2850         }
2851
2852         if (mtu)
2853                 *mtu = resp->mtu;
2854
2855         switch (resp->port_partition_type) {
2856         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2857         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2858         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2859                 /* FALLTHROUGH */
2860                 bp->port_partition_type = resp->port_partition_type;
2861                 break;
2862         default:
2863                 bp->port_partition_type = 0;
2864                 break;
2865         }
2866
2867         HWRM_UNLOCK();
2868
2869         return rc;
2870 }
2871
2872 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2873                                    struct hwrm_func_qcaps_output *qcaps)
2874 {
2875         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2876         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2877                sizeof(qcaps->mac_address));
2878         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2879         qcaps->max_rx_rings = fcfg->num_rx_rings;
2880         qcaps->max_tx_rings = fcfg->num_tx_rings;
2881         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2882         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2883         qcaps->max_vfs = 0;
2884         qcaps->first_vf_id = 0;
2885         qcaps->max_vnics = fcfg->num_vnics;
2886         qcaps->max_decap_records = 0;
2887         qcaps->max_encap_records = 0;
2888         qcaps->max_tx_wm_flows = 0;
2889         qcaps->max_tx_em_flows = 0;
2890         qcaps->max_rx_wm_flows = 0;
2891         qcaps->max_rx_em_flows = 0;
2892         qcaps->max_flow_id = 0;
2893         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2894         qcaps->max_sp_tx_rings = 0;
2895         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2896 }
2897
2898 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2899 {
2900         struct hwrm_func_cfg_input req = {0};
2901         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2902         uint32_t enables;
2903         int rc;
2904
2905         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2906                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2907                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2908                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2909                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2910                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2911                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2912                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2913                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2914
2915         if (BNXT_HAS_RING_GRPS(bp)) {
2916                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2917                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2918         } else if (BNXT_HAS_NQ(bp)) {
2919                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2920                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2921         }
2922
2923         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2924         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2925         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2926                                    RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2927                                    BNXT_NUM_VLANS);
2928         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2929         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2930         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2931         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2932         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2933         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2934         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2935         req.fid = rte_cpu_to_le_16(0xffff);
2936         req.enables = rte_cpu_to_le_32(enables);
2937
2938         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2939
2940         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2941
2942         HWRM_CHECK_RESULT();
2943         HWRM_UNLOCK();
2944
2945         return rc;
2946 }
2947
2948 static void populate_vf_func_cfg_req(struct bnxt *bp,
2949                                      struct hwrm_func_cfg_input *req,
2950                                      int num_vfs)
2951 {
2952         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2953                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2954                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2955                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2956                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2957                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2958                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2959                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2960                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2961                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2962
2963         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2964                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2965                                     BNXT_NUM_VLANS);
2966         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2967                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2968                                     BNXT_NUM_VLANS);
2969         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2970                                                 (num_vfs + 1));
2971         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2972         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2973                                                (num_vfs + 1));
2974         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2975         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2976         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2977         /* TODO: For now, do not support VMDq/RFS on VFs. */
2978         req->num_vnics = rte_cpu_to_le_16(1);
2979         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2980                                                  (num_vfs + 1));
2981 }
2982
2983 static void add_random_mac_if_needed(struct bnxt *bp,
2984                                      struct hwrm_func_cfg_input *cfg_req,
2985                                      int vf)
2986 {
2987         struct rte_ether_addr mac;
2988
2989         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2990                 return;
2991
2992         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2993                 cfg_req->enables |=
2994                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2995                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2996                 bp->pf.vf_info[vf].random_mac = true;
2997         } else {
2998                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2999                         RTE_ETHER_ADDR_LEN);
3000         }
3001 }
3002
3003 static void reserve_resources_from_vf(struct bnxt *bp,
3004                                       struct hwrm_func_cfg_input *cfg_req,
3005                                       int vf)
3006 {
3007         struct hwrm_func_qcaps_input req = {0};
3008         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3009         int rc;
3010
3011         /* Get the actual allocated values now */
3012         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3013         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3014         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3015
3016         if (rc) {
3017                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3018                 copy_func_cfg_to_qcaps(cfg_req, resp);
3019         } else if (resp->error_code) {
3020                 rc = rte_le_to_cpu_16(resp->error_code);
3021                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3022                 copy_func_cfg_to_qcaps(cfg_req, resp);
3023         }
3024
3025         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3026         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3027         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3028         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3029         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3030         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3031         /*
3032          * TODO: While not supporting VMDq with VFs, max_vnics is always
3033          * forced to 1 in this case
3034          */
3035         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3036         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3037
3038         HWRM_UNLOCK();
3039 }
3040
3041 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3042 {
3043         struct hwrm_func_qcfg_input req = {0};
3044         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3045         int rc;
3046
3047         /* Check for zero MAC address */
3048         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3049         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3050         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3051         HWRM_CHECK_RESULT();
3052         rc = rte_le_to_cpu_16(resp->vlan);
3053
3054         HWRM_UNLOCK();
3055
3056         return rc;
3057 }
3058
3059 static int update_pf_resource_max(struct bnxt *bp)
3060 {
3061         struct hwrm_func_qcfg_input req = {0};
3062         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3063         int rc;
3064
3065         /* And copy the allocated numbers into the pf struct */
3066         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3067         req.fid = rte_cpu_to_le_16(0xffff);
3068         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3069         HWRM_CHECK_RESULT();
3070
3071         /* Only TX ring value reflects actual allocation? TODO */
3072         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3073         bp->pf.evb_mode = resp->evb_mode;
3074
3075         HWRM_UNLOCK();
3076
3077         return rc;
3078 }
3079
3080 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3081 {
3082         int rc;
3083
3084         if (!BNXT_PF(bp)) {
3085                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3086                 return -EINVAL;
3087         }
3088
3089         rc = bnxt_hwrm_func_qcaps(bp);
3090         if (rc)
3091                 return rc;
3092
3093         bp->pf.func_cfg_flags &=
3094                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3095                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3096         bp->pf.func_cfg_flags |=
3097                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3098         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3099         rc = __bnxt_hwrm_func_qcaps(bp);
3100         return rc;
3101 }
3102
3103 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3104 {
3105         struct hwrm_func_cfg_input req = {0};
3106         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3107         int i;
3108         size_t sz;
3109         int rc = 0;
3110         size_t req_buf_sz;
3111
3112         if (!BNXT_PF(bp)) {
3113                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3114                 return -EINVAL;
3115         }
3116
3117         rc = bnxt_hwrm_func_qcaps(bp);
3118
3119         if (rc)
3120                 return rc;
3121
3122         bp->pf.active_vfs = num_vfs;
3123
3124         /*
3125          * First, configure the PF to only use one TX ring.  This ensures that
3126          * there are enough rings for all VFs.
3127          *
3128          * If we don't do this, when we call func_alloc() later, we will lock
3129          * extra rings to the PF that won't be available during func_cfg() of
3130          * the VFs.
3131          *
3132          * This has been fixed with firmware versions above 20.6.54
3133          */
3134         bp->pf.func_cfg_flags &=
3135                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3136                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3137         bp->pf.func_cfg_flags |=
3138                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3139         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3140         if (rc)
3141                 return rc;
3142
3143         /*
3144          * Now, create and register a buffer to hold forwarded VF requests
3145          */
3146         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3147         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3148                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3149         if (bp->pf.vf_req_buf == NULL) {
3150                 rc = -ENOMEM;
3151                 goto error_free;
3152         }
3153         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3154                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3155         for (i = 0; i < num_vfs; i++)
3156                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3157                                         (i * HWRM_MAX_REQ_LEN);
3158
3159         rc = bnxt_hwrm_func_buf_rgtr(bp);
3160         if (rc)
3161                 goto error_free;
3162
3163         populate_vf_func_cfg_req(bp, &req, num_vfs);
3164
3165         bp->pf.active_vfs = 0;
3166         for (i = 0; i < num_vfs; i++) {
3167                 add_random_mac_if_needed(bp, &req, i);
3168
3169                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3170                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3171                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3172                 rc = bnxt_hwrm_send_message(bp,
3173                                             &req,
3174                                             sizeof(req),
3175                                             BNXT_USE_CHIMP_MB);
3176
3177                 /* Clear enable flag for next pass */
3178                 req.enables &= ~rte_cpu_to_le_32(
3179                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3180
3181                 if (rc || resp->error_code) {
3182                         PMD_DRV_LOG(ERR,
3183                                 "Failed to initizlie VF %d\n", i);
3184                         PMD_DRV_LOG(ERR,
3185                                 "Not all VFs available. (%d, %d)\n",
3186                                 rc, resp->error_code);
3187                         HWRM_UNLOCK();
3188                         break;
3189                 }
3190
3191                 HWRM_UNLOCK();
3192
3193                 reserve_resources_from_vf(bp, &req, i);
3194                 bp->pf.active_vfs++;
3195                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3196         }
3197
3198         /*
3199          * Now configure the PF to use "the rest" of the resources
3200          * We're using STD_TX_RING_MODE here though which will limit the TX
3201          * rings.  This will allow QoS to function properly.  Not setting this
3202          * will cause PF rings to break bandwidth settings.
3203          */
3204         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3205         if (rc)
3206                 goto error_free;
3207
3208         rc = update_pf_resource_max(bp);
3209         if (rc)
3210                 goto error_free;
3211
3212         return rc;
3213
3214 error_free:
3215         bnxt_hwrm_func_buf_unrgtr(bp);
3216         return rc;
3217 }
3218
3219 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3220 {
3221         struct hwrm_func_cfg_input req = {0};
3222         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3223         int rc;
3224
3225         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3226
3227         req.fid = rte_cpu_to_le_16(0xffff);
3228         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3229         req.evb_mode = bp->pf.evb_mode;
3230
3231         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3232         HWRM_CHECK_RESULT();
3233         HWRM_UNLOCK();
3234
3235         return rc;
3236 }
3237
3238 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3239                                 uint8_t tunnel_type)
3240 {
3241         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3242         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3243         int rc = 0;
3244
3245         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3246         req.tunnel_type = tunnel_type;
3247         req.tunnel_dst_port_val = port;
3248         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3249         HWRM_CHECK_RESULT();
3250
3251         switch (tunnel_type) {
3252         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3253                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3254                 bp->vxlan_port = port;
3255                 break;
3256         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3257                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3258                 bp->geneve_port = port;
3259                 break;
3260         default:
3261                 break;
3262         }
3263
3264         HWRM_UNLOCK();
3265
3266         return rc;
3267 }
3268
3269 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3270                                 uint8_t tunnel_type)
3271 {
3272         struct hwrm_tunnel_dst_port_free_input req = {0};
3273         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3274         int rc = 0;
3275
3276         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3277
3278         req.tunnel_type = tunnel_type;
3279         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3280         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3281
3282         HWRM_CHECK_RESULT();
3283         HWRM_UNLOCK();
3284
3285         return rc;
3286 }
3287
3288 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3289                                         uint32_t flags)
3290 {
3291         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3292         struct hwrm_func_cfg_input req = {0};
3293         int rc;
3294
3295         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3296
3297         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3298         req.flags = rte_cpu_to_le_32(flags);
3299         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3300
3301         HWRM_CHECK_RESULT();
3302         HWRM_UNLOCK();
3303
3304         return rc;
3305 }
3306
3307 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3308 {
3309         uint32_t *flag = flagp;
3310
3311         vnic->flags = *flag;
3312 }
3313
3314 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3315 {
3316         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3317 }
3318
3319 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3320 {
3321         int rc = 0;
3322         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3323         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3324
3325         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3326
3327         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3328         req.req_buf_page_size = rte_cpu_to_le_16(
3329                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3330         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3331         req.req_buf_page_addr0 =
3332                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3333         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3334                 PMD_DRV_LOG(ERR,
3335                         "unable to map buffer address to physical memory\n");
3336                 return -ENOMEM;
3337         }
3338
3339         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3340
3341         HWRM_CHECK_RESULT();
3342         HWRM_UNLOCK();
3343
3344         return rc;
3345 }
3346
3347 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3348 {
3349         int rc = 0;
3350         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3351         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3352
3353         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3354                 return 0;
3355
3356         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3357
3358         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3359
3360         HWRM_CHECK_RESULT();
3361         HWRM_UNLOCK();
3362
3363         return rc;
3364 }
3365
3366 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3367 {
3368         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3369         struct hwrm_func_cfg_input req = {0};
3370         int rc;
3371
3372         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3373
3374         req.fid = rte_cpu_to_le_16(0xffff);
3375         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3376         req.enables = rte_cpu_to_le_32(
3377                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3378         req.async_event_cr = rte_cpu_to_le_16(
3379                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3380         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3381
3382         HWRM_CHECK_RESULT();
3383         HWRM_UNLOCK();
3384
3385         return rc;
3386 }
3387
3388 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3389 {
3390         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3391         struct hwrm_func_vf_cfg_input req = {0};
3392         int rc;
3393
3394         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3395
3396         req.enables = rte_cpu_to_le_32(
3397                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3398         req.async_event_cr = rte_cpu_to_le_16(
3399                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3400         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3401
3402         HWRM_CHECK_RESULT();
3403         HWRM_UNLOCK();
3404
3405         return rc;
3406 }
3407
3408 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3409 {
3410         struct hwrm_func_cfg_input req = {0};
3411         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3412         uint16_t dflt_vlan, fid;
3413         uint32_t func_cfg_flags;
3414         int rc = 0;
3415
3416         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3417
3418         if (is_vf) {
3419                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3420                 fid = bp->pf.vf_info[vf].fid;
3421                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3422         } else {
3423                 fid = rte_cpu_to_le_16(0xffff);
3424                 func_cfg_flags = bp->pf.func_cfg_flags;
3425                 dflt_vlan = bp->vlan;
3426         }
3427
3428         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3429         req.fid = rte_cpu_to_le_16(fid);
3430         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3431         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3432
3433         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3434
3435         HWRM_CHECK_RESULT();
3436         HWRM_UNLOCK();
3437
3438         return rc;
3439 }
3440
3441 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3442                         uint16_t max_bw, uint16_t enables)
3443 {
3444         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3445         struct hwrm_func_cfg_input req = {0};
3446         int rc;
3447
3448         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3449
3450         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3451         req.enables |= rte_cpu_to_le_32(enables);
3452         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3453         req.max_bw = rte_cpu_to_le_32(max_bw);
3454         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3455
3456         HWRM_CHECK_RESULT();
3457         HWRM_UNLOCK();
3458
3459         return rc;
3460 }
3461
3462 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3463 {
3464         struct hwrm_func_cfg_input req = {0};
3465         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3466         int rc = 0;
3467
3468         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3469
3470         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3471         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3472         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3473         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3474
3475         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3476
3477         HWRM_CHECK_RESULT();
3478         HWRM_UNLOCK();
3479
3480         return rc;
3481 }
3482
3483 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3484 {
3485         int rc;
3486
3487         if (BNXT_PF(bp))
3488                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3489         else
3490                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3491
3492         return rc;
3493 }
3494
3495 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3496                               void *encaped, size_t ec_size)
3497 {
3498         int rc = 0;
3499         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3500         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3501
3502         if (ec_size > sizeof(req.encap_request))
3503                 return -1;
3504
3505         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3506
3507         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3508         memcpy(req.encap_request, encaped, ec_size);
3509
3510         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3511
3512         HWRM_CHECK_RESULT();
3513         HWRM_UNLOCK();
3514
3515         return rc;
3516 }
3517
3518 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3519                                        struct rte_ether_addr *mac)
3520 {
3521         struct hwrm_func_qcfg_input req = {0};
3522         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3523         int rc;
3524
3525         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3526
3527         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3528         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3529
3530         HWRM_CHECK_RESULT();
3531
3532         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3533
3534         HWRM_UNLOCK();
3535
3536         return rc;
3537 }
3538
3539 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3540                             void *encaped, size_t ec_size)
3541 {
3542         int rc = 0;
3543         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3544         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3545
3546         if (ec_size > sizeof(req.encap_request))
3547                 return -1;
3548
3549         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3550
3551         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3552         memcpy(req.encap_request, encaped, ec_size);
3553
3554         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3555
3556         HWRM_CHECK_RESULT();
3557         HWRM_UNLOCK();
3558
3559         return rc;
3560 }
3561
3562 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3563                          struct rte_eth_stats *stats, uint8_t rx)
3564 {
3565         int rc = 0;
3566         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3567         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3568
3569         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3570
3571         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3572
3573         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3574
3575         HWRM_CHECK_RESULT();
3576
3577         if (rx) {
3578                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3579                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3580                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3581                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3582                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3583                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3584                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3585                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3586         } else {
3587                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3588                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3589                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3590                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3591                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3592                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3593         }
3594
3595
3596         HWRM_UNLOCK();
3597
3598         return rc;
3599 }
3600
3601 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3602 {
3603         struct hwrm_port_qstats_input req = {0};
3604         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3605         struct bnxt_pf_info *pf = &bp->pf;
3606         int rc;
3607
3608         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3609
3610         req.port_id = rte_cpu_to_le_16(pf->port_id);
3611         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3612         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3613         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3614
3615         HWRM_CHECK_RESULT();
3616         HWRM_UNLOCK();
3617
3618         return rc;
3619 }
3620
3621 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3622 {
3623         struct hwrm_port_clr_stats_input req = {0};
3624         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3625         struct bnxt_pf_info *pf = &bp->pf;
3626         int rc;
3627
3628         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3629         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3630             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3631                 return 0;
3632
3633         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3634
3635         req.port_id = rte_cpu_to_le_16(pf->port_id);
3636         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3637
3638         HWRM_CHECK_RESULT();
3639         HWRM_UNLOCK();
3640
3641         return rc;
3642 }
3643
3644 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3645 {
3646         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3647         struct hwrm_port_led_qcaps_input req = {0};
3648         int rc;
3649
3650         if (BNXT_VF(bp))
3651                 return 0;
3652
3653         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3654         req.port_id = bp->pf.port_id;
3655         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3656
3657         HWRM_CHECK_RESULT();
3658
3659         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3660                 unsigned int i;
3661
3662                 bp->num_leds = resp->num_leds;
3663                 memcpy(bp->leds, &resp->led0_id,
3664                         sizeof(bp->leds[0]) * bp->num_leds);
3665                 for (i = 0; i < bp->num_leds; i++) {
3666                         struct bnxt_led_info *led = &bp->leds[i];
3667
3668                         uint16_t caps = led->led_state_caps;
3669
3670                         if (!led->led_group_id ||
3671                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3672                                 bp->num_leds = 0;
3673                                 break;
3674                         }
3675                 }
3676         }
3677
3678         HWRM_UNLOCK();
3679
3680         return rc;
3681 }
3682
3683 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3684 {
3685         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3686         struct hwrm_port_led_cfg_input req = {0};
3687         struct bnxt_led_cfg *led_cfg;
3688         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3689         uint16_t duration = 0;
3690         int rc, i;
3691
3692         if (!bp->num_leds || BNXT_VF(bp))
3693                 return -EOPNOTSUPP;
3694
3695         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3696
3697         if (led_on) {
3698                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3699                 duration = rte_cpu_to_le_16(500);
3700         }
3701         req.port_id = bp->pf.port_id;
3702         req.num_leds = bp->num_leds;
3703         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3704         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3705                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3706                 led_cfg->led_id = bp->leds[i].led_id;
3707                 led_cfg->led_state = led_state;
3708                 led_cfg->led_blink_on = duration;
3709                 led_cfg->led_blink_off = duration;
3710                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3711         }
3712
3713         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3714
3715         HWRM_CHECK_RESULT();
3716         HWRM_UNLOCK();
3717
3718         return rc;
3719 }
3720
3721 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3722                                uint32_t *length)
3723 {
3724         int rc;
3725         struct hwrm_nvm_get_dir_info_input req = {0};
3726         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3727
3728         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3729
3730         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3731
3732         HWRM_CHECK_RESULT();
3733
3734         *entries = rte_le_to_cpu_32(resp->entries);
3735         *length = rte_le_to_cpu_32(resp->entry_length);
3736
3737         HWRM_UNLOCK();
3738         return rc;
3739 }
3740
3741 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3742 {
3743         int rc;
3744         uint32_t dir_entries;
3745         uint32_t entry_length;
3746         uint8_t *buf;
3747         size_t buflen;
3748         rte_iova_t dma_handle;
3749         struct hwrm_nvm_get_dir_entries_input req = {0};
3750         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3751
3752         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3753         if (rc != 0)
3754                 return rc;
3755
3756         *data++ = dir_entries;
3757         *data++ = entry_length;
3758         len -= 2;
3759         memset(data, 0xff, len);
3760
3761         buflen = dir_entries * entry_length;
3762         buf = rte_malloc("nvm_dir", buflen, 0);
3763         rte_mem_lock_page(buf);
3764         if (buf == NULL)
3765                 return -ENOMEM;
3766         dma_handle = rte_mem_virt2iova(buf);
3767         if (dma_handle == RTE_BAD_IOVA) {
3768                 PMD_DRV_LOG(ERR,
3769                         "unable to map response address to physical memory\n");
3770                 return -ENOMEM;
3771         }
3772         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3773         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3774         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3775
3776         if (rc == 0)
3777                 memcpy(data, buf, len > buflen ? buflen : len);
3778
3779         rte_free(buf);
3780         HWRM_CHECK_RESULT();
3781         HWRM_UNLOCK();
3782
3783         return rc;
3784 }
3785
3786 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3787                              uint32_t offset, uint32_t length,
3788                              uint8_t *data)
3789 {
3790         int rc;
3791         uint8_t *buf;
3792         rte_iova_t dma_handle;
3793         struct hwrm_nvm_read_input req = {0};
3794         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3795
3796         buf = rte_malloc("nvm_item", length, 0);
3797         rte_mem_lock_page(buf);
3798         if (!buf)
3799                 return -ENOMEM;
3800
3801         dma_handle = rte_mem_virt2iova(buf);
3802         if (dma_handle == RTE_BAD_IOVA) {
3803                 PMD_DRV_LOG(ERR,
3804                         "unable to map response address to physical memory\n");
3805                 return -ENOMEM;
3806         }
3807         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3808         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3809         req.dir_idx = rte_cpu_to_le_16(index);
3810         req.offset = rte_cpu_to_le_32(offset);
3811         req.len = rte_cpu_to_le_32(length);
3812         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3813         if (rc == 0)
3814                 memcpy(data, buf, length);
3815
3816         rte_free(buf);
3817         HWRM_CHECK_RESULT();
3818         HWRM_UNLOCK();
3819
3820         return rc;
3821 }
3822
3823 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3824 {
3825         int rc;
3826         struct hwrm_nvm_erase_dir_entry_input req = {0};
3827         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3828
3829         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3830         req.dir_idx = rte_cpu_to_le_16(index);
3831         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3832         HWRM_CHECK_RESULT();
3833         HWRM_UNLOCK();
3834
3835         return rc;
3836 }
3837
3838
3839 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3840                           uint16_t dir_ordinal, uint16_t dir_ext,
3841                           uint16_t dir_attr, const uint8_t *data,
3842                           size_t data_len)
3843 {
3844         int rc;
3845         struct hwrm_nvm_write_input req = {0};
3846         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3847         rte_iova_t dma_handle;
3848         uint8_t *buf;
3849
3850         buf = rte_malloc("nvm_write", data_len, 0);
3851         rte_mem_lock_page(buf);
3852         if (!buf)
3853                 return -ENOMEM;
3854
3855         dma_handle = rte_mem_virt2iova(buf);
3856         if (dma_handle == RTE_BAD_IOVA) {
3857                 PMD_DRV_LOG(ERR,
3858                         "unable to map response address to physical memory\n");
3859                 return -ENOMEM;
3860         }
3861         memcpy(buf, data, data_len);
3862
3863         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3864
3865         req.dir_type = rte_cpu_to_le_16(dir_type);
3866         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3867         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3868         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3869         req.dir_data_length = rte_cpu_to_le_32(data_len);
3870         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3871
3872         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3873
3874         rte_free(buf);
3875         HWRM_CHECK_RESULT();
3876         HWRM_UNLOCK();
3877
3878         return rc;
3879 }
3880
3881 static void
3882 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3883 {
3884         uint32_t *count = cbdata;
3885
3886         *count = *count + 1;
3887 }
3888
3889 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3890                                      struct bnxt_vnic_info *vnic __rte_unused)
3891 {
3892         return 0;
3893 }
3894
3895 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3896 {
3897         uint32_t count = 0;
3898
3899         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3900             &count, bnxt_vnic_count_hwrm_stub);
3901
3902         return count;
3903 }
3904
3905 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3906                                         uint16_t *vnic_ids)
3907 {
3908         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3909         struct hwrm_func_vf_vnic_ids_query_output *resp =
3910                                                 bp->hwrm_cmd_resp_addr;
3911         int rc;
3912
3913         /* First query all VNIC ids */
3914         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3915
3916         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3917         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3918         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3919
3920         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3921                 HWRM_UNLOCK();
3922                 PMD_DRV_LOG(ERR,
3923                 "unable to map VNIC ID table address to physical memory\n");
3924                 return -ENOMEM;
3925         }
3926         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3927         HWRM_CHECK_RESULT();
3928         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3929
3930         HWRM_UNLOCK();
3931
3932         return rc;
3933 }
3934
3935 /*
3936  * This function queries the VNIC IDs  for a specified VF. It then calls
3937  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3938  * Then it calls the hwrm_cb function to program this new vnic configuration.
3939  */
3940 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3941         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3942         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3943 {
3944         struct bnxt_vnic_info vnic;
3945         int rc = 0;
3946         int i, num_vnic_ids;
3947         uint16_t *vnic_ids;
3948         size_t vnic_id_sz;
3949         size_t sz;
3950
3951         /* First query all VNIC ids */
3952         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3953         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3954                         RTE_CACHE_LINE_SIZE);
3955         if (vnic_ids == NULL)
3956                 return -ENOMEM;
3957
3958         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3959                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3960
3961         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3962
3963         if (num_vnic_ids < 0)
3964                 return num_vnic_ids;
3965
3966         /* Retrieve VNIC, update bd_stall then update */
3967
3968         for (i = 0; i < num_vnic_ids; i++) {
3969                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3970                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3971                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3972                 if (rc)
3973                         break;
3974                 if (vnic.mru <= 4)      /* Indicates unallocated */
3975                         continue;
3976
3977                 vnic_cb(&vnic, cbdata);
3978
3979                 rc = hwrm_cb(bp, &vnic);
3980                 if (rc)
3981                         break;
3982         }
3983
3984         rte_free(vnic_ids);
3985
3986         return rc;
3987 }
3988
3989 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3990                                               bool on)
3991 {
3992         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3993         struct hwrm_func_cfg_input req = {0};
3994         int rc;
3995
3996         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3997
3998         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3999         req.enables |= rte_cpu_to_le_32(
4000                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4001         req.vlan_antispoof_mode = on ?
4002                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4003                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4004         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4005
4006         HWRM_CHECK_RESULT();
4007         HWRM_UNLOCK();
4008
4009         return rc;
4010 }
4011
4012 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4013 {
4014         struct bnxt_vnic_info vnic;
4015         uint16_t *vnic_ids;
4016         size_t vnic_id_sz;
4017         int num_vnic_ids, i;
4018         size_t sz;
4019         int rc;
4020
4021         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4022         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4023                         RTE_CACHE_LINE_SIZE);
4024         if (vnic_ids == NULL)
4025                 return -ENOMEM;
4026
4027         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4028                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4029
4030         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4031         if (rc <= 0)
4032                 goto exit;
4033         num_vnic_ids = rc;
4034
4035         /*
4036          * Loop through to find the default VNIC ID.
4037          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4038          * by sending the hwrm_func_qcfg command to the firmware.
4039          */
4040         for (i = 0; i < num_vnic_ids; i++) {
4041                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4042                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4043                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4044                                         bp->pf.first_vf_id + vf);
4045                 if (rc)
4046                         goto exit;
4047                 if (vnic.func_default) {
4048                         rte_free(vnic_ids);
4049                         return vnic.fw_vnic_id;
4050                 }
4051         }
4052         /* Could not find a default VNIC. */
4053         PMD_DRV_LOG(ERR, "No default VNIC\n");
4054 exit:
4055         rte_free(vnic_ids);
4056         return rc;
4057 }
4058
4059 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4060                          uint16_t dst_id,
4061                          struct bnxt_filter_info *filter)
4062 {
4063         int rc = 0;
4064         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4065         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4066         uint32_t enables = 0;
4067
4068         if (filter->fw_em_filter_id != UINT64_MAX)
4069                 bnxt_hwrm_clear_em_filter(bp, filter);
4070
4071         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4072
4073         req.flags = rte_cpu_to_le_32(filter->flags);
4074
4075         enables = filter->enables |
4076               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4077         req.dst_id = rte_cpu_to_le_16(dst_id);
4078
4079         if (filter->ip_addr_type) {
4080                 req.ip_addr_type = filter->ip_addr_type;
4081                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4082         }
4083         if (enables &
4084             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4085                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4086         if (enables &
4087             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4088                 memcpy(req.src_macaddr, filter->src_macaddr,
4089                        RTE_ETHER_ADDR_LEN);
4090         if (enables &
4091             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4092                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4093                        RTE_ETHER_ADDR_LEN);
4094         if (enables &
4095             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4096                 req.ovlan_vid = filter->l2_ovlan;
4097         if (enables &
4098             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4099                 req.ivlan_vid = filter->l2_ivlan;
4100         if (enables &
4101             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4102                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4103         if (enables &
4104             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4105                 req.ip_protocol = filter->ip_protocol;
4106         if (enables &
4107             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4108                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4109         if (enables &
4110             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4111                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4112         if (enables &
4113             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4114                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4115         if (enables &
4116             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4117                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4118         if (enables &
4119             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4120                 req.mirror_vnic_id = filter->mirror_vnic_id;
4121
4122         req.enables = rte_cpu_to_le_32(enables);
4123
4124         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4125
4126         HWRM_CHECK_RESULT();
4127
4128         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4129         HWRM_UNLOCK();
4130
4131         return rc;
4132 }
4133
4134 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4135 {
4136         int rc = 0;
4137         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4138         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4139
4140         if (filter->fw_em_filter_id == UINT64_MAX)
4141                 return 0;
4142
4143         PMD_DRV_LOG(ERR, "Clear EM filter\n");
4144         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4145
4146         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4147
4148         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4149
4150         HWRM_CHECK_RESULT();
4151         HWRM_UNLOCK();
4152
4153         filter->fw_em_filter_id = UINT64_MAX;
4154         filter->fw_l2_filter_id = UINT64_MAX;
4155
4156         return 0;
4157 }
4158
4159 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4160                          uint16_t dst_id,
4161                          struct bnxt_filter_info *filter)
4162 {
4163         int rc = 0;
4164         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4165         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4166                                                 bp->hwrm_cmd_resp_addr;
4167         uint32_t enables = 0;
4168
4169         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4170                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4171
4172         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4173
4174         req.flags = rte_cpu_to_le_32(filter->flags);
4175
4176         enables = filter->enables |
4177               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4178         req.dst_id = rte_cpu_to_le_16(dst_id);
4179
4180
4181         if (filter->ip_addr_type) {
4182                 req.ip_addr_type = filter->ip_addr_type;
4183                 enables |=
4184                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4185         }
4186         if (enables &
4187             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4188                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4189         if (enables &
4190             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4191                 memcpy(req.src_macaddr, filter->src_macaddr,
4192                        RTE_ETHER_ADDR_LEN);
4193         //if (enables &
4194             //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4195                 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4196                        //RTE_ETHER_ADDR_LEN);
4197         if (enables &
4198             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4199                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4200         if (enables &
4201             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4202                 req.ip_protocol = filter->ip_protocol;
4203         if (enables &
4204             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4205                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4206         if (enables &
4207             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4208                 req.src_ipaddr_mask[0] =
4209                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4210         if (enables &
4211             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4212                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4213         if (enables &
4214             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4215                 req.dst_ipaddr_mask[0] =
4216                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4217         if (enables &
4218             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4219                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4220         if (enables &
4221             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4222                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4223         if (enables &
4224             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4225                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4226         if (enables &
4227             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4228                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4229         if (enables &
4230             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4231                 req.mirror_vnic_id = filter->mirror_vnic_id;
4232
4233         req.enables = rte_cpu_to_le_32(enables);
4234
4235         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4236
4237         HWRM_CHECK_RESULT();
4238
4239         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4240         HWRM_UNLOCK();
4241
4242         return rc;
4243 }
4244
4245 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4246                                 struct bnxt_filter_info *filter)
4247 {
4248         int rc = 0;
4249         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4250         struct hwrm_cfa_ntuple_filter_free_output *resp =
4251                                                 bp->hwrm_cmd_resp_addr;
4252
4253         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4254                 return 0;
4255
4256         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4257
4258         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4259
4260         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4261
4262         HWRM_CHECK_RESULT();
4263         HWRM_UNLOCK();
4264
4265         filter->fw_ntuple_filter_id = UINT64_MAX;
4266
4267         return 0;
4268 }
4269
4270 static int
4271 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4272 {
4273         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4274         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4275         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4276         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4277         uint16_t *ring_tbl = vnic->rss_table;
4278         int nr_ctxs = vnic->num_lb_ctxts;
4279         int max_rings = bp->rx_nr_rings;
4280         int i, j, k, cnt;
4281         int rc = 0;
4282
4283         for (i = 0, k = 0; i < nr_ctxs; i++) {
4284                 struct bnxt_rx_ring_info *rxr;
4285                 struct bnxt_cp_ring_info *cpr;
4286
4287                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4288
4289                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4290                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4291                 req.hash_mode_flags = vnic->hash_mode;
4292
4293                 req.ring_grp_tbl_addr =
4294                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4295                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4296                                      2 * sizeof(*ring_tbl));
4297                 req.hash_key_tbl_addr =
4298                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4299
4300                 req.ring_table_pair_index = i;
4301                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4302
4303                 for (j = 0; j < 64; j++) {
4304                         uint16_t ring_id;
4305
4306                         /* Find next active ring. */
4307                         for (cnt = 0; cnt < max_rings; cnt++) {
4308                                 if (rx_queue_state[k] !=
4309                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4310                                         break;
4311                                 if (++k == max_rings)
4312                                         k = 0;
4313                         }
4314
4315                         /* Return if no rings are active. */
4316                         if (cnt == max_rings)
4317                                 return 0;
4318
4319                         /* Add rx/cp ring pair to RSS table. */
4320                         rxr = rxqs[k]->rx_ring;
4321                         cpr = rxqs[k]->cp_ring;
4322
4323                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4324                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4325                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4326                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4327
4328                         if (++k == max_rings)
4329                                 k = 0;
4330                 }
4331                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4332                                             BNXT_USE_CHIMP_MB);
4333
4334                 HWRM_CHECK_RESULT();
4335                 HWRM_UNLOCK();
4336         }
4337
4338         return rc;
4339 }
4340
4341 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4342 {
4343         unsigned int rss_idx, fw_idx, i;
4344
4345         if (!(vnic->rss_table && vnic->hash_type))
4346                 return 0;
4347
4348         if (BNXT_CHIP_THOR(bp))
4349                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4350
4351         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4352                 return 0;
4353
4354         if (vnic->rss_table && vnic->hash_type) {
4355                 /*
4356                  * Fill the RSS hash & redirection table with
4357                  * ring group ids for all VNICs
4358                  */
4359                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4360                         rss_idx++, fw_idx++) {
4361                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4362                                 fw_idx %= bp->rx_cp_nr_rings;
4363                                 if (vnic->fw_grp_ids[fw_idx] !=
4364                                     INVALID_HW_RING_ID)
4365                                         break;
4366                                 fw_idx++;
4367                         }
4368                         if (i == bp->rx_cp_nr_rings)
4369                                 return 0;
4370                         vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4371                 }
4372                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4373         }
4374
4375         return 0;
4376 }
4377
4378 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4379         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4380 {
4381         uint16_t flags;
4382
4383         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4384
4385         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4386         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4387
4388         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4389         req->num_cmpl_dma_aggr_during_int =
4390                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4391
4392         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4393
4394         /* min timer set to 1/2 of interrupt timer */
4395         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4396
4397         /* buf timer set to 1/4 of interrupt timer */
4398         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4399
4400         req->cmpl_aggr_dma_tmr_during_int =
4401                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4402
4403         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4404                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4405         req->flags = rte_cpu_to_le_16(flags);
4406 }
4407
4408 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4409                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4410 {
4411         struct hwrm_ring_aggint_qcaps_input req = {0};
4412         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4413         uint32_t enables;
4414         uint16_t flags;
4415         int rc;
4416
4417         HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4418         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4419         HWRM_CHECK_RESULT();
4420
4421         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4422         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4423
4424         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4425                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4426         agg_req->flags = rte_cpu_to_le_16(flags);
4427         enables =
4428          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4429          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4430         agg_req->enables = rte_cpu_to_le_32(enables);
4431
4432         HWRM_UNLOCK();
4433         return rc;
4434 }
4435
4436 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4437                         struct bnxt_coal *coal, uint16_t ring_id)
4438 {
4439         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4440         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4441                                                 bp->hwrm_cmd_resp_addr;
4442         int rc;
4443
4444         /* Set ring coalesce parameters only for 100G NICs */
4445         if (BNXT_CHIP_THOR(bp)) {
4446                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4447                         return -1;
4448         } else if (bnxt_stratus_device(bp)) {
4449                 bnxt_hwrm_set_coal_params(coal, &req);
4450         } else {
4451                 return 0;
4452         }
4453
4454         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4455         req.ring_id = rte_cpu_to_le_16(ring_id);
4456         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4457         HWRM_CHECK_RESULT();
4458         HWRM_UNLOCK();
4459         return 0;
4460 }
4461
4462 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4463 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4464 {
4465         struct hwrm_func_backing_store_qcaps_input req = {0};
4466         struct hwrm_func_backing_store_qcaps_output *resp =
4467                 bp->hwrm_cmd_resp_addr;
4468         struct bnxt_ctx_pg_info *ctx_pg;
4469         struct bnxt_ctx_mem_info *ctx;
4470         int total_alloc_len;
4471         int rc, i;
4472
4473         if (!BNXT_CHIP_THOR(bp) ||
4474             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4475             BNXT_VF(bp) ||
4476             bp->ctx)
4477                 return 0;
4478
4479         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4480         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4481         HWRM_CHECK_RESULT_SILENT();
4482
4483         total_alloc_len = sizeof(*ctx);
4484         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4485                           RTE_CACHE_LINE_SIZE);
4486         if (!ctx) {
4487                 rc = -ENOMEM;
4488                 goto ctx_err;
4489         }
4490
4491         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4492                             sizeof(*ctx_pg) * BNXT_MAX_Q,
4493                             RTE_CACHE_LINE_SIZE);
4494         if (!ctx_pg) {
4495                 rc = -ENOMEM;
4496                 goto ctx_err;
4497         }
4498         for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4499                 ctx->tqm_mem[i] = ctx_pg;
4500
4501         bp->ctx = ctx;
4502         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4503         ctx->qp_min_qp1_entries =
4504                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4505         ctx->qp_max_l2_entries =
4506                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4507         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4508         ctx->srq_max_l2_entries =
4509                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4510         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4511         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4512         ctx->cq_max_l2_entries =
4513                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4514         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4515         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4516         ctx->vnic_max_vnic_entries =
4517                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4518         ctx->vnic_max_ring_table_entries =
4519                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4520         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4521         ctx->stat_max_entries =
4522                 rte_le_to_cpu_32(resp->stat_max_entries);
4523         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4524         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4525         ctx->tqm_min_entries_per_ring =
4526                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4527         ctx->tqm_max_entries_per_ring =
4528                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4529         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4530         if (!ctx->tqm_entries_multiple)
4531                 ctx->tqm_entries_multiple = 1;
4532         ctx->mrav_max_entries =
4533                 rte_le_to_cpu_32(resp->mrav_max_entries);
4534         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4535         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4536         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4537 ctx_err:
4538         HWRM_UNLOCK();
4539         return rc;
4540 }
4541
4542 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4543 {
4544         struct hwrm_func_backing_store_cfg_input req = {0};
4545         struct hwrm_func_backing_store_cfg_output *resp =
4546                 bp->hwrm_cmd_resp_addr;
4547         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4548         struct bnxt_ctx_pg_info *ctx_pg;
4549         uint32_t *num_entries;
4550         uint64_t *pg_dir;
4551         uint8_t *pg_attr;
4552         uint32_t ena;
4553         int i, rc;
4554
4555         if (!ctx)
4556                 return 0;
4557
4558         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4559         req.enables = rte_cpu_to_le_32(enables);
4560
4561         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4562                 ctx_pg = &ctx->qp_mem;
4563                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4564                 req.qp_num_qp1_entries =
4565                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4566                 req.qp_num_l2_entries =
4567                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4568                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4569                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4570                                       &req.qpc_pg_size_qpc_lvl,
4571                                       &req.qpc_page_dir);
4572         }
4573
4574         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4575                 ctx_pg = &ctx->srq_mem;
4576                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4577                 req.srq_num_l2_entries =
4578                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4579                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4580                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4581                                       &req.srq_pg_size_srq_lvl,
4582                                       &req.srq_page_dir);
4583         }
4584
4585         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4586                 ctx_pg = &ctx->cq_mem;
4587                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4588                 req.cq_num_l2_entries =
4589                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4590                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4591                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4592                                       &req.cq_pg_size_cq_lvl,
4593                                       &req.cq_page_dir);
4594         }
4595
4596         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4597                 ctx_pg = &ctx->vnic_mem;
4598                 req.vnic_num_vnic_entries =
4599                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4600                 req.vnic_num_ring_table_entries =
4601                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4602                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4603                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4604                                       &req.vnic_pg_size_vnic_lvl,
4605                                       &req.vnic_page_dir);
4606         }
4607
4608         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4609                 ctx_pg = &ctx->stat_mem;
4610                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4611                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4612                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4613                                       &req.stat_pg_size_stat_lvl,
4614                                       &req.stat_page_dir);
4615         }
4616
4617         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4618         num_entries = &req.tqm_sp_num_entries;
4619         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4620         pg_dir = &req.tqm_sp_page_dir;
4621         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4622         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4623                 if (!(enables & ena))
4624                         continue;
4625
4626                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4627
4628                 ctx_pg = ctx->tqm_mem[i];
4629                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4630                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4631         }
4632
4633         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4634         HWRM_CHECK_RESULT();
4635         HWRM_UNLOCK();
4636
4637         return rc;
4638 }
4639
4640 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4641 {
4642         struct hwrm_port_qstats_ext_input req = {0};
4643         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4644         struct bnxt_pf_info *pf = &bp->pf;
4645         int rc;
4646
4647         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4648               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4649                 return 0;
4650
4651         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4652
4653         req.port_id = rte_cpu_to_le_16(pf->port_id);
4654         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4655                 req.tx_stat_host_addr =
4656                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4657                 req.tx_stat_size =
4658                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4659         }
4660         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4661                 req.rx_stat_host_addr =
4662                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4663                 req.rx_stat_size =
4664                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4665         }
4666         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4667
4668         if (rc) {
4669                 bp->fw_rx_port_stats_ext_size = 0;
4670                 bp->fw_tx_port_stats_ext_size = 0;
4671         } else {
4672                 bp->fw_rx_port_stats_ext_size =
4673                         rte_le_to_cpu_16(resp->rx_stat_size);
4674                 bp->fw_tx_port_stats_ext_size =
4675                         rte_le_to_cpu_16(resp->tx_stat_size);
4676         }
4677
4678         HWRM_CHECK_RESULT();
4679         HWRM_UNLOCK();
4680
4681         return rc;
4682 }
4683
4684 int
4685 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4686 {
4687         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4688         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4689                 bp->hwrm_cmd_resp_addr;
4690         int rc = 0;
4691
4692         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4693         req.tunnel_type = type;
4694         req.dest_fid = bp->fw_fid;
4695         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4696         HWRM_CHECK_RESULT();
4697
4698         HWRM_UNLOCK();
4699
4700         return rc;
4701 }
4702
4703 int
4704 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4705 {
4706         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4707         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4708                 bp->hwrm_cmd_resp_addr;
4709         int rc = 0;
4710
4711         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4712         req.tunnel_type = type;
4713         req.dest_fid = bp->fw_fid;
4714         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4715         HWRM_CHECK_RESULT();
4716
4717         HWRM_UNLOCK();
4718
4719         return rc;
4720 }
4721
4722 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4723 {
4724         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4725         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4726                 bp->hwrm_cmd_resp_addr;
4727         int rc = 0;
4728
4729         HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4730         req.src_fid = bp->fw_fid;
4731         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4732         HWRM_CHECK_RESULT();
4733
4734         if (type)
4735                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4736
4737         HWRM_UNLOCK();
4738
4739         return rc;
4740 }
4741
4742 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4743                                    uint16_t *dst_fid)
4744 {
4745         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4746         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4747                 bp->hwrm_cmd_resp_addr;
4748         int rc = 0;
4749
4750         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4751         req.src_fid = bp->fw_fid;
4752         req.tunnel_type = tun_type;
4753         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4754         HWRM_CHECK_RESULT();
4755
4756         if (dst_fid)
4757                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4758
4759         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4760
4761         HWRM_UNLOCK();
4762
4763         return rc;
4764 }
4765
4766 int bnxt_hwrm_set_mac(struct bnxt *bp)
4767 {
4768         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4769         struct hwrm_func_vf_cfg_input req = {0};
4770         int rc = 0;
4771
4772         if (!BNXT_VF(bp))
4773                 return 0;
4774
4775         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4776
4777         req.enables =
4778                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4779         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4780
4781         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4782
4783         HWRM_CHECK_RESULT();
4784
4785         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4786         HWRM_UNLOCK();
4787
4788         return rc;
4789 }
4790
4791 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4792 {
4793         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4794         struct hwrm_func_drv_if_change_input req = {0};
4795         uint32_t flags;
4796         int rc;
4797
4798         if (!(bp->flags & BNXT_FLAG_FW_CAP_IF_CHANGE))
4799                 return 0;
4800
4801         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4802          * If we issue FUNC_DRV_IF_CHANGE with flags down before
4803          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4804          */
4805         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4806                 return 0;
4807
4808         HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4809
4810         if (up)
4811                 req.flags =
4812                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4813
4814         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4815
4816         HWRM_CHECK_RESULT();
4817         flags = rte_le_to_cpu_32(resp->flags);
4818         HWRM_UNLOCK();
4819
4820         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4821                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4822                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4823         }
4824
4825         return 0;
4826 }
4827
4828 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4829 {
4830         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4831         struct bnxt_error_recovery_info *info = bp->recovery_info;
4832         struct hwrm_error_recovery_qcfg_input req = {0};
4833         uint32_t flags = 0;
4834         unsigned int i;
4835         int rc;
4836
4837         /* Older FW does not have error recovery support */
4838         if (!(bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY))
4839                 return 0;
4840
4841         if (!info) {
4842                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4843                                    sizeof(*info), 0);
4844                 bp->recovery_info = info;
4845                 if (info == NULL)
4846                         return -ENOMEM;
4847         } else {
4848                 memset(info, 0, sizeof(*info));
4849         }
4850
4851         HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4852
4853         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4854
4855         HWRM_CHECK_RESULT();
4856
4857         flags = rte_le_to_cpu_32(resp->flags);
4858         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4859                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4860         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4861                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4862
4863         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4864             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4865                 rc = -EINVAL;
4866                 goto err;
4867         }
4868
4869         /* FW returned values are in units of 100msec */
4870         info->driver_polling_freq =
4871                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4872         info->master_func_wait_period =
4873                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4874         info->normal_func_wait_period =
4875                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4876         info->master_func_wait_period_after_reset =
4877                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4878         info->max_bailout_time_after_reset =
4879                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4880         info->status_regs[BNXT_FW_STATUS_REG] =
4881                 rte_le_to_cpu_32(resp->fw_health_status_reg);
4882         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4883                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4884         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4885                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4886         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4887                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4888         info->reg_array_cnt =
4889                 rte_le_to_cpu_32(resp->reg_array_cnt);
4890
4891         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4892                 rc = -EINVAL;
4893                 goto err;
4894         }
4895
4896         for (i = 0; i < info->reg_array_cnt; i++) {
4897                 info->reset_reg[i] =
4898                         rte_le_to_cpu_32(resp->reset_reg[i]);
4899                 info->reset_reg_val[i] =
4900                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
4901                 info->delay_after_reset[i] =
4902                         resp->delay_after_reset[i];
4903         }
4904 err:
4905         HWRM_UNLOCK();
4906
4907         /* Map the FW status registers */
4908         if (!rc)
4909                 rc = bnxt_map_fw_health_status_regs(bp);
4910
4911         if (rc) {
4912                 rte_free(bp->recovery_info);
4913                 bp->recovery_info = NULL;
4914         }
4915         return rc;
4916 }
4917
4918 int bnxt_hwrm_fw_reset(struct bnxt *bp)
4919 {
4920         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
4921         struct hwrm_fw_reset_input req = {0};
4922         int rc;
4923
4924         if (!BNXT_PF(bp))
4925                 return -EOPNOTSUPP;
4926
4927         HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
4928
4929         req.embedded_proc_type =
4930                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
4931         req.selfrst_status =
4932                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
4933         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
4934
4935         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4936                                     BNXT_USE_KONG(bp));
4937
4938         HWRM_CHECK_RESULT();
4939         HWRM_UNLOCK();
4940
4941         return rc;
4942 }
4943
4944 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
4945 {
4946         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
4947         struct hwrm_port_ts_query_input req = {0};
4948         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4949         uint32_t flags = 0;
4950         int rc;
4951
4952         if (!ptp)
4953                 return 0;
4954
4955         HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
4956
4957         switch (path) {
4958         case BNXT_PTP_FLAGS_PATH_TX:
4959                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
4960                 break;
4961         case BNXT_PTP_FLAGS_PATH_RX:
4962                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
4963                 break;
4964         case BNXT_PTP_FLAGS_CURRENT_TIME:
4965                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
4966                 break;
4967         }
4968
4969         req.flags = rte_cpu_to_le_32(flags);
4970         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
4971
4972         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4973
4974         HWRM_CHECK_RESULT();
4975
4976         if (timestamp) {
4977                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
4978                 *timestamp |=
4979                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
4980         }
4981         HWRM_UNLOCK();
4982
4983         return rc;
4984 }
4985
4986 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
4987 {
4988         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
4989                                         bp->hwrm_cmd_resp_addr;
4990         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
4991         uint32_t flags = 0;
4992         int rc = 0;
4993
4994         if (!(bp->flags & BNXT_FLAG_ADV_FLOW_MGMT))
4995                 return rc;
4996
4997         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
4998                 PMD_DRV_LOG(DEBUG,
4999                             "Not a PF or trusted VF. Command not supported\n");
5000                 return 0;
5001         }
5002
5003         HWRM_PREP(req, CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5004         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5005
5006         HWRM_CHECK_RESULT();
5007         flags = rte_le_to_cpu_32(resp->flags);
5008         HWRM_UNLOCK();
5009
5010         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5011                 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5012                 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");
5013         }
5014
5015         return rc;
5016 }