drivers/net/bnxt/bnxt_hwrm.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) Broadcom Limited.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Broadcom Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <unistd.h>
  35
  36 #include <unistd.h>
  37
  38 #include <rte_byteorder.h>
  39 #include <rte_common.h>
  40 #include <rte_cycles.h>
  41 #include <rte_malloc.h>
  42 #include <rte_memzone.h>
  43 #include <rte_version.h>
  44
  45 #include "bnxt.h"
  46 #include "bnxt_cpr.h"
  47 #include "bnxt_filter.h"
  48 #include "bnxt_hwrm.h"
  49 #include "bnxt_rxq.h"
  50 #include "bnxt_rxr.h"
  51 #include "bnxt_ring.h"
  52 #include "bnxt_txq.h"
  53 #include "bnxt_txr.h"
  54 #include "bnxt_vnic.h"
  55 #include "hsi_struct_def_dpdk.h"
  56
  57 #include <rte_io.h>
  58
  59 #define HWRM_CMD_TIMEOUT                2000
  60
  61 struct bnxt_plcmodes_cfg {
  62         uint32_t        flags;
  63         uint16_t        jumbo_thresh;
  64         uint16_t        hds_offset;
  65         uint16_t        hds_threshold;
  66 };
  67
  68 static int page_getenum(size_t size)
  69 {
  70         if (size <= 1 << 4)
  71                 return 4;
  72         if (size <= 1 << 12)
  73                 return 12;
  74         if (size <= 1 << 13)
  75                 return 13;
  76         if (size <= 1 << 16)
  77                 return 16;
  78         if (size <= 1 << 21)
  79                 return 21;
  80         if (size <= 1 << 22)
  81                 return 22;
  82         if (size <= 1 << 30)
  83                 return 30;
  84         RTE_LOG(ERR, PMD, "Page size %zu out of range\n", size);
  85         return sizeof(void *) * 8 - 1;
  86 }
  87
  88 static int page_roundup(size_t size)
  89 {
  90         return 1 << page_getenum(size);
  91 }
  92
  93 /*
  94  * HWRM Functions (sent to HWRM)
  95  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  96  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  97  * command was failed by the ChiMP.
  98  */
  99
 100 static int bnxt_hwrm_send_message_locked(struct bnxt *bp, void *msg,
 101                                         uint32_t msg_len)
 102 {
 103         unsigned int i;
 104         struct input *req = msg;
 105         struct output *resp = bp->hwrm_cmd_resp_addr;
 106         uint32_t *data = msg;
 107         uint8_t *bar;
 108         uint8_t *valid;
 109
 110         /* Write request msg to hwrm channel */
 111         for (i = 0; i < msg_len; i += 4) {
 112                 bar = (uint8_t *)bp->bar0 + i;
 113                 rte_write32(*data, bar);
 114                 data++;
 115         }
 116
 117         /* Zero the rest of the request space */
 118         for (; i < bp->max_req_len; i += 4) {
 119                 bar = (uint8_t *)bp->bar0 + i;
 120                 rte_write32(0, bar);
 121         }
 122
 123         /* Ring channel doorbell */
 124         bar = (uint8_t *)bp->bar0 + 0x100;
 125         rte_write32(1, bar);
 126
 127         /* Poll for the valid bit */
 128         for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
 129                 /* Sanity check on the resp->resp_len */
 130                 rte_rmb();
 131                 if (resp->resp_len && resp->resp_len <=
 132                                 bp->max_resp_len) {
 133                         /* Last byte of resp contains the valid key */
 134                         valid = (uint8_t *)resp + resp->resp_len - 1;
 135                         if (*valid == HWRM_RESP_VALID_KEY)
 136                                 break;
 137                 }
 138                 rte_delay_us(600);
 139         }
 140
 141         if (i >= HWRM_CMD_TIMEOUT) {
 142                 RTE_LOG(ERR, PMD, "Error sending msg 0x%04x\n",
 143                         req->req_type);
 144                 goto err_ret;
 145         }
 146         return 0;
 147
 148 err_ret:
 149         return -1;
 150 }
 151
 152 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg, uint32_t msg_len)
 153 {
 154         int rc;
 155
 156         rte_spinlock_lock(&bp->hwrm_lock);
 157         rc = bnxt_hwrm_send_message_locked(bp, msg, msg_len);
 158         rte_spinlock_unlock(&bp->hwrm_lock);
 159         return rc;
 160 }
 161
 162 #define HWRM_PREP(req, type, cr, resp) \
 163         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 164         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 165         req.cmpl_ring = rte_cpu_to_le_16(cr); \
 166         req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 167         req.target_id = rte_cpu_to_le_16(0xffff); \
 168         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr)
 169
 170 #define HWRM_CHECK_RESULT \
 171         { \
 172                 if (rc) { \
 173                         RTE_LOG(ERR, PMD, "%s failed rc:%d\n", \
 174                                 __func__, rc); \
 175                         return rc; \
 176                 } \
 177                 if (resp->error_code) { \
 178                         rc = rte_le_to_cpu_16(resp->error_code); \
 179                         if (resp->resp_len >= 16) { \
 180                                 struct hwrm_err_output *tmp_hwrm_err_op = \
 181                                                         (void *)resp; \
 182                                 RTE_LOG(ERR, PMD, \
 183                                         "%s error %d:%d:%08x:%04x\n", \
 184                                         __func__, \
 185                                         rc, tmp_hwrm_err_op->cmd_err, \
 186                                         rte_le_to_cpu_32(\
 187                                                 tmp_hwrm_err_op->opaque_0), \
 188                                         rte_le_to_cpu_16(\
 189                                                 tmp_hwrm_err_op->opaque_1)); \
 190                         } \
 191                         else { \
 192                                 RTE_LOG(ERR, PMD, \
 193                                         "%s error %d\n", __func__, rc); \
 194                         } \
 195                         return rc; \
 196                 } \
 197         }
 198
 199 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 200 {
 201         int rc = 0;
 202         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 203         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 204
 205         HWRM_PREP(req, CFA_L2_SET_RX_MASK, -1, resp);
 206         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 207         req.mask = 0;
 208
 209         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 210
 211         HWRM_CHECK_RESULT;
 212
 213         return rc;
 214 }
 215
 216 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 217                                  struct bnxt_vnic_info *vnic,
 218                                  uint16_t vlan_count,
 219                                  struct bnxt_vlan_table_entry *vlan_table)
 220 {
 221         int rc = 0;
 222         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 223         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 224         uint32_t mask = 0;
 225
 226         HWRM_PREP(req, CFA_L2_SET_RX_MASK, -1, resp);
 227         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 228
 229         /* FIXME add multicast flag, when multicast adding options is supported
 230          * by ethtool.
 231          */
 232         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 233                 mask = HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 234         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 235                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 236         if (vnic->mc_addr_cnt) {
 237                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 238                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 239                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 240         }
 241         req.mask = rte_cpu_to_le_32(HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST |
 242                                     mask);
 243         if (vlan_count && vlan_table) {
 244                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 245                 req.vlan_tag_tbl_addr = rte_cpu_to_le_16(
 246                          rte_mem_virt2phy(vlan_table));
 247                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 248         }
 249
 250         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 251
 252         HWRM_CHECK_RESULT;
 253
 254         return rc;
 255 }
 256
 257 int bnxt_hwrm_clear_filter(struct bnxt *bp,
 258                            struct bnxt_filter_info *filter)
 259 {
 260         int rc = 0;
 261         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 262         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 263
 264         HWRM_PREP(req, CFA_L2_FILTER_FREE, -1, resp);
 265
 266         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 267
 268         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 269
 270         HWRM_CHECK_RESULT;
 271
 272         filter->fw_l2_filter_id = -1;
 273
 274         return 0;
 275 }
 276
 277 int bnxt_hwrm_set_filter(struct bnxt *bp,
 278                          uint16_t dst_id,
 279                          struct bnxt_filter_info *filter)
 280 {
 281         int rc = 0;
 282         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 283         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 284         uint32_t enables = 0;
 285
 286         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, -1, resp);
 287
 288         req.flags = rte_cpu_to_le_32(filter->flags);
 289
 290         enables = filter->enables |
 291               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 292         req.dst_id = rte_cpu_to_le_16(dst_id);
 293
 294         if (enables &
 295             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 296                 memcpy(req.l2_addr, filter->l2_addr,
 297                        ETHER_ADDR_LEN);
 298         if (enables &
 299             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 300                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 301                        ETHER_ADDR_LEN);
 302         if (enables &
 303             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 304                 req.l2_ovlan = filter->l2_ovlan;
 305         if (enables &
 306             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 307                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 308         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 309                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 310         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 311                 req.src_type = filter->src_type;
 312
 313         req.enables = rte_cpu_to_le_32(enables);
 314
 315         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 316
 317         HWRM_CHECK_RESULT;
 318
 319         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 320
 321         return rc;
 322 }
 323
 324 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 325 {
 326         int rc = 0;
 327         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 328         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 329         uint16_t new_max_vfs;
 330         int i;
 331
 332         HWRM_PREP(req, FUNC_QCAPS, -1, resp);
 333
 334         req.fid = rte_cpu_to_le_16(0xffff);
 335
 336         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 337
 338         HWRM_CHECK_RESULT;
 339
 340         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 341         if (BNXT_PF(bp)) {
 342                 bp->pf.port_id = resp->port_id;
 343                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 344                 new_max_vfs = bp->pdev->max_vfs;
 345                 if (new_max_vfs != bp->pf.max_vfs) {
 346                         if (bp->pf.vf_info)
 347                                 rte_free(bp->pf.vf_info);
 348                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 349                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 350                         bp->pf.max_vfs = new_max_vfs;
 351                         for (i = 0; i < new_max_vfs; i++) {
 352                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 353                                 bp->pf.vf_info[i].vlan_table =
 354                                         rte_zmalloc("VF VLAN table",
 355                                                     getpagesize(),
 356                                                     getpagesize());
 357                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 358                                         RTE_LOG(ERR, PMD,
 359                                         "Fail to alloc VLAN table for VF %d\n",
 360                                         i);
 361                                 else
 362                                         rte_mem_lock_page(
 363                                                 bp->pf.vf_info[i].vlan_table);
 364                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 365                         }
 366                 }
 367         }
 368
 369         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 370         memcpy(bp->dflt_mac_addr, &resp->mac_address, ETHER_ADDR_LEN);
 371         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 372         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 373         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 374         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 375         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 376         /* TODO: For now, do not support VMDq/RFS on VFs. */
 377         if (BNXT_PF(bp)) {
 378                 if (bp->pf.max_vfs)
 379                         bp->max_vnics = 1;
 380                 else
 381                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 382         } else {
 383                 bp->max_vnics = 1;
 384         }
 385         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 386         if (BNXT_PF(bp))
 387                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 388
 389         return rc;
 390 }
 391
 392 int bnxt_hwrm_func_reset(struct bnxt *bp)
 393 {
 394         int rc = 0;
 395         struct hwrm_func_reset_input req = {.req_type = 0 };
 396         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 397
 398         HWRM_PREP(req, FUNC_RESET, -1, resp);
 399
 400         req.enables = rte_cpu_to_le_32(0);
 401
 402         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 403
 404         HWRM_CHECK_RESULT;
 405
 406         return rc;
 407 }
 408
 409 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 410 {
 411         int rc;
 412         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 413         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 414
 415         if (bp->flags & BNXT_FLAG_REGISTERED)
 416                 return 0;
 417
 418         HWRM_PREP(req, FUNC_DRV_RGTR, -1, resp);
 419         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 420                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 421         req.ver_maj = RTE_VER_YEAR;
 422         req.ver_min = RTE_VER_MONTH;
 423         req.ver_upd = RTE_VER_MINOR;
 424
 425         if (BNXT_PF(bp)) {
 426                 req.enables |= rte_cpu_to_le_32(
 427                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_INPUT_FWD);
 428                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 429                        RTE_MIN(sizeof(req.vf_req_fwd),
 430                                sizeof(bp->pf.vf_req_fwd)));
 431         }
 432
 433         req.async_event_fwd[0] |= rte_cpu_to_le_32(0x1);   /* TODO: Use MACRO */
 434         memset(req.async_event_fwd, 0xff, sizeof(req.async_event_fwd));
 435
 436         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 437
 438         HWRM_CHECK_RESULT;
 439
 440         bp->flags |= BNXT_FLAG_REGISTERED;
 441
 442         return rc;
 443 }
 444
 445 int bnxt_hwrm_ver_get(struct bnxt *bp)
 446 {
 447         int rc = 0;
 448         struct hwrm_ver_get_input req = {.req_type = 0 };
 449         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 450         uint32_t my_version;
 451         uint32_t fw_version;
 452         uint16_t max_resp_len;
 453         char type[RTE_MEMZONE_NAMESIZE];
 454
 455         HWRM_PREP(req, VER_GET, -1, resp);
 456
 457         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 458         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 459         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 460
 461         /*
 462          * Hold the lock since we may be adjusting the response pointers.
 463          */
 464         rte_spinlock_lock(&bp->hwrm_lock);
 465         rc = bnxt_hwrm_send_message_locked(bp, &req, sizeof(req));
 466
 467         HWRM_CHECK_RESULT;
 468
 469         RTE_LOG(INFO, PMD, "%d.%d.%d:%d.%d.%d\n",
 470                 resp->hwrm_intf_maj, resp->hwrm_intf_min,
 471                 resp->hwrm_intf_upd,
 472                 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
 473         bp->fw_ver = (resp->hwrm_fw_maj << 24) | (resp->hwrm_fw_min << 16) |
 474                         (resp->hwrm_fw_bld << 8) | resp->hwrm_fw_rsvd;
 475         RTE_LOG(INFO, PMD, "Driver HWRM version: %d.%d.%d\n",
 476                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 477
 478         my_version = HWRM_VERSION_MAJOR << 16;
 479         my_version |= HWRM_VERSION_MINOR << 8;
 480         my_version |= HWRM_VERSION_UPDATE;
 481
 482         fw_version = resp->hwrm_intf_maj << 16;
 483         fw_version |= resp->hwrm_intf_min << 8;
 484         fw_version |= resp->hwrm_intf_upd;
 485
 486         if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
 487                 RTE_LOG(ERR, PMD, "Unsupported firmware API version\n");
 488                 rc = -EINVAL;
 489                 goto error;
 490         }
 491
 492         if (my_version != fw_version) {
 493                 RTE_LOG(INFO, PMD, "BNXT Driver/HWRM API mismatch.\n");
 494                 if (my_version < fw_version) {
 495                         RTE_LOG(INFO, PMD,
 496                                 "Firmware API version is newer than driver.\n");
 497                         RTE_LOG(INFO, PMD,
 498                                 "The driver may be missing features.\n");
 499                 } else {
 500                         RTE_LOG(INFO, PMD,
 501                                 "Firmware API version is older than driver.\n");
 502                         RTE_LOG(INFO, PMD,
 503                                 "Not all driver features may be functional.\n");
 504                 }
 505         }
 506
 507         if (bp->max_req_len > resp->max_req_win_len) {
 508                 RTE_LOG(ERR, PMD, "Unsupported request length\n");
 509                 rc = -EINVAL;
 510         }
 511         bp->max_req_len = resp->max_req_win_len;
 512         max_resp_len = resp->max_resp_len;
 513         if (bp->max_resp_len != max_resp_len) {
 514                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 515                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 516                         bp->pdev->addr.devid, bp->pdev->addr.function);
 517
 518                 rte_free(bp->hwrm_cmd_resp_addr);
 519
 520                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 521                 if (bp->hwrm_cmd_resp_addr == NULL) {
 522                         rc = -ENOMEM;
 523                         goto error;
 524                 }
 525                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
 526                 bp->hwrm_cmd_resp_dma_addr =
 527                         rte_mem_virt2phy(bp->hwrm_cmd_resp_addr);
 528                 if (bp->hwrm_cmd_resp_dma_addr == 0) {
 529                         RTE_LOG(ERR, PMD,
 530                         "Unable to map response buffer to physical memory.\n");
 531                         rc = -ENOMEM;
 532                         goto error;
 533                 }
 534                 bp->max_resp_len = max_resp_len;
 535         }
 536
 537 error:
 538         rte_spinlock_unlock(&bp->hwrm_lock);
 539         return rc;
 540 }
 541
 542 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
 543 {
 544         int rc;
 545         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
 546         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
 547
 548         if (!(bp->flags & BNXT_FLAG_REGISTERED))
 549                 return 0;
 550
 551         HWRM_PREP(req, FUNC_DRV_UNRGTR, -1, resp);
 552         req.flags = flags;
 553
 554         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 555
 556         HWRM_CHECK_RESULT;
 557
 558         bp->flags &= ~BNXT_FLAG_REGISTERED;
 559
 560         return rc;
 561 }
 562
 563 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
 564 {
 565         int rc = 0;
 566         struct hwrm_port_phy_cfg_input req = {0};
 567         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 568         uint32_t enables = 0;
 569
 570         HWRM_PREP(req, PORT_PHY_CFG, -1, resp);
 571
 572         if (conf->link_up) {
 573                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
 574                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
 575                 /*
 576                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
 577                  * any auto mode, even "none".
 578                  */
 579                 if (!conf->link_speed) {
 580                         req.auto_mode |= conf->auto_mode;
 581                         enables = HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
 582                         req.auto_link_speed_mask = conf->auto_link_speed_mask;
 583                         enables |=
 584                            HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
 585                         req.auto_link_speed = bp->link_info.auto_link_speed;
 586                         enables |=
 587                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
 588                 }
 589                 req.auto_duplex = conf->duplex;
 590                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
 591                 req.auto_pause = conf->auto_pause;
 592                 req.force_pause = conf->force_pause;
 593                 /* Set force_pause if there is no auto or if there is a force */
 594                 if (req.auto_pause && !req.force_pause)
 595                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
 596                 else
 597                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
 598
 599                 req.enables = rte_cpu_to_le_32(enables);
 600         } else {
 601                 req.flags =
 602                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
 603                 RTE_LOG(INFO, PMD, "Force Link Down\n");
 604         }
 605
 606         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 607
 608         HWRM_CHECK_RESULT;
 609
 610         return rc;
 611 }
 612
 613 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
 614                                    struct bnxt_link_info *link_info)
 615 {
 616         int rc = 0;
 617         struct hwrm_port_phy_qcfg_input req = {0};
 618         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 619
 620         HWRM_PREP(req, PORT_PHY_QCFG, -1, resp);
 621
 622         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 623
 624         HWRM_CHECK_RESULT;
 625
 626         link_info->phy_link_status = resp->link;
 627         if (link_info->phy_link_status != HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK) {
 628                 link_info->link_up = 1;
 629                 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
 630         } else {
 631                 link_info->link_up = 0;
 632                 link_info->link_speed = 0;
 633         }
 634         link_info->duplex = resp->duplex;
 635         link_info->pause = resp->pause;
 636         link_info->auto_pause = resp->auto_pause;
 637         link_info->force_pause = resp->force_pause;
 638         link_info->auto_mode = resp->auto_mode;
 639
 640         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
 641         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
 642         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
 643         link_info->phy_ver[0] = resp->phy_maj;
 644         link_info->phy_ver[1] = resp->phy_min;
 645         link_info->phy_ver[2] = resp->phy_bld;
 646
 647         return rc;
 648 }
 649
 650 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
 651 {
 652         int rc = 0;
 653         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
 654         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
 655
 656         HWRM_PREP(req, QUEUE_QPORTCFG, -1, resp);
 657
 658         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 659
 660         HWRM_CHECK_RESULT;
 661
 662 #define GET_QUEUE_INFO(x) \
 663         bp->cos_queue[x].id = resp->queue_id##x; \
 664         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
 665
 666         GET_QUEUE_INFO(0);
 667         GET_QUEUE_INFO(1);
 668         GET_QUEUE_INFO(2);
 669         GET_QUEUE_INFO(3);
 670         GET_QUEUE_INFO(4);
 671         GET_QUEUE_INFO(5);
 672         GET_QUEUE_INFO(6);
 673         GET_QUEUE_INFO(7);
 674
 675         return rc;
 676 }
 677
 678 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
 679                          struct bnxt_ring *ring,
 680                          uint32_t ring_type, uint32_t map_index,
 681                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
 682 {
 683         int rc = 0;
 684         uint32_t enables = 0;
 685         struct hwrm_ring_alloc_input req = {.req_type = 0 };
 686         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 687
 688         HWRM_PREP(req, RING_ALLOC, -1, resp);
 689
 690         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
 691         req.fbo = rte_cpu_to_le_32(0);
 692         /* Association of ring index with doorbell index */
 693         req.logical_id = rte_cpu_to_le_16(map_index);
 694         req.length = rte_cpu_to_le_32(ring->ring_size);
 695
 696         switch (ring_type) {
 697         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
 698                 req.queue_id = bp->cos_queue[0].id;
 699                 /* FALLTHROUGH */
 700         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
 701                 req.ring_type = ring_type;
 702                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
 703                 req.stat_ctx_id = rte_cpu_to_le_16(stats_ctx_id);
 704                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
 705                         enables |=
 706                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
 707                 break;
 708         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
 709                 req.ring_type = ring_type;
 710                 /*
 711                  * TODO: Some HWRM versions crash with
 712                  * HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
 713                  */
 714                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
 715                 break;
 716         default:
 717                 RTE_LOG(ERR, PMD, "hwrm alloc invalid ring type %d\n",
 718                         ring_type);
 719                 return -1;
 720         }
 721         req.enables = rte_cpu_to_le_32(enables);
 722
 723         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 724
 725         if (rc || resp->error_code) {
 726                 if (rc == 0 && resp->error_code)
 727                         rc = rte_le_to_cpu_16(resp->error_code);
 728                 switch (ring_type) {
 729                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
 730                         RTE_LOG(ERR, PMD,
 731                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
 732                         return rc;
 733                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
 734                         RTE_LOG(ERR, PMD,
 735                                 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
 736                         return rc;
 737                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
 738                         RTE_LOG(ERR, PMD,
 739                                 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
 740                         return rc;
 741                 default:
 742                         RTE_LOG(ERR, PMD, "Invalid ring. rc:%d\n", rc);
 743                         return rc;
 744                 }
 745         }
 746
 747         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
 748         return rc;
 749 }
 750
 751 int bnxt_hwrm_ring_free(struct bnxt *bp,
 752                         struct bnxt_ring *ring, uint32_t ring_type)
 753 {
 754         int rc;
 755         struct hwrm_ring_free_input req = {.req_type = 0 };
 756         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
 757
 758         HWRM_PREP(req, RING_FREE, -1, resp);
 759
 760         req.ring_type = ring_type;
 761         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
 762
 763         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 764
 765         if (rc || resp->error_code) {
 766                 if (rc == 0 && resp->error_code)
 767                         rc = rte_le_to_cpu_16(resp->error_code);
 768
 769                 switch (ring_type) {
 770                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
 771                         RTE_LOG(ERR, PMD, "hwrm_ring_free cp failed. rc:%d\n",
 772                                 rc);
 773                         return rc;
 774                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
 775                         RTE_LOG(ERR, PMD, "hwrm_ring_free rx failed. rc:%d\n",
 776                                 rc);
 777                         return rc;
 778                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
 779                         RTE_LOG(ERR, PMD, "hwrm_ring_free tx failed. rc:%d\n",
 780                                 rc);
 781                         return rc;
 782                 default:
 783                         RTE_LOG(ERR, PMD, "Invalid ring, rc:%d\n", rc);
 784                         return rc;
 785                 }
 786         }
 787         return 0;
 788 }
 789
 790 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
 791 {
 792         int rc = 0;
 793         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
 794         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 795
 796         HWRM_PREP(req, RING_GRP_ALLOC, -1, resp);
 797
 798         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
 799         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
 800         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
 801         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
 802
 803         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 804
 805         HWRM_CHECK_RESULT;
 806
 807         bp->grp_info[idx].fw_grp_id =
 808             rte_le_to_cpu_16(resp->ring_group_id);
 809
 810         return rc;
 811 }
 812
 813 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
 814 {
 815         int rc;
 816         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
 817         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
 818
 819         HWRM_PREP(req, RING_GRP_FREE, -1, resp);
 820
 821         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
 822
 823         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 824
 825         HWRM_CHECK_RESULT;
 826
 827         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
 828         return rc;
 829 }
 830
 831 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
 832 {
 833         int rc = 0;
 834         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
 835         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
 836
 837         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
 838                 return rc;
 839
 840         HWRM_PREP(req, STAT_CTX_CLR_STATS, -1, resp);
 841
 842         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
 843
 844         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 845
 846         HWRM_CHECK_RESULT;
 847
 848         return rc;
 849 }
 850
 851 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
 852                                 unsigned int idx __rte_unused)
 853 {
 854         int rc;
 855         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
 856         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 857
 858         HWRM_PREP(req, STAT_CTX_ALLOC, -1, resp);
 859
 860         req.update_period_ms = rte_cpu_to_le_32(0);
 861
 862         req.stats_dma_addr =
 863             rte_cpu_to_le_64(cpr->hw_stats_map);
 864
 865         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 866
 867         HWRM_CHECK_RESULT;
 868
 869         cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
 870
 871         return rc;
 872 }
 873
 874 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
 875                                 unsigned int idx __rte_unused)
 876 {
 877         int rc;
 878         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
 879         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
 880
 881         HWRM_PREP(req, STAT_CTX_FREE, -1, resp);
 882
 883         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
 884
 885         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 886
 887         HWRM_CHECK_RESULT;
 888
 889         return rc;
 890 }
 891
 892 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 893 {
 894         int rc = 0, i, j;
 895         struct hwrm_vnic_alloc_input req = { 0 };
 896         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 897
 898         /* map ring groups to this vnic */
 899         RTE_LOG(DEBUG, PMD, "Alloc VNIC. Start %x, End %x\n",
 900                 vnic->start_grp_id, vnic->end_grp_id);
 901         for (i = vnic->start_grp_id, j = 0; i <= vnic->end_grp_id; i++, j++)
 902                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
 903         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
 904         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
 905         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
 906         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
 907         vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
 908                                 ETHER_CRC_LEN + VLAN_TAG_SIZE;
 909         HWRM_PREP(req, VNIC_ALLOC, -1, resp);
 910
 911         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 912
 913         HWRM_CHECK_RESULT;
 914
 915         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
 916         return rc;
 917 }
 918
 919 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
 920                                         struct bnxt_vnic_info *vnic,
 921                                         struct bnxt_plcmodes_cfg *pmode)
 922 {
 923         int rc = 0;
 924         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
 925         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 926
 927         HWRM_PREP(req, VNIC_PLCMODES_QCFG, -1, resp);
 928
 929         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
 930
 931         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 932
 933         HWRM_CHECK_RESULT;
 934
 935         pmode->flags = rte_le_to_cpu_32(resp->flags);
 936         /* dflt_vnic bit doesn't exist in the _cfg command */
 937         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
 938         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
 939         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
 940         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
 941
 942         return rc;
 943 }
 944
 945 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
 946                                        struct bnxt_vnic_info *vnic,
 947                                        struct bnxt_plcmodes_cfg *pmode)
 948 {
 949         int rc = 0;
 950         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
 951         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 952
 953         HWRM_PREP(req, VNIC_PLCMODES_CFG, -1, resp);
 954
 955         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
 956         req.flags = rte_cpu_to_le_32(pmode->flags);
 957         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
 958         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
 959         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
 960         req.enables = rte_cpu_to_le_32(
 961             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
 962             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
 963             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
 964         );
 965
 966         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 967
 968         HWRM_CHECK_RESULT;
 969
 970         return rc;
 971 }
 972
 973 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 974 {
 975         int rc = 0;
 976         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
 977         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 978         uint32_t ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
 979         struct bnxt_plcmodes_cfg pmodes;
 980
 981         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
 982         if (rc)
 983                 return rc;
 984
 985         HWRM_PREP(req, VNIC_CFG, -1, resp);
 986
 987         /* Only RSS support for now TBD: COS & LB */
 988         req.enables =
 989             rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP |
 990                              HWRM_VNIC_CFG_INPUT_ENABLES_MRU);
 991         if (vnic->lb_rule != 0xffff)
 992                 ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
 993         if (vnic->cos_rule != 0xffff)
 994                 ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
 995         if (vnic->rss_rule != 0xffff)
 996                 ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
 997         req.enables |= rte_cpu_to_le_32(ctx_enable_flag);
 998         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 999         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1000         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1001         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1002         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1003         req.mru = rte_cpu_to_le_16(vnic->mru);
1004         if (vnic->func_default)
1005                 req.flags |=
1006                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1007         if (vnic->vlan_strip)
1008                 req.flags |=
1009                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1010         if (vnic->bd_stall)
1011                 req.flags |=
1012                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1013         if (vnic->roce_dual)
1014                 req.flags |= rte_cpu_to_le_32(
1015                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1016         if (vnic->roce_only)
1017                 req.flags |= rte_cpu_to_le_32(
1018                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1019         if (vnic->rss_dflt_cr)
1020                 req.flags |= rte_cpu_to_le_32(
1021                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1022
1023         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1024
1025         HWRM_CHECK_RESULT;
1026
1027         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1028
1029         return rc;
1030 }
1031
1032 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1033                 int16_t fw_vf_id)
1034 {
1035         int rc = 0;
1036         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1037         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1038
1039         HWRM_PREP(req, VNIC_QCFG, -1, resp);
1040
1041         req.enables =
1042                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1043         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1044         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1045
1046         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1047
1048         HWRM_CHECK_RESULT;
1049
1050         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1051         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1052         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1053         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1054         vnic->mru = rte_le_to_cpu_16(resp->mru);
1055         vnic->func_default = rte_le_to_cpu_32(
1056                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1057         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1058                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1059         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1060                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1061         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1062                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1063         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1064                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1065         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1066                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1067
1068         return rc;
1069 }
1070
1071 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1072 {
1073         int rc = 0;
1074         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1075         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1076                                                 bp->hwrm_cmd_resp_addr;
1077
1078         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, -1, resp);
1079
1080         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1081
1082         HWRM_CHECK_RESULT;
1083
1084         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1085
1086         return rc;
1087 }
1088
1089 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1090 {
1091         int rc = 0;
1092         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1093         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1094                                                 bp->hwrm_cmd_resp_addr;
1095
1096         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, -1, resp);
1097
1098         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->rss_rule);
1099
1100         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1101
1102         HWRM_CHECK_RESULT;
1103
1104         vnic->rss_rule = INVALID_HW_RING_ID;
1105
1106         return rc;
1107 }
1108
1109 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1110 {
1111         int rc = 0;
1112         struct hwrm_vnic_free_input req = {.req_type = 0 };
1113         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1114
1115         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
1116                 return rc;
1117
1118         HWRM_PREP(req, VNIC_FREE, -1, resp);
1119
1120         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1121
1122         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1123
1124         HWRM_CHECK_RESULT;
1125
1126         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1127         return rc;
1128 }
1129
1130 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1131                            struct bnxt_vnic_info *vnic)
1132 {
1133         int rc = 0;
1134         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1135         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1136
1137         HWRM_PREP(req, VNIC_RSS_CFG, -1, resp);
1138
1139         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1140
1141         req.ring_grp_tbl_addr =
1142             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1143         req.hash_key_tbl_addr =
1144             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1145         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1146
1147         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1148
1149         HWRM_CHECK_RESULT;
1150
1151         return rc;
1152 }
1153
1154 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1155                         struct bnxt_vnic_info *vnic)
1156 {
1157         int rc = 0;
1158         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1159         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1160         uint16_t size;
1161
1162         HWRM_PREP(req, VNIC_PLCMODES_CFG, -1, resp);
1163
1164         req.flags = rte_cpu_to_le_32(
1165                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1166
1167         req.enables = rte_cpu_to_le_32(
1168                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1169
1170         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1171         size -= RTE_PKTMBUF_HEADROOM;
1172
1173         req.jumbo_thresh = rte_cpu_to_le_16(size);
1174         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1175
1176         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1177
1178         HWRM_CHECK_RESULT;
1179
1180         return rc;
1181 }
1182
1183 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1184                         struct bnxt_vnic_info *vnic, bool enable)
1185 {
1186         int rc = 0;
1187         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1188         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1189
1190         HWRM_PREP(req, VNIC_TPA_CFG, -1, resp);
1191
1192         if (enable) {
1193                 req.enables = rte_cpu_to_le_32(
1194                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1195                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1196                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1197                 req.flags = rte_cpu_to_le_32(
1198                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1199                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1200                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1201                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1202                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1203                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1204                 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1205                 req.max_agg_segs = rte_cpu_to_le_16(5);
1206                 req.max_aggs =
1207                         rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1208                 req.min_agg_len = rte_cpu_to_le_32(512);
1209         }
1210
1211         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1212
1213         HWRM_CHECK_RESULT;
1214
1215         return rc;
1216 }
1217
1218 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1219 {
1220         struct hwrm_func_cfg_input req = {0};
1221         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1222         int rc;
1223
1224         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1225         req.enables = rte_cpu_to_le_32(
1226                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1227         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1228         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1229
1230         HWRM_PREP(req, FUNC_CFG, -1, resp);
1231
1232         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1233         HWRM_CHECK_RESULT;
1234
1235         bp->pf.vf_info[vf].random_mac = false;
1236
1237         return rc;
1238 }
1239
1240 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1241                                   uint64_t *dropped)
1242 {
1243         int rc = 0;
1244         struct hwrm_func_qstats_input req = {.req_type = 0};
1245         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1246
1247         HWRM_PREP(req, FUNC_QSTATS, -1, resp);
1248
1249         req.fid = rte_cpu_to_le_16(fid);
1250
1251         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1252
1253         HWRM_CHECK_RESULT;
1254
1255         if (dropped)
1256                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1257
1258         return rc;
1259 }
1260
1261 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1262                           struct rte_eth_stats *stats)
1263 {
1264         int rc = 0;
1265         struct hwrm_func_qstats_input req = {.req_type = 0};
1266         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1267
1268         HWRM_PREP(req, FUNC_QSTATS, -1, resp);
1269
1270         req.fid = rte_cpu_to_le_16(fid);
1271
1272         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1273
1274         HWRM_CHECK_RESULT;
1275
1276         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1277         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1278         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1279         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1280         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1281         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1282
1283         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1284         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1285         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1286         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1287         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1288         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1289
1290         stats->ierrors = rte_le_to_cpu_64(resp->rx_err_pkts);
1291         stats->oerrors = rte_le_to_cpu_64(resp->tx_err_pkts);
1292
1293         stats->imissed = rte_le_to_cpu_64(resp->rx_drop_pkts);
1294
1295         return rc;
1296 }
1297
1298 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1299 {
1300         int rc = 0;
1301         struct hwrm_func_clr_stats_input req = {.req_type = 0};
1302         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1303
1304         HWRM_PREP(req, FUNC_CLR_STATS, -1, resp);
1305
1306         req.fid = rte_cpu_to_le_16(fid);
1307
1308         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1309
1310         HWRM_CHECK_RESULT;
1311
1312         return rc;
1313 }
1314
1315 /*
1316  * HWRM utility functions
1317  */
1318
1319 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1320 {
1321         unsigned int i;
1322         int rc = 0;
1323
1324         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1325                 struct bnxt_tx_queue *txq;
1326                 struct bnxt_rx_queue *rxq;
1327                 struct bnxt_cp_ring_info *cpr;
1328
1329                 if (i >= bp->rx_cp_nr_rings) {
1330                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1331                         cpr = txq->cp_ring;
1332                 } else {
1333                         rxq = bp->rx_queues[i];
1334                         cpr = rxq->cp_ring;
1335                 }
1336
1337                 rc = bnxt_hwrm_stat_clear(bp, cpr);
1338                 if (rc)
1339                         return rc;
1340         }
1341         return 0;
1342 }
1343
1344 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1345 {
1346         int rc;
1347         unsigned int i;
1348         struct bnxt_cp_ring_info *cpr;
1349
1350         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1351
1352                 if (i >= bp->rx_cp_nr_rings)
1353                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
1354                 else
1355                         cpr = bp->rx_queues[i]->cp_ring;
1356                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
1357                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
1358                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1359                         /*
1360                          * TODO. Need a better way to reset grp_info.stats_ctx
1361                          * for Rx rings only. stats_ctx is not saved for Tx
1362                          * in grp_info.
1363                          */
1364                         bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
1365                         if (rc)
1366                                 return rc;
1367                 }
1368         }
1369         return 0;
1370 }
1371
1372 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
1373 {
1374         unsigned int i;
1375         int rc = 0;
1376
1377         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1378                 struct bnxt_tx_queue *txq;
1379                 struct bnxt_rx_queue *rxq;
1380                 struct bnxt_cp_ring_info *cpr;
1381
1382                 if (i >= bp->rx_cp_nr_rings) {
1383                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1384                         cpr = txq->cp_ring;
1385                 } else {
1386                         rxq = bp->rx_queues[i];
1387                         cpr = rxq->cp_ring;
1388                 }
1389
1390                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
1391
1392                 if (rc)
1393                         return rc;
1394         }
1395         return rc;
1396 }
1397
1398 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
1399 {
1400         uint16_t idx;
1401         uint32_t rc = 0;
1402
1403         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
1404
1405                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID) {
1406                         RTE_LOG(ERR, PMD,
1407                                 "Attempt to free invalid ring group %d\n",
1408                                 idx);
1409                         continue;
1410                 }
1411
1412                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
1413
1414                 if (rc)
1415                         return rc;
1416         }
1417         return rc;
1418 }
1419
1420 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1421                                 unsigned int idx __rte_unused)
1422 {
1423         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
1424
1425         bnxt_hwrm_ring_free(bp, cp_ring,
1426                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
1427         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
1428         bp->grp_info[idx].cp_fw_ring_id = INVALID_HW_RING_ID;
1429         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
1430                         sizeof(*cpr->cp_desc_ring));
1431         cpr->cp_raw_cons = 0;
1432 }
1433
1434 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
1435 {
1436         unsigned int i;
1437         int rc = 0;
1438
1439         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
1440                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
1441                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
1442                 struct bnxt_ring *ring = txr->tx_ring_struct;
1443                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
1444                 unsigned int idx = bp->rx_cp_nr_rings + i + 1;
1445
1446                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1447                         bnxt_hwrm_ring_free(bp, ring,
1448                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
1449                         ring->fw_ring_id = INVALID_HW_RING_ID;
1450                         memset(txr->tx_desc_ring, 0,
1451                                         txr->tx_ring_struct->ring_size *
1452                                         sizeof(*txr->tx_desc_ring));
1453                         memset(txr->tx_buf_ring, 0,
1454                                         txr->tx_ring_struct->ring_size *
1455                                         sizeof(*txr->tx_buf_ring));
1456                         txr->tx_prod = 0;
1457                         txr->tx_cons = 0;
1458                 }
1459                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1460                         bnxt_free_cp_ring(bp, cpr, idx);
1461                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1462                 }
1463         }
1464
1465         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1466                 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
1467                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1468                 struct bnxt_ring *ring = rxr->rx_ring_struct;
1469                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1470                 unsigned int idx = i + 1;
1471
1472                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1473                         bnxt_hwrm_ring_free(bp, ring,
1474                                         HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1475                         ring->fw_ring_id = INVALID_HW_RING_ID;
1476                         bp->grp_info[idx].rx_fw_ring_id = INVALID_HW_RING_ID;
1477                         memset(rxr->rx_desc_ring, 0,
1478                                         rxr->rx_ring_struct->ring_size *
1479                                         sizeof(*rxr->rx_desc_ring));
1480                         memset(rxr->rx_buf_ring, 0,
1481                                         rxr->rx_ring_struct->ring_size *
1482                                         sizeof(*rxr->rx_buf_ring));
1483                         rxr->rx_prod = 0;
1484                         memset(rxr->ag_buf_ring, 0,
1485                                         rxr->ag_ring_struct->ring_size *
1486                                         sizeof(*rxr->ag_buf_ring));
1487                         rxr->ag_prod = 0;
1488                 }
1489                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1490                         bnxt_free_cp_ring(bp, cpr, idx);
1491                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
1492                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1493                 }
1494         }
1495
1496         /* Default completion ring */
1497         {
1498                 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1499
1500                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1501                         bnxt_free_cp_ring(bp, cpr, 0);
1502                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1503                 }
1504         }
1505
1506         return rc;
1507 }
1508
1509 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
1510 {
1511         uint16_t i;
1512         uint32_t rc = 0;
1513
1514         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1515                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
1516                 if (rc)
1517                         return rc;
1518         }
1519         return rc;
1520 }
1521
1522 void bnxt_free_hwrm_resources(struct bnxt *bp)
1523 {
1524         /* Release memzone */
1525         rte_free(bp->hwrm_cmd_resp_addr);
1526         bp->hwrm_cmd_resp_addr = NULL;
1527         bp->hwrm_cmd_resp_dma_addr = 0;
1528 }
1529
1530 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
1531 {
1532         struct rte_pci_device *pdev = bp->pdev;
1533         char type[RTE_MEMZONE_NAMESIZE];
1534
1535         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
1536                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
1537         bp->max_req_len = HWRM_MAX_REQ_LEN;
1538         bp->max_resp_len = HWRM_MAX_RESP_LEN;
1539         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
1540         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1541         if (bp->hwrm_cmd_resp_addr == NULL)
1542                 return -ENOMEM;
1543         bp->hwrm_cmd_resp_dma_addr =
1544                 rte_mem_virt2phy(bp->hwrm_cmd_resp_addr);
1545         if (bp->hwrm_cmd_resp_dma_addr == 0) {
1546                 RTE_LOG(ERR, PMD,
1547                         "unable to map response address to physical memory\n");
1548                 return -ENOMEM;
1549         }
1550         rte_spinlock_init(&bp->hwrm_lock);
1551
1552         return 0;
1553 }
1554
1555 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1556 {
1557         struct bnxt_filter_info *filter;
1558         int rc = 0;
1559
1560         STAILQ_FOREACH(filter, &vnic->filter, next) {
1561                 rc = bnxt_hwrm_clear_filter(bp, filter);
1562                 if (rc)
1563                         break;
1564         }
1565         return rc;
1566 }
1567
1568 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1569 {
1570         struct bnxt_filter_info *filter;
1571         int rc = 0;
1572
1573         STAILQ_FOREACH(filter, &vnic->filter, next) {
1574                 rc = bnxt_hwrm_set_filter(bp, vnic->fw_vnic_id, filter);
1575                 if (rc)
1576                         break;
1577         }
1578         return rc;
1579 }
1580
1581 void bnxt_free_tunnel_ports(struct bnxt *bp)
1582 {
1583         if (bp->vxlan_port_cnt)
1584                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
1585                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
1586         bp->vxlan_port = 0;
1587         if (bp->geneve_port_cnt)
1588                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
1589                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
1590         bp->geneve_port = 0;
1591 }
1592
1593 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
1594 {
1595         struct bnxt_vnic_info *vnic;
1596         unsigned int i;
1597
1598         if (bp->vnic_info == NULL)
1599                 return;
1600
1601         vnic = &bp->vnic_info[0];
1602         if (BNXT_PF(bp))
1603                 bnxt_hwrm_cfa_l2_clear_rx_mask(bp, vnic);
1604
1605         /* VNIC resources */
1606         for (i = 0; i < bp->nr_vnics; i++) {
1607                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1608
1609                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
1610
1611                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
1612
1613                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
1614
1615                 bnxt_hwrm_vnic_free(bp, vnic);
1616         }
1617         /* Ring resources */
1618         bnxt_free_all_hwrm_rings(bp);
1619         bnxt_free_all_hwrm_ring_grps(bp);
1620         bnxt_free_all_hwrm_stat_ctxs(bp);
1621         bnxt_free_tunnel_ports(bp);
1622 }
1623
1624 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
1625 {
1626         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1627
1628         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
1629                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1630
1631         switch (conf_link_speed) {
1632         case ETH_LINK_SPEED_10M_HD:
1633         case ETH_LINK_SPEED_100M_HD:
1634                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
1635         }
1636         return hw_link_duplex;
1637 }
1638
1639 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
1640 {
1641         uint16_t eth_link_speed = 0;
1642
1643         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
1644                 return ETH_LINK_SPEED_AUTONEG;
1645
1646         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
1647         case ETH_LINK_SPEED_100M:
1648         case ETH_LINK_SPEED_100M_HD:
1649                 eth_link_speed =
1650                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
1651                 break;
1652         case ETH_LINK_SPEED_1G:
1653                 eth_link_speed =
1654                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
1655                 break;
1656         case ETH_LINK_SPEED_2_5G:
1657                 eth_link_speed =
1658                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
1659                 break;
1660         case ETH_LINK_SPEED_10G:
1661                 eth_link_speed =
1662                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
1663                 break;
1664         case ETH_LINK_SPEED_20G:
1665                 eth_link_speed =
1666                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
1667                 break;
1668         case ETH_LINK_SPEED_25G:
1669                 eth_link_speed =
1670                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
1671                 break;
1672         case ETH_LINK_SPEED_40G:
1673                 eth_link_speed =
1674                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
1675                 break;
1676         case ETH_LINK_SPEED_50G:
1677                 eth_link_speed =
1678                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
1679                 break;
1680         default:
1681                 RTE_LOG(ERR, PMD,
1682                         "Unsupported link speed %d; default to AUTO\n",
1683                         conf_link_speed);
1684                 break;
1685         }
1686         return eth_link_speed;
1687 }
1688
1689 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
1690                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
1691                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
1692                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G)
1693
1694 static int bnxt_valid_link_speed(uint32_t link_speed, uint8_t port_id)
1695 {
1696         uint32_t one_speed;
1697
1698         if (link_speed == ETH_LINK_SPEED_AUTONEG)
1699                 return 0;
1700
1701         if (link_speed & ETH_LINK_SPEED_FIXED) {
1702                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
1703
1704                 if (one_speed & (one_speed - 1)) {
1705                         RTE_LOG(ERR, PMD,
1706                                 "Invalid advertised speeds (%u) for port %u\n",
1707                                 link_speed, port_id);
1708                         return -EINVAL;
1709                 }
1710                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
1711                         RTE_LOG(ERR, PMD,
1712                                 "Unsupported advertised speed (%u) for port %u\n",
1713                                 link_speed, port_id);
1714                         return -EINVAL;
1715                 }
1716         } else {
1717                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
1718                         RTE_LOG(ERR, PMD,
1719                                 "Unsupported advertised speeds (%u) for port %u\n",
1720                                 link_speed, port_id);
1721                         return -EINVAL;
1722                 }
1723         }
1724         return 0;
1725 }
1726
1727 static uint16_t bnxt_parse_eth_link_speed_mask(uint32_t link_speed)
1728 {
1729         uint16_t ret = 0;
1730
1731         if (link_speed == ETH_LINK_SPEED_AUTONEG)
1732                 link_speed = BNXT_SUPPORTED_SPEEDS;
1733
1734         if (link_speed & ETH_LINK_SPEED_100M)
1735                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1736         if (link_speed & ETH_LINK_SPEED_100M_HD)
1737                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1738         if (link_speed & ETH_LINK_SPEED_1G)
1739                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
1740         if (link_speed & ETH_LINK_SPEED_2_5G)
1741                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
1742         if (link_speed & ETH_LINK_SPEED_10G)
1743                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
1744         if (link_speed & ETH_LINK_SPEED_20G)
1745                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
1746         if (link_speed & ETH_LINK_SPEED_25G)
1747                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
1748         if (link_speed & ETH_LINK_SPEED_40G)
1749                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
1750         if (link_speed & ETH_LINK_SPEED_50G)
1751                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
1752         return ret;
1753 }
1754
1755 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
1756 {
1757         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
1758
1759         switch (hw_link_speed) {
1760         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
1761                 eth_link_speed = ETH_SPEED_NUM_100M;
1762                 break;
1763         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
1764                 eth_link_speed = ETH_SPEED_NUM_1G;
1765                 break;
1766         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
1767                 eth_link_speed = ETH_SPEED_NUM_2_5G;
1768                 break;
1769         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
1770                 eth_link_speed = ETH_SPEED_NUM_10G;
1771                 break;
1772         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
1773                 eth_link_speed = ETH_SPEED_NUM_20G;
1774                 break;
1775         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
1776                 eth_link_speed = ETH_SPEED_NUM_25G;
1777                 break;
1778         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
1779                 eth_link_speed = ETH_SPEED_NUM_40G;
1780                 break;
1781         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
1782                 eth_link_speed = ETH_SPEED_NUM_50G;
1783                 break;
1784         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
1785         default:
1786                 RTE_LOG(ERR, PMD, "HWRM link speed %d not defined\n",
1787                         hw_link_speed);
1788                 break;
1789         }
1790         return eth_link_speed;
1791 }
1792
1793 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
1794 {
1795         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
1796
1797         switch (hw_link_duplex) {
1798         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
1799         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
1800                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
1801                 break;
1802         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
1803                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
1804                 break;
1805         default:
1806                 RTE_LOG(ERR, PMD, "HWRM link duplex %d not defined\n",
1807                         hw_link_duplex);
1808                 break;
1809         }
1810         return eth_link_duplex;
1811 }
1812
1813 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
1814 {
1815         int rc = 0;
1816         struct bnxt_link_info *link_info = &bp->link_info;
1817
1818         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
1819         if (rc) {
1820                 RTE_LOG(ERR, PMD,
1821                         "Get link config failed with rc %d\n", rc);
1822                 goto exit;
1823         }
1824         if (link_info->link_up)
1825                 link->link_speed =
1826                         bnxt_parse_hw_link_speed(link_info->link_speed);
1827         else
1828                 link->link_speed = ETH_LINK_SPEED_10M;
1829         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
1830         link->link_status = link_info->link_up;
1831         link->link_autoneg = link_info->auto_mode ==
1832                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
1833                 ETH_LINK_SPEED_FIXED : ETH_LINK_SPEED_AUTONEG;
1834 exit:
1835         return rc;
1836 }
1837
1838 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
1839 {
1840         int rc = 0;
1841         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1842         struct bnxt_link_info link_req;
1843         uint16_t speed;
1844
1845         if (BNXT_NPAR_PF(bp) || BNXT_VF(bp))
1846                 return 0;
1847
1848         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
1849                         bp->eth_dev->data->port_id);
1850         if (rc)
1851                 goto error;
1852
1853         memset(&link_req, 0, sizeof(link_req));
1854         link_req.link_up = link_up;
1855         if (!link_up)
1856                 goto port_phy_cfg;
1857
1858         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
1859         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
1860         if (speed == 0) {
1861                 link_req.phy_flags |=
1862                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
1863                 link_req.auto_mode =
1864                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1865                 link_req.auto_link_speed_mask =
1866                         bnxt_parse_eth_link_speed_mask(dev_conf->link_speeds);
1867         } else {
1868                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
1869                 link_req.link_speed = speed;
1870                 RTE_LOG(INFO, PMD, "Set Link Speed %x\n", speed);
1871         }
1872         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
1873         link_req.auto_pause = bp->link_info.auto_pause;
1874         link_req.force_pause = bp->link_info.force_pause;
1875
1876 port_phy_cfg:
1877         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
1878         if (rc) {
1879                 RTE_LOG(ERR, PMD,
1880                         "Set link config failed with rc %d\n", rc);
1881         }
1882
1883         rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1884 error:
1885         return rc;
1886 }
1887
1888 /* JIRA 22088 */
1889 int bnxt_hwrm_func_qcfg(struct bnxt *bp)
1890 {
1891         struct hwrm_func_qcfg_input req = {0};
1892         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1893         int rc = 0;
1894
1895         HWRM_PREP(req, FUNC_QCFG, -1, resp);
1896         req.fid = rte_cpu_to_le_16(0xffff);
1897
1898         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1899
1900         HWRM_CHECK_RESULT;
1901
1902         /* Hard Coded.. 0xfff VLAN ID mask */
1903         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
1904
1905         switch (resp->port_partition_type) {
1906         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
1907         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
1908         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
1909                 bp->port_partition_type = resp->port_partition_type;
1910                 break;
1911         default:
1912                 bp->port_partition_type = 0;
1913                 break;
1914         }
1915
1916         return rc;
1917 }
1918
1919 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
1920                                    struct hwrm_func_qcaps_output *qcaps)
1921 {
1922         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
1923         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
1924                sizeof(qcaps->mac_address));
1925         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
1926         qcaps->max_rx_rings = fcfg->num_rx_rings;
1927         qcaps->max_tx_rings = fcfg->num_tx_rings;
1928         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
1929         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
1930         qcaps->max_vfs = 0;
1931         qcaps->first_vf_id = 0;
1932         qcaps->max_vnics = fcfg->num_vnics;
1933         qcaps->max_decap_records = 0;
1934         qcaps->max_encap_records = 0;
1935         qcaps->max_tx_wm_flows = 0;
1936         qcaps->max_tx_em_flows = 0;
1937         qcaps->max_rx_wm_flows = 0;
1938         qcaps->max_rx_em_flows = 0;
1939         qcaps->max_flow_id = 0;
1940         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
1941         qcaps->max_sp_tx_rings = 0;
1942         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
1943 }
1944
1945 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
1946 {
1947         struct hwrm_func_cfg_input req = {0};
1948         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1949         int rc;
1950
1951         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
1952                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
1953                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
1954                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
1955                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
1956                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
1957                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
1958                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1959                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
1960                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
1961         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
1962         req.mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1963                                    ETHER_CRC_LEN + VLAN_TAG_SIZE);
1964         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1965                                    ETHER_CRC_LEN + VLAN_TAG_SIZE);
1966         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1967         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
1968         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
1969         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
1970         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
1971         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
1972         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
1973         req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
1974         req.fid = rte_cpu_to_le_16(0xffff);
1975
1976         HWRM_PREP(req, FUNC_CFG, -1, resp);
1977
1978         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1979         HWRM_CHECK_RESULT;
1980
1981         return rc;
1982 }
1983
1984 static void populate_vf_func_cfg_req(struct bnxt *bp,
1985                                      struct hwrm_func_cfg_input *req,
1986                                      int num_vfs)
1987 {
1988         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
1989                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
1990                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
1991                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
1992                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
1993                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
1994                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
1995                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1996                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
1997                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
1998
1999         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2000                                     ETHER_CRC_LEN + VLAN_TAG_SIZE);
2001         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2002                                     ETHER_CRC_LEN + VLAN_TAG_SIZE);
2003         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2004                                                 (num_vfs + 1));
2005         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2006         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2007                                                (num_vfs + 1));
2008         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2009         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2010         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2011         /* TODO: For now, do not support VMDq/RFS on VFs. */
2012         req->num_vnics = rte_cpu_to_le_16(1);
2013         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2014                                                  (num_vfs + 1));
2015 }
2016
2017 static void add_random_mac_if_needed(struct bnxt *bp,
2018                                      struct hwrm_func_cfg_input *cfg_req,
2019                                      int vf)
2020 {
2021         struct ether_addr mac;
2022
2023         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2024                 return;
2025
2026         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2027                 cfg_req->enables |=
2028                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2029                 eth_random_addr(cfg_req->dflt_mac_addr);
2030                 bp->pf.vf_info[vf].random_mac = true;
2031         } else {
2032                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes, ETHER_ADDR_LEN);
2033         }
2034 }
2035
2036 static void reserve_resources_from_vf(struct bnxt *bp,
2037                                       struct hwrm_func_cfg_input *cfg_req,
2038                                       int vf)
2039 {
2040         struct hwrm_func_qcaps_input req = {0};
2041         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2042         int rc;
2043
2044         /* Get the actual allocated values now */
2045         HWRM_PREP(req, FUNC_QCAPS, -1, resp);
2046         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2047         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2048
2049         if (rc) {
2050                 RTE_LOG(ERR, PMD, "hwrm_func_qcaps failed rc:%d\n", rc);
2051                 copy_func_cfg_to_qcaps(cfg_req, resp);
2052         } else if (resp->error_code) {
2053                 rc = rte_le_to_cpu_16(resp->error_code);
2054                 RTE_LOG(ERR, PMD, "hwrm_func_qcaps error %d\n", rc);
2055                 copy_func_cfg_to_qcaps(cfg_req, resp);
2056         }
2057
2058         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2059         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2060         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2061         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2062         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2063         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2064         /*
2065          * TODO: While not supporting VMDq with VFs, max_vnics is always
2066          * forced to 1 in this case
2067          */
2068         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2069         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2070 }
2071
2072 static int update_pf_resource_max(struct bnxt *bp)
2073 {
2074         struct hwrm_func_qcfg_input req = {0};
2075         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2076         int rc;
2077
2078         /* And copy the allocated numbers into the pf struct */
2079         HWRM_PREP(req, FUNC_QCFG, -1, resp);
2080         req.fid = rte_cpu_to_le_16(0xffff);
2081         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2082         HWRM_CHECK_RESULT;
2083
2084         /* Only TX ring value reflects actual allocation? TODO */
2085         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2086         bp->pf.evb_mode = resp->evb_mode;
2087
2088         return rc;
2089 }
2090
2091 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2092 {
2093         int rc;
2094
2095         if (!BNXT_PF(bp)) {
2096                 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
2097                 return -1;
2098         }
2099
2100         rc = bnxt_hwrm_func_qcaps(bp);
2101         if (rc)
2102                 return rc;
2103
2104         bp->pf.func_cfg_flags &=
2105                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2106                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2107         bp->pf.func_cfg_flags |=
2108                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2109         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2110         return rc;
2111 }
2112
2113 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2114 {
2115         struct hwrm_func_cfg_input req = {0};
2116         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2117         int i;
2118         size_t sz;
2119         int rc = 0;
2120         size_t req_buf_sz;
2121
2122         if (!BNXT_PF(bp)) {
2123                 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
2124                 return -1;
2125         }
2126
2127         rc = bnxt_hwrm_func_qcaps(bp);
2128
2129         if (rc)
2130                 return rc;
2131
2132         bp->pf.active_vfs = num_vfs;
2133
2134         /*
2135          * First, configure the PF to only use one TX ring.  This ensures that
2136          * there are enough rings for all VFs.
2137          *
2138          * If we don't do this, when we call func_alloc() later, we will lock
2139          * extra rings to the PF that won't be available during func_cfg() of
2140          * the VFs.
2141          *
2142          * This has been fixed with firmware versions above 20.6.54
2143          */
2144         bp->pf.func_cfg_flags &=
2145                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2146                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2147         bp->pf.func_cfg_flags |=
2148                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2149         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2150         if (rc)
2151                 return rc;
2152
2153         /*
2154          * Now, create and register a buffer to hold forwarded VF requests
2155          */
2156         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2157         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2158                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2159         if (bp->pf.vf_req_buf == NULL) {
2160                 rc = -ENOMEM;
2161                 goto error_free;
2162         }
2163         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2164                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2165         for (i = 0; i < num_vfs; i++)
2166                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2167                                         (i * HWRM_MAX_REQ_LEN);
2168
2169         rc = bnxt_hwrm_func_buf_rgtr(bp);
2170         if (rc)
2171                 goto error_free;
2172
2173         populate_vf_func_cfg_req(bp, &req, num_vfs);
2174
2175         bp->pf.active_vfs = 0;
2176         for (i = 0; i < num_vfs; i++) {
2177                 add_random_mac_if_needed(bp, &req, i);
2178
2179                 HWRM_PREP(req, FUNC_CFG, -1, resp);
2180                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2181                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
2182                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2183
2184                 /* Clear enable flag for next pass */
2185                 req.enables &= ~rte_cpu_to_le_32(
2186                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2187
2188                 if (rc || resp->error_code) {
2189                         RTE_LOG(ERR, PMD,
2190                                 "Failed to initizlie VF %d\n", i);
2191                         RTE_LOG(ERR, PMD,
2192                                 "Not all VFs available. (%d, %d)\n",
2193                                 rc, resp->error_code);
2194                         break;
2195                 }
2196
2197                 reserve_resources_from_vf(bp, &req, i);
2198                 bp->pf.active_vfs++;
2199         }
2200
2201         /*
2202          * Now configure the PF to use "the rest" of the resources
2203          * We're using STD_TX_RING_MODE here though which will limit the TX
2204          * rings.  This will allow QoS to function properly.  Not setting this
2205          * will cause PF rings to break bandwidth settings.
2206          */
2207         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2208         if (rc)
2209                 goto error_free;
2210
2211         rc = update_pf_resource_max(bp);
2212         if (rc)
2213                 goto error_free;
2214
2215         return rc;
2216
2217 error_free:
2218         bnxt_hwrm_func_buf_unrgtr(bp);
2219         return rc;
2220 }
2221
2222 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
2223 {
2224         struct hwrm_func_cfg_input req = {0};
2225         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2226         int rc;
2227
2228         HWRM_PREP(req, FUNC_CFG, -1, resp);
2229
2230         req.fid = rte_cpu_to_le_16(0xffff);
2231         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
2232         req.evb_mode = bp->pf.evb_mode;
2233
2234         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2235         HWRM_CHECK_RESULT;
2236
2237         return rc;
2238 }
2239
2240 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
2241                                 uint8_t tunnel_type)
2242 {
2243         struct hwrm_tunnel_dst_port_alloc_input req = {0};
2244         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2245         int rc = 0;
2246
2247         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, -1, resp);
2248         req.tunnel_type = tunnel_type;
2249         req.tunnel_dst_port_val = port;
2250         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2251         HWRM_CHECK_RESULT;
2252
2253         switch (tunnel_type) {
2254         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
2255                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2256                 bp->vxlan_port = port;
2257                 break;
2258         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
2259                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
2260                 bp->geneve_port = port;
2261                 break;
2262         default:
2263                 break;
2264         }
2265         return rc;
2266 }
2267
2268 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
2269                                 uint8_t tunnel_type)
2270 {
2271         struct hwrm_tunnel_dst_port_free_input req = {0};
2272         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
2273         int rc = 0;
2274
2275         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, -1, resp);
2276         req.tunnel_type = tunnel_type;
2277         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
2278         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2279         HWRM_CHECK_RESULT;
2280
2281         return rc;
2282 }
2283
2284 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf)
2285 {
2286         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2287         struct hwrm_func_cfg_input req = {0};
2288         int rc;
2289
2290         HWRM_PREP(req, FUNC_CFG, -1, resp);
2291         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2292         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2293         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2294         HWRM_CHECK_RESULT;
2295
2296         return rc;
2297 }
2298
2299 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
2300 {
2301         int rc = 0;
2302         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
2303         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
2304
2305         HWRM_PREP(req, FUNC_BUF_RGTR, -1, resp);
2306
2307         req.req_buf_num_pages = rte_cpu_to_le_16(1);
2308         req.req_buf_page_size = rte_cpu_to_le_16(
2309                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
2310         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
2311         req.req_buf_page_addr[0] =
2312                 rte_cpu_to_le_64(rte_mem_virt2phy(bp->pf.vf_req_buf));
2313         if (req.req_buf_page_addr[0] == 0) {
2314                 RTE_LOG(ERR, PMD,
2315                         "unable to map buffer address to physical memory\n");
2316                 return -ENOMEM;
2317         }
2318
2319         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2320
2321         HWRM_CHECK_RESULT;
2322
2323         return rc;
2324 }
2325
2326 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
2327 {
2328         int rc = 0;
2329         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
2330         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
2331
2332         HWRM_PREP(req, FUNC_BUF_UNRGTR, -1, resp);
2333
2334         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2335
2336         HWRM_CHECK_RESULT;
2337
2338         return rc;
2339 }
2340
2341 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
2342 {
2343         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2344         struct hwrm_func_cfg_input req = {0};
2345         int rc;
2346
2347         HWRM_PREP(req, FUNC_CFG, -1, resp);
2348         req.fid = rte_cpu_to_le_16(0xffff);
2349         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2350         req.enables = rte_cpu_to_le_32(
2351                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2352         req.async_event_cr = rte_cpu_to_le_16(
2353                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2354         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2355         HWRM_CHECK_RESULT;
2356
2357         return rc;
2358 }
2359
2360 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
2361 {
2362         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2363         struct hwrm_func_vf_cfg_input req = {0};
2364         int rc;
2365
2366         HWRM_PREP(req, FUNC_VF_CFG, -1, resp);
2367         req.enables = rte_cpu_to_le_32(
2368                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2369         req.async_event_cr = rte_cpu_to_le_16(
2370                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2371         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2372         HWRM_CHECK_RESULT;
2373
2374         return rc;
2375 }
2376
2377 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
2378 {
2379         struct hwrm_func_cfg_input req = {0};
2380         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2381         uint16_t dflt_vlan, fid;
2382         uint32_t func_cfg_flags;
2383         int rc = 0;
2384
2385         HWRM_PREP(req, FUNC_CFG, -1, resp);
2386
2387         if (is_vf) {
2388                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
2389                 fid = bp->pf.vf_info[vf].fid;
2390                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
2391         } else {
2392                 fid = rte_cpu_to_le_16(0xffff);
2393                 func_cfg_flags = bp->pf.func_cfg_flags;
2394                 dflt_vlan = bp->vlan;
2395         }
2396
2397         req.flags = rte_cpu_to_le_32(func_cfg_flags);
2398         req.fid = rte_cpu_to_le_16(fid);
2399         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2400         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
2401
2402         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2403         HWRM_CHECK_RESULT;
2404
2405         return rc;
2406 }
2407
2408 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
2409                         uint16_t max_bw, uint16_t enables)
2410 {
2411         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2412         struct hwrm_func_cfg_input req = {0};
2413         int rc;
2414
2415         HWRM_PREP(req, FUNC_CFG, -1, resp);
2416         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2417         req.enables |= rte_cpu_to_le_32(enables);
2418         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2419         req.max_bw = rte_cpu_to_le_32(max_bw);
2420         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2421         HWRM_CHECK_RESULT;
2422
2423         return rc;
2424 }
2425
2426 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
2427                               void *encaped, size_t ec_size)
2428 {
2429         int rc = 0;
2430         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
2431         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2432
2433         if (ec_size > sizeof(req.encap_request))
2434                 return -1;
2435
2436         HWRM_PREP(req, REJECT_FWD_RESP, -1, resp);
2437
2438         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2439         memcpy(req.encap_request, encaped, ec_size);
2440
2441         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2442
2443         HWRM_CHECK_RESULT;
2444
2445         return rc;
2446 }
2447
2448 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
2449                                        struct ether_addr *mac)
2450 {
2451         struct hwrm_func_qcfg_input req = {0};
2452         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2453         int rc;
2454
2455         HWRM_PREP(req, FUNC_QCFG, -1, resp);
2456         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2457         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2458
2459         HWRM_CHECK_RESULT;
2460
2461         memcpy(mac->addr_bytes, resp->mac_address, ETHER_ADDR_LEN);
2462         return rc;
2463 }
2464
2465 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
2466                             void *encaped, size_t ec_size)
2467 {
2468         int rc = 0;
2469         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
2470         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2471
2472         if (ec_size > sizeof(req.encap_request))
2473                 return -1;
2474
2475         HWRM_PREP(req, EXEC_FWD_RESP, -1, resp);
2476
2477         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2478         memcpy(req.encap_request, encaped, ec_size);
2479
2480         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2481
2482         HWRM_CHECK_RESULT;
2483
2484         return rc;
2485 }
2486
2487 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
2488                          struct rte_eth_stats *stats)
2489 {
2490         int rc = 0;
2491         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
2492         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
2493
2494         HWRM_PREP(req, STAT_CTX_QUERY, -1, resp);
2495
2496         req.stat_ctx_id = rte_cpu_to_le_32(cid);
2497
2498         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2499
2500         HWRM_CHECK_RESULT;
2501
2502         stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2503         stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2504         stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2505         stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2506         stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2507         stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2508
2509         stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2510         stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2511         stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2512         stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2513         stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2514         stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2515
2516         stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
2517         stats->q_errors[idx] += rte_le_to_cpu_64(resp->tx_err_pkts);
2518         stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
2519
2520         return rc;
2521 }
2522
2523 int bnxt_hwrm_port_qstats(struct bnxt *bp)
2524 {
2525         struct hwrm_port_qstats_input req = {0};
2526         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2527         struct bnxt_pf_info *pf = &bp->pf;
2528         int rc;
2529
2530         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2531                 return 0;
2532
2533         HWRM_PREP(req, PORT_QSTATS, -1, resp);
2534         req.port_id = rte_cpu_to_le_16(pf->port_id);
2535         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
2536         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
2537         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2538         HWRM_CHECK_RESULT;
2539         return rc;
2540 }
2541
2542 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
2543 {
2544         struct hwrm_port_clr_stats_input req = {0};
2545         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2546         struct bnxt_pf_info *pf = &bp->pf;
2547         int rc;
2548
2549         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2550                 return 0;
2551
2552         HWRM_PREP(req, PORT_CLR_STATS, -1, resp);
2553         req.port_id = rte_cpu_to_le_16(pf->port_id);
2554         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2555         HWRM_CHECK_RESULT;
2556         return rc;
2557 }
2558
2559 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
2560 {
2561         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2562         struct hwrm_port_led_qcaps_input req = {0};
2563         int rc;
2564
2565         if (BNXT_VF(bp))
2566                 return 0;
2567
2568         HWRM_PREP(req, PORT_LED_QCAPS, -1, resp);
2569         req.port_id = bp->pf.port_id;
2570         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2571         HWRM_CHECK_RESULT;
2572
2573         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
2574                 unsigned int i;
2575
2576                 bp->num_leds = resp->num_leds;
2577                 memcpy(bp->leds, &resp->led0_id,
2578                         sizeof(bp->leds[0]) * bp->num_leds);
2579                 for (i = 0; i < bp->num_leds; i++) {
2580                         struct bnxt_led_info *led = &bp->leds[i];
2581
2582                         uint16_t caps = led->led_state_caps;
2583
2584                         if (!led->led_group_id ||
2585                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
2586                                 bp->num_leds = 0;
2587                                 break;
2588                         }
2589                 }
2590         }
2591         return rc;
2592 }
2593
2594 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
2595 {
2596         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2597         struct hwrm_port_led_cfg_input req = {0};
2598         struct bnxt_led_cfg *led_cfg;
2599         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
2600         uint16_t duration = 0;
2601         int rc, i;
2602
2603         if (!bp->num_leds || BNXT_VF(bp))
2604                 return -EOPNOTSUPP;
2605
2606         HWRM_PREP(req, PORT_LED_CFG, -1, resp);
2607         if (led_on) {
2608                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
2609                 duration = rte_cpu_to_le_16(500);
2610         }
2611         req.port_id = bp->pf.port_id;
2612         req.num_leds = bp->num_leds;
2613         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
2614         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
2615                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
2616                 led_cfg->led_id = bp->leds[i].led_id;
2617                 led_cfg->led_state = led_state;
2618                 led_cfg->led_blink_on = duration;
2619                 led_cfg->led_blink_off = duration;
2620                 led_cfg->led_group_id = bp->leds[i].led_group_id;
2621         }
2622
2623         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2624         HWRM_CHECK_RESULT;
2625
2626         return rc;
2627 }
2628
2629 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
2630                                         uint16_t *vnic_ids)
2631 {
2632         struct hwrm_func_vf_vnic_ids_query_input req = {0};
2633         struct hwrm_func_vf_vnic_ids_query_output *resp =
2634                                                 bp->hwrm_cmd_resp_addr;
2635         int rc;
2636
2637         /* First query all VNIC ids */
2638         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, -1, resp_vf_vnic_ids);
2639
2640         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
2641         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
2642         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2phy(vnic_ids));
2643
2644         if (req.vnic_id_tbl_addr == 0) {
2645                 RTE_LOG(ERR, PMD,
2646                 "unable to map VNIC ID table address to physical memory\n");
2647                 return -ENOMEM;
2648         }
2649         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2650         if (rc) {
2651                 RTE_LOG(ERR, PMD, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
2652                 return -1;
2653         } else if (resp->error_code) {
2654                 rc = rte_le_to_cpu_16(resp->error_code);
2655                 RTE_LOG(ERR, PMD, "hwrm_func_vf_vnic_query error %d\n", rc);
2656                 return -1;
2657         }
2658
2659         return rte_le_to_cpu_32(resp->vnic_id_cnt);
2660 }
2661
2662 /*
2663  * This function queries the VNIC IDs  for a specified VF. It then calls
2664  * the vnic_cb to update the necessary field in vnic_info with cbdata.
2665  * Then it calls the hwrm_cb function to program this new vnic configuration.
2666  */
2667 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
2668         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
2669         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
2670 {
2671         struct bnxt_vnic_info vnic;
2672         int rc = 0;
2673         int i, num_vnic_ids;
2674         uint16_t *vnic_ids;
2675         size_t vnic_id_sz;
2676         size_t sz;
2677
2678         /* First query all VNIC ids */
2679         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
2680         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
2681                         RTE_CACHE_LINE_SIZE);
2682         if (vnic_ids == NULL) {
2683                 rc = -ENOMEM;
2684                 return rc;
2685         }
2686         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
2687                 rte_mem_lock_page(((char *)vnic_ids) + sz);
2688
2689         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
2690
2691         if (num_vnic_ids < 0)
2692                 return num_vnic_ids;
2693
2694         /* Retrieve VNIC, update bd_stall then update */
2695
2696         for (i = 0; i < num_vnic_ids; i++) {
2697                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
2698                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
2699                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
2700                 if (rc)
2701                         break;
2702                 if (vnic.mru == 4)      /* Indicates unallocated */
2703                         continue;
2704
2705                 vnic_cb(&vnic, cbdata);
2706
2707                 rc = hwrm_cb(bp, &vnic);
2708                 if (rc)
2709                         break;
2710         }
2711
2712         rte_free(vnic_ids);
2713
2714         return rc;
2715 }
2716
2717 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
2718                                               bool on)
2719 {
2720         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2721         struct hwrm_func_cfg_input req = {0};
2722         int rc;
2723
2724         HWRM_PREP(req, FUNC_CFG, -1, resp);
2725         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2726         req.enables |= rte_cpu_to_le_32(
2727                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
2728         req.vlan_antispoof_mode = on ?
2729                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
2730                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
2731         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2732         HWRM_CHECK_RESULT;
2733
2734         return rc;
2735 }
2736
2737 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
2738 {
2739         struct bnxt_vnic_info vnic;
2740         uint16_t *vnic_ids;
2741         size_t vnic_id_sz;
2742         int num_vnic_ids, i;
2743         size_t sz;
2744         int rc;
2745
2746         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
2747         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
2748                         RTE_CACHE_LINE_SIZE);
2749         if (vnic_ids == NULL) {
2750                 rc = -ENOMEM;
2751                 return rc;
2752         }
2753
2754         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
2755                 rte_mem_lock_page(((char *)vnic_ids) + sz);
2756
2757         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
2758         if (rc <= 0)
2759                 goto exit;
2760         num_vnic_ids = rc;
2761
2762         /*
2763          * Loop through to find the default VNIC ID.
2764          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
2765          * by sending the hwrm_func_qcfg command to the firmware.
2766          */
2767         for (i = 0; i < num_vnic_ids; i++) {
2768                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
2769                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
2770                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
2771                                         bp->pf.first_vf_id + vf);
2772                 if (rc)
2773                         goto exit;
2774                 if (vnic.func_default) {
2775                         rte_free(vnic_ids);
2776                         return vnic.fw_vnic_id;
2777                 }
2778         }
2779         /* Could not find a default VNIC. */
2780         RTE_LOG(ERR, PMD, "No default VNIC\n");
2781 exit:
2782         rte_free(vnic_ids);
2783         return -1;
2784 }