drivers/net/bnxt/bnxt_hwrm.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) Broadcom Limited.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Broadcom Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <rte_byteorder.h>
  35 #include <rte_common.h>
  36 #include <rte_cycles.h>
  37 #include <rte_malloc.h>
  38 #include <rte_memzone.h>
  39 #include <rte_version.h>
  40
  41 #include "bnxt.h"
  42 #include "bnxt_cpr.h"
  43 #include "bnxt_filter.h"
  44 #include "bnxt_hwrm.h"
  45 #include "bnxt_rxq.h"
  46 #include "bnxt_ring.h"
  47 #include "bnxt_txq.h"
  48 #include "bnxt_vnic.h"
  49 #include "hsi_struct_def_dpdk.h"
  50
  51 #define HWRM_CMD_TIMEOUT                2000
  52
  53 /*
  54  * HWRM Functions (sent to HWRM)
  55  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  56  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  57  * command was failed by the ChiMP.
  58  */
  59
  60 static int bnxt_hwrm_send_message_locked(struct bnxt *bp, void *msg,
  61                                         uint32_t msg_len)
  62 {
  63         unsigned int i;
  64         struct input *req = msg;
  65         struct output *resp = bp->hwrm_cmd_resp_addr;
  66         uint32_t *data = msg;
  67         uint8_t *bar;
  68         uint8_t *valid;
  69
  70         /* Write request msg to hwrm channel */
  71         for (i = 0; i < msg_len; i += 4) {
  72                 bar = (uint8_t *)bp->bar0 + i;
  73                 *(volatile uint32_t *)bar = *data;
  74                 data++;
  75         }
  76
  77         /* Zero the rest of the request space */
  78         for (; i < bp->max_req_len; i += 4) {
  79                 bar = (uint8_t *)bp->bar0 + i;
  80                 *(volatile uint32_t *)bar = 0;
  81         }
  82
  83         /* Ring channel doorbell */
  84         bar = (uint8_t *)bp->bar0 + 0x100;
  85         *(volatile uint32_t *)bar = 1;
  86
  87         /* Poll for the valid bit */
  88         for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
  89                 /* Sanity check on the resp->resp_len */
  90                 rte_rmb();
  91                 if (resp->resp_len && resp->resp_len <=
  92                                 bp->max_resp_len) {
  93                         /* Last byte of resp contains the valid key */
  94                         valid = (uint8_t *)resp + resp->resp_len - 1;
  95                         if (*valid == HWRM_RESP_VALID_KEY)
  96                                 break;
  97                 }
  98                 rte_delay_us(600);
  99         }
 100
 101         if (i >= HWRM_CMD_TIMEOUT) {
 102                 RTE_LOG(ERR, PMD, "Error sending msg %x\n",
 103                         req->req_type);
 104                 goto err_ret;
 105         }
 106         return 0;
 107
 108 err_ret:
 109         return -1;
 110 }
 111
 112 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg, uint32_t msg_len)
 113 {
 114         int rc;
 115
 116         rte_spinlock_lock(&bp->hwrm_lock);
 117         rc = bnxt_hwrm_send_message_locked(bp, msg, msg_len);
 118         rte_spinlock_unlock(&bp->hwrm_lock);
 119         return rc;
 120 }
 121
 122 #define HWRM_PREP(req, type, cr, resp) \
 123         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 124         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 125         req.cmpl_ring = rte_cpu_to_le_16(cr); \
 126         req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 127         req.target_id = rte_cpu_to_le_16(0xffff); \
 128         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr)
 129
 130 #define HWRM_CHECK_RESULT \
 131         { \
 132                 if (rc) { \
 133                         RTE_LOG(ERR, PMD, "%s failed rc:%d\n", \
 134                                 __func__, rc); \
 135                         return rc; \
 136                 } \
 137                 if (resp->error_code) { \
 138                         rc = rte_le_to_cpu_16(resp->error_code); \
 139                         RTE_LOG(ERR, PMD, "%s error %d\n", __func__, rc); \
 140                         return rc; \
 141                 } \
 142         }
 143
 144 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 145 {
 146         int rc = 0;
 147         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 148         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 149
 150         HWRM_PREP(req, CFA_L2_SET_RX_MASK, -1, resp);
 151         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 152         req.mask = 0;
 153
 154         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 155
 156         HWRM_CHECK_RESULT;
 157
 158         return rc;
 159 }
 160
 161 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 162 {
 163         int rc = 0;
 164         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 165         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 166         uint32_t mask = 0;
 167
 168         HWRM_PREP(req, CFA_L2_SET_RX_MASK, -1, resp);
 169         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 170
 171         /* FIXME add multicast flag, when multicast adding options is supported
 172          * by ethtool.
 173          */
 174         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 175                 mask = HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 176         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 177                 mask = HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 178         req.mask = rte_cpu_to_le_32(HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST |
 179                                     HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST |
 180                                     mask);
 181
 182         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 183
 184         HWRM_CHECK_RESULT;
 185
 186         return rc;
 187 }
 188
 189 int bnxt_hwrm_clear_filter(struct bnxt *bp,
 190                            struct bnxt_filter_info *filter)
 191 {
 192         int rc = 0;
 193         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 194         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 195
 196         HWRM_PREP(req, CFA_L2_FILTER_FREE, -1, resp);
 197
 198         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 199
 200         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 201
 202         HWRM_CHECK_RESULT;
 203
 204         filter->fw_l2_filter_id = -1;
 205
 206         return 0;
 207 }
 208
 209 int bnxt_hwrm_set_filter(struct bnxt *bp,
 210                          struct bnxt_vnic_info *vnic,
 211                          struct bnxt_filter_info *filter)
 212 {
 213         int rc = 0;
 214         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 215         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 216         uint32_t enables = 0;
 217
 218         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, -1, resp);
 219
 220         req.flags = rte_cpu_to_le_32(filter->flags);
 221
 222         enables = filter->enables |
 223               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 224         req.dst_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 225
 226         if (enables &
 227             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 228                 memcpy(req.l2_addr, filter->l2_addr,
 229                        ETHER_ADDR_LEN);
 230         if (enables &
 231             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 232                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 233                        ETHER_ADDR_LEN);
 234         if (enables &
 235             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 236                 req.l2_ovlan = filter->l2_ovlan;
 237         if (enables &
 238             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 239                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 240
 241         req.enables = rte_cpu_to_le_32(enables);
 242
 243         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 244
 245         HWRM_CHECK_RESULT;
 246
 247         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 248
 249         return rc;
 250 }
 251
 252 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, void *fwd_cmd)
 253 {
 254         int rc;
 255         struct hwrm_exec_fwd_resp_input req = {.req_type = 0 };
 256         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
 257
 258         HWRM_PREP(req, EXEC_FWD_RESP, -1, resp);
 259
 260         memcpy(req.encap_request, fwd_cmd,
 261                sizeof(req.encap_request));
 262
 263         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 264
 265         HWRM_CHECK_RESULT;
 266
 267         return rc;
 268 }
 269
 270 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 271 {
 272         int rc = 0;
 273         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 274         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 275
 276         HWRM_PREP(req, FUNC_QCAPS, -1, resp);
 277
 278         req.fid = rte_cpu_to_le_16(0xffff);
 279
 280         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 281
 282         HWRM_CHECK_RESULT;
 283
 284         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 285         if (BNXT_PF(bp)) {
 286                 struct bnxt_pf_info *pf = &bp->pf;
 287
 288                 pf->fw_fid = rte_le_to_cpu_32(resp->fid);
 289                 pf->port_id = resp->port_id;
 290                 memcpy(pf->mac_addr, resp->perm_mac_address, ETHER_ADDR_LEN);
 291                 pf->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 292                 pf->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 293                 pf->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 294                 pf->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 295                 pf->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 296                 pf->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 297                 pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 298                 pf->max_vfs = rte_le_to_cpu_16(resp->max_vfs);
 299         } else {
 300                 struct bnxt_vf_info *vf = &bp->vf;
 301
 302                 vf->fw_fid = rte_le_to_cpu_32(resp->fid);
 303                 memcpy(vf->mac_addr, &resp->perm_mac_address, ETHER_ADDR_LEN);
 304                 vf->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 305                 vf->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 306                 vf->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 307                 vf->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 308                 vf->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 309                 vf->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 310         }
 311
 312         return rc;
 313 }
 314
 315 int bnxt_hwrm_func_reset(struct bnxt *bp)
 316 {
 317         int rc = 0;
 318         struct hwrm_func_reset_input req = {.req_type = 0 };
 319         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 320
 321         HWRM_PREP(req, FUNC_RESET, -1, resp);
 322
 323         req.enables = rte_cpu_to_le_32(0);
 324
 325         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 326
 327         HWRM_CHECK_RESULT;
 328
 329         return rc;
 330 }
 331
 332 int bnxt_hwrm_func_driver_register(struct bnxt *bp, uint32_t flags,
 333                                    uint32_t *vf_req_fwd)
 334 {
 335         int rc;
 336         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 337         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 338
 339         if (bp->flags & BNXT_FLAG_REGISTERED)
 340                 return 0;
 341
 342         HWRM_PREP(req, FUNC_DRV_RGTR, -1, resp);
 343         req.flags = flags;
 344         req.enables = HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER;
 345         req.ver_maj = RTE_VER_YEAR;
 346         req.ver_min = RTE_VER_MONTH;
 347         req.ver_upd = RTE_VER_MINOR;
 348
 349         memcpy(req.vf_req_fwd, vf_req_fwd, sizeof(req.vf_req_fwd));
 350
 351         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 352
 353         HWRM_CHECK_RESULT;
 354
 355         bp->flags |= BNXT_FLAG_REGISTERED;
 356
 357         return rc;
 358 }
 359
 360 int bnxt_hwrm_ver_get(struct bnxt *bp)
 361 {
 362         int rc = 0;
 363         struct hwrm_ver_get_input req = {.req_type = 0 };
 364         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 365         uint32_t my_version;
 366         uint32_t fw_version;
 367         uint16_t max_resp_len;
 368         char type[RTE_MEMZONE_NAMESIZE];
 369
 370         HWRM_PREP(req, VER_GET, -1, resp);
 371
 372         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 373         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 374         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 375
 376         /*
 377          * Hold the lock since we may be adjusting the response pointers.
 378          */
 379         rte_spinlock_lock(&bp->hwrm_lock);
 380         rc = bnxt_hwrm_send_message_locked(bp, &req, sizeof(req));
 381
 382         HWRM_CHECK_RESULT;
 383
 384         RTE_LOG(INFO, PMD, "%d.%d.%d:%d.%d.%d\n",
 385                 resp->hwrm_intf_maj, resp->hwrm_intf_min,
 386                 resp->hwrm_intf_upd,
 387                 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
 388
 389         my_version = HWRM_VERSION_MAJOR << 16;
 390         my_version |= HWRM_VERSION_MINOR << 8;
 391         my_version |= HWRM_VERSION_UPDATE;
 392
 393         fw_version = resp->hwrm_intf_maj << 16;
 394         fw_version |= resp->hwrm_intf_min << 8;
 395         fw_version |= resp->hwrm_intf_upd;
 396
 397         if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
 398                 RTE_LOG(ERR, PMD, "Unsupported firmware API version\n");
 399                 rc = -EINVAL;
 400                 goto error;
 401         }
 402
 403         if (my_version != fw_version) {
 404                 RTE_LOG(INFO, PMD, "BNXT Driver/HWRM API mismatch.\n");
 405                 if (my_version < fw_version) {
 406                         RTE_LOG(INFO, PMD,
 407                                 "Firmware API version is newer than driver.\n");
 408                         RTE_LOG(INFO, PMD,
 409                                 "The driver may be missing features.\n");
 410                 } else {
 411                         RTE_LOG(INFO, PMD,
 412                                 "Firmware API version is older than driver.\n");
 413                         RTE_LOG(INFO, PMD,
 414                                 "Not all driver features may be functional.\n");
 415                 }
 416         }
 417
 418         if (bp->max_req_len > resp->max_req_win_len) {
 419                 RTE_LOG(ERR, PMD, "Unsupported request length\n");
 420                 rc = -EINVAL;
 421         }
 422         bp->max_req_len = resp->max_req_win_len;
 423         max_resp_len = resp->max_resp_len;
 424         if (bp->max_resp_len != max_resp_len) {
 425                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 426                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 427                         bp->pdev->addr.devid, bp->pdev->addr.function);
 428
 429                 rte_free(bp->hwrm_cmd_resp_addr);
 430
 431                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 432                 if (bp->hwrm_cmd_resp_addr == NULL) {
 433                         rc = -ENOMEM;
 434                         goto error;
 435                 }
 436                 bp->hwrm_cmd_resp_dma_addr =
 437                         rte_malloc_virt2phy(bp->hwrm_cmd_resp_addr);
 438                 bp->max_resp_len = max_resp_len;
 439         }
 440
 441 error:
 442         rte_spinlock_unlock(&bp->hwrm_lock);
 443         return rc;
 444 }
 445
 446 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
 447 {
 448         int rc;
 449         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
 450         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
 451
 452         if (!(bp->flags & BNXT_FLAG_REGISTERED))
 453                 return 0;
 454
 455         HWRM_PREP(req, FUNC_DRV_UNRGTR, -1, resp);
 456         req.flags = flags;
 457
 458         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 459
 460         HWRM_CHECK_RESULT;
 461
 462         bp->flags &= ~BNXT_FLAG_REGISTERED;
 463
 464         return rc;
 465 }
 466
 467 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
 468 {
 469         int rc = 0;
 470         struct hwrm_port_phy_cfg_input req = {.req_type = 0};
 471         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 472
 473         HWRM_PREP(req, PORT_PHY_CFG, -1, resp);
 474
 475         req.flags = conf->phy_flags;
 476         if (conf->link_up) {
 477                 req.force_link_speed = conf->link_speed;
 478                 /*
 479                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
 480                  * any auto mode, even "none".
 481                  */
 482                 if (req.auto_mode == HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE) {
 483                         req.flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
 484                 } else {
 485                         req.auto_mode = conf->auto_mode;
 486                         req.enables |=
 487                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
 488                         req.auto_link_speed_mask = conf->auto_link_speed_mask;
 489                         req.enables |=
 490                            HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
 491                         req.auto_link_speed = conf->auto_link_speed;
 492                         req.enables |=
 493                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
 494                 }
 495                 req.auto_duplex = conf->duplex;
 496                 req.enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
 497                 req.auto_pause = conf->auto_pause;
 498                 /* Set force_pause if there is no auto or if there is a force */
 499                 if (req.auto_pause)
 500                         req.enables |=
 501                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
 502                 else
 503                         req.enables |=
 504                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
 505                 req.force_pause = conf->force_pause;
 506                 if (req.force_pause)
 507                         req.enables |=
 508                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
 509         } else {
 510                 req.flags &= ~HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
 511                 req.flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DOWN;
 512                 req.force_link_speed = 0;
 513         }
 514
 515         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 516
 517         HWRM_CHECK_RESULT;
 518
 519         return rc;
 520 }
 521
 522 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
 523 {
 524         int rc = 0;
 525         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
 526         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
 527
 528         HWRM_PREP(req, QUEUE_QPORTCFG, -1, resp);
 529
 530         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 531
 532         HWRM_CHECK_RESULT;
 533
 534 #define GET_QUEUE_INFO(x) \
 535         bp->cos_queue[x].id = resp->queue_id##x; \
 536         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
 537
 538         GET_QUEUE_INFO(0);
 539         GET_QUEUE_INFO(1);
 540         GET_QUEUE_INFO(2);
 541         GET_QUEUE_INFO(3);
 542         GET_QUEUE_INFO(4);
 543         GET_QUEUE_INFO(5);
 544         GET_QUEUE_INFO(6);
 545         GET_QUEUE_INFO(7);
 546
 547         return rc;
 548 }
 549
 550 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
 551 {
 552         int rc = 0;
 553         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
 554         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
 555
 556         HWRM_PREP(req, STAT_CTX_CLR_STATS, -1, resp);
 557
 558         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
 559                 return rc;
 560
 561         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
 562         req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++);
 563
 564         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 565
 566         HWRM_CHECK_RESULT;
 567
 568         return rc;
 569 }
 570
 571 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp,
 572                              struct bnxt_cp_ring_info *cpr, unsigned int idx)
 573 {
 574         int rc;
 575         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
 576         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 577
 578         HWRM_PREP(req, STAT_CTX_ALLOC, -1, resp);
 579
 580         req.update_period_ms = rte_cpu_to_le_32(1000);
 581
 582         req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++);
 583         req.stats_dma_addr =
 584             rte_cpu_to_le_64(cpr->hw_stats_map);
 585
 586         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 587
 588         HWRM_CHECK_RESULT;
 589
 590         cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
 591         bp->grp_info[idx].fw_stats_ctx = cpr->hw_stats_ctx_id;
 592
 593         return rc;
 594 }
 595
 596 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 597 {
 598         int rc = 0, i, j;
 599         struct hwrm_vnic_alloc_input req = {.req_type = 0 };
 600         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 601
 602         /* map ring groups to this vnic */
 603         for (i = vnic->start_grp_id, j = 0; i <= vnic->end_grp_id; i++, j++) {
 604                 if (bp->grp_info[i].fw_grp_id == (uint16_t)HWRM_NA_SIGNATURE) {
 605                         RTE_LOG(ERR, PMD,
 606                                 "Not enough ring groups avail:%x req:%x\n", j,
 607                                 (vnic->end_grp_id - vnic->start_grp_id) + 1);
 608                         break;
 609                 }
 610                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
 611         }
 612
 613         vnic->fw_rss_cos_lb_ctx = (uint16_t)HWRM_NA_SIGNATURE;
 614         vnic->ctx_is_rss_cos_lb = HW_CONTEXT_NONE;
 615
 616         HWRM_PREP(req, VNIC_ALLOC, -1, resp);
 617
 618         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 619
 620         HWRM_CHECK_RESULT;
 621
 622         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
 623         return rc;
 624 }
 625
 626 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 627 {
 628         int rc = 0;
 629         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
 630         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 631
 632         HWRM_PREP(req, VNIC_CFG, -1, resp);
 633
 634         /* Only RSS support for now TBD: COS & LB */
 635         req.enables =
 636             rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP |
 637                              HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE |
 638                              HWRM_VNIC_CFG_INPUT_ENABLES_MRU);
 639         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 640         req.dflt_ring_grp =
 641                 rte_cpu_to_le_16(bp->grp_info[vnic->start_grp_id].fw_grp_id);
 642         req.rss_rule = rte_cpu_to_le_16(vnic->fw_rss_cos_lb_ctx);
 643         req.cos_rule = rte_cpu_to_le_16(0xffff);
 644         req.lb_rule = rte_cpu_to_le_16(0xffff);
 645         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
 646                                    ETHER_CRC_LEN + VLAN_TAG_SIZE);
 647         if (vnic->func_default)
 648                 req.flags = 1;
 649         if (vnic->vlan_strip)
 650                 req.flags |=
 651                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
 652
 653         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 654
 655         HWRM_CHECK_RESULT;
 656
 657         return rc;
 658 }
 659
 660 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 661 {
 662         int rc = 0;
 663         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
 664         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
 665                                                 bp->hwrm_cmd_resp_addr;
 666
 667         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, -1, resp);
 668
 669         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 670
 671         HWRM_CHECK_RESULT;
 672
 673         vnic->fw_rss_cos_lb_ctx = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
 674
 675         return rc;
 676 }
 677
 678 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 679 {
 680         int rc = 0;
 681         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
 682         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
 683                                                 bp->hwrm_cmd_resp_addr;
 684
 685         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, -1, resp);
 686
 687         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->fw_rss_cos_lb_ctx);
 688
 689         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 690
 691         HWRM_CHECK_RESULT;
 692
 693         vnic->fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
 694
 695         return rc;
 696 }
 697
 698 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 699 {
 700         int rc = 0;
 701         struct hwrm_vnic_free_input req = {.req_type = 0 };
 702         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
 703
 704         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 705                 return rc;
 706
 707         HWRM_PREP(req, VNIC_FREE, -1, resp);
 708
 709         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 710
 711         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 712
 713         HWRM_CHECK_RESULT;
 714
 715         vnic->fw_vnic_id = INVALID_HW_RING_ID;
 716         return rc;
 717 }
 718
 719 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
 720                            struct bnxt_vnic_info *vnic)
 721 {
 722         int rc = 0;
 723         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
 724         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 725
 726         HWRM_PREP(req, VNIC_RSS_CFG, -1, resp);
 727
 728         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
 729
 730         req.ring_grp_tbl_addr =
 731             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
 732         req.hash_key_tbl_addr =
 733             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
 734         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_rss_cos_lb_ctx);
 735
 736         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 737
 738         HWRM_CHECK_RESULT;
 739
 740         return rc;
 741 }
 742
 743 /*
 744  * HWRM utility functions
 745  */
 746
 747 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
 748 {
 749         unsigned int i;
 750         int rc = 0;
 751
 752         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
 753                 struct bnxt_tx_queue *txq;
 754                 struct bnxt_rx_queue *rxq;
 755                 struct bnxt_cp_ring_info *cpr;
 756
 757                 if (i >= bp->rx_cp_nr_rings) {
 758                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
 759                         cpr = txq->cp_ring;
 760                 } else {
 761                         rxq = bp->rx_queues[i];
 762                         cpr = rxq->cp_ring;
 763                 }
 764
 765                 rc = bnxt_hwrm_stat_clear(bp, cpr);
 766                 if (rc)
 767                         return rc;
 768         }
 769         return 0;
 770 }
 771
 772 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
 773 {
 774         unsigned int i;
 775         int rc = 0;
 776
 777         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
 778                 struct bnxt_tx_queue *txq;
 779                 struct bnxt_rx_queue *rxq;
 780                 struct bnxt_cp_ring_info *cpr;
 781                 unsigned int idx = i + 1;
 782
 783                 if (i >= bp->rx_cp_nr_rings) {
 784                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
 785                         cpr = txq->cp_ring;
 786                 } else {
 787                         rxq = bp->rx_queues[i];
 788                         cpr = rxq->cp_ring;
 789                 }
 790
 791                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, idx);
 792
 793                 if (rc)
 794                         return rc;
 795         }
 796         return rc;
 797 }
 798
 799 void bnxt_free_hwrm_resources(struct bnxt *bp)
 800 {
 801         /* Release memzone */
 802         rte_free(bp->hwrm_cmd_resp_addr);
 803         bp->hwrm_cmd_resp_addr = NULL;
 804         bp->hwrm_cmd_resp_dma_addr = 0;
 805 }
 806
 807 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
 808 {
 809         struct rte_pci_device *pdev = bp->pdev;
 810         char type[RTE_MEMZONE_NAMESIZE];
 811
 812         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
 813                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 814         bp->max_req_len = HWRM_MAX_REQ_LEN;
 815         bp->max_resp_len = HWRM_MAX_RESP_LEN;
 816         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
 817         if (bp->hwrm_cmd_resp_addr == NULL)
 818                 return -ENOMEM;
 819         bp->hwrm_cmd_resp_dma_addr =
 820                 rte_malloc_virt2phy(bp->hwrm_cmd_resp_addr);
 821         rte_spinlock_init(&bp->hwrm_lock);
 822
 823         return 0;
 824 }
 825
 826 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
 827 {
 828         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
 829
 830         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
 831                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
 832
 833         switch (conf_link_speed) {
 834         case ETH_LINK_SPEED_10M_HD:
 835         case ETH_LINK_SPEED_100M_HD:
 836                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
 837         }
 838         return hw_link_duplex;
 839 }
 840
 841 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
 842 {
 843         uint16_t eth_link_speed = 0;
 844
 845         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
 846                 return ETH_LINK_SPEED_AUTONEG;
 847
 848         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
 849         case ETH_LINK_SPEED_100M:
 850         case ETH_LINK_SPEED_100M_HD:
 851                 eth_link_speed =
 852                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB;
 853                 break;
 854         case ETH_LINK_SPEED_1G:
 855                 eth_link_speed =
 856                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
 857                 break;
 858         case ETH_LINK_SPEED_2_5G:
 859                 eth_link_speed =
 860                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
 861                 break;
 862         case ETH_LINK_SPEED_10G:
 863                 eth_link_speed =
 864                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
 865                 break;
 866         case ETH_LINK_SPEED_20G:
 867                 eth_link_speed =
 868                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
 869                 break;
 870         case ETH_LINK_SPEED_25G:
 871                 eth_link_speed =
 872                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
 873                 break;
 874         case ETH_LINK_SPEED_40G:
 875                 eth_link_speed =
 876                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
 877                 break;
 878         case ETH_LINK_SPEED_50G:
 879                 eth_link_speed =
 880                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
 881                 break;
 882         default:
 883                 RTE_LOG(ERR, PMD,
 884                         "Unsupported link speed %d; default to AUTO\n",
 885                         conf_link_speed);
 886                 break;
 887         }
 888         return eth_link_speed;
 889 }
 890
 891 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
 892                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
 893                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
 894                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G)
 895
 896 static int bnxt_valid_link_speed(uint32_t link_speed, uint8_t port_id)
 897 {
 898         uint32_t one_speed;
 899
 900         if (link_speed == ETH_LINK_SPEED_AUTONEG)
 901                 return 0;
 902
 903         if (link_speed & ETH_LINK_SPEED_FIXED) {
 904                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
 905
 906                 if (one_speed & (one_speed - 1)) {
 907                         RTE_LOG(ERR, PMD,
 908                                 "Invalid advertised speeds (%u) for port %u\n",
 909                                 link_speed, port_id);
 910                         return -EINVAL;
 911                 }
 912                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
 913                         RTE_LOG(ERR, PMD,
 914                                 "Unsupported advertised speed (%u) for port %u\n",
 915                                 link_speed, port_id);
 916                         return -EINVAL;
 917                 }
 918         } else {
 919                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
 920                         RTE_LOG(ERR, PMD,
 921                                 "Unsupported advertised speeds (%u) for port %u\n",
 922                                 link_speed, port_id);
 923                         return -EINVAL;
 924                 }
 925         }
 926         return 0;
 927 }
 928
 929 static uint16_t bnxt_parse_eth_link_speed_mask(uint32_t link_speed)
 930 {
 931         uint16_t ret = 0;
 932
 933         if (link_speed == ETH_LINK_SPEED_AUTONEG)
 934                 link_speed = BNXT_SUPPORTED_SPEEDS;
 935
 936         if (link_speed & ETH_LINK_SPEED_100M)
 937                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
 938         if (link_speed & ETH_LINK_SPEED_100M_HD)
 939                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
 940         if (link_speed & ETH_LINK_SPEED_1G)
 941                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
 942         if (link_speed & ETH_LINK_SPEED_2_5G)
 943                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
 944         if (link_speed & ETH_LINK_SPEED_10G)
 945                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
 946         if (link_speed & ETH_LINK_SPEED_20G)
 947                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
 948         if (link_speed & ETH_LINK_SPEED_25G)
 949                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
 950         if (link_speed & ETH_LINK_SPEED_40G)
 951                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
 952         if (link_speed & ETH_LINK_SPEED_50G)
 953                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
 954         return ret;
 955 }
 956
 957 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
 958 {
 959         int rc = 0;
 960         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 961         struct bnxt_link_info link_req;
 962         uint16_t speed;
 963
 964         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
 965                         bp->eth_dev->data->port_id);
 966         if (rc)
 967                 goto error;
 968
 969         memset(&link_req, 0, sizeof(link_req));
 970         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
 971         link_req.link_up = link_up;
 972         if (speed == 0) {
 973                 link_req.phy_flags =
 974                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
 975                 link_req.auto_mode =
 976                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW;
 977                 link_req.auto_link_speed_mask =
 978                         bnxt_parse_eth_link_speed_mask(dev_conf->link_speeds);
 979                 link_req.auto_link_speed =
 980                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB;
 981         } else {
 982                 link_req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
 983                 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE |
 984                         HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
 985                 link_req.link_speed = speed;
 986         }
 987         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
 988         link_req.auto_pause = bp->link_info.auto_pause;
 989         link_req.force_pause = bp->link_info.force_pause;
 990
 991         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
 992         if (rc) {
 993                 RTE_LOG(ERR, PMD,
 994                         "Set link config failed with rc %d\n", rc);
 995         }
 996
 997 error:
 998         return rc;
 999 }