drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #include <rte_io.h>
  28
  29 #define HWRM_CMD_TIMEOUT                6000000
  30 #define HWRM_SPEC_CODE_1_8_3            0x10803
  31 #define HWRM_VERSION_1_9_1              0x10901
  32 #define HWRM_VERSION_1_9_2              0x10903
  33
  34 struct bnxt_plcmodes_cfg {
  35         uint32_t        flags;
  36         uint16_t        jumbo_thresh;
  37         uint16_t        hds_offset;
  38         uint16_t        hds_threshold;
  39 };
  40
  41 static int page_getenum(size_t size)
  42 {
  43         if (size <= 1 << 4)
  44                 return 4;
  45         if (size <= 1 << 12)
  46                 return 12;
  47         if (size <= 1 << 13)
  48                 return 13;
  49         if (size <= 1 << 16)
  50                 return 16;
  51         if (size <= 1 << 21)
  52                 return 21;
  53         if (size <= 1 << 22)
  54                 return 22;
  55         if (size <= 1 << 30)
  56                 return 30;
  57         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  58         return sizeof(void *) * 8 - 1;
  59 }
  60
  61 static int page_roundup(size_t size)
  62 {
  63         return 1 << page_getenum(size);
  64 }
  65
  66 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  67                                   uint8_t *pg_attr,
  68                                   uint64_t *pg_dir)
  69 {
  70         if (rmem->nr_pages > 1) {
  71                 *pg_attr = 1;
  72                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  73         } else {
  74                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  75         }
  76 }
  77
  78 /*
  79  * HWRM Functions (sent to HWRM)
  80  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  81  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  82  * command was failed by the ChiMP.
  83  */
  84
  85 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  86                                   uint32_t msg_len, bool use_kong_mb)
  87 {
  88         unsigned int i;
  89         struct input *req = msg;
  90         struct output *resp = bp->hwrm_cmd_resp_addr;
  91         uint32_t *data = msg;
  92         uint8_t *bar;
  93         uint8_t *valid;
  94         uint16_t max_req_len = bp->max_req_len;
  95         struct hwrm_short_input short_input = { 0 };
  96         uint16_t bar_offset = use_kong_mb ?
  97                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  98         uint16_t mb_trigger_offset = use_kong_mb ?
  99                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 100
 101         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 102             msg_len > bp->max_req_len) {
 103                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 104
 105                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 106                 memcpy(short_cmd_req, req, msg_len);
 107
 108                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 109                 short_input.signature = rte_cpu_to_le_16(
 110                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 111                 short_input.size = rte_cpu_to_le_16(msg_len);
 112                 short_input.req_addr =
 113                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 114
 115                 data = (uint32_t *)&short_input;
 116                 msg_len = sizeof(short_input);
 117
 118                 /* Sync memory write before updating doorbell */
 119                 rte_wmb();
 120
 121                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 122         }
 123
 124         /* Write request msg to hwrm channel */
 125         for (i = 0; i < msg_len; i += 4) {
 126                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 127                 rte_write32(*data, bar);
 128                 data++;
 129         }
 130
 131         /* Zero the rest of the request space */
 132         for (; i < max_req_len; i += 4) {
 133                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 134                 rte_write32(0, bar);
 135         }
 136
 137         /* Ring channel doorbell */
 138         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 139         rte_write32(1, bar);
 140
 141         /* Poll for the valid bit */
 142         for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
 143                 /* Sanity check on the resp->resp_len */
 144                 rte_rmb();
 145                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 146                         /* Last byte of resp contains the valid key */
 147                         valid = (uint8_t *)resp + resp->resp_len - 1;
 148                         if (*valid == HWRM_RESP_VALID_KEY)
 149                                 break;
 150                 }
 151                 rte_delay_us(1);
 152         }
 153
 154         if (i >= HWRM_CMD_TIMEOUT) {
 155                 PMD_DRV_LOG(ERR, "Error sending msg 0x%04x\n",
 156                         req->req_type);
 157                 goto err_ret;
 158         }
 159         return 0;
 160
 161 err_ret:
 162         return -1;
 163 }
 164
 165 /*
 166  * HWRM_PREP() should be used to prepare *ALL* HWRM commands.  It grabs the
 167  * spinlock, and does initial processing.
 168  *
 169  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 170  * releases the spinlock only if it returns.  If the regular int return codes
 171  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 172  * directly, rather it should be copied and modified to suit the function.
 173  *
 174  * HWRM_UNLOCK() must be called after all response processing is completed.
 175  */
 176 #define HWRM_PREP(req, type, kong) do { \
 177         rte_spinlock_lock(&bp->hwrm_lock); \
 178         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 179         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 180         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 181         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 182                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 183         req.target_id = rte_cpu_to_le_16(0xffff); \
 184         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 185 } while (0)
 186
 187 #define HWRM_CHECK_RESULT_SILENT() do {\
 188         if (rc) { \
 189                 rte_spinlock_unlock(&bp->hwrm_lock); \
 190                 return rc; \
 191         } \
 192         if (resp->error_code) { \
 193                 rc = rte_le_to_cpu_16(resp->error_code); \
 194                 rte_spinlock_unlock(&bp->hwrm_lock); \
 195                 return rc; \
 196         } \
 197 } while (0)
 198
 199 #define HWRM_CHECK_RESULT() do {\
 200         if (rc) { \
 201                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 202                 rte_spinlock_unlock(&bp->hwrm_lock); \
 203                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 204                         rc = -EACCES; \
 205                 else if (rc > 0) \
 206                         rc = -EINVAL; \
 207                 return rc; \
 208         } \
 209         if (resp->error_code) { \
 210                 rc = rte_le_to_cpu_16(resp->error_code); \
 211                 if (resp->resp_len >= 16) { \
 212                         struct hwrm_err_output *tmp_hwrm_err_op = \
 213                                                 (void *)resp; \
 214                         PMD_DRV_LOG(ERR, \
 215                                 "error %d:%d:%08x:%04x\n", \
 216                                 rc, tmp_hwrm_err_op->cmd_err, \
 217                                 rte_le_to_cpu_32(\
 218                                         tmp_hwrm_err_op->opaque_0), \
 219                                 rte_le_to_cpu_16(\
 220                                         tmp_hwrm_err_op->opaque_1)); \
 221                 } else { \
 222                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 223                 } \
 224                 rte_spinlock_unlock(&bp->hwrm_lock); \
 225                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 226                         rc = -EACCES; \
 227                 else if (rc > 0) \
 228                         rc = -EINVAL; \
 229                 return rc; \
 230         } \
 231 } while (0)
 232
 233 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 234
 235 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 236 {
 237         int rc = 0;
 238         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 239         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 240
 241         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 242         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 243         req.mask = 0;
 244
 245         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 246
 247         HWRM_CHECK_RESULT();
 248         HWRM_UNLOCK();
 249
 250         return rc;
 251 }
 252
 253 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 254                                  struct bnxt_vnic_info *vnic,
 255                                  uint16_t vlan_count,
 256                                  struct bnxt_vlan_table_entry *vlan_table)
 257 {
 258         int rc = 0;
 259         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 260         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 261         uint32_t mask = 0;
 262
 263         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 264                 return rc;
 265
 266         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 267         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 268
 269         /* FIXME add multicast flag, when multicast adding options is supported
 270          * by ethtool.
 271          */
 272         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 273                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 274         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 275                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 276         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 277                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 278         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 279                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 280         if (vnic->flags & BNXT_VNIC_INFO_MCAST)
 281                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 282         if (vnic->mc_addr_cnt) {
 283                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 284                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 285                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 286         }
 287         if (vlan_table) {
 288                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 289                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 290                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 291                          rte_mem_virt2iova(vlan_table));
 292                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 293         }
 294         req.mask = rte_cpu_to_le_32(mask);
 295
 296         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 297
 298         HWRM_CHECK_RESULT();
 299         HWRM_UNLOCK();
 300
 301         return rc;
 302 }
 303
 304 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 305                         uint16_t vlan_count,
 306                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 307 {
 308         int rc = 0;
 309         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 310         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 311                                                 bp->hwrm_cmd_resp_addr;
 312
 313         /*
 314          * Older HWRM versions did not support this command, and the set_rx_mask
 315          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 316          * removed from set_rx_mask call, and this command was added.
 317          *
 318          * This command is also present from 1.7.8.11 and higher,
 319          * as well as 1.7.8.0
 320          */
 321         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 322                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 323                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 324                                         (11)))
 325                                 return 0;
 326                 }
 327         }
 328         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 329         req.fid = rte_cpu_to_le_16(fid);
 330
 331         req.vlan_tag_mask_tbl_addr =
 332                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 333         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 334
 335         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 336
 337         HWRM_CHECK_RESULT();
 338         HWRM_UNLOCK();
 339
 340         return rc;
 341 }
 342
 343 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 344                            struct bnxt_filter_info *filter)
 345 {
 346         int rc = 0;
 347         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 348         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 349
 350         if (filter->fw_l2_filter_id == UINT64_MAX)
 351                 return 0;
 352
 353         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 354
 355         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 356
 357         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 358
 359         HWRM_CHECK_RESULT();
 360         HWRM_UNLOCK();
 361
 362         filter->fw_l2_filter_id = UINT64_MAX;
 363
 364         return 0;
 365 }
 366
 367 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 368                          uint16_t dst_id,
 369                          struct bnxt_filter_info *filter)
 370 {
 371         int rc = 0;
 372         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 373         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 374         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 375         const struct rte_eth_vmdq_rx_conf *conf =
 376                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 377         uint32_t enables = 0;
 378         uint16_t j = dst_id - 1;
 379
 380         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 381         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 382             conf->pool_map[j].pools & (1UL << j)) {
 383                 PMD_DRV_LOG(DEBUG,
 384                         "Add vlan %u to vmdq pool %u\n",
 385                         conf->pool_map[j].vlan_id, j);
 386
 387                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 388                 filter->enables |=
 389                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 390                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 391         }
 392
 393         if (filter->fw_l2_filter_id != UINT64_MAX)
 394                 bnxt_hwrm_clear_l2_filter(bp, filter);
 395
 396         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 397
 398         req.flags = rte_cpu_to_le_32(filter->flags);
 399         req.flags |=
 400         rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST);
 401
 402         enables = filter->enables |
 403               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 404         req.dst_id = rte_cpu_to_le_16(dst_id);
 405
 406         if (enables &
 407             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 408                 memcpy(req.l2_addr, filter->l2_addr,
 409                        RTE_ETHER_ADDR_LEN);
 410         if (enables &
 411             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 412                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 413                        RTE_ETHER_ADDR_LEN);
 414         if (enables &
 415             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 416                 req.l2_ovlan = filter->l2_ovlan;
 417         if (enables &
 418             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 419                 req.l2_ivlan = filter->l2_ivlan;
 420         if (enables &
 421             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 422                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 423         if (enables &
 424             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 425                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 426         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 427                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 428         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 429                 req.src_type = filter->src_type;
 430
 431         req.enables = rte_cpu_to_le_32(enables);
 432
 433         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 434
 435         HWRM_CHECK_RESULT();
 436
 437         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 438         HWRM_UNLOCK();
 439
 440         return rc;
 441 }
 442
 443 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 444 {
 445         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 446         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 447         uint32_t flags = 0;
 448         int rc;
 449
 450         if (!ptp)
 451                 return 0;
 452
 453         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 454
 455         if (ptp->rx_filter)
 456                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 457         else
 458                 flags |=
 459                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 460         if (ptp->tx_tstamp_en)
 461                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 462         else
 463                 flags |=
 464                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 465         req.flags = rte_cpu_to_le_32(flags);
 466         req.enables = rte_cpu_to_le_32
 467                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 468         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 469
 470         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 471         HWRM_UNLOCK();
 472
 473         return rc;
 474 }
 475
 476 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 477 {
 478         int rc = 0;
 479         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 480         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 481         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 482
 483 /*      if (bp->hwrm_spec_code < 0x10801 || ptp)  TBD  */
 484         if (ptp)
 485                 return 0;
 486
 487         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 488
 489         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 490
 491         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 492
 493         HWRM_CHECK_RESULT();
 494
 495         if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 496                 return 0;
 497
 498         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 499         if (!ptp)
 500                 return -ENOMEM;
 501
 502         ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 503                 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 504         ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 505                 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 506         ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 507                 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 508         ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 509                 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 510         ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 511                 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 512         ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 513                 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 514         ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 515                 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 516         ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 517                 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 518         ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 519                 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 520
 521         ptp->bp = bp;
 522         bp->ptp_cfg = ptp;
 523
 524         return 0;
 525 }
 526
 527 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 528 {
 529         int rc = 0;
 530         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 531         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 532         uint16_t new_max_vfs;
 533         uint32_t flags;
 534         int i;
 535
 536         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 537
 538         req.fid = rte_cpu_to_le_16(0xffff);
 539
 540         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 541
 542         HWRM_CHECK_RESULT();
 543
 544         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 545         flags = rte_le_to_cpu_32(resp->flags);
 546         if (BNXT_PF(bp)) {
 547                 bp->pf.port_id = resp->port_id;
 548                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 549                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 550                 new_max_vfs = bp->pdev->max_vfs;
 551                 if (new_max_vfs != bp->pf.max_vfs) {
 552                         if (bp->pf.vf_info)
 553                                 rte_free(bp->pf.vf_info);
 554                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 555                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 556                         bp->pf.max_vfs = new_max_vfs;
 557                         for (i = 0; i < new_max_vfs; i++) {
 558                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 559                                 bp->pf.vf_info[i].vlan_table =
 560                                         rte_zmalloc("VF VLAN table",
 561                                                     getpagesize(),
 562                                                     getpagesize());
 563                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 564                                         PMD_DRV_LOG(ERR,
 565                                         "Fail to alloc VLAN table for VF %d\n",
 566                                         i);
 567                                 else
 568                                         rte_mem_lock_page(
 569                                                 bp->pf.vf_info[i].vlan_table);
 570                                 bp->pf.vf_info[i].vlan_as_table =
 571                                         rte_zmalloc("VF VLAN AS table",
 572                                                     getpagesize(),
 573                                                     getpagesize());
 574                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 575                                         PMD_DRV_LOG(ERR,
 576                                         "Alloc VLAN AS table for VF %d fail\n",
 577                                         i);
 578                                 else
 579                                         rte_mem_lock_page(
 580                                                bp->pf.vf_info[i].vlan_as_table);
 581                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 582                         }
 583                 }
 584         }
 585
 586         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 587         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 588         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 589         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 590         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 591         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 592         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 593         /* TODO: For now, do not support VMDq/RFS on VFs. */
 594         if (BNXT_PF(bp)) {
 595                 if (bp->pf.max_vfs)
 596                         bp->max_vnics = 1;
 597                 else
 598                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 599         } else {
 600                 bp->max_vnics = 1;
 601         }
 602         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 603         if (BNXT_PF(bp)) {
 604                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 605                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 606                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 607                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 608                         HWRM_UNLOCK();
 609                         bnxt_hwrm_ptp_qcfg(bp);
 610                 }
 611         }
 612
 613         HWRM_UNLOCK();
 614
 615         return rc;
 616 }
 617
 618 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 619 {
 620         int rc;
 621
 622         rc = __bnxt_hwrm_func_qcaps(bp);
 623         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 624                 rc = bnxt_alloc_ctx_mem(bp);
 625                 if (rc)
 626                         return rc;
 627
 628                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 629                 if (!rc)
 630                         bp->flags |= BNXT_FLAG_NEW_RM;
 631         }
 632
 633         return rc;
 634 }
 635
 636 int bnxt_hwrm_func_reset(struct bnxt *bp)
 637 {
 638         int rc = 0;
 639         struct hwrm_func_reset_input req = {.req_type = 0 };
 640         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 641
 642         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 643
 644         req.enables = rte_cpu_to_le_32(0);
 645
 646         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 647
 648         HWRM_CHECK_RESULT();
 649         HWRM_UNLOCK();
 650
 651         return rc;
 652 }
 653
 654 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 655 {
 656         int rc;
 657         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 658         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 659
 660         if (bp->flags & BNXT_FLAG_REGISTERED)
 661                 return 0;
 662
 663         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 664         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 665                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 666         req.ver_maj = RTE_VER_YEAR;
 667         req.ver_min = RTE_VER_MONTH;
 668         req.ver_upd = RTE_VER_MINOR;
 669
 670         if (BNXT_PF(bp)) {
 671                 req.enables |= rte_cpu_to_le_32(
 672                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 673                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 674                        RTE_MIN(sizeof(req.vf_req_fwd),
 675                                sizeof(bp->pf.vf_req_fwd)));
 676
 677                 /*
 678                  * PF can sniff HWRM API issued by VF. This can be set up by
 679                  * linux driver and inherited by the DPDK PF driver. Clear
 680                  * this HWRM sniffer list in FW because DPDK PF driver does
 681                  * not support this.
 682                  */
 683                 req.flags =
 684                 rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE);
 685         }
 686
 687         req.async_event_fwd[0] |=
 688                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 689                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 690                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE);
 691         req.async_event_fwd[1] |=
 692                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 693                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 694
 695         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 696
 697         HWRM_CHECK_RESULT();
 698         HWRM_UNLOCK();
 699
 700         bp->flags |= BNXT_FLAG_REGISTERED;
 701
 702         return rc;
 703 }
 704
 705 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 706 {
 707         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 708                 return 0;
 709
 710         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 711 }
 712
 713 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 714 {
 715         int rc;
 716         uint32_t flags = 0;
 717         uint32_t enables;
 718         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 719         struct hwrm_func_vf_cfg_input req = {0};
 720
 721         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 722
 723         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 724                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 725                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 726                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 727                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 728
 729         if (BNXT_HAS_RING_GRPS(bp)) {
 730                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 731                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 732         }
 733
 734         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 735         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 736                                             AGG_RING_MULTIPLIER);
 737         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 738         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 739                                               bp->tx_nr_rings);
 740         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 741         if (bp->vf_resv_strategy ==
 742             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 743                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 744                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 745                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 746                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 747                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 748                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 749         }
 750
 751         if (test)
 752                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 753                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 754                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 755                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 756                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 757                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 758
 759         if (test && BNXT_HAS_RING_GRPS(bp))
 760                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 761
 762         req.flags = rte_cpu_to_le_32(flags);
 763         req.enables |= rte_cpu_to_le_32(enables);
 764
 765         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 766
 767         if (test)
 768                 HWRM_CHECK_RESULT_SILENT();
 769         else
 770                 HWRM_CHECK_RESULT();
 771
 772         HWRM_UNLOCK();
 773         return rc;
 774 }
 775
 776 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 777 {
 778         int rc;
 779         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 780         struct hwrm_func_resource_qcaps_input req = {0};
 781
 782         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 783         req.fid = rte_cpu_to_le_16(0xffff);
 784
 785         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 786
 787         HWRM_CHECK_RESULT();
 788
 789         if (BNXT_VF(bp)) {
 790                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 791                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 792                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 793                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 794                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 795                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 796                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 797                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 798         }
 799         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 800         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 801         if (bp->vf_resv_strategy >
 802             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 803                 bp->vf_resv_strategy =
 804                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 805
 806         HWRM_UNLOCK();
 807         return rc;
 808 }
 809
 810 int bnxt_hwrm_ver_get(struct bnxt *bp)
 811 {
 812         int rc = 0;
 813         struct hwrm_ver_get_input req = {.req_type = 0 };
 814         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 815         uint32_t fw_version;
 816         uint16_t max_resp_len;
 817         char type[RTE_MEMZONE_NAMESIZE];
 818         uint32_t dev_caps_cfg;
 819
 820         bp->max_req_len = HWRM_MAX_REQ_LEN;
 821         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 822
 823         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 824         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 825         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 826
 827         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 828
 829         HWRM_CHECK_RESULT();
 830
 831         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 832                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 833                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 834                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 835         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 836                      (resp->hwrm_fw_min_8b << 16) |
 837                      (resp->hwrm_fw_bld_8b << 8) |
 838                      resp->hwrm_fw_rsvd_8b;
 839         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 840                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 841
 842         fw_version = resp->hwrm_intf_maj_8b << 16;
 843         fw_version |= resp->hwrm_intf_min_8b << 8;
 844         fw_version |= resp->hwrm_intf_upd_8b;
 845         bp->hwrm_spec_code = fw_version;
 846
 847         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
 848                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 849                 rc = -EINVAL;
 850                 goto error;
 851         }
 852
 853         if (bp->max_req_len > resp->max_req_win_len) {
 854                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
 855                 rc = -EINVAL;
 856         }
 857         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 858         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
 859         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
 860                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
 861
 862         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
 863         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 864
 865         if (bp->max_resp_len != max_resp_len) {
 866                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 867                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 868                         bp->pdev->addr.devid, bp->pdev->addr.function);
 869
 870                 rte_free(bp->hwrm_cmd_resp_addr);
 871
 872                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 873                 if (bp->hwrm_cmd_resp_addr == NULL) {
 874                         rc = -ENOMEM;
 875                         goto error;
 876                 }
 877                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
 878                 bp->hwrm_cmd_resp_dma_addr =
 879                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
 880                 if (bp->hwrm_cmd_resp_dma_addr == 0) {
 881                         PMD_DRV_LOG(ERR,
 882                         "Unable to map response buffer to physical memory.\n");
 883                         rc = -ENOMEM;
 884                         goto error;
 885                 }
 886                 bp->max_resp_len = max_resp_len;
 887         }
 888
 889         if ((dev_caps_cfg &
 890                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 891             (dev_caps_cfg &
 892              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
 893                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
 894                 bp->flags |= BNXT_FLAG_SHORT_CMD;
 895         }
 896
 897         if (((dev_caps_cfg &
 898               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 899              (dev_caps_cfg &
 900               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
 901             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
 902                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
 903                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 904                         bp->pdev->addr.devid, bp->pdev->addr.function);
 905
 906                 rte_free(bp->hwrm_short_cmd_req_addr);
 907
 908                 bp->hwrm_short_cmd_req_addr =
 909                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
 910                 if (bp->hwrm_short_cmd_req_addr == NULL) {
 911                         rc = -ENOMEM;
 912                         goto error;
 913                 }
 914                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
 915                 bp->hwrm_short_cmd_req_dma_addr =
 916                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
 917                 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
 918                         rte_free(bp->hwrm_short_cmd_req_addr);
 919                         PMD_DRV_LOG(ERR,
 920                                 "Unable to map buffer to physical memory.\n");
 921                         rc = -ENOMEM;
 922                         goto error;
 923                 }
 924         }
 925         if (dev_caps_cfg &
 926             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
 927                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
 928                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
 929         }
 930         if (dev_caps_cfg &
 931             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
 932                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
 933
 934 error:
 935         HWRM_UNLOCK();
 936         return rc;
 937 }
 938
 939 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
 940 {
 941         int rc;
 942         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
 943         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
 944
 945         if (!(bp->flags & BNXT_FLAG_REGISTERED))
 946                 return 0;
 947
 948         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
 949         req.flags = flags;
 950
 951         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 952
 953         HWRM_CHECK_RESULT();
 954         HWRM_UNLOCK();
 955
 956         bp->flags &= ~BNXT_FLAG_REGISTERED;
 957
 958         return rc;
 959 }
 960
 961 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
 962 {
 963         int rc = 0;
 964         struct hwrm_port_phy_cfg_input req = {0};
 965         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 966         uint32_t enables = 0;
 967
 968         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
 969
 970         if (conf->link_up) {
 971                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
 972                 if (bp->link_info.auto_mode && conf->link_speed) {
 973                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
 974                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
 975                 }
 976
 977                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
 978                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
 979                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
 980                 /*
 981                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
 982                  * any auto mode, even "none".
 983                  */
 984                 if (!conf->link_speed) {
 985                         /* No speeds specified. Enable AutoNeg - all speeds */
 986                         req.auto_mode =
 987                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
 988                 }
 989                 /* AutoNeg - Advertise speeds specified. */
 990                 if (conf->auto_link_speed_mask &&
 991                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
 992                         req.auto_mode =
 993                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
 994                         req.auto_link_speed_mask =
 995                                 conf->auto_link_speed_mask;
 996                         enables |=
 997                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
 998                 }
 999
1000                 req.auto_duplex = conf->duplex;
1001                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1002                 req.auto_pause = conf->auto_pause;
1003                 req.force_pause = conf->force_pause;
1004                 /* Set force_pause if there is no auto or if there is a force */
1005                 if (req.auto_pause && !req.force_pause)
1006                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1007                 else
1008                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1009
1010                 req.enables = rte_cpu_to_le_32(enables);
1011         } else {
1012                 req.flags =
1013                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1014                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1015         }
1016
1017         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1018
1019         HWRM_CHECK_RESULT();
1020         HWRM_UNLOCK();
1021
1022         return rc;
1023 }
1024
1025 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1026                                    struct bnxt_link_info *link_info)
1027 {
1028         int rc = 0;
1029         struct hwrm_port_phy_qcfg_input req = {0};
1030         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1031
1032         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1033
1034         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1035
1036         HWRM_CHECK_RESULT();
1037
1038         link_info->phy_link_status = resp->link;
1039         link_info->link_up =
1040                 (link_info->phy_link_status ==
1041                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1042         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1043         link_info->duplex = resp->duplex_cfg;
1044         link_info->pause = resp->pause;
1045         link_info->auto_pause = resp->auto_pause;
1046         link_info->force_pause = resp->force_pause;
1047         link_info->auto_mode = resp->auto_mode;
1048         link_info->phy_type = resp->phy_type;
1049         link_info->media_type = resp->media_type;
1050
1051         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1052         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1053         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1054         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1055         link_info->phy_ver[0] = resp->phy_maj;
1056         link_info->phy_ver[1] = resp->phy_min;
1057         link_info->phy_ver[2] = resp->phy_bld;
1058
1059         HWRM_UNLOCK();
1060
1061         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1062         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1063         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1064         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1065         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1066                     link_info->auto_link_speed_mask);
1067         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1068                     link_info->force_link_speed);
1069
1070         return rc;
1071 }
1072
1073 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1074 {
1075         int rc = 0;
1076         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1077         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1078         int i;
1079
1080         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1081
1082         req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1083         /* HWRM Version >= 1.9.1 */
1084         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1085                 req.drv_qmap_cap =
1086                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1087         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1088
1089         HWRM_CHECK_RESULT();
1090
1091 #define GET_QUEUE_INFO(x) \
1092         bp->cos_queue[x].id = resp->queue_id##x; \
1093         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1094
1095         GET_QUEUE_INFO(0);
1096         GET_QUEUE_INFO(1);
1097         GET_QUEUE_INFO(2);
1098         GET_QUEUE_INFO(3);
1099         GET_QUEUE_INFO(4);
1100         GET_QUEUE_INFO(5);
1101         GET_QUEUE_INFO(6);
1102         GET_QUEUE_INFO(7);
1103
1104         HWRM_UNLOCK();
1105
1106         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1107                 bp->tx_cosq_id = bp->cos_queue[0].id;
1108         } else {
1109                 /* iterate and find the COSq profile to use for Tx */
1110                 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1111                         if (bp->cos_queue[i].profile ==
1112                                 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1113                                 bp->tx_cosq_id = bp->cos_queue[i].id;
1114                                 break;
1115                         }
1116                 }
1117         }
1118
1119         bp->max_tc = resp->max_configurable_queues;
1120         bp->max_lltc = resp->max_configurable_lossless_queues;
1121         if (bp->max_tc > BNXT_MAX_QUEUE)
1122                 bp->max_tc = BNXT_MAX_QUEUE;
1123         bp->max_q = bp->max_tc;
1124
1125         PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1126
1127         return rc;
1128 }
1129
1130 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1131                          struct bnxt_ring *ring,
1132                          uint32_t ring_type, uint32_t map_index,
1133                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1134 {
1135         int rc = 0;
1136         uint32_t enables = 0;
1137         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1138         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1139         struct rte_mempool *mb_pool;
1140         uint16_t rx_buf_size;
1141
1142         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1143
1144         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1145         req.fbo = rte_cpu_to_le_32(0);
1146         /* Association of ring index with doorbell index */
1147         req.logical_id = rte_cpu_to_le_16(map_index);
1148         req.length = rte_cpu_to_le_32(ring->ring_size);
1149
1150         switch (ring_type) {
1151         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1152                 req.ring_type = ring_type;
1153                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1154                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1155                 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1156                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1157                         enables |=
1158                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1159                 break;
1160         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1161                 req.ring_type = ring_type;
1162                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1163                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1164                 if (BNXT_CHIP_THOR(bp)) {
1165                         mb_pool = bp->rx_queues[0]->mb_pool;
1166                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1167                                       RTE_PKTMBUF_HEADROOM;
1168                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1169                         enables |=
1170                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1171                 }
1172                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1173                         enables |=
1174                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1175                 break;
1176         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1177                 req.ring_type = ring_type;
1178                 if (BNXT_HAS_NQ(bp)) {
1179                         /* Association of cp ring with nq */
1180                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1181                         enables |=
1182                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1183                 }
1184                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1185                 break;
1186         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1187                 req.ring_type = ring_type;
1188                 req.page_size = BNXT_PAGE_SHFT;
1189                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1190                 break;
1191         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1192                 req.ring_type = ring_type;
1193                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1194
1195                 mb_pool = bp->rx_queues[0]->mb_pool;
1196                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1197                               RTE_PKTMBUF_HEADROOM;
1198                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1199
1200                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1201                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1202                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1203                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1204                 break;
1205         default:
1206                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1207                         ring_type);
1208                 HWRM_UNLOCK();
1209                 return -1;
1210         }
1211         req.enables = rte_cpu_to_le_32(enables);
1212
1213         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1214
1215         if (rc || resp->error_code) {
1216                 if (rc == 0 && resp->error_code)
1217                         rc = rte_le_to_cpu_16(resp->error_code);
1218                 switch (ring_type) {
1219                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1220                         PMD_DRV_LOG(ERR,
1221                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1222                         HWRM_UNLOCK();
1223                         return rc;
1224                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1225                         PMD_DRV_LOG(ERR,
1226                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1227                         HWRM_UNLOCK();
1228                         return rc;
1229                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1230                         PMD_DRV_LOG(ERR,
1231                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1232                                     rc);
1233                         HWRM_UNLOCK();
1234                         return rc;
1235                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1236                         PMD_DRV_LOG(ERR,
1237                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1238                         HWRM_UNLOCK();
1239                         return rc;
1240                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1241                         PMD_DRV_LOG(ERR,
1242                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1243                         HWRM_UNLOCK();
1244                         return rc;
1245                 default:
1246                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1247                         HWRM_UNLOCK();
1248                         return rc;
1249                 }
1250         }
1251
1252         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1253         HWRM_UNLOCK();
1254         return rc;
1255 }
1256
1257 int bnxt_hwrm_ring_free(struct bnxt *bp,
1258                         struct bnxt_ring *ring, uint32_t ring_type)
1259 {
1260         int rc;
1261         struct hwrm_ring_free_input req = {.req_type = 0 };
1262         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1263
1264         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1265
1266         req.ring_type = ring_type;
1267         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1268
1269         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1270
1271         if (rc || resp->error_code) {
1272                 if (rc == 0 && resp->error_code)
1273                         rc = rte_le_to_cpu_16(resp->error_code);
1274                 HWRM_UNLOCK();
1275
1276                 switch (ring_type) {
1277                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1278                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1279                                 rc);
1280                         return rc;
1281                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1282                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1283                                 rc);
1284                         return rc;
1285                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1286                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1287                                 rc);
1288                         return rc;
1289                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1290                         PMD_DRV_LOG(ERR,
1291                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1292                         return rc;
1293                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1294                         PMD_DRV_LOG(ERR,
1295                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1296                         return rc;
1297                 default:
1298                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1299                         return rc;
1300                 }
1301         }
1302         HWRM_UNLOCK();
1303         return 0;
1304 }
1305
1306 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1307 {
1308         int rc = 0;
1309         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1310         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1311
1312         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1313
1314         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1315         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1316         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1317         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1318
1319         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1320
1321         HWRM_CHECK_RESULT();
1322
1323         bp->grp_info[idx].fw_grp_id =
1324             rte_le_to_cpu_16(resp->ring_group_id);
1325
1326         HWRM_UNLOCK();
1327
1328         return rc;
1329 }
1330
1331 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1332 {
1333         int rc;
1334         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1335         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1336
1337         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1338
1339         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1340
1341         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1342
1343         HWRM_CHECK_RESULT();
1344         HWRM_UNLOCK();
1345
1346         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1347         return rc;
1348 }
1349
1350 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1351 {
1352         int rc = 0;
1353         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1354         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1355
1356         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1357                 return rc;
1358
1359         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1360
1361         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1362
1363         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1364
1365         HWRM_CHECK_RESULT();
1366         HWRM_UNLOCK();
1367
1368         return rc;
1369 }
1370
1371 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1372                                 unsigned int idx __rte_unused)
1373 {
1374         int rc;
1375         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1376         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1377
1378         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1379
1380         req.update_period_ms = rte_cpu_to_le_32(0);
1381
1382         req.stats_dma_addr =
1383             rte_cpu_to_le_64(cpr->hw_stats_map);
1384
1385         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1386
1387         HWRM_CHECK_RESULT();
1388
1389         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1390
1391         HWRM_UNLOCK();
1392
1393         return rc;
1394 }
1395
1396 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1397                                 unsigned int idx __rte_unused)
1398 {
1399         int rc;
1400         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1401         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1402
1403         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1404
1405         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1406
1407         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1408
1409         HWRM_CHECK_RESULT();
1410         HWRM_UNLOCK();
1411
1412         return rc;
1413 }
1414
1415 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1416 {
1417         int rc = 0, i, j;
1418         struct hwrm_vnic_alloc_input req = { 0 };
1419         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1420
1421         if (!BNXT_HAS_RING_GRPS(bp))
1422                 goto skip_ring_grps;
1423
1424         /* map ring groups to this vnic */
1425         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1426                 vnic->start_grp_id, vnic->end_grp_id);
1427         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1428                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1429
1430         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1431         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1432         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1433         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1434
1435 skip_ring_grps:
1436         vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1437                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1438         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1439
1440         if (vnic->func_default)
1441                 req.flags =
1442                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1443         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1444
1445         HWRM_CHECK_RESULT();
1446
1447         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1448         HWRM_UNLOCK();
1449         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1450         return rc;
1451 }
1452
1453 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1454                                         struct bnxt_vnic_info *vnic,
1455                                         struct bnxt_plcmodes_cfg *pmode)
1456 {
1457         int rc = 0;
1458         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1459         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1460
1461         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1462
1463         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1464
1465         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1466
1467         HWRM_CHECK_RESULT();
1468
1469         pmode->flags = rte_le_to_cpu_32(resp->flags);
1470         /* dflt_vnic bit doesn't exist in the _cfg command */
1471         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1472         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1473         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1474         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1475
1476         HWRM_UNLOCK();
1477
1478         return rc;
1479 }
1480
1481 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1482                                        struct bnxt_vnic_info *vnic,
1483                                        struct bnxt_plcmodes_cfg *pmode)
1484 {
1485         int rc = 0;
1486         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1487         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1488
1489         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1490
1491         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1492         req.flags = rte_cpu_to_le_32(pmode->flags);
1493         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1494         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1495         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1496         req.enables = rte_cpu_to_le_32(
1497             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1498             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1499             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1500         );
1501
1502         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1503
1504         HWRM_CHECK_RESULT();
1505         HWRM_UNLOCK();
1506
1507         return rc;
1508 }
1509
1510 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1511 {
1512         int rc = 0;
1513         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1514         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1515         uint32_t ctx_enable_flag = 0;
1516         struct bnxt_plcmodes_cfg pmodes;
1517         uint32_t enables = 0;
1518
1519         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1520                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1521                 return rc;
1522         }
1523
1524         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1525         if (rc)
1526                 return rc;
1527
1528         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1529
1530         if (BNXT_CHIP_THOR(bp)) {
1531                 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1532                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1533                 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1534
1535                 req.default_rx_ring_id =
1536                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1537                 req.default_cmpl_ring_id =
1538                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1539                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1540                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1541                 goto config_mru;
1542         }
1543
1544         /* Only RSS support for now TBD: COS & LB */
1545         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1546         if (vnic->lb_rule != 0xffff)
1547                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1548         if (vnic->cos_rule != 0xffff)
1549                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1550         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1551                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1552                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1553         }
1554         enables |= ctx_enable_flag;
1555         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1556         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1557         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1558         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1559
1560 config_mru:
1561         req.enables = rte_cpu_to_le_32(enables);
1562         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1563         req.mru = rte_cpu_to_le_16(vnic->mru);
1564         /* Configure default VNIC only once. */
1565         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1566                 req.flags |=
1567                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1568                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1569         }
1570         if (vnic->vlan_strip)
1571                 req.flags |=
1572                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1573         if (vnic->bd_stall)
1574                 req.flags |=
1575                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1576         if (vnic->roce_dual)
1577                 req.flags |= rte_cpu_to_le_32(
1578                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1579         if (vnic->roce_only)
1580                 req.flags |= rte_cpu_to_le_32(
1581                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1582         if (vnic->rss_dflt_cr)
1583                 req.flags |= rte_cpu_to_le_32(
1584                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1585
1586         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1587
1588         HWRM_CHECK_RESULT();
1589         HWRM_UNLOCK();
1590
1591         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1592
1593         return rc;
1594 }
1595
1596 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1597                 int16_t fw_vf_id)
1598 {
1599         int rc = 0;
1600         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1601         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1602
1603         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1604                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1605                 return rc;
1606         }
1607         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1608
1609         req.enables =
1610                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1611         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1612         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1613
1614         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1615
1616         HWRM_CHECK_RESULT();
1617
1618         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1619         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1620         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1621         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1622         vnic->mru = rte_le_to_cpu_16(resp->mru);
1623         vnic->func_default = rte_le_to_cpu_32(
1624                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1625         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1626                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1627         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1628                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1629         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1630                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1631         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1632                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1633         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1634                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1635
1636         HWRM_UNLOCK();
1637
1638         return rc;
1639 }
1640
1641 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1642 {
1643         int rc = 0;
1644         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1645         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1646                                                 bp->hwrm_cmd_resp_addr;
1647
1648         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1649
1650         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1651
1652         HWRM_CHECK_RESULT();
1653
1654         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1655         HWRM_UNLOCK();
1656         PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1657
1658         return rc;
1659 }
1660
1661 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1662 {
1663         int rc = 0;
1664         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1665         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1666                                                 bp->hwrm_cmd_resp_addr;
1667
1668         if (vnic->rss_rule == (uint16_t)HWRM_NA_SIGNATURE) {
1669                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1670                 return rc;
1671         }
1672         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1673
1674         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->rss_rule);
1675
1676         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1677
1678         HWRM_CHECK_RESULT();
1679         HWRM_UNLOCK();
1680
1681         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1682
1683         return rc;
1684 }
1685
1686 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1687 {
1688         int rc = 0;
1689         struct hwrm_vnic_free_input req = {.req_type = 0 };
1690         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1691
1692         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1693                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1694                 return rc;
1695         }
1696
1697         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1698
1699         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1700
1701         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1702
1703         HWRM_CHECK_RESULT();
1704         HWRM_UNLOCK();
1705
1706         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1707         /* Configure default VNIC again if necessary. */
1708         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1709                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1710
1711         return rc;
1712 }
1713
1714 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1715                            struct bnxt_vnic_info *vnic)
1716 {
1717         int rc = 0;
1718         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1719         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1720
1721         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1722
1723         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1724         req.hash_mode_flags = vnic->hash_mode;
1725
1726         req.ring_grp_tbl_addr =
1727             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1728         req.hash_key_tbl_addr =
1729             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1730         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1731         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1732
1733         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1734
1735         HWRM_CHECK_RESULT();
1736         HWRM_UNLOCK();
1737
1738         return rc;
1739 }
1740
1741 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1742                         struct bnxt_vnic_info *vnic)
1743 {
1744         int rc = 0;
1745         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1746         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1747         uint16_t size;
1748
1749         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1750                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1751                 return rc;
1752         }
1753
1754         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1755
1756         req.flags = rte_cpu_to_le_32(
1757                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1758
1759         req.enables = rte_cpu_to_le_32(
1760                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1761
1762         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1763         size -= RTE_PKTMBUF_HEADROOM;
1764
1765         req.jumbo_thresh = rte_cpu_to_le_16(size);
1766         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1767
1768         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1769
1770         HWRM_CHECK_RESULT();
1771         HWRM_UNLOCK();
1772
1773         return rc;
1774 }
1775
1776 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1777                         struct bnxt_vnic_info *vnic, bool enable)
1778 {
1779         int rc = 0;
1780         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1781         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1782
1783         if (BNXT_CHIP_THOR(bp))
1784                 return 0;
1785
1786         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1787
1788         if (enable) {
1789                 req.enables = rte_cpu_to_le_32(
1790                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1791                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1792                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1793                 req.flags = rte_cpu_to_le_32(
1794                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1795                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1796                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1797                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1798                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1799                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1800                 req.max_agg_segs = rte_cpu_to_le_16(5);
1801                 req.max_aggs =
1802                         rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1803                 req.min_agg_len = rte_cpu_to_le_32(512);
1804         }
1805         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1806
1807         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1808
1809         HWRM_CHECK_RESULT();
1810         HWRM_UNLOCK();
1811
1812         return rc;
1813 }
1814
1815 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1816 {
1817         struct hwrm_func_cfg_input req = {0};
1818         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1819         int rc;
1820
1821         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1822         req.enables = rte_cpu_to_le_32(
1823                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1824         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1825         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1826
1827         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1828
1829         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1830         HWRM_CHECK_RESULT();
1831         HWRM_UNLOCK();
1832
1833         bp->pf.vf_info[vf].random_mac = false;
1834
1835         return rc;
1836 }
1837
1838 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1839                                   uint64_t *dropped)
1840 {
1841         int rc = 0;
1842         struct hwrm_func_qstats_input req = {.req_type = 0};
1843         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1844
1845         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1846
1847         req.fid = rte_cpu_to_le_16(fid);
1848
1849         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1850
1851         HWRM_CHECK_RESULT();
1852
1853         if (dropped)
1854                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1855
1856         HWRM_UNLOCK();
1857
1858         return rc;
1859 }
1860
1861 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1862                           struct rte_eth_stats *stats)
1863 {
1864         int rc = 0;
1865         struct hwrm_func_qstats_input req = {.req_type = 0};
1866         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1867
1868         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1869
1870         req.fid = rte_cpu_to_le_16(fid);
1871
1872         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1873
1874         HWRM_CHECK_RESULT();
1875
1876         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1877         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1878         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1879         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1880         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1881         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1882
1883         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1884         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1885         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1886         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1887         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1888         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1889
1890         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
1891         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
1892         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
1893
1894         HWRM_UNLOCK();
1895
1896         return rc;
1897 }
1898
1899 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1900 {
1901         int rc = 0;
1902         struct hwrm_func_clr_stats_input req = {.req_type = 0};
1903         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1904
1905         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
1906
1907         req.fid = rte_cpu_to_le_16(fid);
1908
1909         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1910
1911         HWRM_CHECK_RESULT();
1912         HWRM_UNLOCK();
1913
1914         return rc;
1915 }
1916
1917 /*
1918  * HWRM utility functions
1919  */
1920
1921 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1922 {
1923         unsigned int i;
1924         int rc = 0;
1925
1926         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1927                 struct bnxt_tx_queue *txq;
1928                 struct bnxt_rx_queue *rxq;
1929                 struct bnxt_cp_ring_info *cpr;
1930
1931                 if (i >= bp->rx_cp_nr_rings) {
1932                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1933                         cpr = txq->cp_ring;
1934                 } else {
1935                         rxq = bp->rx_queues[i];
1936                         cpr = rxq->cp_ring;
1937                 }
1938
1939                 rc = bnxt_hwrm_stat_clear(bp, cpr);
1940                 if (rc)
1941                         return rc;
1942         }
1943         return 0;
1944 }
1945
1946 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1947 {
1948         int rc;
1949         unsigned int i;
1950         struct bnxt_cp_ring_info *cpr;
1951
1952         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1953
1954                 if (i >= bp->rx_cp_nr_rings) {
1955                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
1956                 } else {
1957                         cpr = bp->rx_queues[i]->cp_ring;
1958                         bp->grp_info[i].fw_stats_ctx = -1;
1959                 }
1960                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
1961                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
1962                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1963                         if (rc)
1964                                 return rc;
1965                 }
1966         }
1967         return 0;
1968 }
1969
1970 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
1971 {
1972         unsigned int i;
1973         int rc = 0;
1974
1975         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1976                 struct bnxt_tx_queue *txq;
1977                 struct bnxt_rx_queue *rxq;
1978                 struct bnxt_cp_ring_info *cpr;
1979
1980                 if (i >= bp->rx_cp_nr_rings) {
1981                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1982                         cpr = txq->cp_ring;
1983                 } else {
1984                         rxq = bp->rx_queues[i];
1985                         cpr = rxq->cp_ring;
1986                 }
1987
1988                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
1989
1990                 if (rc)
1991                         return rc;
1992         }
1993         return rc;
1994 }
1995
1996 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
1997 {
1998         uint16_t idx;
1999         uint32_t rc = 0;
2000
2001         if (!BNXT_HAS_RING_GRPS(bp))
2002                 return 0;
2003
2004         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2005
2006                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2007                         continue;
2008
2009                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2010
2011                 if (rc)
2012                         return rc;
2013         }
2014         return rc;
2015 }
2016
2017 static void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2018 {
2019         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2020
2021         bnxt_hwrm_ring_free(bp, cp_ring,
2022                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2023         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2024         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2025                                      sizeof(*cpr->cp_desc_ring));
2026         cpr->cp_raw_cons = 0;
2027 }
2028
2029 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2030 {
2031         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2032
2033         bnxt_hwrm_ring_free(bp, cp_ring,
2034                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2035         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2036         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2037                         sizeof(*cpr->cp_desc_ring));
2038         cpr->cp_raw_cons = 0;
2039 }
2040
2041 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2042 {
2043         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2044         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2045         struct bnxt_ring *ring = rxr->rx_ring_struct;
2046         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2047
2048         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2049                 bnxt_hwrm_ring_free(bp, ring,
2050                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2051                 ring->fw_ring_id = INVALID_HW_RING_ID;
2052                 bp->grp_info[queue_index].rx_fw_ring_id = INVALID_HW_RING_ID;
2053                 memset(rxr->rx_desc_ring, 0,
2054                        rxr->rx_ring_struct->ring_size *
2055                        sizeof(*rxr->rx_desc_ring));
2056                 memset(rxr->rx_buf_ring, 0,
2057                        rxr->rx_ring_struct->ring_size *
2058                        sizeof(*rxr->rx_buf_ring));
2059                 rxr->rx_prod = 0;
2060         }
2061         ring = rxr->ag_ring_struct;
2062         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2063                 bnxt_hwrm_ring_free(bp, ring,
2064                                     BNXT_CHIP_THOR(bp) ?
2065                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2066                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2067                 ring->fw_ring_id = INVALID_HW_RING_ID;
2068                 memset(rxr->ag_buf_ring, 0,
2069                        rxr->ag_ring_struct->ring_size *
2070                        sizeof(*rxr->ag_buf_ring));
2071                 rxr->ag_prod = 0;
2072                 bp->grp_info[queue_index].ag_fw_ring_id = INVALID_HW_RING_ID;
2073         }
2074         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2075                 bnxt_free_cp_ring(bp, cpr);
2076                 if (rxq->nq_ring)
2077                         bnxt_free_nq_ring(bp, rxq->nq_ring);
2078         }
2079
2080         bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2081 }
2082
2083 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2084 {
2085         unsigned int i;
2086
2087         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2088                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2089                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2090                 struct bnxt_ring *ring = txr->tx_ring_struct;
2091                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2092
2093                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2094                         bnxt_hwrm_ring_free(bp, ring,
2095                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2096                         ring->fw_ring_id = INVALID_HW_RING_ID;
2097                         memset(txr->tx_desc_ring, 0,
2098                                         txr->tx_ring_struct->ring_size *
2099                                         sizeof(*txr->tx_desc_ring));
2100                         memset(txr->tx_buf_ring, 0,
2101                                         txr->tx_ring_struct->ring_size *
2102                                         sizeof(*txr->tx_buf_ring));
2103                         txr->tx_prod = 0;
2104                         txr->tx_cons = 0;
2105                 }
2106                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2107                         bnxt_free_cp_ring(bp, cpr);
2108                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2109                         if (txq->nq_ring)
2110                                 bnxt_free_nq_ring(bp, txq->nq_ring);
2111                 }
2112         }
2113
2114         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2115                 bnxt_free_hwrm_rx_ring(bp, i);
2116
2117         return 0;
2118 }
2119
2120 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2121 {
2122         uint16_t i;
2123         uint32_t rc = 0;
2124
2125         if (!BNXT_HAS_RING_GRPS(bp))
2126                 return 0;
2127
2128         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2129                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2130                 if (rc)
2131                         return rc;
2132         }
2133         return rc;
2134 }
2135
2136 void bnxt_free_hwrm_resources(struct bnxt *bp)
2137 {
2138         /* Release memzone */
2139         rte_free(bp->hwrm_cmd_resp_addr);
2140         rte_free(bp->hwrm_short_cmd_req_addr);
2141         bp->hwrm_cmd_resp_addr = NULL;
2142         bp->hwrm_short_cmd_req_addr = NULL;
2143         bp->hwrm_cmd_resp_dma_addr = 0;
2144         bp->hwrm_short_cmd_req_dma_addr = 0;
2145 }
2146
2147 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2148 {
2149         struct rte_pci_device *pdev = bp->pdev;
2150         char type[RTE_MEMZONE_NAMESIZE];
2151
2152         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2153                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2154         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2155         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2156         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2157         if (bp->hwrm_cmd_resp_addr == NULL)
2158                 return -ENOMEM;
2159         bp->hwrm_cmd_resp_dma_addr =
2160                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2161         if (bp->hwrm_cmd_resp_dma_addr == 0) {
2162                 PMD_DRV_LOG(ERR,
2163                         "unable to map response address to physical memory\n");
2164                 return -ENOMEM;
2165         }
2166         rte_spinlock_init(&bp->hwrm_lock);
2167
2168         return 0;
2169 }
2170
2171 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2172 {
2173         struct bnxt_filter_info *filter;
2174         int rc = 0;
2175
2176         STAILQ_FOREACH(filter, &vnic->filter, next) {
2177                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2178                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2179                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2180                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2181                 else
2182                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2183                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2184                 //if (rc)
2185                         //break;
2186         }
2187         return rc;
2188 }
2189
2190 static int
2191 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2192 {
2193         struct bnxt_filter_info *filter;
2194         struct rte_flow *flow;
2195         int rc = 0;
2196
2197         STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2198                 filter = flow->filter;
2199                 PMD_DRV_LOG(ERR, "filter type %d\n", filter->filter_type);
2200                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2201                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2202                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2203                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2204                 else
2205                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2206
2207                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2208                 rte_free(flow);
2209                 //if (rc)
2210                         //break;
2211         }
2212         return rc;
2213 }
2214
2215 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2216 {
2217         struct bnxt_filter_info *filter;
2218         int rc = 0;
2219
2220         STAILQ_FOREACH(filter, &vnic->filter, next) {
2221                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2222                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2223                                                      filter);
2224                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2225                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2226                                                          filter);
2227                 else
2228                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2229                                                      filter);
2230                 if (rc)
2231                         break;
2232         }
2233         return rc;
2234 }
2235
2236 void bnxt_free_tunnel_ports(struct bnxt *bp)
2237 {
2238         if (bp->vxlan_port_cnt)
2239                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2240                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2241         bp->vxlan_port = 0;
2242         if (bp->geneve_port_cnt)
2243                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2244                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2245         bp->geneve_port = 0;
2246 }
2247
2248 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2249 {
2250         int i;
2251
2252         if (bp->vnic_info == NULL)
2253                 return;
2254
2255         /*
2256          * Cleanup VNICs in reverse order, to make sure the L2 filter
2257          * from vnic0 is last to be cleaned up.
2258          */
2259         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2260                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2261
2262                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2263
2264                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2265
2266                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2267
2268                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2269
2270                 bnxt_hwrm_vnic_free(bp, vnic);
2271
2272                 rte_free(vnic->fw_grp_ids);
2273         }
2274         /* Ring resources */
2275         bnxt_free_all_hwrm_rings(bp);
2276         bnxt_free_all_hwrm_ring_grps(bp);
2277         bnxt_free_all_hwrm_stat_ctxs(bp);
2278         bnxt_free_tunnel_ports(bp);
2279 }
2280
2281 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2282 {
2283         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2284
2285         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2286                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2287
2288         switch (conf_link_speed) {
2289         case ETH_LINK_SPEED_10M_HD:
2290         case ETH_LINK_SPEED_100M_HD:
2291                 /* FALLTHROUGH */
2292                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2293         }
2294         return hw_link_duplex;
2295 }
2296
2297 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2298 {
2299         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2300 }
2301
2302 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2303 {
2304         uint16_t eth_link_speed = 0;
2305
2306         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2307                 return ETH_LINK_SPEED_AUTONEG;
2308
2309         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2310         case ETH_LINK_SPEED_100M:
2311         case ETH_LINK_SPEED_100M_HD:
2312                 /* FALLTHROUGH */
2313                 eth_link_speed =
2314                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2315                 break;
2316         case ETH_LINK_SPEED_1G:
2317                 eth_link_speed =
2318                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2319                 break;
2320         case ETH_LINK_SPEED_2_5G:
2321                 eth_link_speed =
2322                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2323                 break;
2324         case ETH_LINK_SPEED_10G:
2325                 eth_link_speed =
2326                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2327                 break;
2328         case ETH_LINK_SPEED_20G:
2329                 eth_link_speed =
2330                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2331                 break;
2332         case ETH_LINK_SPEED_25G:
2333                 eth_link_speed =
2334                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2335                 break;
2336         case ETH_LINK_SPEED_40G:
2337                 eth_link_speed =
2338                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2339                 break;
2340         case ETH_LINK_SPEED_50G:
2341                 eth_link_speed =
2342                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2343                 break;
2344         case ETH_LINK_SPEED_100G:
2345                 eth_link_speed =
2346                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2347                 break;
2348         default:
2349                 PMD_DRV_LOG(ERR,
2350                         "Unsupported link speed %d; default to AUTO\n",
2351                         conf_link_speed);
2352                 break;
2353         }
2354         return eth_link_speed;
2355 }
2356
2357 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2358                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2359                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2360                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2361
2362 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2363 {
2364         uint32_t one_speed;
2365
2366         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2367                 return 0;
2368
2369         if (link_speed & ETH_LINK_SPEED_FIXED) {
2370                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2371
2372                 if (one_speed & (one_speed - 1)) {
2373                         PMD_DRV_LOG(ERR,
2374                                 "Invalid advertised speeds (%u) for port %u\n",
2375                                 link_speed, port_id);
2376                         return -EINVAL;
2377                 }
2378                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2379                         PMD_DRV_LOG(ERR,
2380                                 "Unsupported advertised speed (%u) for port %u\n",
2381                                 link_speed, port_id);
2382                         return -EINVAL;
2383                 }
2384         } else {
2385                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2386                         PMD_DRV_LOG(ERR,
2387                                 "Unsupported advertised speeds (%u) for port %u\n",
2388                                 link_speed, port_id);
2389                         return -EINVAL;
2390                 }
2391         }
2392         return 0;
2393 }
2394
2395 static uint16_t
2396 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2397 {
2398         uint16_t ret = 0;
2399
2400         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2401                 if (bp->link_info.support_speeds)
2402                         return bp->link_info.support_speeds;
2403                 link_speed = BNXT_SUPPORTED_SPEEDS;
2404         }
2405
2406         if (link_speed & ETH_LINK_SPEED_100M)
2407                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2408         if (link_speed & ETH_LINK_SPEED_100M_HD)
2409                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2410         if (link_speed & ETH_LINK_SPEED_1G)
2411                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2412         if (link_speed & ETH_LINK_SPEED_2_5G)
2413                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2414         if (link_speed & ETH_LINK_SPEED_10G)
2415                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2416         if (link_speed & ETH_LINK_SPEED_20G)
2417                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2418         if (link_speed & ETH_LINK_SPEED_25G)
2419                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2420         if (link_speed & ETH_LINK_SPEED_40G)
2421                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2422         if (link_speed & ETH_LINK_SPEED_50G)
2423                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2424         if (link_speed & ETH_LINK_SPEED_100G)
2425                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2426         return ret;
2427 }
2428
2429 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2430 {
2431         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2432
2433         switch (hw_link_speed) {
2434         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2435                 eth_link_speed = ETH_SPEED_NUM_100M;
2436                 break;
2437         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2438                 eth_link_speed = ETH_SPEED_NUM_1G;
2439                 break;
2440         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2441                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2442                 break;
2443         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2444                 eth_link_speed = ETH_SPEED_NUM_10G;
2445                 break;
2446         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2447                 eth_link_speed = ETH_SPEED_NUM_20G;
2448                 break;
2449         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2450                 eth_link_speed = ETH_SPEED_NUM_25G;
2451                 break;
2452         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2453                 eth_link_speed = ETH_SPEED_NUM_40G;
2454                 break;
2455         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2456                 eth_link_speed = ETH_SPEED_NUM_50G;
2457                 break;
2458         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2459                 eth_link_speed = ETH_SPEED_NUM_100G;
2460                 break;
2461         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2462         default:
2463                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2464                         hw_link_speed);
2465                 break;
2466         }
2467         return eth_link_speed;
2468 }
2469
2470 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2471 {
2472         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2473
2474         switch (hw_link_duplex) {
2475         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2476         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2477                 /* FALLTHROUGH */
2478                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2479                 break;
2480         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2481                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2482                 break;
2483         default:
2484                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2485                         hw_link_duplex);
2486                 break;
2487         }
2488         return eth_link_duplex;
2489 }
2490
2491 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2492 {
2493         int rc = 0;
2494         struct bnxt_link_info *link_info = &bp->link_info;
2495
2496         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2497         if (rc) {
2498                 PMD_DRV_LOG(ERR,
2499                         "Get link config failed with rc %d\n", rc);
2500                 goto exit;
2501         }
2502         if (link_info->link_speed)
2503                 link->link_speed =
2504                         bnxt_parse_hw_link_speed(link_info->link_speed);
2505         else
2506                 link->link_speed = ETH_SPEED_NUM_NONE;
2507         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2508         link->link_status = link_info->link_up;
2509         link->link_autoneg = link_info->auto_mode ==
2510                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2511                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2512 exit:
2513         return rc;
2514 }
2515
2516 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2517 {
2518         int rc = 0;
2519         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2520         struct bnxt_link_info link_req;
2521         uint16_t speed, autoneg;
2522
2523         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2524                 return 0;
2525
2526         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2527                         bp->eth_dev->data->port_id);
2528         if (rc)
2529                 goto error;
2530
2531         memset(&link_req, 0, sizeof(link_req));
2532         link_req.link_up = link_up;
2533         if (!link_up)
2534                 goto port_phy_cfg;
2535
2536         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2537         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2538         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2539         /* Autoneg can be done only when the FW allows */
2540         if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2541                                 bp->link_info.force_link_speed)) {
2542                 link_req.phy_flags |=
2543                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2544                 link_req.auto_link_speed_mask =
2545                         bnxt_parse_eth_link_speed_mask(bp,
2546                                                        dev_conf->link_speeds);
2547         } else {
2548                 if (bp->link_info.phy_type ==
2549                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2550                     bp->link_info.phy_type ==
2551                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2552                     bp->link_info.media_type ==
2553                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2554                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2555                         return -EINVAL;
2556                 }
2557
2558                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2559                 /* If user wants a particular speed try that first. */
2560                 if (speed)
2561                         link_req.link_speed = speed;
2562                 else if (bp->link_info.force_link_speed)
2563                         link_req.link_speed = bp->link_info.force_link_speed;
2564                 else
2565                         link_req.link_speed = bp->link_info.auto_link_speed;
2566         }
2567         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2568         link_req.auto_pause = bp->link_info.auto_pause;
2569         link_req.force_pause = bp->link_info.force_pause;
2570
2571 port_phy_cfg:
2572         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2573         if (rc) {
2574                 PMD_DRV_LOG(ERR,
2575                         "Set link config failed with rc %d\n", rc);
2576         }
2577
2578 error:
2579         return rc;
2580 }
2581
2582 /* JIRA 22088 */
2583 int bnxt_hwrm_func_qcfg(struct bnxt *bp)
2584 {
2585         struct hwrm_func_qcfg_input req = {0};
2586         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2587         uint16_t flags;
2588         int rc = 0;
2589
2590         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2591         req.fid = rte_cpu_to_le_16(0xffff);
2592
2593         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2594
2595         HWRM_CHECK_RESULT();
2596
2597         /* Hard Coded.. 0xfff VLAN ID mask */
2598         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2599         flags = rte_le_to_cpu_16(resp->flags);
2600         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2601                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2602
2603         if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2604                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2605                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2606         }
2607
2608         switch (resp->port_partition_type) {
2609         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2610         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2611         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2612                 /* FALLTHROUGH */
2613                 bp->port_partition_type = resp->port_partition_type;
2614                 break;
2615         default:
2616                 bp->port_partition_type = 0;
2617                 break;
2618         }
2619
2620         HWRM_UNLOCK();
2621
2622         return rc;
2623 }
2624
2625 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2626                                    struct hwrm_func_qcaps_output *qcaps)
2627 {
2628         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2629         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2630                sizeof(qcaps->mac_address));
2631         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2632         qcaps->max_rx_rings = fcfg->num_rx_rings;
2633         qcaps->max_tx_rings = fcfg->num_tx_rings;
2634         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2635         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2636         qcaps->max_vfs = 0;
2637         qcaps->first_vf_id = 0;
2638         qcaps->max_vnics = fcfg->num_vnics;
2639         qcaps->max_decap_records = 0;
2640         qcaps->max_encap_records = 0;
2641         qcaps->max_tx_wm_flows = 0;
2642         qcaps->max_tx_em_flows = 0;
2643         qcaps->max_rx_wm_flows = 0;
2644         qcaps->max_rx_em_flows = 0;
2645         qcaps->max_flow_id = 0;
2646         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2647         qcaps->max_sp_tx_rings = 0;
2648         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2649 }
2650
2651 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2652 {
2653         struct hwrm_func_cfg_input req = {0};
2654         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2655         uint32_t enables;
2656         int rc;
2657
2658         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2659                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2660                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2661                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2662                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2663                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2664                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2665                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2666                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2667
2668         if (BNXT_HAS_RING_GRPS(bp)) {
2669                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2670                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2671         } else if (BNXT_HAS_NQ(bp)) {
2672                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2673                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2674         }
2675
2676         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2677         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2678         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2679                                    RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2680                                    BNXT_NUM_VLANS);
2681         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2682         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2683         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2684         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2685         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2686         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2687         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2688         req.fid = rte_cpu_to_le_16(0xffff);
2689         req.enables = rte_cpu_to_le_32(enables);
2690
2691         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2692
2693         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2694
2695         HWRM_CHECK_RESULT();
2696         HWRM_UNLOCK();
2697
2698         return rc;
2699 }
2700
2701 static void populate_vf_func_cfg_req(struct bnxt *bp,
2702                                      struct hwrm_func_cfg_input *req,
2703                                      int num_vfs)
2704 {
2705         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2706                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2707                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2708                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2709                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2710                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2711                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2712                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2713                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2714                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2715
2716         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2717                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2718                                     BNXT_NUM_VLANS);
2719         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2720                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2721                                     BNXT_NUM_VLANS);
2722         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2723                                                 (num_vfs + 1));
2724         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2725         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2726                                                (num_vfs + 1));
2727         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2728         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2729         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2730         /* TODO: For now, do not support VMDq/RFS on VFs. */
2731         req->num_vnics = rte_cpu_to_le_16(1);
2732         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2733                                                  (num_vfs + 1));
2734 }
2735
2736 static void add_random_mac_if_needed(struct bnxt *bp,
2737                                      struct hwrm_func_cfg_input *cfg_req,
2738                                      int vf)
2739 {
2740         struct rte_ether_addr mac;
2741
2742         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2743                 return;
2744
2745         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2746                 cfg_req->enables |=
2747                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2748                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2749                 bp->pf.vf_info[vf].random_mac = true;
2750         } else {
2751                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2752                         RTE_ETHER_ADDR_LEN);
2753         }
2754 }
2755
2756 static void reserve_resources_from_vf(struct bnxt *bp,
2757                                       struct hwrm_func_cfg_input *cfg_req,
2758                                       int vf)
2759 {
2760         struct hwrm_func_qcaps_input req = {0};
2761         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2762         int rc;
2763
2764         /* Get the actual allocated values now */
2765         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2766         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2767         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2768
2769         if (rc) {
2770                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2771                 copy_func_cfg_to_qcaps(cfg_req, resp);
2772         } else if (resp->error_code) {
2773                 rc = rte_le_to_cpu_16(resp->error_code);
2774                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2775                 copy_func_cfg_to_qcaps(cfg_req, resp);
2776         }
2777
2778         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2779         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2780         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2781         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2782         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2783         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2784         /*
2785          * TODO: While not supporting VMDq with VFs, max_vnics is always
2786          * forced to 1 in this case
2787          */
2788         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2789         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2790
2791         HWRM_UNLOCK();
2792 }
2793
2794 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2795 {
2796         struct hwrm_func_qcfg_input req = {0};
2797         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2798         int rc;
2799
2800         /* Check for zero MAC address */
2801         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2802         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2803         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2804         if (rc) {
2805                 PMD_DRV_LOG(ERR, "hwrm_func_qcfg failed rc:%d\n", rc);
2806                 return -1;
2807         } else if (resp->error_code) {
2808                 rc = rte_le_to_cpu_16(resp->error_code);
2809                 PMD_DRV_LOG(ERR, "hwrm_func_qcfg error %d\n", rc);
2810                 return -1;
2811         }
2812         rc = rte_le_to_cpu_16(resp->vlan);
2813
2814         HWRM_UNLOCK();
2815
2816         return rc;
2817 }
2818
2819 static int update_pf_resource_max(struct bnxt *bp)
2820 {
2821         struct hwrm_func_qcfg_input req = {0};
2822         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2823         int rc;
2824
2825         /* And copy the allocated numbers into the pf struct */
2826         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2827         req.fid = rte_cpu_to_le_16(0xffff);
2828         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2829         HWRM_CHECK_RESULT();
2830
2831         /* Only TX ring value reflects actual allocation? TODO */
2832         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2833         bp->pf.evb_mode = resp->evb_mode;
2834
2835         HWRM_UNLOCK();
2836
2837         return rc;
2838 }
2839
2840 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2841 {
2842         int rc;
2843
2844         if (!BNXT_PF(bp)) {
2845                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2846                 return -1;
2847         }
2848
2849         rc = bnxt_hwrm_func_qcaps(bp);
2850         if (rc)
2851                 return rc;
2852
2853         bp->pf.func_cfg_flags &=
2854                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2855                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2856         bp->pf.func_cfg_flags |=
2857                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2858         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2859         rc = __bnxt_hwrm_func_qcaps(bp);
2860         return rc;
2861 }
2862
2863 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2864 {
2865         struct hwrm_func_cfg_input req = {0};
2866         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2867         int i;
2868         size_t sz;
2869         int rc = 0;
2870         size_t req_buf_sz;
2871
2872         if (!BNXT_PF(bp)) {
2873                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2874                 return -1;
2875         }
2876
2877         rc = bnxt_hwrm_func_qcaps(bp);
2878
2879         if (rc)
2880                 return rc;
2881
2882         bp->pf.active_vfs = num_vfs;
2883
2884         /*
2885          * First, configure the PF to only use one TX ring.  This ensures that
2886          * there are enough rings for all VFs.
2887          *
2888          * If we don't do this, when we call func_alloc() later, we will lock
2889          * extra rings to the PF that won't be available during func_cfg() of
2890          * the VFs.
2891          *
2892          * This has been fixed with firmware versions above 20.6.54
2893          */
2894         bp->pf.func_cfg_flags &=
2895                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2896                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2897         bp->pf.func_cfg_flags |=
2898                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2899         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2900         if (rc)
2901                 return rc;
2902
2903         /*
2904          * Now, create and register a buffer to hold forwarded VF requests
2905          */
2906         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2907         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2908                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2909         if (bp->pf.vf_req_buf == NULL) {
2910                 rc = -ENOMEM;
2911                 goto error_free;
2912         }
2913         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2914                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2915         for (i = 0; i < num_vfs; i++)
2916                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2917                                         (i * HWRM_MAX_REQ_LEN);
2918
2919         rc = bnxt_hwrm_func_buf_rgtr(bp);
2920         if (rc)
2921                 goto error_free;
2922
2923         populate_vf_func_cfg_req(bp, &req, num_vfs);
2924
2925         bp->pf.active_vfs = 0;
2926         for (i = 0; i < num_vfs; i++) {
2927                 add_random_mac_if_needed(bp, &req, i);
2928
2929                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2930                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2931                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
2932                 rc = bnxt_hwrm_send_message(bp,
2933                                             &req,
2934                                             sizeof(req),
2935                                             BNXT_USE_CHIMP_MB);
2936
2937                 /* Clear enable flag for next pass */
2938                 req.enables &= ~rte_cpu_to_le_32(
2939                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2940
2941                 if (rc || resp->error_code) {
2942                         PMD_DRV_LOG(ERR,
2943                                 "Failed to initizlie VF %d\n", i);
2944                         PMD_DRV_LOG(ERR,
2945                                 "Not all VFs available. (%d, %d)\n",
2946                                 rc, resp->error_code);
2947                         HWRM_UNLOCK();
2948                         break;
2949                 }
2950
2951                 HWRM_UNLOCK();
2952
2953                 reserve_resources_from_vf(bp, &req, i);
2954                 bp->pf.active_vfs++;
2955                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
2956         }
2957
2958         /*
2959          * Now configure the PF to use "the rest" of the resources
2960          * We're using STD_TX_RING_MODE here though which will limit the TX
2961          * rings.  This will allow QoS to function properly.  Not setting this
2962          * will cause PF rings to break bandwidth settings.
2963          */
2964         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2965         if (rc)
2966                 goto error_free;
2967
2968         rc = update_pf_resource_max(bp);
2969         if (rc)
2970                 goto error_free;
2971
2972         return rc;
2973
2974 error_free:
2975         bnxt_hwrm_func_buf_unrgtr(bp);
2976         return rc;
2977 }
2978
2979 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
2980 {
2981         struct hwrm_func_cfg_input req = {0};
2982         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2983         int rc;
2984
2985         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2986
2987         req.fid = rte_cpu_to_le_16(0xffff);
2988         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
2989         req.evb_mode = bp->pf.evb_mode;
2990
2991         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2992         HWRM_CHECK_RESULT();
2993         HWRM_UNLOCK();
2994
2995         return rc;
2996 }
2997
2998 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
2999                                 uint8_t tunnel_type)
3000 {
3001         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3002         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3003         int rc = 0;
3004
3005         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3006         req.tunnel_type = tunnel_type;
3007         req.tunnel_dst_port_val = port;
3008         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3009         HWRM_CHECK_RESULT();
3010
3011         switch (tunnel_type) {
3012         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3013                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3014                 bp->vxlan_port = port;
3015                 break;
3016         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3017                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3018                 bp->geneve_port = port;
3019                 break;
3020         default:
3021                 break;
3022         }
3023
3024         HWRM_UNLOCK();
3025
3026         return rc;
3027 }
3028
3029 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3030                                 uint8_t tunnel_type)
3031 {
3032         struct hwrm_tunnel_dst_port_free_input req = {0};
3033         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3034         int rc = 0;
3035
3036         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3037
3038         req.tunnel_type = tunnel_type;
3039         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3040         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3041
3042         HWRM_CHECK_RESULT();
3043         HWRM_UNLOCK();
3044
3045         return rc;
3046 }
3047
3048 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3049                                         uint32_t flags)
3050 {
3051         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3052         struct hwrm_func_cfg_input req = {0};
3053         int rc;
3054
3055         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3056
3057         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3058         req.flags = rte_cpu_to_le_32(flags);
3059         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3060
3061         HWRM_CHECK_RESULT();
3062         HWRM_UNLOCK();
3063
3064         return rc;
3065 }
3066
3067 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3068 {
3069         uint32_t *flag = flagp;
3070
3071         vnic->flags = *flag;
3072 }
3073
3074 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3075 {
3076         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3077 }
3078
3079 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3080 {
3081         int rc = 0;
3082         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3083         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3084
3085         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3086
3087         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3088         req.req_buf_page_size = rte_cpu_to_le_16(
3089                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3090         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3091         req.req_buf_page_addr0 =
3092                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3093         if (req.req_buf_page_addr0 == 0) {
3094                 PMD_DRV_LOG(ERR,
3095                         "unable to map buffer address to physical memory\n");
3096                 return -ENOMEM;
3097         }
3098
3099         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3100
3101         HWRM_CHECK_RESULT();
3102         HWRM_UNLOCK();
3103
3104         return rc;
3105 }
3106
3107 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3108 {
3109         int rc = 0;
3110         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3111         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3112
3113         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3114
3115         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3116
3117         HWRM_CHECK_RESULT();
3118         HWRM_UNLOCK();
3119
3120         return rc;
3121 }
3122
3123 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3124 {
3125         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3126         struct hwrm_func_cfg_input req = {0};
3127         int rc;
3128
3129         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3130
3131         req.fid = rte_cpu_to_le_16(0xffff);
3132         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3133         req.enables = rte_cpu_to_le_32(
3134                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3135         req.async_event_cr = rte_cpu_to_le_16(
3136                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
3137         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3138
3139         HWRM_CHECK_RESULT();
3140         HWRM_UNLOCK();
3141
3142         return rc;
3143 }
3144
3145 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3146 {
3147         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3148         struct hwrm_func_vf_cfg_input req = {0};
3149         int rc;
3150
3151         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3152
3153         req.enables = rte_cpu_to_le_32(
3154                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3155         req.async_event_cr = rte_cpu_to_le_16(
3156                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
3157         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3158
3159         HWRM_CHECK_RESULT();
3160         HWRM_UNLOCK();
3161
3162         return rc;
3163 }
3164
3165 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3166 {
3167         struct hwrm_func_cfg_input req = {0};
3168         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3169         uint16_t dflt_vlan, fid;
3170         uint32_t func_cfg_flags;
3171         int rc = 0;
3172
3173         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3174
3175         if (is_vf) {
3176                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3177                 fid = bp->pf.vf_info[vf].fid;
3178                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3179         } else {
3180                 fid = rte_cpu_to_le_16(0xffff);
3181                 func_cfg_flags = bp->pf.func_cfg_flags;
3182                 dflt_vlan = bp->vlan;
3183         }
3184
3185         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3186         req.fid = rte_cpu_to_le_16(fid);
3187         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3188         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3189
3190         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3191
3192         HWRM_CHECK_RESULT();
3193         HWRM_UNLOCK();
3194
3195         return rc;
3196 }
3197
3198 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3199                         uint16_t max_bw, uint16_t enables)
3200 {
3201         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3202         struct hwrm_func_cfg_input req = {0};
3203         int rc;
3204
3205         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3206
3207         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3208         req.enables |= rte_cpu_to_le_32(enables);
3209         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3210         req.max_bw = rte_cpu_to_le_32(max_bw);
3211         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3212
3213         HWRM_CHECK_RESULT();
3214         HWRM_UNLOCK();
3215
3216         return rc;
3217 }
3218
3219 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3220 {
3221         struct hwrm_func_cfg_input req = {0};
3222         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3223         int rc = 0;
3224
3225         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3226
3227         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3228         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3229         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3230         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3231
3232         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3233
3234         HWRM_CHECK_RESULT();
3235         HWRM_UNLOCK();
3236
3237         return rc;
3238 }
3239
3240 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3241 {
3242         int rc;
3243
3244         if (BNXT_PF(bp))
3245                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3246         else
3247                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3248
3249         return rc;
3250 }
3251
3252 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3253                               void *encaped, size_t ec_size)
3254 {
3255         int rc = 0;
3256         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3257         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3258
3259         if (ec_size > sizeof(req.encap_request))
3260                 return -1;
3261
3262         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3263
3264         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3265         memcpy(req.encap_request, encaped, ec_size);
3266
3267         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3268
3269         HWRM_CHECK_RESULT();
3270         HWRM_UNLOCK();
3271
3272         return rc;
3273 }
3274
3275 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3276                                        struct rte_ether_addr *mac)
3277 {
3278         struct hwrm_func_qcfg_input req = {0};
3279         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3280         int rc;
3281
3282         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3283
3284         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3285         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3286
3287         HWRM_CHECK_RESULT();
3288
3289         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3290
3291         HWRM_UNLOCK();
3292
3293         return rc;
3294 }
3295
3296 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3297                             void *encaped, size_t ec_size)
3298 {
3299         int rc = 0;
3300         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3301         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3302
3303         if (ec_size > sizeof(req.encap_request))
3304                 return -1;
3305
3306         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3307
3308         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3309         memcpy(req.encap_request, encaped, ec_size);
3310
3311         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3312
3313         HWRM_CHECK_RESULT();
3314         HWRM_UNLOCK();
3315
3316         return rc;
3317 }
3318
3319 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3320                          struct rte_eth_stats *stats, uint8_t rx)
3321 {
3322         int rc = 0;
3323         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3324         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3325
3326         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3327
3328         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3329
3330         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3331
3332         HWRM_CHECK_RESULT();
3333
3334         if (rx) {
3335                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3336                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3337                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3338                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3339                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3340                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3341                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3342                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3343         } else {
3344                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3345                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3346                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3347                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3348                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3349                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3350         }
3351
3352
3353         HWRM_UNLOCK();
3354
3355         return rc;
3356 }
3357
3358 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3359 {
3360         struct hwrm_port_qstats_input req = {0};
3361         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3362         struct bnxt_pf_info *pf = &bp->pf;
3363         int rc;
3364
3365         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3366
3367         req.port_id = rte_cpu_to_le_16(pf->port_id);
3368         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3369         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3370         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3371
3372         HWRM_CHECK_RESULT();
3373         HWRM_UNLOCK();
3374
3375         return rc;
3376 }
3377
3378 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3379 {
3380         struct hwrm_port_clr_stats_input req = {0};
3381         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3382         struct bnxt_pf_info *pf = &bp->pf;
3383         int rc;
3384
3385         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3386         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3387             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3388                 return 0;
3389
3390         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3391
3392         req.port_id = rte_cpu_to_le_16(pf->port_id);
3393         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3394
3395         HWRM_CHECK_RESULT();
3396         HWRM_UNLOCK();
3397
3398         return rc;
3399 }
3400
3401 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3402 {
3403         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3404         struct hwrm_port_led_qcaps_input req = {0};
3405         int rc;
3406
3407         if (BNXT_VF(bp))
3408                 return 0;
3409
3410         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3411         req.port_id = bp->pf.port_id;
3412         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3413
3414         HWRM_CHECK_RESULT();
3415
3416         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3417                 unsigned int i;
3418
3419                 bp->num_leds = resp->num_leds;
3420                 memcpy(bp->leds, &resp->led0_id,
3421                         sizeof(bp->leds[0]) * bp->num_leds);
3422                 for (i = 0; i < bp->num_leds; i++) {
3423                         struct bnxt_led_info *led = &bp->leds[i];
3424
3425                         uint16_t caps = led->led_state_caps;
3426
3427                         if (!led->led_group_id ||
3428                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3429                                 bp->num_leds = 0;
3430                                 break;
3431                         }
3432                 }
3433         }
3434
3435         HWRM_UNLOCK();
3436
3437         return rc;
3438 }
3439
3440 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3441 {
3442         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3443         struct hwrm_port_led_cfg_input req = {0};
3444         struct bnxt_led_cfg *led_cfg;
3445         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3446         uint16_t duration = 0;
3447         int rc, i;
3448
3449         if (!bp->num_leds || BNXT_VF(bp))
3450                 return -EOPNOTSUPP;
3451
3452         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3453
3454         if (led_on) {
3455                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3456                 duration = rte_cpu_to_le_16(500);
3457         }
3458         req.port_id = bp->pf.port_id;
3459         req.num_leds = bp->num_leds;
3460         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3461         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3462                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3463                 led_cfg->led_id = bp->leds[i].led_id;
3464                 led_cfg->led_state = led_state;
3465                 led_cfg->led_blink_on = duration;
3466                 led_cfg->led_blink_off = duration;
3467                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3468         }
3469
3470         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3471
3472         HWRM_CHECK_RESULT();
3473         HWRM_UNLOCK();
3474
3475         return rc;
3476 }
3477
3478 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3479                                uint32_t *length)
3480 {
3481         int rc;
3482         struct hwrm_nvm_get_dir_info_input req = {0};
3483         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3484
3485         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3486
3487         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3488
3489         HWRM_CHECK_RESULT();
3490         HWRM_UNLOCK();
3491
3492         if (!rc) {
3493                 *entries = rte_le_to_cpu_32(resp->entries);
3494                 *length = rte_le_to_cpu_32(resp->entry_length);
3495         }
3496         return rc;
3497 }
3498
3499 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3500 {
3501         int rc;
3502         uint32_t dir_entries;
3503         uint32_t entry_length;
3504         uint8_t *buf;
3505         size_t buflen;
3506         rte_iova_t dma_handle;
3507         struct hwrm_nvm_get_dir_entries_input req = {0};
3508         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3509
3510         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3511         if (rc != 0)
3512                 return rc;
3513
3514         *data++ = dir_entries;
3515         *data++ = entry_length;
3516         len -= 2;
3517         memset(data, 0xff, len);
3518
3519         buflen = dir_entries * entry_length;
3520         buf = rte_malloc("nvm_dir", buflen, 0);
3521         rte_mem_lock_page(buf);
3522         if (buf == NULL)
3523                 return -ENOMEM;
3524         dma_handle = rte_mem_virt2iova(buf);
3525         if (dma_handle == 0) {
3526                 PMD_DRV_LOG(ERR,
3527                         "unable to map response address to physical memory\n");
3528                 return -ENOMEM;
3529         }
3530         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3531         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3532         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3533
3534         if (rc == 0)
3535                 memcpy(data, buf, len > buflen ? buflen : len);
3536
3537         rte_free(buf);
3538         HWRM_CHECK_RESULT();
3539         HWRM_UNLOCK();
3540
3541         return rc;
3542 }
3543
3544 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3545                              uint32_t offset, uint32_t length,
3546                              uint8_t *data)
3547 {
3548         int rc;
3549         uint8_t *buf;
3550         rte_iova_t dma_handle;
3551         struct hwrm_nvm_read_input req = {0};
3552         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3553
3554         buf = rte_malloc("nvm_item", length, 0);
3555         rte_mem_lock_page(buf);
3556         if (!buf)
3557                 return -ENOMEM;
3558
3559         dma_handle = rte_mem_virt2iova(buf);
3560         if (dma_handle == 0) {
3561                 PMD_DRV_LOG(ERR,
3562                         "unable to map response address to physical memory\n");
3563                 return -ENOMEM;
3564         }
3565         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3566         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3567         req.dir_idx = rte_cpu_to_le_16(index);
3568         req.offset = rte_cpu_to_le_32(offset);
3569         req.len = rte_cpu_to_le_32(length);
3570         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3571         if (rc == 0)
3572                 memcpy(data, buf, length);
3573
3574         rte_free(buf);
3575         HWRM_CHECK_RESULT();
3576         HWRM_UNLOCK();
3577
3578         return rc;
3579 }
3580
3581 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3582 {
3583         int rc;
3584         struct hwrm_nvm_erase_dir_entry_input req = {0};
3585         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3586
3587         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3588         req.dir_idx = rte_cpu_to_le_16(index);
3589         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3590         HWRM_CHECK_RESULT();
3591         HWRM_UNLOCK();
3592
3593         return rc;
3594 }
3595
3596
3597 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3598                           uint16_t dir_ordinal, uint16_t dir_ext,
3599                           uint16_t dir_attr, const uint8_t *data,
3600                           size_t data_len)
3601 {
3602         int rc;
3603         struct hwrm_nvm_write_input req = {0};
3604         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3605         rte_iova_t dma_handle;
3606         uint8_t *buf;
3607
3608         buf = rte_malloc("nvm_write", data_len, 0);
3609         rte_mem_lock_page(buf);
3610         if (!buf)
3611                 return -ENOMEM;
3612
3613         dma_handle = rte_mem_virt2iova(buf);
3614         if (dma_handle == 0) {
3615                 PMD_DRV_LOG(ERR,
3616                         "unable to map response address to physical memory\n");
3617                 return -ENOMEM;
3618         }
3619         memcpy(buf, data, data_len);
3620
3621         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3622
3623         req.dir_type = rte_cpu_to_le_16(dir_type);
3624         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3625         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3626         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3627         req.dir_data_length = rte_cpu_to_le_32(data_len);
3628         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3629
3630         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3631
3632         rte_free(buf);
3633         HWRM_CHECK_RESULT();
3634         HWRM_UNLOCK();
3635
3636         return rc;
3637 }
3638
3639 static void
3640 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3641 {
3642         uint32_t *count = cbdata;
3643
3644         *count = *count + 1;
3645 }
3646
3647 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3648                                      struct bnxt_vnic_info *vnic __rte_unused)
3649 {
3650         return 0;
3651 }
3652
3653 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3654 {
3655         uint32_t count = 0;
3656
3657         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3658             &count, bnxt_vnic_count_hwrm_stub);
3659
3660         return count;
3661 }
3662
3663 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3664                                         uint16_t *vnic_ids)
3665 {
3666         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3667         struct hwrm_func_vf_vnic_ids_query_output *resp =
3668                                                 bp->hwrm_cmd_resp_addr;
3669         int rc;
3670
3671         /* First query all VNIC ids */
3672         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3673
3674         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3675         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3676         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3677
3678         if (req.vnic_id_tbl_addr == 0) {
3679                 HWRM_UNLOCK();
3680                 PMD_DRV_LOG(ERR,
3681                 "unable to map VNIC ID table address to physical memory\n");
3682                 return -ENOMEM;
3683         }
3684         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3685         if (rc) {
3686                 HWRM_UNLOCK();
3687                 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
3688                 return -1;
3689         } else if (resp->error_code) {
3690                 rc = rte_le_to_cpu_16(resp->error_code);
3691                 HWRM_UNLOCK();
3692                 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query error %d\n", rc);
3693                 return -1;
3694         }
3695         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3696
3697         HWRM_UNLOCK();
3698
3699         return rc;
3700 }
3701
3702 /*
3703  * This function queries the VNIC IDs  for a specified VF. It then calls
3704  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3705  * Then it calls the hwrm_cb function to program this new vnic configuration.
3706  */
3707 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3708         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3709         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3710 {
3711         struct bnxt_vnic_info vnic;
3712         int rc = 0;
3713         int i, num_vnic_ids;
3714         uint16_t *vnic_ids;
3715         size_t vnic_id_sz;
3716         size_t sz;
3717
3718         /* First query all VNIC ids */
3719         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3720         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3721                         RTE_CACHE_LINE_SIZE);
3722         if (vnic_ids == NULL) {
3723                 rc = -ENOMEM;
3724                 return rc;
3725         }
3726         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3727                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3728
3729         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3730
3731         if (num_vnic_ids < 0)
3732                 return num_vnic_ids;
3733
3734         /* Retrieve VNIC, update bd_stall then update */
3735
3736         for (i = 0; i < num_vnic_ids; i++) {
3737                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3738                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3739                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3740                 if (rc)
3741                         break;
3742                 if (vnic.mru <= 4)      /* Indicates unallocated */
3743                         continue;
3744
3745                 vnic_cb(&vnic, cbdata);
3746
3747                 rc = hwrm_cb(bp, &vnic);
3748                 if (rc)
3749                         break;
3750         }
3751
3752         rte_free(vnic_ids);
3753
3754         return rc;
3755 }
3756
3757 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3758                                               bool on)
3759 {
3760         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3761         struct hwrm_func_cfg_input req = {0};
3762         int rc;
3763
3764         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3765
3766         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3767         req.enables |= rte_cpu_to_le_32(
3768                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3769         req.vlan_antispoof_mode = on ?
3770                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3771                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3772         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3773
3774         HWRM_CHECK_RESULT();
3775         HWRM_UNLOCK();
3776
3777         return rc;
3778 }
3779
3780 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3781 {
3782         struct bnxt_vnic_info vnic;
3783         uint16_t *vnic_ids;
3784         size_t vnic_id_sz;
3785         int num_vnic_ids, i;
3786         size_t sz;
3787         int rc;
3788
3789         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3790         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3791                         RTE_CACHE_LINE_SIZE);
3792         if (vnic_ids == NULL) {
3793                 rc = -ENOMEM;
3794                 return rc;
3795         }
3796
3797         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3798                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3799
3800         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3801         if (rc <= 0)
3802                 goto exit;
3803         num_vnic_ids = rc;
3804
3805         /*
3806          * Loop through to find the default VNIC ID.
3807          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3808          * by sending the hwrm_func_qcfg command to the firmware.
3809          */
3810         for (i = 0; i < num_vnic_ids; i++) {
3811                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3812                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3813                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3814                                         bp->pf.first_vf_id + vf);
3815                 if (rc)
3816                         goto exit;
3817                 if (vnic.func_default) {
3818                         rte_free(vnic_ids);
3819                         return vnic.fw_vnic_id;
3820                 }
3821         }
3822         /* Could not find a default VNIC. */
3823         PMD_DRV_LOG(ERR, "No default VNIC\n");
3824 exit:
3825         rte_free(vnic_ids);
3826         return -1;
3827 }
3828
3829 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3830                          uint16_t dst_id,
3831                          struct bnxt_filter_info *filter)
3832 {
3833         int rc = 0;
3834         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3835         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3836         uint32_t enables = 0;
3837
3838         if (filter->fw_em_filter_id != UINT64_MAX)
3839                 bnxt_hwrm_clear_em_filter(bp, filter);
3840
3841         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
3842
3843         req.flags = rte_cpu_to_le_32(filter->flags);
3844
3845         enables = filter->enables |
3846               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3847         req.dst_id = rte_cpu_to_le_16(dst_id);
3848
3849         if (filter->ip_addr_type) {
3850                 req.ip_addr_type = filter->ip_addr_type;
3851                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3852         }
3853         if (enables &
3854             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3855                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3856         if (enables &
3857             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3858                 memcpy(req.src_macaddr, filter->src_macaddr,
3859                        RTE_ETHER_ADDR_LEN);
3860         if (enables &
3861             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3862                 memcpy(req.dst_macaddr, filter->dst_macaddr,
3863                        RTE_ETHER_ADDR_LEN);
3864         if (enables &
3865             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3866                 req.ovlan_vid = filter->l2_ovlan;
3867         if (enables &
3868             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3869                 req.ivlan_vid = filter->l2_ivlan;
3870         if (enables &
3871             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3872                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3873         if (enables &
3874             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3875                 req.ip_protocol = filter->ip_protocol;
3876         if (enables &
3877             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3878                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3879         if (enables &
3880             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3881                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3882         if (enables &
3883             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3884                 req.src_port = rte_cpu_to_be_16(filter->src_port);
3885         if (enables &
3886             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3887                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3888         if (enables &
3889             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3890                 req.mirror_vnic_id = filter->mirror_vnic_id;
3891
3892         req.enables = rte_cpu_to_le_32(enables);
3893
3894         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3895
3896         HWRM_CHECK_RESULT();
3897
3898         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3899         HWRM_UNLOCK();
3900
3901         return rc;
3902 }
3903
3904 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3905 {
3906         int rc = 0;
3907         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3908         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3909
3910         if (filter->fw_em_filter_id == UINT64_MAX)
3911                 return 0;
3912
3913         PMD_DRV_LOG(ERR, "Clear EM filter\n");
3914         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
3915
3916         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
3917
3918         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3919
3920         HWRM_CHECK_RESULT();
3921         HWRM_UNLOCK();
3922
3923         filter->fw_em_filter_id = UINT64_MAX;
3924         filter->fw_l2_filter_id = UINT64_MAX;
3925
3926         return 0;
3927 }
3928
3929 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
3930                          uint16_t dst_id,
3931                          struct bnxt_filter_info *filter)
3932 {
3933         int rc = 0;
3934         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
3935         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3936                                                 bp->hwrm_cmd_resp_addr;
3937         uint32_t enables = 0;
3938
3939         if (filter->fw_ntuple_filter_id != UINT64_MAX)
3940                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
3941
3942         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
3943
3944         req.flags = rte_cpu_to_le_32(filter->flags);
3945
3946         enables = filter->enables |
3947               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
3948         req.dst_id = rte_cpu_to_le_16(dst_id);
3949
3950
3951         if (filter->ip_addr_type) {
3952                 req.ip_addr_type = filter->ip_addr_type;
3953                 enables |=
3954                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3955         }
3956         if (enables &
3957             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3958                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3959         if (enables &
3960             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3961                 memcpy(req.src_macaddr, filter->src_macaddr,
3962                        RTE_ETHER_ADDR_LEN);
3963         //if (enables &
3964             //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
3965                 //memcpy(req.dst_macaddr, filter->dst_macaddr,
3966                        //RTE_ETHER_ADDR_LEN);
3967         if (enables &
3968             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
3969                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3970         if (enables &
3971             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3972                 req.ip_protocol = filter->ip_protocol;
3973         if (enables &
3974             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3975                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
3976         if (enables &
3977             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
3978                 req.src_ipaddr_mask[0] =
3979                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
3980         if (enables &
3981             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
3982                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
3983         if (enables &
3984             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
3985                 req.dst_ipaddr_mask[0] =
3986                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
3987         if (enables &
3988             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
3989                 req.src_port = rte_cpu_to_le_16(filter->src_port);
3990         if (enables &
3991             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
3992                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
3993         if (enables &
3994             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
3995                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
3996         if (enables &
3997             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
3998                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
3999         if (enables &
4000             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4001                 req.mirror_vnic_id = filter->mirror_vnic_id;
4002
4003         req.enables = rte_cpu_to_le_32(enables);
4004
4005         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4006
4007         HWRM_CHECK_RESULT();
4008
4009         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4010         HWRM_UNLOCK();
4011
4012         return rc;
4013 }
4014
4015 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4016                                 struct bnxt_filter_info *filter)
4017 {
4018         int rc = 0;
4019         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4020         struct hwrm_cfa_ntuple_filter_free_output *resp =
4021                                                 bp->hwrm_cmd_resp_addr;
4022
4023         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4024                 return 0;
4025
4026         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4027
4028         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4029
4030         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4031
4032         HWRM_CHECK_RESULT();
4033         HWRM_UNLOCK();
4034
4035         filter->fw_ntuple_filter_id = UINT64_MAX;
4036
4037         return 0;
4038 }
4039
4040 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4041 {
4042         unsigned int rss_idx, fw_idx, i;
4043
4044         if (vnic->rss_table && vnic->hash_type) {
4045                 /*
4046                  * Fill the RSS hash & redirection table with
4047                  * ring group ids for all VNICs
4048                  */
4049                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4050                         rss_idx++, fw_idx++) {
4051                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4052                                 fw_idx %= bp->rx_cp_nr_rings;
4053                                 if (vnic->fw_grp_ids[fw_idx] !=
4054                                     INVALID_HW_RING_ID)
4055                                         break;
4056                                 fw_idx++;
4057                         }
4058                         if (i == bp->rx_cp_nr_rings)
4059                                 return 0;
4060                         vnic->rss_table[rss_idx] =
4061                                 vnic->fw_grp_ids[fw_idx];
4062                 }
4063                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4064         }
4065         return 0;
4066 }
4067
4068 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4069         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4070 {
4071         uint16_t flags;
4072
4073         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4074
4075         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4076         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4077
4078         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4079         req->num_cmpl_dma_aggr_during_int =
4080                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4081
4082         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4083
4084         /* min timer set to 1/2 of interrupt timer */
4085         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4086
4087         /* buf timer set to 1/4 of interrupt timer */
4088         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4089
4090         req->cmpl_aggr_dma_tmr_during_int =
4091                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4092
4093         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4094                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4095         req->flags = rte_cpu_to_le_16(flags);
4096 }
4097
4098 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4099                         struct bnxt_coal *coal, uint16_t ring_id)
4100 {
4101         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4102         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4103                                                 bp->hwrm_cmd_resp_addr;
4104         int rc;
4105
4106         /* Set ring coalesce parameters only for Stratus 100G NIC */
4107         if (!bnxt_stratus_device(bp))
4108                 return 0;
4109
4110         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4111         bnxt_hwrm_set_coal_params(coal, &req);
4112         req.ring_id = rte_cpu_to_le_16(ring_id);
4113         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4114         HWRM_CHECK_RESULT();
4115         HWRM_UNLOCK();
4116         return 0;
4117 }
4118
4119 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4120 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4121 {
4122         struct hwrm_func_backing_store_qcaps_input req = {0};
4123         struct hwrm_func_backing_store_qcaps_output *resp =
4124                 bp->hwrm_cmd_resp_addr;
4125         int rc;
4126
4127         if (!BNXT_CHIP_THOR(bp) ||
4128             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4129             BNXT_VF(bp) ||
4130             bp->ctx)
4131                 return 0;
4132
4133         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4134         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4135         HWRM_CHECK_RESULT_SILENT();
4136
4137         if (!rc) {
4138                 struct bnxt_ctx_pg_info *ctx_pg;
4139                 struct bnxt_ctx_mem_info *ctx;
4140                 int total_alloc_len;
4141                 int i;
4142
4143                 total_alloc_len = sizeof(*ctx);
4144                 ctx = rte_malloc("bnxt_ctx_mem", total_alloc_len,
4145                                  RTE_CACHE_LINE_SIZE);
4146                 if (!ctx) {
4147                         rc = -ENOMEM;
4148                         goto ctx_err;
4149                 }
4150                 memset(ctx, 0, total_alloc_len);
4151
4152                 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4153                                     sizeof(*ctx_pg) * BNXT_MAX_Q,
4154                                     RTE_CACHE_LINE_SIZE);
4155                 if (!ctx_pg) {
4156                         rc = -ENOMEM;
4157                         goto ctx_err;
4158                 }
4159                 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4160                         ctx->tqm_mem[i] = ctx_pg;
4161
4162                 bp->ctx = ctx;
4163                 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4164                 ctx->qp_min_qp1_entries =
4165                         rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4166                 ctx->qp_max_l2_entries =
4167                         rte_le_to_cpu_16(resp->qp_max_l2_entries);
4168                 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4169                 ctx->srq_max_l2_entries =
4170                         rte_le_to_cpu_16(resp->srq_max_l2_entries);
4171                 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4172                 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4173                 ctx->cq_max_l2_entries =
4174                         rte_le_to_cpu_16(resp->cq_max_l2_entries);
4175                 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4176                 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4177                 ctx->vnic_max_vnic_entries =
4178                         rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4179                 ctx->vnic_max_ring_table_entries =
4180                         rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4181                 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4182                 ctx->stat_max_entries =
4183                         rte_le_to_cpu_32(resp->stat_max_entries);
4184                 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4185                 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4186                 ctx->tqm_min_entries_per_ring =
4187                         rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4188                 ctx->tqm_max_entries_per_ring =
4189                         rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4190                 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4191                 if (!ctx->tqm_entries_multiple)
4192                         ctx->tqm_entries_multiple = 1;
4193                 ctx->mrav_max_entries =
4194                         rte_le_to_cpu_32(resp->mrav_max_entries);
4195                 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4196                 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4197                 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4198         } else {
4199                 rc = 0;
4200         }
4201 ctx_err:
4202         HWRM_UNLOCK();
4203         return rc;
4204 }
4205
4206 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4207 {
4208         struct hwrm_func_backing_store_cfg_input req = {0};
4209         struct hwrm_func_backing_store_cfg_output *resp =
4210                 bp->hwrm_cmd_resp_addr;
4211         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4212         struct bnxt_ctx_pg_info *ctx_pg;
4213         uint32_t *num_entries;
4214         uint64_t *pg_dir;
4215         uint8_t *pg_attr;
4216         uint32_t ena;
4217         int i, rc;
4218
4219         if (!ctx)
4220                 return 0;
4221
4222         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4223         req.enables = rte_cpu_to_le_32(enables);
4224
4225         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4226                 ctx_pg = &ctx->qp_mem;
4227                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4228                 req.qp_num_qp1_entries =
4229                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4230                 req.qp_num_l2_entries =
4231                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4232                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4233                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4234                                       &req.qpc_pg_size_qpc_lvl,
4235                                       &req.qpc_page_dir);
4236         }
4237
4238         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4239                 ctx_pg = &ctx->srq_mem;
4240                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4241                 req.srq_num_l2_entries =
4242                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4243                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4244                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4245                                       &req.srq_pg_size_srq_lvl,
4246                                       &req.srq_page_dir);
4247         }
4248
4249         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4250                 ctx_pg = &ctx->cq_mem;
4251                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4252                 req.cq_num_l2_entries =
4253                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4254                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4255                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4256                                       &req.cq_pg_size_cq_lvl,
4257                                       &req.cq_page_dir);
4258         }
4259
4260         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4261                 ctx_pg = &ctx->vnic_mem;
4262                 req.vnic_num_vnic_entries =
4263                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4264                 req.vnic_num_ring_table_entries =
4265                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4266                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4267                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4268                                       &req.vnic_pg_size_vnic_lvl,
4269                                       &req.vnic_page_dir);
4270         }
4271
4272         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4273                 ctx_pg = &ctx->stat_mem;
4274                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4275                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4276                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4277                                       &req.stat_pg_size_stat_lvl,
4278                                       &req.stat_page_dir);
4279         }
4280
4281         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4282         num_entries = &req.tqm_sp_num_entries;
4283         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4284         pg_dir = &req.tqm_sp_page_dir;
4285         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4286         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4287                 if (!(enables & ena))
4288                         continue;
4289
4290                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4291
4292                 ctx_pg = ctx->tqm_mem[i];
4293                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4294                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4295         }
4296
4297         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4298         HWRM_CHECK_RESULT();
4299         HWRM_UNLOCK();
4300         if (rc)
4301                 rc = -EIO;
4302         return rc;
4303 }
4304
4305 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4306 {
4307         struct hwrm_port_qstats_ext_input req = {0};
4308         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4309         struct bnxt_pf_info *pf = &bp->pf;
4310         int rc;
4311
4312         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4313               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4314                 return 0;
4315
4316         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4317
4318         req.port_id = rte_cpu_to_le_16(pf->port_id);
4319         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4320                 req.tx_stat_host_addr =
4321                         rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4322                 req.tx_stat_size =
4323                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4324         }
4325         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4326                 req.rx_stat_host_addr =
4327                         rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4328                 req.rx_stat_size =
4329                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4330         }
4331         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4332
4333         if (rc) {
4334                 bp->fw_rx_port_stats_ext_size = 0;
4335                 bp->fw_tx_port_stats_ext_size = 0;
4336         } else {
4337                 bp->fw_rx_port_stats_ext_size =
4338                         rte_le_to_cpu_16(resp->rx_stat_size);
4339                 bp->fw_tx_port_stats_ext_size =
4340                         rte_le_to_cpu_16(resp->tx_stat_size);
4341         }
4342
4343         HWRM_CHECK_RESULT();
4344         HWRM_UNLOCK();
4345
4346         return rc;
4347 }