drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #include <rte_io.h>
  28
  29 #define HWRM_CMD_TIMEOUT                10000
  30
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(void *) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 /*
  64  * HWRM Functions (sent to HWRM)
  65  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  66  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  67  * command was failed by the ChiMP.
  68  */
  69
  70 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  71                                         uint32_t msg_len)
  72 {
  73         unsigned int i;
  74         struct input *req = msg;
  75         struct output *resp = bp->hwrm_cmd_resp_addr;
  76         uint32_t *data = msg;
  77         uint8_t *bar;
  78         uint8_t *valid;
  79         uint16_t max_req_len = bp->max_req_len;
  80         struct hwrm_short_input short_input = { 0 };
  81
  82         if (bp->flags & BNXT_FLAG_SHORT_CMD) {
  83                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
  84
  85                 memset(short_cmd_req, 0, bp->max_req_len);
  86                 memcpy(short_cmd_req, req, msg_len);
  87
  88                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
  89                 short_input.signature = rte_cpu_to_le_16(
  90                                         HWRM_SHORT_REQ_SIGNATURE_SHORT_CMD);
  91                 short_input.size = rte_cpu_to_le_16(msg_len);
  92                 short_input.req_addr =
  93                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
  94
  95                 data = (uint32_t *)&short_input;
  96                 msg_len = sizeof(short_input);
  97
  98                 /* Sync memory write before updating doorbell */
  99                 rte_wmb();
 100
 101                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 102         }
 103
 104         /* Write request msg to hwrm channel */
 105         for (i = 0; i < msg_len; i += 4) {
 106                 bar = (uint8_t *)bp->bar0 + i;
 107                 rte_write32(*data, bar);
 108                 data++;
 109         }
 110
 111         /* Zero the rest of the request space */
 112         for (; i < max_req_len; i += 4) {
 113                 bar = (uint8_t *)bp->bar0 + i;
 114                 rte_write32(0, bar);
 115         }
 116
 117         /* Ring channel doorbell */
 118         bar = (uint8_t *)bp->bar0 + 0x100;
 119         rte_write32(1, bar);
 120
 121         /* Poll for the valid bit */
 122         for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
 123                 /* Sanity check on the resp->resp_len */
 124                 rte_rmb();
 125                 if (resp->resp_len && resp->resp_len <=
 126                                 bp->max_resp_len) {
 127                         /* Last byte of resp contains the valid key */
 128                         valid = (uint8_t *)resp + resp->resp_len - 1;
 129                         if (*valid == HWRM_RESP_VALID_KEY)
 130                                 break;
 131                 }
 132                 rte_delay_us(600);
 133         }
 134
 135         if (i >= HWRM_CMD_TIMEOUT) {
 136                 PMD_DRV_LOG(ERR, "Error sending msg 0x%04x\n",
 137                         req->req_type);
 138                 goto err_ret;
 139         }
 140         return 0;
 141
 142 err_ret:
 143         return -1;
 144 }
 145
 146 /*
 147  * HWRM_PREP() should be used to prepare *ALL* HWRM commands.  It grabs the
 148  * spinlock, and does initial processing.
 149  *
 150  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 151  * releases the spinlock only if it returns.  If the regular int return codes
 152  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 153  * directly, rather it should be copied and modified to suit the function.
 154  *
 155  * HWRM_UNLOCK() must be called after all response processing is completed.
 156  */
 157 #define HWRM_PREP(req, type) do { \
 158         rte_spinlock_lock(&bp->hwrm_lock); \
 159         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 160         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 161         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 162         req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 163         req.target_id = rte_cpu_to_le_16(0xffff); \
 164         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 165 } while (0)
 166
 167 #define HWRM_CHECK_RESULT() do {\
 168         if (rc) { \
 169                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 170                 rte_spinlock_unlock(&bp->hwrm_lock); \
 171                 return rc; \
 172         } \
 173         if (resp->error_code) { \
 174                 rc = rte_le_to_cpu_16(resp->error_code); \
 175                 if (resp->resp_len >= 16) { \
 176                         struct hwrm_err_output *tmp_hwrm_err_op = \
 177                                                 (void *)resp; \
 178                         PMD_DRV_LOG(ERR, \
 179                                 "error %d:%d:%08x:%04x\n", \
 180                                 rc, tmp_hwrm_err_op->cmd_err, \
 181                                 rte_le_to_cpu_32(\
 182                                         tmp_hwrm_err_op->opaque_0), \
 183                                 rte_le_to_cpu_16(\
 184                                         tmp_hwrm_err_op->opaque_1)); \
 185                 } else { \
 186                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 187                 } \
 188                 rte_spinlock_unlock(&bp->hwrm_lock); \
 189                 return rc; \
 190         } \
 191 } while (0)
 192
 193 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 194
 195 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 196 {
 197         int rc = 0;
 198         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 199         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 200
 201         HWRM_PREP(req, CFA_L2_SET_RX_MASK);
 202         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 203         req.mask = 0;
 204
 205         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 206
 207         HWRM_CHECK_RESULT();
 208         HWRM_UNLOCK();
 209
 210         return rc;
 211 }
 212
 213 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 214                                  struct bnxt_vnic_info *vnic,
 215                                  uint16_t vlan_count,
 216                                  struct bnxt_vlan_table_entry *vlan_table)
 217 {
 218         int rc = 0;
 219         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 220         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 221         uint32_t mask = 0;
 222
 223         HWRM_PREP(req, CFA_L2_SET_RX_MASK);
 224         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 225
 226         /* FIXME add multicast flag, when multicast adding options is supported
 227          * by ethtool.
 228          */
 229         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 230                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 231         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 232                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 233         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 234                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 235         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 236                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 237         if (vnic->flags & BNXT_VNIC_INFO_MCAST)
 238                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 239         if (vnic->mc_addr_cnt) {
 240                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 241                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 242                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 243         }
 244         if (vlan_table) {
 245                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 246                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 247                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 248                          rte_mem_virt2iova(vlan_table));
 249                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 250         }
 251         req.mask = rte_cpu_to_le_32(mask);
 252
 253         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 254
 255         HWRM_CHECK_RESULT();
 256         HWRM_UNLOCK();
 257
 258         return rc;
 259 }
 260
 261 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 262                         uint16_t vlan_count,
 263                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 264 {
 265         int rc = 0;
 266         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 267         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 268                                                 bp->hwrm_cmd_resp_addr;
 269
 270         /*
 271          * Older HWRM versions did not support this command, and the set_rx_mask
 272          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 273          * removed from set_rx_mask call, and this command was added.
 274          *
 275          * This command is also present from 1.7.8.11 and higher,
 276          * as well as 1.7.8.0
 277          */
 278         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 279                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 280                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 281                                         (11)))
 282                                 return 0;
 283                 }
 284         }
 285         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG);
 286         req.fid = rte_cpu_to_le_16(fid);
 287
 288         req.vlan_tag_mask_tbl_addr =
 289                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 290         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 291
 292         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 293
 294         HWRM_CHECK_RESULT();
 295         HWRM_UNLOCK();
 296
 297         return rc;
 298 }
 299
 300 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 301                            struct bnxt_filter_info *filter)
 302 {
 303         int rc = 0;
 304         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 305         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 306
 307         if (filter->fw_l2_filter_id == UINT64_MAX)
 308                 return 0;
 309
 310         HWRM_PREP(req, CFA_L2_FILTER_FREE);
 311
 312         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 313
 314         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 315
 316         HWRM_CHECK_RESULT();
 317         HWRM_UNLOCK();
 318
 319         filter->fw_l2_filter_id = -1;
 320
 321         return 0;
 322 }
 323
 324 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 325                          uint16_t dst_id,
 326                          struct bnxt_filter_info *filter)
 327 {
 328         int rc = 0;
 329         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 330         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 331         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 332         const struct rte_eth_vmdq_rx_conf *conf =
 333                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 334         uint32_t enables = 0;
 335         uint16_t j = dst_id - 1;
 336
 337         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 338         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 339             conf->pool_map[j].pools & (1UL << j)) {
 340                 PMD_DRV_LOG(DEBUG,
 341                         "Add vlan %u to vmdq pool %u\n",
 342                         conf->pool_map[j].vlan_id, j);
 343
 344                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 345                 filter->enables |=
 346                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 347                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 348         }
 349
 350         if (filter->fw_l2_filter_id != UINT64_MAX)
 351                 bnxt_hwrm_clear_l2_filter(bp, filter);
 352
 353         HWRM_PREP(req, CFA_L2_FILTER_ALLOC);
 354
 355         req.flags = rte_cpu_to_le_32(filter->flags);
 356
 357         enables = filter->enables |
 358               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 359         req.dst_id = rte_cpu_to_le_16(dst_id);
 360
 361         if (enables &
 362             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 363                 memcpy(req.l2_addr, filter->l2_addr,
 364                        ETHER_ADDR_LEN);
 365         if (enables &
 366             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 367                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 368                        ETHER_ADDR_LEN);
 369         if (enables &
 370             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 371                 req.l2_ovlan = filter->l2_ovlan;
 372         if (enables &
 373             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 374                 req.l2_ovlan = filter->l2_ivlan;
 375         if (enables &
 376             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 377                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 378         if (enables &
 379             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 380                 req.l2_ovlan_mask = filter->l2_ivlan_mask;
 381         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 382                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 383         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 384                 req.src_type = filter->src_type;
 385
 386         req.enables = rte_cpu_to_le_32(enables);
 387
 388         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 389
 390         HWRM_CHECK_RESULT();
 391
 392         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 393         HWRM_UNLOCK();
 394
 395         return rc;
 396 }
 397
 398 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 399 {
 400         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 401         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 402         uint32_t flags = 0;
 403         int rc;
 404
 405         if (!ptp)
 406                 return 0;
 407
 408         HWRM_PREP(req, PORT_MAC_CFG);
 409
 410         if (ptp->rx_filter)
 411                 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 412         else
 413                 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 414         if (ptp->tx_tstamp_en)
 415                 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 416         else
 417                 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 418         req.flags = rte_cpu_to_le_32(flags);
 419         req.enables =
 420         rte_cpu_to_le_32(PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 421         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 422
 423         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 424         HWRM_UNLOCK();
 425
 426         return rc;
 427 }
 428
 429 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 430 {
 431         int rc = 0;
 432         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 433         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 434         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 435
 436 /*      if (bp->hwrm_spec_code < 0x10801 || ptp)  TBD  */
 437         if (ptp)
 438                 return 0;
 439
 440         HWRM_PREP(req, PORT_MAC_PTP_QCFG);
 441
 442         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 443
 444         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 445
 446         HWRM_CHECK_RESULT();
 447
 448         if (!(resp->flags & PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS))
 449                 return 0;
 450
 451         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 452         if (!ptp)
 453                 return -ENOMEM;
 454
 455         ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 456                 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 457         ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 458                 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 459         ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 460                 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 461         ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 462                 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 463         ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 464                 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 465         ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 466                 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 467         ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 468                 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 469         ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 470                 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 471         ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 472                 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 473
 474         ptp->bp = bp;
 475         bp->ptp_cfg = ptp;
 476
 477         return 0;
 478 }
 479
 480 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 481 {
 482         int rc = 0;
 483         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 484         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 485         uint16_t new_max_vfs;
 486         uint32_t flags;
 487         int i;
 488
 489         HWRM_PREP(req, FUNC_QCAPS);
 490
 491         req.fid = rte_cpu_to_le_16(0xffff);
 492
 493         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 494
 495         HWRM_CHECK_RESULT();
 496
 497         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 498         flags = rte_le_to_cpu_32(resp->flags);
 499         if (BNXT_PF(bp)) {
 500                 bp->pf.port_id = resp->port_id;
 501                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 502                 new_max_vfs = bp->pdev->max_vfs;
 503                 if (new_max_vfs != bp->pf.max_vfs) {
 504                         if (bp->pf.vf_info)
 505                                 rte_free(bp->pf.vf_info);
 506                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 507                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 508                         bp->pf.max_vfs = new_max_vfs;
 509                         for (i = 0; i < new_max_vfs; i++) {
 510                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 511                                 bp->pf.vf_info[i].vlan_table =
 512                                         rte_zmalloc("VF VLAN table",
 513                                                     getpagesize(),
 514                                                     getpagesize());
 515                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 516                                         PMD_DRV_LOG(ERR,
 517                                         "Fail to alloc VLAN table for VF %d\n",
 518                                         i);
 519                                 else
 520                                         rte_mem_lock_page(
 521                                                 bp->pf.vf_info[i].vlan_table);
 522                                 bp->pf.vf_info[i].vlan_as_table =
 523                                         rte_zmalloc("VF VLAN AS table",
 524                                                     getpagesize(),
 525                                                     getpagesize());
 526                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 527                                         PMD_DRV_LOG(ERR,
 528                                         "Alloc VLAN AS table for VF %d fail\n",
 529                                         i);
 530                                 else
 531                                         rte_mem_lock_page(
 532                                                bp->pf.vf_info[i].vlan_as_table);
 533                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 534                         }
 535                 }
 536         }
 537
 538         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 539         memcpy(bp->dflt_mac_addr, &resp->mac_address, ETHER_ADDR_LEN);
 540         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 541         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 542         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 543         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 544         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 545         /* TODO: For now, do not support VMDq/RFS on VFs. */
 546         if (BNXT_PF(bp)) {
 547                 if (bp->pf.max_vfs)
 548                         bp->max_vnics = 1;
 549                 else
 550                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 551         } else {
 552                 bp->max_vnics = 1;
 553         }
 554         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 555         if (BNXT_PF(bp)) {
 556                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 557                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 558                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 559                         PMD_DRV_LOG(INFO, "PTP SUPPORTED\n");
 560                         HWRM_UNLOCK();
 561                         bnxt_hwrm_ptp_qcfg(bp);
 562                 }
 563         }
 564
 565         HWRM_UNLOCK();
 566
 567         return rc;
 568 }
 569
 570 int bnxt_hwrm_func_reset(struct bnxt *bp)
 571 {
 572         int rc = 0;
 573         struct hwrm_func_reset_input req = {.req_type = 0 };
 574         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 575
 576         HWRM_PREP(req, FUNC_RESET);
 577
 578         req.enables = rte_cpu_to_le_32(0);
 579
 580         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 581
 582         HWRM_CHECK_RESULT();
 583         HWRM_UNLOCK();
 584
 585         return rc;
 586 }
 587
 588 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 589 {
 590         int rc;
 591         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 592         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 593
 594         if (bp->flags & BNXT_FLAG_REGISTERED)
 595                 return 0;
 596
 597         HWRM_PREP(req, FUNC_DRV_RGTR);
 598         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 599                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 600         req.ver_maj = RTE_VER_YEAR;
 601         req.ver_min = RTE_VER_MONTH;
 602         req.ver_upd = RTE_VER_MINOR;
 603
 604         if (BNXT_PF(bp)) {
 605                 req.enables |= rte_cpu_to_le_32(
 606                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_INPUT_FWD);
 607                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 608                        RTE_MIN(sizeof(req.vf_req_fwd),
 609                                sizeof(bp->pf.vf_req_fwd)));
 610         }
 611
 612         req.async_event_fwd[0] |=
 613                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 614                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 615                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE);
 616         req.async_event_fwd[1] |=
 617                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 618                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 619
 620         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 621
 622         HWRM_CHECK_RESULT();
 623         HWRM_UNLOCK();
 624
 625         bp->flags |= BNXT_FLAG_REGISTERED;
 626
 627         return rc;
 628 }
 629
 630 int bnxt_hwrm_ver_get(struct bnxt *bp)
 631 {
 632         int rc = 0;
 633         struct hwrm_ver_get_input req = {.req_type = 0 };
 634         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 635         uint32_t my_version;
 636         uint32_t fw_version;
 637         uint16_t max_resp_len;
 638         char type[RTE_MEMZONE_NAMESIZE];
 639         uint32_t dev_caps_cfg;
 640
 641         bp->max_req_len = HWRM_MAX_REQ_LEN;
 642         HWRM_PREP(req, VER_GET);
 643
 644         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 645         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 646         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 647
 648         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 649
 650         HWRM_CHECK_RESULT();
 651
 652         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 653                 resp->hwrm_intf_maj, resp->hwrm_intf_min,
 654                 resp->hwrm_intf_upd,
 655                 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
 656         bp->fw_ver = (resp->hwrm_fw_maj << 24) | (resp->hwrm_fw_min << 16) |
 657                         (resp->hwrm_fw_bld << 8) | resp->hwrm_fw_rsvd;
 658         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 659                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 660
 661         my_version = HWRM_VERSION_MAJOR << 16;
 662         my_version |= HWRM_VERSION_MINOR << 8;
 663         my_version |= HWRM_VERSION_UPDATE;
 664
 665         fw_version = resp->hwrm_intf_maj << 16;
 666         fw_version |= resp->hwrm_intf_min << 8;
 667         fw_version |= resp->hwrm_intf_upd;
 668
 669         if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
 670                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 671                 rc = -EINVAL;
 672                 goto error;
 673         }
 674
 675         if (my_version != fw_version) {
 676                 PMD_DRV_LOG(INFO, "BNXT Driver/HWRM API mismatch.\n");
 677                 if (my_version < fw_version) {
 678                         PMD_DRV_LOG(INFO,
 679                                 "Firmware API version is newer than driver.\n");
 680                         PMD_DRV_LOG(INFO,
 681                                 "The driver may be missing features.\n");
 682                 } else {
 683                         PMD_DRV_LOG(INFO,
 684                                 "Firmware API version is older than driver.\n");
 685                         PMD_DRV_LOG(INFO,
 686                                 "Not all driver features may be functional.\n");
 687                 }
 688         }
 689
 690         if (bp->max_req_len > resp->max_req_win_len) {
 691                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
 692                 rc = -EINVAL;
 693         }
 694         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 695         max_resp_len = resp->max_resp_len;
 696         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 697
 698         if (bp->max_resp_len != max_resp_len) {
 699                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 700                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 701                         bp->pdev->addr.devid, bp->pdev->addr.function);
 702
 703                 rte_free(bp->hwrm_cmd_resp_addr);
 704
 705                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 706                 if (bp->hwrm_cmd_resp_addr == NULL) {
 707                         rc = -ENOMEM;
 708                         goto error;
 709                 }
 710                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
 711                 bp->hwrm_cmd_resp_dma_addr =
 712                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
 713                 if (bp->hwrm_cmd_resp_dma_addr == 0) {
 714                         PMD_DRV_LOG(ERR,
 715                         "Unable to map response buffer to physical memory.\n");
 716                         rc = -ENOMEM;
 717                         goto error;
 718                 }
 719                 bp->max_resp_len = max_resp_len;
 720         }
 721
 722         if ((dev_caps_cfg &
 723                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 724             (dev_caps_cfg &
 725              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_INPUTUIRED)) {
 726                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
 727
 728                 rte_free(bp->hwrm_short_cmd_req_addr);
 729
 730                 bp->hwrm_short_cmd_req_addr = rte_malloc(type,
 731                                                         bp->max_req_len, 0);
 732                 if (bp->hwrm_short_cmd_req_addr == NULL) {
 733                         rc = -ENOMEM;
 734                         goto error;
 735                 }
 736                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
 737                 bp->hwrm_short_cmd_req_dma_addr =
 738                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
 739                 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
 740                         rte_free(bp->hwrm_short_cmd_req_addr);
 741                         PMD_DRV_LOG(ERR,
 742                                 "Unable to map buffer to physical memory.\n");
 743                         rc = -ENOMEM;
 744                         goto error;
 745                 }
 746
 747                 bp->flags |= BNXT_FLAG_SHORT_CMD;
 748         }
 749
 750 error:
 751         HWRM_UNLOCK();
 752         return rc;
 753 }
 754
 755 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
 756 {
 757         int rc;
 758         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
 759         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
 760
 761         if (!(bp->flags & BNXT_FLAG_REGISTERED))
 762                 return 0;
 763
 764         HWRM_PREP(req, FUNC_DRV_UNRGTR);
 765         req.flags = flags;
 766
 767         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 768
 769         HWRM_CHECK_RESULT();
 770         HWRM_UNLOCK();
 771
 772         bp->flags &= ~BNXT_FLAG_REGISTERED;
 773
 774         return rc;
 775 }
 776
 777 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
 778 {
 779         int rc = 0;
 780         struct hwrm_port_phy_cfg_input req = {0};
 781         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 782         uint32_t enables = 0;
 783
 784         HWRM_PREP(req, PORT_PHY_CFG);
 785
 786         if (conf->link_up) {
 787                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
 788                 if (bp->link_info.auto_mode && conf->link_speed) {
 789                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
 790                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
 791                 }
 792
 793                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
 794                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
 795                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
 796                 /*
 797                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
 798                  * any auto mode, even "none".
 799                  */
 800                 if (!conf->link_speed) {
 801                         /* No speeds specified. Enable AutoNeg - all speeds */
 802                         req.auto_mode =
 803                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
 804                 }
 805                 /* AutoNeg - Advertise speeds specified. */
 806                 if (conf->auto_link_speed_mask &&
 807                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
 808                         req.auto_mode =
 809                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
 810                         req.auto_link_speed_mask =
 811                                 conf->auto_link_speed_mask;
 812                         enables |=
 813                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
 814                 }
 815
 816                 req.auto_duplex = conf->duplex;
 817                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
 818                 req.auto_pause = conf->auto_pause;
 819                 req.force_pause = conf->force_pause;
 820                 /* Set force_pause if there is no auto or if there is a force */
 821                 if (req.auto_pause && !req.force_pause)
 822                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
 823                 else
 824                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
 825
 826                 req.enables = rte_cpu_to_le_32(enables);
 827         } else {
 828                 req.flags =
 829                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
 830                 PMD_DRV_LOG(INFO, "Force Link Down\n");
 831         }
 832
 833         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 834
 835         HWRM_CHECK_RESULT();
 836         HWRM_UNLOCK();
 837
 838         return rc;
 839 }
 840
 841 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
 842                                    struct bnxt_link_info *link_info)
 843 {
 844         int rc = 0;
 845         struct hwrm_port_phy_qcfg_input req = {0};
 846         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 847
 848         HWRM_PREP(req, PORT_PHY_QCFG);
 849
 850         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 851
 852         HWRM_CHECK_RESULT();
 853
 854         link_info->phy_link_status = resp->link;
 855         link_info->link_up =
 856                 (link_info->phy_link_status ==
 857                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
 858         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
 859         link_info->duplex = resp->duplex_cfg;
 860         link_info->pause = resp->pause;
 861         link_info->auto_pause = resp->auto_pause;
 862         link_info->force_pause = resp->force_pause;
 863         link_info->auto_mode = resp->auto_mode;
 864         link_info->phy_type = resp->phy_type;
 865         link_info->media_type = resp->media_type;
 866
 867         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
 868         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
 869         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
 870         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
 871         link_info->phy_ver[0] = resp->phy_maj;
 872         link_info->phy_ver[1] = resp->phy_min;
 873         link_info->phy_ver[2] = resp->phy_bld;
 874
 875         HWRM_UNLOCK();
 876
 877         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
 878         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
 879         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
 880         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
 881         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
 882                     link_info->auto_link_speed_mask);
 883         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
 884                     link_info->force_link_speed);
 885
 886         return rc;
 887 }
 888
 889 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
 890 {
 891         int rc = 0;
 892         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
 893         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
 894
 895         HWRM_PREP(req, QUEUE_QPORTCFG);
 896
 897         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 898
 899         HWRM_CHECK_RESULT();
 900
 901 #define GET_QUEUE_INFO(x) \
 902         bp->cos_queue[x].id = resp->queue_id##x; \
 903         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
 904
 905         GET_QUEUE_INFO(0);
 906         GET_QUEUE_INFO(1);
 907         GET_QUEUE_INFO(2);
 908         GET_QUEUE_INFO(3);
 909         GET_QUEUE_INFO(4);
 910         GET_QUEUE_INFO(5);
 911         GET_QUEUE_INFO(6);
 912         GET_QUEUE_INFO(7);
 913
 914         HWRM_UNLOCK();
 915
 916         return rc;
 917 }
 918
 919 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
 920                          struct bnxt_ring *ring,
 921                          uint32_t ring_type, uint32_t map_index,
 922                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
 923 {
 924         int rc = 0;
 925         uint32_t enables = 0;
 926         struct hwrm_ring_alloc_input req = {.req_type = 0 };
 927         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 928
 929         HWRM_PREP(req, RING_ALLOC);
 930
 931         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
 932         req.fbo = rte_cpu_to_le_32(0);
 933         /* Association of ring index with doorbell index */
 934         req.logical_id = rte_cpu_to_le_16(map_index);
 935         req.length = rte_cpu_to_le_32(ring->ring_size);
 936
 937         switch (ring_type) {
 938         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
 939                 req.queue_id = bp->cos_queue[0].id;
 940                 /* FALLTHROUGH */
 941         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
 942                 req.ring_type = ring_type;
 943                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
 944                 req.stat_ctx_id = rte_cpu_to_le_16(stats_ctx_id);
 945                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
 946                         enables |=
 947                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
 948                 break;
 949         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
 950                 req.ring_type = ring_type;
 951                 /*
 952                  * TODO: Some HWRM versions crash with
 953                  * HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
 954                  */
 955                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
 956                 break;
 957         default:
 958                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
 959                         ring_type);
 960                 HWRM_UNLOCK();
 961                 return -1;
 962         }
 963         req.enables = rte_cpu_to_le_32(enables);
 964
 965         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 966
 967         if (rc || resp->error_code) {
 968                 if (rc == 0 && resp->error_code)
 969                         rc = rte_le_to_cpu_16(resp->error_code);
 970                 switch (ring_type) {
 971                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
 972                         PMD_DRV_LOG(ERR,
 973                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
 974                         HWRM_UNLOCK();
 975                         return rc;
 976                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
 977                         PMD_DRV_LOG(ERR,
 978                                 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
 979                         HWRM_UNLOCK();
 980                         return rc;
 981                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
 982                         PMD_DRV_LOG(ERR,
 983                                 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
 984                         HWRM_UNLOCK();
 985                         return rc;
 986                 default:
 987                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
 988                         HWRM_UNLOCK();
 989                         return rc;
 990                 }
 991         }
 992
 993         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
 994         HWRM_UNLOCK();
 995         return rc;
 996 }
 997
 998 int bnxt_hwrm_ring_free(struct bnxt *bp,
 999                         struct bnxt_ring *ring, uint32_t ring_type)
1000 {
1001         int rc;
1002         struct hwrm_ring_free_input req = {.req_type = 0 };
1003         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1004
1005         HWRM_PREP(req, RING_FREE);
1006
1007         req.ring_type = ring_type;
1008         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1009
1010         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1011
1012         if (rc || resp->error_code) {
1013                 if (rc == 0 && resp->error_code)
1014                         rc = rte_le_to_cpu_16(resp->error_code);
1015                 HWRM_UNLOCK();
1016
1017                 switch (ring_type) {
1018                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1019                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1020                                 rc);
1021                         return rc;
1022                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1023                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1024                                 rc);
1025                         return rc;
1026                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1027                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1028                                 rc);
1029                         return rc;
1030                 default:
1031                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1032                         return rc;
1033                 }
1034         }
1035         HWRM_UNLOCK();
1036         return 0;
1037 }
1038
1039 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1040 {
1041         int rc = 0;
1042         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1043         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1044
1045         HWRM_PREP(req, RING_GRP_ALLOC);
1046
1047         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1048         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1049         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1050         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1051
1052         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1053
1054         HWRM_CHECK_RESULT();
1055
1056         bp->grp_info[idx].fw_grp_id =
1057             rte_le_to_cpu_16(resp->ring_group_id);
1058
1059         HWRM_UNLOCK();
1060
1061         return rc;
1062 }
1063
1064 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1065 {
1066         int rc;
1067         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1068         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1069
1070         HWRM_PREP(req, RING_GRP_FREE);
1071
1072         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1073
1074         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1075
1076         HWRM_CHECK_RESULT();
1077         HWRM_UNLOCK();
1078
1079         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1080         return rc;
1081 }
1082
1083 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1084 {
1085         int rc = 0;
1086         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1087         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1088
1089         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1090                 return rc;
1091
1092         HWRM_PREP(req, STAT_CTX_CLR_STATS);
1093
1094         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1095
1096         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1097
1098         HWRM_CHECK_RESULT();
1099         HWRM_UNLOCK();
1100
1101         return rc;
1102 }
1103
1104 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1105                                 unsigned int idx __rte_unused)
1106 {
1107         int rc;
1108         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1109         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1110
1111         HWRM_PREP(req, STAT_CTX_ALLOC);
1112
1113         req.update_period_ms = rte_cpu_to_le_32(0);
1114
1115         req.stats_dma_addr =
1116             rte_cpu_to_le_64(cpr->hw_stats_map);
1117
1118         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1119
1120         HWRM_CHECK_RESULT();
1121
1122         cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
1123
1124         HWRM_UNLOCK();
1125
1126         return rc;
1127 }
1128
1129 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1130                                 unsigned int idx __rte_unused)
1131 {
1132         int rc;
1133         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1134         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1135
1136         HWRM_PREP(req, STAT_CTX_FREE);
1137
1138         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1139
1140         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1141
1142         HWRM_CHECK_RESULT();
1143         HWRM_UNLOCK();
1144
1145         return rc;
1146 }
1147
1148 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1149 {
1150         int rc = 0, i, j;
1151         struct hwrm_vnic_alloc_input req = { 0 };
1152         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1153
1154         /* map ring groups to this vnic */
1155         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1156                 vnic->start_grp_id, vnic->end_grp_id);
1157         for (i = vnic->start_grp_id, j = 0; i <= vnic->end_grp_id; i++, j++)
1158                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1159         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1160         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1161         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1162         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1163         vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1164                                 ETHER_CRC_LEN + VLAN_TAG_SIZE;
1165         HWRM_PREP(req, VNIC_ALLOC);
1166
1167         if (vnic->func_default)
1168                 req.flags = HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT;
1169         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1170
1171         HWRM_CHECK_RESULT();
1172
1173         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1174         HWRM_UNLOCK();
1175         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1176         return rc;
1177 }
1178
1179 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1180                                         struct bnxt_vnic_info *vnic,
1181                                         struct bnxt_plcmodes_cfg *pmode)
1182 {
1183         int rc = 0;
1184         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1185         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1186
1187         HWRM_PREP(req, VNIC_PLCMODES_QCFG);
1188
1189         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1190
1191         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1192
1193         HWRM_CHECK_RESULT();
1194
1195         pmode->flags = rte_le_to_cpu_32(resp->flags);
1196         /* dflt_vnic bit doesn't exist in the _cfg command */
1197         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1198         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1199         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1200         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1201
1202         HWRM_UNLOCK();
1203
1204         return rc;
1205 }
1206
1207 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1208                                        struct bnxt_vnic_info *vnic,
1209                                        struct bnxt_plcmodes_cfg *pmode)
1210 {
1211         int rc = 0;
1212         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1213         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1214
1215         HWRM_PREP(req, VNIC_PLCMODES_CFG);
1216
1217         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1218         req.flags = rte_cpu_to_le_32(pmode->flags);
1219         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1220         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1221         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1222         req.enables = rte_cpu_to_le_32(
1223             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1224             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1225             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1226         );
1227
1228         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1229
1230         HWRM_CHECK_RESULT();
1231         HWRM_UNLOCK();
1232
1233         return rc;
1234 }
1235
1236 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1237 {
1238         int rc = 0;
1239         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1240         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1241         uint32_t ctx_enable_flag = 0;
1242         struct bnxt_plcmodes_cfg pmodes;
1243
1244         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1245                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1246                 return rc;
1247         }
1248
1249         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1250         if (rc)
1251                 return rc;
1252
1253         HWRM_PREP(req, VNIC_CFG);
1254
1255         /* Only RSS support for now TBD: COS & LB */
1256         req.enables =
1257             rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP);
1258         if (vnic->lb_rule != 0xffff)
1259                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1260         if (vnic->cos_rule != 0xffff)
1261                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1262         if (vnic->rss_rule != 0xffff) {
1263                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1264                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1265         }
1266         req.enables |= rte_cpu_to_le_32(ctx_enable_flag);
1267         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1268         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1269         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1270         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1271         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1272         req.mru = rte_cpu_to_le_16(vnic->mru);
1273         if (vnic->func_default)
1274                 req.flags |=
1275                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1276         if (vnic->vlan_strip)
1277                 req.flags |=
1278                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1279         if (vnic->bd_stall)
1280                 req.flags |=
1281                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1282         if (vnic->roce_dual)
1283                 req.flags |= rte_cpu_to_le_32(
1284                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1285         if (vnic->roce_only)
1286                 req.flags |= rte_cpu_to_le_32(
1287                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1288         if (vnic->rss_dflt_cr)
1289                 req.flags |= rte_cpu_to_le_32(
1290                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1291
1292         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1293
1294         HWRM_CHECK_RESULT();
1295         HWRM_UNLOCK();
1296
1297         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1298
1299         return rc;
1300 }
1301
1302 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1303                 int16_t fw_vf_id)
1304 {
1305         int rc = 0;
1306         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1307         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1308
1309         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1310                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1311                 return rc;
1312         }
1313         HWRM_PREP(req, VNIC_QCFG);
1314
1315         req.enables =
1316                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1317         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1318         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1319
1320         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1321
1322         HWRM_CHECK_RESULT();
1323
1324         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1325         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1326         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1327         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1328         vnic->mru = rte_le_to_cpu_16(resp->mru);
1329         vnic->func_default = rte_le_to_cpu_32(
1330                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1331         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1332                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1333         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1334                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1335         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1336                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1337         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1338                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1339         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1340                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1341
1342         HWRM_UNLOCK();
1343
1344         return rc;
1345 }
1346
1347 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1348 {
1349         int rc = 0;
1350         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1351         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1352                                                 bp->hwrm_cmd_resp_addr;
1353
1354         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC);
1355
1356         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1357
1358         HWRM_CHECK_RESULT();
1359
1360         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1361         HWRM_UNLOCK();
1362         PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1363
1364         return rc;
1365 }
1366
1367 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1368 {
1369         int rc = 0;
1370         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1371         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1372                                                 bp->hwrm_cmd_resp_addr;
1373
1374         if (vnic->rss_rule == 0xffff) {
1375                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1376                 return rc;
1377         }
1378         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE);
1379
1380         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->rss_rule);
1381
1382         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1383
1384         HWRM_CHECK_RESULT();
1385         HWRM_UNLOCK();
1386
1387         vnic->rss_rule = INVALID_HW_RING_ID;
1388
1389         return rc;
1390 }
1391
1392 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1393 {
1394         int rc = 0;
1395         struct hwrm_vnic_free_input req = {.req_type = 0 };
1396         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1397
1398         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1399                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1400                 return rc;
1401         }
1402
1403         HWRM_PREP(req, VNIC_FREE);
1404
1405         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1406
1407         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1408
1409         HWRM_CHECK_RESULT();
1410         HWRM_UNLOCK();
1411
1412         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1413         return rc;
1414 }
1415
1416 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1417                            struct bnxt_vnic_info *vnic)
1418 {
1419         int rc = 0;
1420         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1421         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1422
1423         HWRM_PREP(req, VNIC_RSS_CFG);
1424
1425         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1426
1427         req.ring_grp_tbl_addr =
1428             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1429         req.hash_key_tbl_addr =
1430             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1431         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1432
1433         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1434
1435         HWRM_CHECK_RESULT();
1436         HWRM_UNLOCK();
1437
1438         return rc;
1439 }
1440
1441 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1442                         struct bnxt_vnic_info *vnic)
1443 {
1444         int rc = 0;
1445         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1446         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1447         uint16_t size;
1448
1449         HWRM_PREP(req, VNIC_PLCMODES_CFG);
1450
1451         req.flags = rte_cpu_to_le_32(
1452                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1453
1454         req.enables = rte_cpu_to_le_32(
1455                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1456
1457         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1458         size -= RTE_PKTMBUF_HEADROOM;
1459
1460         req.jumbo_thresh = rte_cpu_to_le_16(size);
1461         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1462
1463         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1464
1465         HWRM_CHECK_RESULT();
1466         HWRM_UNLOCK();
1467
1468         return rc;
1469 }
1470
1471 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1472                         struct bnxt_vnic_info *vnic, bool enable)
1473 {
1474         int rc = 0;
1475         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1476         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1477
1478         HWRM_PREP(req, VNIC_TPA_CFG);
1479
1480         if (enable) {
1481                 req.enables = rte_cpu_to_le_32(
1482                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1483                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1484                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1485                 req.flags = rte_cpu_to_le_32(
1486                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1487                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1488                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1489                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1490                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1491                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1492                 req.max_agg_segs = rte_cpu_to_le_16(5);
1493                 req.max_aggs =
1494                         rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1495                 req.min_agg_len = rte_cpu_to_le_32(512);
1496         }
1497         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1498
1499         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1500
1501         HWRM_CHECK_RESULT();
1502         HWRM_UNLOCK();
1503
1504         return rc;
1505 }
1506
1507 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1508 {
1509         struct hwrm_func_cfg_input req = {0};
1510         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1511         int rc;
1512
1513         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1514         req.enables = rte_cpu_to_le_32(
1515                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1516         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1517         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1518
1519         HWRM_PREP(req, FUNC_CFG);
1520
1521         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1522         HWRM_CHECK_RESULT();
1523         HWRM_UNLOCK();
1524
1525         bp->pf.vf_info[vf].random_mac = false;
1526
1527         return rc;
1528 }
1529
1530 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1531                                   uint64_t *dropped)
1532 {
1533         int rc = 0;
1534         struct hwrm_func_qstats_input req = {.req_type = 0};
1535         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1536
1537         HWRM_PREP(req, FUNC_QSTATS);
1538
1539         req.fid = rte_cpu_to_le_16(fid);
1540
1541         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1542
1543         HWRM_CHECK_RESULT();
1544
1545         if (dropped)
1546                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1547
1548         HWRM_UNLOCK();
1549
1550         return rc;
1551 }
1552
1553 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1554                           struct rte_eth_stats *stats)
1555 {
1556         int rc = 0;
1557         struct hwrm_func_qstats_input req = {.req_type = 0};
1558         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1559
1560         HWRM_PREP(req, FUNC_QSTATS);
1561
1562         req.fid = rte_cpu_to_le_16(fid);
1563
1564         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1565
1566         HWRM_CHECK_RESULT();
1567
1568         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1569         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1570         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1571         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1572         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1573         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1574
1575         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1576         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1577         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1578         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1579         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1580         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1581
1582         stats->ierrors = rte_le_to_cpu_64(resp->rx_err_pkts);
1583         stats->oerrors = rte_le_to_cpu_64(resp->tx_err_pkts);
1584
1585         stats->imissed = rte_le_to_cpu_64(resp->rx_drop_pkts);
1586
1587         HWRM_UNLOCK();
1588
1589         return rc;
1590 }
1591
1592 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1593 {
1594         int rc = 0;
1595         struct hwrm_func_clr_stats_input req = {.req_type = 0};
1596         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1597
1598         HWRM_PREP(req, FUNC_CLR_STATS);
1599
1600         req.fid = rte_cpu_to_le_16(fid);
1601
1602         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1603
1604         HWRM_CHECK_RESULT();
1605         HWRM_UNLOCK();
1606
1607         return rc;
1608 }
1609
1610 /*
1611  * HWRM utility functions
1612  */
1613
1614 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1615 {
1616         unsigned int i;
1617         int rc = 0;
1618
1619         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1620                 struct bnxt_tx_queue *txq;
1621                 struct bnxt_rx_queue *rxq;
1622                 struct bnxt_cp_ring_info *cpr;
1623
1624                 if (i >= bp->rx_cp_nr_rings) {
1625                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1626                         cpr = txq->cp_ring;
1627                 } else {
1628                         rxq = bp->rx_queues[i];
1629                         cpr = rxq->cp_ring;
1630                 }
1631
1632                 rc = bnxt_hwrm_stat_clear(bp, cpr);
1633                 if (rc)
1634                         return rc;
1635         }
1636         return 0;
1637 }
1638
1639 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1640 {
1641         int rc;
1642         unsigned int i;
1643         struct bnxt_cp_ring_info *cpr;
1644
1645         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1646
1647                 if (i >= bp->rx_cp_nr_rings) {
1648                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
1649                 } else {
1650                         cpr = bp->rx_queues[i]->cp_ring;
1651                         bp->grp_info[i].fw_stats_ctx = -1;
1652                 }
1653                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
1654                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
1655                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1656                         if (rc)
1657                                 return rc;
1658                 }
1659         }
1660         return 0;
1661 }
1662
1663 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
1664 {
1665         unsigned int i;
1666         int rc = 0;
1667
1668         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1669                 struct bnxt_tx_queue *txq;
1670                 struct bnxt_rx_queue *rxq;
1671                 struct bnxt_cp_ring_info *cpr;
1672
1673                 if (i >= bp->rx_cp_nr_rings) {
1674                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1675                         cpr = txq->cp_ring;
1676                 } else {
1677                         rxq = bp->rx_queues[i];
1678                         cpr = rxq->cp_ring;
1679                 }
1680
1681                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
1682
1683                 if (rc)
1684                         return rc;
1685         }
1686         return rc;
1687 }
1688
1689 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
1690 {
1691         uint16_t idx;
1692         uint32_t rc = 0;
1693
1694         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
1695
1696                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
1697                         continue;
1698
1699                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
1700
1701                 if (rc)
1702                         return rc;
1703         }
1704         return rc;
1705 }
1706
1707 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1708                                 unsigned int idx __rte_unused)
1709 {
1710         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
1711
1712         bnxt_hwrm_ring_free(bp, cp_ring,
1713                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
1714         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
1715         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
1716                         sizeof(*cpr->cp_desc_ring));
1717         cpr->cp_raw_cons = 0;
1718 }
1719
1720 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
1721 {
1722         unsigned int i;
1723         int rc = 0;
1724
1725         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
1726                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
1727                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
1728                 struct bnxt_ring *ring = txr->tx_ring_struct;
1729                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
1730                 unsigned int idx = bp->rx_cp_nr_rings + i + 1;
1731
1732                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1733                         bnxt_hwrm_ring_free(bp, ring,
1734                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
1735                         ring->fw_ring_id = INVALID_HW_RING_ID;
1736                         memset(txr->tx_desc_ring, 0,
1737                                         txr->tx_ring_struct->ring_size *
1738                                         sizeof(*txr->tx_desc_ring));
1739                         memset(txr->tx_buf_ring, 0,
1740                                         txr->tx_ring_struct->ring_size *
1741                                         sizeof(*txr->tx_buf_ring));
1742                         txr->tx_prod = 0;
1743                         txr->tx_cons = 0;
1744                 }
1745                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1746                         bnxt_free_cp_ring(bp, cpr, idx);
1747                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1748                 }
1749         }
1750
1751         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1752                 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
1753                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1754                 struct bnxt_ring *ring = rxr->rx_ring_struct;
1755                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1756                 unsigned int idx = i + 1;
1757
1758                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1759                         bnxt_hwrm_ring_free(bp, ring,
1760                                         HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1761                         ring->fw_ring_id = INVALID_HW_RING_ID;
1762                         bp->grp_info[idx].rx_fw_ring_id = INVALID_HW_RING_ID;
1763                         memset(rxr->rx_desc_ring, 0,
1764                                         rxr->rx_ring_struct->ring_size *
1765                                         sizeof(*rxr->rx_desc_ring));
1766                         memset(rxr->rx_buf_ring, 0,
1767                                         rxr->rx_ring_struct->ring_size *
1768                                         sizeof(*rxr->rx_buf_ring));
1769                         rxr->rx_prod = 0;
1770                 }
1771                 ring = rxr->ag_ring_struct;
1772                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1773                         bnxt_hwrm_ring_free(bp, ring,
1774                                             HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1775                         ring->fw_ring_id = INVALID_HW_RING_ID;
1776                         memset(rxr->ag_buf_ring, 0,
1777                                rxr->ag_ring_struct->ring_size *
1778                                sizeof(*rxr->ag_buf_ring));
1779                         rxr->ag_prod = 0;
1780                         bp->grp_info[i].ag_fw_ring_id = INVALID_HW_RING_ID;
1781                 }
1782                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1783                         bnxt_free_cp_ring(bp, cpr, idx);
1784                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
1785                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1786                 }
1787         }
1788
1789         /* Default completion ring */
1790         {
1791                 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1792
1793                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1794                         bnxt_free_cp_ring(bp, cpr, 0);
1795                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1796                 }
1797         }
1798
1799         return rc;
1800 }
1801
1802 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
1803 {
1804         uint16_t i;
1805         uint32_t rc = 0;
1806
1807         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1808                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
1809                 if (rc)
1810                         return rc;
1811         }
1812         return rc;
1813 }
1814
1815 void bnxt_free_hwrm_resources(struct bnxt *bp)
1816 {
1817         /* Release memzone */
1818         rte_free(bp->hwrm_cmd_resp_addr);
1819         rte_free(bp->hwrm_short_cmd_req_addr);
1820         bp->hwrm_cmd_resp_addr = NULL;
1821         bp->hwrm_short_cmd_req_addr = NULL;
1822         bp->hwrm_cmd_resp_dma_addr = 0;
1823         bp->hwrm_short_cmd_req_dma_addr = 0;
1824 }
1825
1826 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
1827 {
1828         struct rte_pci_device *pdev = bp->pdev;
1829         char type[RTE_MEMZONE_NAMESIZE];
1830
1831         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
1832                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
1833         bp->max_resp_len = HWRM_MAX_RESP_LEN;
1834         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
1835         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1836         if (bp->hwrm_cmd_resp_addr == NULL)
1837                 return -ENOMEM;
1838         bp->hwrm_cmd_resp_dma_addr =
1839                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1840         if (bp->hwrm_cmd_resp_dma_addr == 0) {
1841                 PMD_DRV_LOG(ERR,
1842                         "unable to map response address to physical memory\n");
1843                 return -ENOMEM;
1844         }
1845         rte_spinlock_init(&bp->hwrm_lock);
1846
1847         return 0;
1848 }
1849
1850 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1851 {
1852         struct bnxt_filter_info *filter;
1853         int rc = 0;
1854
1855         STAILQ_FOREACH(filter, &vnic->filter, next) {
1856                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1857                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
1858                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1859                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
1860                 else
1861                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1862                 //if (rc)
1863                         //break;
1864         }
1865         return rc;
1866 }
1867
1868 static int
1869 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1870 {
1871         struct bnxt_filter_info *filter;
1872         struct rte_flow *flow;
1873         int rc = 0;
1874
1875         STAILQ_FOREACH(flow, &vnic->flow_list, next) {
1876                 filter = flow->filter;
1877                 PMD_DRV_LOG(ERR, "filter type %d\n", filter->filter_type);
1878                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1879                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
1880                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1881                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
1882                 else
1883                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1884
1885                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
1886                 rte_free(flow);
1887                 //if (rc)
1888                         //break;
1889         }
1890         return rc;
1891 }
1892
1893 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1894 {
1895         struct bnxt_filter_info *filter;
1896         int rc = 0;
1897
1898         STAILQ_FOREACH(filter, &vnic->filter, next) {
1899                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1900                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
1901                                                      filter);
1902                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1903                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
1904                                                          filter);
1905                 else
1906                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
1907                                                      filter);
1908                 if (rc)
1909                         break;
1910         }
1911         return rc;
1912 }
1913
1914 void bnxt_free_tunnel_ports(struct bnxt *bp)
1915 {
1916         if (bp->vxlan_port_cnt)
1917                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
1918                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
1919         bp->vxlan_port = 0;
1920         if (bp->geneve_port_cnt)
1921                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
1922                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
1923         bp->geneve_port = 0;
1924 }
1925
1926 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
1927 {
1928         int i;
1929
1930         if (bp->vnic_info == NULL)
1931                 return;
1932
1933         /*
1934          * Cleanup VNICs in reverse order, to make sure the L2 filter
1935          * from vnic0 is last to be cleaned up.
1936          */
1937         for (i = bp->nr_vnics - 1; i >= 0; i--) {
1938                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1939
1940                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
1941
1942                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
1943
1944                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
1945
1946                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
1947
1948                 bnxt_hwrm_vnic_free(bp, vnic);
1949         }
1950         /* Ring resources */
1951         bnxt_free_all_hwrm_rings(bp);
1952         bnxt_free_all_hwrm_ring_grps(bp);
1953         bnxt_free_all_hwrm_stat_ctxs(bp);
1954         bnxt_free_tunnel_ports(bp);
1955 }
1956
1957 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
1958 {
1959         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1960
1961         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
1962                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1963
1964         switch (conf_link_speed) {
1965         case ETH_LINK_SPEED_10M_HD:
1966         case ETH_LINK_SPEED_100M_HD:
1967                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
1968         }
1969         return hw_link_duplex;
1970 }
1971
1972 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
1973 {
1974         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
1975 }
1976
1977 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
1978 {
1979         uint16_t eth_link_speed = 0;
1980
1981         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
1982                 return ETH_LINK_SPEED_AUTONEG;
1983
1984         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
1985         case ETH_LINK_SPEED_100M:
1986         case ETH_LINK_SPEED_100M_HD:
1987                 eth_link_speed =
1988                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
1989                 break;
1990         case ETH_LINK_SPEED_1G:
1991                 eth_link_speed =
1992                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
1993                 break;
1994         case ETH_LINK_SPEED_2_5G:
1995                 eth_link_speed =
1996                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
1997                 break;
1998         case ETH_LINK_SPEED_10G:
1999                 eth_link_speed =
2000                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2001                 break;
2002         case ETH_LINK_SPEED_20G:
2003                 eth_link_speed =
2004                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2005                 break;
2006         case ETH_LINK_SPEED_25G:
2007                 eth_link_speed =
2008                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2009                 break;
2010         case ETH_LINK_SPEED_40G:
2011                 eth_link_speed =
2012                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2013                 break;
2014         case ETH_LINK_SPEED_50G:
2015                 eth_link_speed =
2016                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2017                 break;
2018         case ETH_LINK_SPEED_100G:
2019                 eth_link_speed =
2020                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2021                 break;
2022         default:
2023                 PMD_DRV_LOG(ERR,
2024                         "Unsupported link speed %d; default to AUTO\n",
2025                         conf_link_speed);
2026                 break;
2027         }
2028         return eth_link_speed;
2029 }
2030
2031 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2032                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2033                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2034                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2035
2036 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2037 {
2038         uint32_t one_speed;
2039
2040         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2041                 return 0;
2042
2043         if (link_speed & ETH_LINK_SPEED_FIXED) {
2044                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2045
2046                 if (one_speed & (one_speed - 1)) {
2047                         PMD_DRV_LOG(ERR,
2048                                 "Invalid advertised speeds (%u) for port %u\n",
2049                                 link_speed, port_id);
2050                         return -EINVAL;
2051                 }
2052                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2053                         PMD_DRV_LOG(ERR,
2054                                 "Unsupported advertised speed (%u) for port %u\n",
2055                                 link_speed, port_id);
2056                         return -EINVAL;
2057                 }
2058         } else {
2059                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2060                         PMD_DRV_LOG(ERR,
2061                                 "Unsupported advertised speeds (%u) for port %u\n",
2062                                 link_speed, port_id);
2063                         return -EINVAL;
2064                 }
2065         }
2066         return 0;
2067 }
2068
2069 static uint16_t
2070 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2071 {
2072         uint16_t ret = 0;
2073
2074         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2075                 if (bp->link_info.support_speeds)
2076                         return bp->link_info.support_speeds;
2077                 link_speed = BNXT_SUPPORTED_SPEEDS;
2078         }
2079
2080         if (link_speed & ETH_LINK_SPEED_100M)
2081                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2082         if (link_speed & ETH_LINK_SPEED_100M_HD)
2083                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2084         if (link_speed & ETH_LINK_SPEED_1G)
2085                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2086         if (link_speed & ETH_LINK_SPEED_2_5G)
2087                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2088         if (link_speed & ETH_LINK_SPEED_10G)
2089                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2090         if (link_speed & ETH_LINK_SPEED_20G)
2091                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2092         if (link_speed & ETH_LINK_SPEED_25G)
2093                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2094         if (link_speed & ETH_LINK_SPEED_40G)
2095                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2096         if (link_speed & ETH_LINK_SPEED_50G)
2097                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2098         if (link_speed & ETH_LINK_SPEED_100G)
2099                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2100         return ret;
2101 }
2102
2103 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2104 {
2105         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2106
2107         switch (hw_link_speed) {
2108         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2109                 eth_link_speed = ETH_SPEED_NUM_100M;
2110                 break;
2111         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2112                 eth_link_speed = ETH_SPEED_NUM_1G;
2113                 break;
2114         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2115                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2116                 break;
2117         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2118                 eth_link_speed = ETH_SPEED_NUM_10G;
2119                 break;
2120         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2121                 eth_link_speed = ETH_SPEED_NUM_20G;
2122                 break;
2123         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2124                 eth_link_speed = ETH_SPEED_NUM_25G;
2125                 break;
2126         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2127                 eth_link_speed = ETH_SPEED_NUM_40G;
2128                 break;
2129         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2130                 eth_link_speed = ETH_SPEED_NUM_50G;
2131                 break;
2132         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2133                 eth_link_speed = ETH_SPEED_NUM_100G;
2134                 break;
2135         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2136         default:
2137                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2138                         hw_link_speed);
2139                 break;
2140         }
2141         return eth_link_speed;
2142 }
2143
2144 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2145 {
2146         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2147
2148         switch (hw_link_duplex) {
2149         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2150         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2151                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2152                 break;
2153         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2154                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2155                 break;
2156         default:
2157                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2158                         hw_link_duplex);
2159                 break;
2160         }
2161         return eth_link_duplex;
2162 }
2163
2164 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2165 {
2166         int rc = 0;
2167         struct bnxt_link_info *link_info = &bp->link_info;
2168
2169         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2170         if (rc) {
2171                 PMD_DRV_LOG(ERR,
2172                         "Get link config failed with rc %d\n", rc);
2173                 goto exit;
2174         }
2175         if (link_info->link_speed)
2176                 link->link_speed =
2177                         bnxt_parse_hw_link_speed(link_info->link_speed);
2178         else
2179                 link->link_speed = ETH_SPEED_NUM_NONE;
2180         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2181         link->link_status = link_info->link_up;
2182         link->link_autoneg = link_info->auto_mode ==
2183                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2184                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2185 exit:
2186         return rc;
2187 }
2188
2189 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2190 {
2191         int rc = 0;
2192         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2193         struct bnxt_link_info link_req;
2194         uint16_t speed, autoneg;
2195
2196         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2197                 return 0;
2198
2199         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2200                         bp->eth_dev->data->port_id);
2201         if (rc)
2202                 goto error;
2203
2204         memset(&link_req, 0, sizeof(link_req));
2205         link_req.link_up = link_up;
2206         if (!link_up)
2207                 goto port_phy_cfg;
2208
2209         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2210         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2211         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2212         /* Autoneg can be done only when the FW allows */
2213         if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2214                                 bp->link_info.force_link_speed)) {
2215                 link_req.phy_flags |=
2216                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2217                 link_req.auto_link_speed_mask =
2218                         bnxt_parse_eth_link_speed_mask(bp,
2219                                                        dev_conf->link_speeds);
2220         } else {
2221                 if (bp->link_info.phy_type ==
2222                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2223                     bp->link_info.phy_type ==
2224                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2225                     bp->link_info.media_type ==
2226                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2227                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2228                         return -EINVAL;
2229                 }
2230
2231                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2232                 /* If user wants a particular speed try that first. */
2233                 if (speed)
2234                         link_req.link_speed = speed;
2235                 else if (bp->link_info.force_link_speed)
2236                         link_req.link_speed = bp->link_info.force_link_speed;
2237                 else
2238                         link_req.link_speed = bp->link_info.auto_link_speed;
2239         }
2240         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2241         link_req.auto_pause = bp->link_info.auto_pause;
2242         link_req.force_pause = bp->link_info.force_pause;
2243
2244 port_phy_cfg:
2245         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2246         if (rc) {
2247                 PMD_DRV_LOG(ERR,
2248                         "Set link config failed with rc %d\n", rc);
2249         }
2250
2251 error:
2252         return rc;
2253 }
2254
2255 /* JIRA 22088 */
2256 int bnxt_hwrm_func_qcfg(struct bnxt *bp)
2257 {
2258         struct hwrm_func_qcfg_input req = {0};
2259         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2260         uint16_t flags;
2261         int rc = 0;
2262
2263         HWRM_PREP(req, FUNC_QCFG);
2264         req.fid = rte_cpu_to_le_16(0xffff);
2265
2266         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2267
2268         HWRM_CHECK_RESULT();
2269
2270         /* Hard Coded.. 0xfff VLAN ID mask */
2271         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2272         flags = rte_le_to_cpu_16(resp->flags);
2273         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2274                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2275
2276         switch (resp->port_partition_type) {
2277         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2278         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2279         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2280                 bp->port_partition_type = resp->port_partition_type;
2281                 break;
2282         default:
2283                 bp->port_partition_type = 0;
2284                 break;
2285         }
2286
2287         HWRM_UNLOCK();
2288
2289         return rc;
2290 }
2291
2292 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2293                                    struct hwrm_func_qcaps_output *qcaps)
2294 {
2295         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2296         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2297                sizeof(qcaps->mac_address));
2298         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2299         qcaps->max_rx_rings = fcfg->num_rx_rings;
2300         qcaps->max_tx_rings = fcfg->num_tx_rings;
2301         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2302         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2303         qcaps->max_vfs = 0;
2304         qcaps->first_vf_id = 0;
2305         qcaps->max_vnics = fcfg->num_vnics;
2306         qcaps->max_decap_records = 0;
2307         qcaps->max_encap_records = 0;
2308         qcaps->max_tx_wm_flows = 0;
2309         qcaps->max_tx_em_flows = 0;
2310         qcaps->max_rx_wm_flows = 0;
2311         qcaps->max_rx_em_flows = 0;
2312         qcaps->max_flow_id = 0;
2313         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2314         qcaps->max_sp_tx_rings = 0;
2315         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2316 }
2317
2318 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2319 {
2320         struct hwrm_func_cfg_input req = {0};
2321         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2322         int rc;
2323
2324         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2325                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2326                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2327                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2328                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2329                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2330                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2331                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2332                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2333                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2334         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2335         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2336         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2337                                    ETHER_CRC_LEN + VLAN_TAG_SIZE);
2338         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2339         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2340         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2341         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2342         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2343         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2344         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2345         req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2346         req.fid = rte_cpu_to_le_16(0xffff);
2347
2348         HWRM_PREP(req, FUNC_CFG);
2349
2350         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2351
2352         HWRM_CHECK_RESULT();
2353         HWRM_UNLOCK();
2354
2355         return rc;
2356 }
2357
2358 static void populate_vf_func_cfg_req(struct bnxt *bp,
2359                                      struct hwrm_func_cfg_input *req,
2360                                      int num_vfs)
2361 {
2362         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2363                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2364                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2365                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2366                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2367                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2368                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2369                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2370                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2371                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2372
2373         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2374                                     ETHER_CRC_LEN + VLAN_TAG_SIZE);
2375         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2376                                     ETHER_CRC_LEN + VLAN_TAG_SIZE);
2377         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2378                                                 (num_vfs + 1));
2379         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2380         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2381                                                (num_vfs + 1));
2382         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2383         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2384         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2385         /* TODO: For now, do not support VMDq/RFS on VFs. */
2386         req->num_vnics = rte_cpu_to_le_16(1);
2387         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2388                                                  (num_vfs + 1));
2389 }
2390
2391 static void add_random_mac_if_needed(struct bnxt *bp,
2392                                      struct hwrm_func_cfg_input *cfg_req,
2393                                      int vf)
2394 {
2395         struct ether_addr mac;
2396
2397         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2398                 return;
2399
2400         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2401                 cfg_req->enables |=
2402                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2403                 eth_random_addr(cfg_req->dflt_mac_addr);
2404                 bp->pf.vf_info[vf].random_mac = true;
2405         } else {
2406                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes, ETHER_ADDR_LEN);
2407         }
2408 }
2409
2410 static void reserve_resources_from_vf(struct bnxt *bp,
2411                                       struct hwrm_func_cfg_input *cfg_req,
2412                                       int vf)
2413 {
2414         struct hwrm_func_qcaps_input req = {0};
2415         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2416         int rc;
2417
2418         /* Get the actual allocated values now */
2419         HWRM_PREP(req, FUNC_QCAPS);
2420         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2421         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2422
2423         if (rc) {
2424                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2425                 copy_func_cfg_to_qcaps(cfg_req, resp);
2426         } else if (resp->error_code) {
2427                 rc = rte_le_to_cpu_16(resp->error_code);
2428                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2429                 copy_func_cfg_to_qcaps(cfg_req, resp);
2430         }
2431
2432         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2433         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2434         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2435         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2436         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2437         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2438         /*
2439          * TODO: While not supporting VMDq with VFs, max_vnics is always
2440          * forced to 1 in this case
2441          */
2442         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2443         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2444
2445         HWRM_UNLOCK();
2446 }
2447
2448 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2449 {
2450         struct hwrm_func_qcfg_input req = {0};
2451         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2452         int rc;
2453
2454         /* Check for zero MAC address */
2455         HWRM_PREP(req, FUNC_QCFG);
2456         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2457         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2458         if (rc) {
2459                 PMD_DRV_LOG(ERR, "hwrm_func_qcfg failed rc:%d\n", rc);
2460                 return -1;
2461         } else if (resp->error_code) {
2462                 rc = rte_le_to_cpu_16(resp->error_code);
2463                 PMD_DRV_LOG(ERR, "hwrm_func_qcfg error %d\n", rc);
2464                 return -1;
2465         }
2466         rc = rte_le_to_cpu_16(resp->vlan);
2467
2468         HWRM_UNLOCK();
2469
2470         return rc;
2471 }
2472
2473 static int update_pf_resource_max(struct bnxt *bp)
2474 {
2475         struct hwrm_func_qcfg_input req = {0};
2476         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2477         int rc;
2478
2479         /* And copy the allocated numbers into the pf struct */
2480         HWRM_PREP(req, FUNC_QCFG);
2481         req.fid = rte_cpu_to_le_16(0xffff);
2482         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2483         HWRM_CHECK_RESULT();
2484
2485         /* Only TX ring value reflects actual allocation? TODO */
2486         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2487         bp->pf.evb_mode = resp->evb_mode;
2488
2489         HWRM_UNLOCK();
2490
2491         return rc;
2492 }
2493
2494 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2495 {
2496         int rc;
2497
2498         if (!BNXT_PF(bp)) {
2499                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2500                 return -1;
2501         }
2502
2503         rc = bnxt_hwrm_func_qcaps(bp);
2504         if (rc)
2505                 return rc;
2506
2507         bp->pf.func_cfg_flags &=
2508                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2509                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2510         bp->pf.func_cfg_flags |=
2511                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2512         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2513         return rc;
2514 }
2515
2516 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2517 {
2518         struct hwrm_func_cfg_input req = {0};
2519         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2520         int i;
2521         size_t sz;
2522         int rc = 0;
2523         size_t req_buf_sz;
2524
2525         if (!BNXT_PF(bp)) {
2526                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2527                 return -1;
2528         }
2529
2530         rc = bnxt_hwrm_func_qcaps(bp);
2531
2532         if (rc)
2533                 return rc;
2534
2535         bp->pf.active_vfs = num_vfs;
2536
2537         /*
2538          * First, configure the PF to only use one TX ring.  This ensures that
2539          * there are enough rings for all VFs.
2540          *
2541          * If we don't do this, when we call func_alloc() later, we will lock
2542          * extra rings to the PF that won't be available during func_cfg() of
2543          * the VFs.
2544          *
2545          * This has been fixed with firmware versions above 20.6.54
2546          */
2547         bp->pf.func_cfg_flags &=
2548                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2549                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2550         bp->pf.func_cfg_flags |=
2551                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2552         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2553         if (rc)
2554                 return rc;
2555
2556         /*
2557          * Now, create and register a buffer to hold forwarded VF requests
2558          */
2559         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2560         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2561                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2562         if (bp->pf.vf_req_buf == NULL) {
2563                 rc = -ENOMEM;
2564                 goto error_free;
2565         }
2566         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2567                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2568         for (i = 0; i < num_vfs; i++)
2569                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2570                                         (i * HWRM_MAX_REQ_LEN);
2571
2572         rc = bnxt_hwrm_func_buf_rgtr(bp);
2573         if (rc)
2574                 goto error_free;
2575
2576         populate_vf_func_cfg_req(bp, &req, num_vfs);
2577
2578         bp->pf.active_vfs = 0;
2579         for (i = 0; i < num_vfs; i++) {
2580                 add_random_mac_if_needed(bp, &req, i);
2581
2582                 HWRM_PREP(req, FUNC_CFG);
2583                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2584                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
2585                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2586
2587                 /* Clear enable flag for next pass */
2588                 req.enables &= ~rte_cpu_to_le_32(
2589                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2590
2591                 if (rc || resp->error_code) {
2592                         PMD_DRV_LOG(ERR,
2593                                 "Failed to initizlie VF %d\n", i);
2594                         PMD_DRV_LOG(ERR,
2595                                 "Not all VFs available. (%d, %d)\n",
2596                                 rc, resp->error_code);
2597                         HWRM_UNLOCK();
2598                         break;
2599                 }
2600
2601                 HWRM_UNLOCK();
2602
2603                 reserve_resources_from_vf(bp, &req, i);
2604                 bp->pf.active_vfs++;
2605                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
2606         }
2607
2608         /*
2609          * Now configure the PF to use "the rest" of the resources
2610          * We're using STD_TX_RING_MODE here though which will limit the TX
2611          * rings.  This will allow QoS to function properly.  Not setting this
2612          * will cause PF rings to break bandwidth settings.
2613          */
2614         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2615         if (rc)
2616                 goto error_free;
2617
2618         rc = update_pf_resource_max(bp);
2619         if (rc)
2620                 goto error_free;
2621
2622         return rc;
2623
2624 error_free:
2625         bnxt_hwrm_func_buf_unrgtr(bp);
2626         return rc;
2627 }
2628
2629 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
2630 {
2631         struct hwrm_func_cfg_input req = {0};
2632         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2633         int rc;
2634
2635         HWRM_PREP(req, FUNC_CFG);
2636
2637         req.fid = rte_cpu_to_le_16(0xffff);
2638         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
2639         req.evb_mode = bp->pf.evb_mode;
2640
2641         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2642         HWRM_CHECK_RESULT();
2643         HWRM_UNLOCK();
2644
2645         return rc;
2646 }
2647
2648 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
2649                                 uint8_t tunnel_type)
2650 {
2651         struct hwrm_tunnel_dst_port_alloc_input req = {0};
2652         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2653         int rc = 0;
2654
2655         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC);
2656         req.tunnel_type = tunnel_type;
2657         req.tunnel_dst_port_val = port;
2658         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2659         HWRM_CHECK_RESULT();
2660
2661         switch (tunnel_type) {
2662         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
2663                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2664                 bp->vxlan_port = port;
2665                 break;
2666         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
2667                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
2668                 bp->geneve_port = port;
2669                 break;
2670         default:
2671                 break;
2672         }
2673
2674         HWRM_UNLOCK();
2675
2676         return rc;
2677 }
2678
2679 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
2680                                 uint8_t tunnel_type)
2681 {
2682         struct hwrm_tunnel_dst_port_free_input req = {0};
2683         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
2684         int rc = 0;
2685
2686         HWRM_PREP(req, TUNNEL_DST_PORT_FREE);
2687
2688         req.tunnel_type = tunnel_type;
2689         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
2690         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2691
2692         HWRM_CHECK_RESULT();
2693         HWRM_UNLOCK();
2694
2695         return rc;
2696 }
2697
2698 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
2699                                         uint32_t flags)
2700 {
2701         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2702         struct hwrm_func_cfg_input req = {0};
2703         int rc;
2704
2705         HWRM_PREP(req, FUNC_CFG);
2706
2707         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2708         req.flags = rte_cpu_to_le_32(flags);
2709         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2710
2711         HWRM_CHECK_RESULT();
2712         HWRM_UNLOCK();
2713
2714         return rc;
2715 }
2716
2717 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
2718 {
2719         uint32_t *flag = flagp;
2720
2721         vnic->flags = *flag;
2722 }
2723
2724 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2725 {
2726         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2727 }
2728
2729 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
2730 {
2731         int rc = 0;
2732         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
2733         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
2734
2735         HWRM_PREP(req, FUNC_BUF_RGTR);
2736
2737         req.req_buf_num_pages = rte_cpu_to_le_16(1);
2738         req.req_buf_page_size = rte_cpu_to_le_16(
2739                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
2740         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
2741         req.req_buf_page_addr[0] =
2742                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
2743         if (req.req_buf_page_addr[0] == 0) {
2744                 PMD_DRV_LOG(ERR,
2745                         "unable to map buffer address to physical memory\n");
2746                 return -ENOMEM;
2747         }
2748
2749         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2750
2751         HWRM_CHECK_RESULT();
2752         HWRM_UNLOCK();
2753
2754         return rc;
2755 }
2756
2757 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
2758 {
2759         int rc = 0;
2760         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
2761         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
2762
2763         HWRM_PREP(req, FUNC_BUF_UNRGTR);
2764
2765         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2766
2767         HWRM_CHECK_RESULT();
2768         HWRM_UNLOCK();
2769
2770         return rc;
2771 }
2772
2773 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
2774 {
2775         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2776         struct hwrm_func_cfg_input req = {0};
2777         int rc;
2778
2779         HWRM_PREP(req, FUNC_CFG);
2780
2781         req.fid = rte_cpu_to_le_16(0xffff);
2782         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2783         req.enables = rte_cpu_to_le_32(
2784                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2785         req.async_event_cr = rte_cpu_to_le_16(
2786                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2787         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2788
2789         HWRM_CHECK_RESULT();
2790         HWRM_UNLOCK();
2791
2792         return rc;
2793 }
2794
2795 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
2796 {
2797         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2798         struct hwrm_func_vf_cfg_input req = {0};
2799         int rc;
2800
2801         HWRM_PREP(req, FUNC_VF_CFG);
2802
2803         req.enables = rte_cpu_to_le_32(
2804                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2805         req.async_event_cr = rte_cpu_to_le_16(
2806                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2807         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2808
2809         HWRM_CHECK_RESULT();
2810         HWRM_UNLOCK();
2811
2812         return rc;
2813 }
2814
2815 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
2816 {
2817         struct hwrm_func_cfg_input req = {0};
2818         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2819         uint16_t dflt_vlan, fid;
2820         uint32_t func_cfg_flags;
2821         int rc = 0;
2822
2823         HWRM_PREP(req, FUNC_CFG);
2824
2825         if (is_vf) {
2826                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
2827                 fid = bp->pf.vf_info[vf].fid;
2828                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
2829         } else {
2830                 fid = rte_cpu_to_le_16(0xffff);
2831                 func_cfg_flags = bp->pf.func_cfg_flags;
2832                 dflt_vlan = bp->vlan;
2833         }
2834
2835         req.flags = rte_cpu_to_le_32(func_cfg_flags);
2836         req.fid = rte_cpu_to_le_16(fid);
2837         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2838         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
2839
2840         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2841
2842         HWRM_CHECK_RESULT();
2843         HWRM_UNLOCK();
2844
2845         return rc;
2846 }
2847
2848 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
2849                         uint16_t max_bw, uint16_t enables)
2850 {
2851         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2852         struct hwrm_func_cfg_input req = {0};
2853         int rc;
2854
2855         HWRM_PREP(req, FUNC_CFG);
2856
2857         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2858         req.enables |= rte_cpu_to_le_32(enables);
2859         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2860         req.max_bw = rte_cpu_to_le_32(max_bw);
2861         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2862
2863         HWRM_CHECK_RESULT();
2864         HWRM_UNLOCK();
2865
2866         return rc;
2867 }
2868
2869 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
2870 {
2871         struct hwrm_func_cfg_input req = {0};
2872         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2873         int rc = 0;
2874
2875         HWRM_PREP(req, FUNC_CFG);
2876
2877         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2878         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2879         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2880         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
2881
2882         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2883
2884         HWRM_CHECK_RESULT();
2885         HWRM_UNLOCK();
2886
2887         return rc;
2888 }
2889
2890 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
2891                               void *encaped, size_t ec_size)
2892 {
2893         int rc = 0;
2894         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
2895         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2896
2897         if (ec_size > sizeof(req.encap_request))
2898                 return -1;
2899
2900         HWRM_PREP(req, REJECT_FWD_RESP);
2901
2902         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2903         memcpy(req.encap_request, encaped, ec_size);
2904
2905         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2906
2907         HWRM_CHECK_RESULT();
2908         HWRM_UNLOCK();
2909
2910         return rc;
2911 }
2912
2913 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
2914                                        struct ether_addr *mac)
2915 {
2916         struct hwrm_func_qcfg_input req = {0};
2917         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2918         int rc;
2919
2920         HWRM_PREP(req, FUNC_QCFG);
2921
2922         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2923         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2924
2925         HWRM_CHECK_RESULT();
2926
2927         memcpy(mac->addr_bytes, resp->mac_address, ETHER_ADDR_LEN);
2928
2929         HWRM_UNLOCK();
2930
2931         return rc;
2932 }
2933
2934 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
2935                             void *encaped, size_t ec_size)
2936 {
2937         int rc = 0;
2938         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
2939         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2940
2941         if (ec_size > sizeof(req.encap_request))
2942                 return -1;
2943
2944         HWRM_PREP(req, EXEC_FWD_RESP);
2945
2946         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2947         memcpy(req.encap_request, encaped, ec_size);
2948
2949         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2950
2951         HWRM_CHECK_RESULT();
2952         HWRM_UNLOCK();
2953
2954         return rc;
2955 }
2956
2957 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
2958                          struct rte_eth_stats *stats, uint8_t rx)
2959 {
2960         int rc = 0;
2961         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
2962         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
2963
2964         HWRM_PREP(req, STAT_CTX_QUERY);
2965
2966         req.stat_ctx_id = rte_cpu_to_le_32(cid);
2967
2968         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2969
2970         HWRM_CHECK_RESULT();
2971
2972         if (rx) {
2973                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2974                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2975                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2976                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2977                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2978                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2979                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
2980                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
2981         } else {
2982                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2983                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2984                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2985                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2986                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2987                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2988                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->tx_err_pkts);
2989         }
2990
2991
2992         HWRM_UNLOCK();
2993
2994         return rc;
2995 }
2996
2997 int bnxt_hwrm_port_qstats(struct bnxt *bp)
2998 {
2999         struct hwrm_port_qstats_input req = {0};
3000         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3001         struct bnxt_pf_info *pf = &bp->pf;
3002         int rc;
3003
3004         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
3005                 return 0;
3006
3007         HWRM_PREP(req, PORT_QSTATS);
3008
3009         req.port_id = rte_cpu_to_le_16(pf->port_id);
3010         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3011         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3012         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3013
3014         HWRM_CHECK_RESULT();
3015         HWRM_UNLOCK();
3016
3017         return rc;
3018 }
3019
3020 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3021 {
3022         struct hwrm_port_clr_stats_input req = {0};
3023         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3024         struct bnxt_pf_info *pf = &bp->pf;
3025         int rc;
3026
3027         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
3028                 return 0;
3029
3030         HWRM_PREP(req, PORT_CLR_STATS);
3031
3032         req.port_id = rte_cpu_to_le_16(pf->port_id);
3033         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3034
3035         HWRM_CHECK_RESULT();
3036         HWRM_UNLOCK();
3037
3038         return rc;
3039 }
3040
3041 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3042 {
3043         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3044         struct hwrm_port_led_qcaps_input req = {0};
3045         int rc;
3046
3047         if (BNXT_VF(bp))
3048                 return 0;
3049
3050         HWRM_PREP(req, PORT_LED_QCAPS);
3051         req.port_id = bp->pf.port_id;
3052         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3053
3054         HWRM_CHECK_RESULT();
3055
3056         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3057                 unsigned int i;
3058
3059                 bp->num_leds = resp->num_leds;
3060                 memcpy(bp->leds, &resp->led0_id,
3061                         sizeof(bp->leds[0]) * bp->num_leds);
3062                 for (i = 0; i < bp->num_leds; i++) {
3063                         struct bnxt_led_info *led = &bp->leds[i];
3064
3065                         uint16_t caps = led->led_state_caps;
3066
3067                         if (!led->led_group_id ||
3068                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3069                                 bp->num_leds = 0;
3070                                 break;
3071                         }
3072                 }
3073         }
3074
3075         HWRM_UNLOCK();
3076
3077         return rc;
3078 }
3079
3080 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3081 {
3082         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3083         struct hwrm_port_led_cfg_input req = {0};
3084         struct bnxt_led_cfg *led_cfg;
3085         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3086         uint16_t duration = 0;
3087         int rc, i;
3088
3089         if (!bp->num_leds || BNXT_VF(bp))
3090                 return -EOPNOTSUPP;
3091
3092         HWRM_PREP(req, PORT_LED_CFG);
3093
3094         if (led_on) {
3095                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3096                 duration = rte_cpu_to_le_16(500);
3097         }
3098         req.port_id = bp->pf.port_id;
3099         req.num_leds = bp->num_leds;
3100         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3101         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3102                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3103                 led_cfg->led_id = bp->leds[i].led_id;
3104                 led_cfg->led_state = led_state;
3105                 led_cfg->led_blink_on = duration;
3106                 led_cfg->led_blink_off = duration;
3107                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3108         }
3109
3110         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3111
3112         HWRM_CHECK_RESULT();
3113         HWRM_UNLOCK();
3114
3115         return rc;
3116 }
3117
3118 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3119                                uint32_t *length)
3120 {
3121         int rc;
3122         struct hwrm_nvm_get_dir_info_input req = {0};
3123         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3124
3125         HWRM_PREP(req, NVM_GET_DIR_INFO);
3126
3127         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3128
3129         HWRM_CHECK_RESULT();
3130         HWRM_UNLOCK();
3131
3132         if (!rc) {
3133                 *entries = rte_le_to_cpu_32(resp->entries);
3134                 *length = rte_le_to_cpu_32(resp->entry_length);
3135         }
3136         return rc;
3137 }
3138
3139 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3140 {
3141         int rc;
3142         uint32_t dir_entries;
3143         uint32_t entry_length;
3144         uint8_t *buf;
3145         size_t buflen;
3146         rte_iova_t dma_handle;
3147         struct hwrm_nvm_get_dir_entries_input req = {0};
3148         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3149
3150         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3151         if (rc != 0)
3152                 return rc;
3153
3154         *data++ = dir_entries;
3155         *data++ = entry_length;
3156         len -= 2;
3157         memset(data, 0xff, len);
3158
3159         buflen = dir_entries * entry_length;
3160         buf = rte_malloc("nvm_dir", buflen, 0);
3161         rte_mem_lock_page(buf);
3162         if (buf == NULL)
3163                 return -ENOMEM;
3164         dma_handle = rte_mem_virt2iova(buf);
3165         if (dma_handle == 0) {
3166                 PMD_DRV_LOG(ERR,
3167                         "unable to map response address to physical memory\n");
3168                 return -ENOMEM;
3169         }
3170         HWRM_PREP(req, NVM_GET_DIR_ENTRIES);
3171         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3172         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3173
3174         HWRM_CHECK_RESULT();
3175         HWRM_UNLOCK();
3176
3177         if (rc == 0)
3178                 memcpy(data, buf, len > buflen ? buflen : len);
3179
3180         rte_free(buf);
3181
3182         return rc;
3183 }
3184
3185 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3186                              uint32_t offset, uint32_t length,
3187                              uint8_t *data)
3188 {
3189         int rc;
3190         uint8_t *buf;
3191         rte_iova_t dma_handle;
3192         struct hwrm_nvm_read_input req = {0};
3193         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3194
3195         buf = rte_malloc("nvm_item", length, 0);
3196         rte_mem_lock_page(buf);
3197         if (!buf)
3198                 return -ENOMEM;
3199
3200         dma_handle = rte_mem_virt2iova(buf);
3201         if (dma_handle == 0) {
3202                 PMD_DRV_LOG(ERR,
3203                         "unable to map response address to physical memory\n");
3204                 return -ENOMEM;
3205         }
3206         HWRM_PREP(req, NVM_READ);
3207         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3208         req.dir_idx = rte_cpu_to_le_16(index);
3209         req.offset = rte_cpu_to_le_32(offset);
3210         req.len = rte_cpu_to_le_32(length);
3211         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3212         HWRM_CHECK_RESULT();
3213         HWRM_UNLOCK();
3214         if (rc == 0)
3215                 memcpy(data, buf, length);
3216
3217         rte_free(buf);
3218         return rc;
3219 }
3220
3221 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3222 {
3223         int rc;
3224         struct hwrm_nvm_erase_dir_entry_input req = {0};
3225         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3226
3227         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY);
3228         req.dir_idx = rte_cpu_to_le_16(index);
3229         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3230         HWRM_CHECK_RESULT();
3231         HWRM_UNLOCK();
3232
3233         return rc;
3234 }
3235
3236
3237 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3238                           uint16_t dir_ordinal, uint16_t dir_ext,
3239                           uint16_t dir_attr, const uint8_t *data,
3240                           size_t data_len)
3241 {
3242         int rc;
3243         struct hwrm_nvm_write_input req = {0};
3244         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3245         rte_iova_t dma_handle;
3246         uint8_t *buf;
3247
3248         HWRM_PREP(req, NVM_WRITE);
3249
3250         req.dir_type = rte_cpu_to_le_16(dir_type);
3251         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3252         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3253         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3254         req.dir_data_length = rte_cpu_to_le_32(data_len);
3255
3256         buf = rte_malloc("nvm_write", data_len, 0);
3257         rte_mem_lock_page(buf);
3258         if (!buf)
3259                 return -ENOMEM;
3260
3261         dma_handle = rte_mem_virt2iova(buf);
3262         if (dma_handle == 0) {
3263                 PMD_DRV_LOG(ERR,
3264                         "unable to map response address to physical memory\n");
3265                 return -ENOMEM;
3266         }
3267         memcpy(buf, data, data_len);
3268         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3269
3270         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3271
3272         HWRM_CHECK_RESULT();
3273         HWRM_UNLOCK();
3274
3275         rte_free(buf);
3276         return rc;
3277 }
3278
3279 static void
3280 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3281 {
3282         uint32_t *count = cbdata;
3283
3284         *count = *count + 1;
3285 }
3286
3287 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3288                                      struct bnxt_vnic_info *vnic __rte_unused)
3289 {
3290         return 0;
3291 }
3292
3293 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3294 {
3295         uint32_t count = 0;
3296
3297         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3298             &count, bnxt_vnic_count_hwrm_stub);
3299
3300         return count;
3301 }
3302
3303 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3304                                         uint16_t *vnic_ids)
3305 {
3306         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3307         struct hwrm_func_vf_vnic_ids_query_output *resp =
3308                                                 bp->hwrm_cmd_resp_addr;
3309         int rc;
3310
3311         /* First query all VNIC ids */
3312         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY);
3313
3314         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3315         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3316         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3317
3318         if (req.vnic_id_tbl_addr == 0) {
3319                 HWRM_UNLOCK();
3320                 PMD_DRV_LOG(ERR,
3321                 "unable to map VNIC ID table address to physical memory\n");
3322                 return -ENOMEM;
3323         }
3324         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3325         if (rc) {
3326                 HWRM_UNLOCK();
3327                 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
3328                 return -1;
3329         } else if (resp->error_code) {
3330                 rc = rte_le_to_cpu_16(resp->error_code);
3331                 HWRM_UNLOCK();
3332                 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query error %d\n", rc);
3333                 return -1;
3334         }
3335         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3336
3337         HWRM_UNLOCK();
3338
3339         return rc;
3340 }
3341
3342 /*
3343  * This function queries the VNIC IDs  for a specified VF. It then calls
3344  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3345  * Then it calls the hwrm_cb function to program this new vnic configuration.
3346  */
3347 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3348         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3349         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3350 {
3351         struct bnxt_vnic_info vnic;
3352         int rc = 0;
3353         int i, num_vnic_ids;
3354         uint16_t *vnic_ids;
3355         size_t vnic_id_sz;
3356         size_t sz;
3357
3358         /* First query all VNIC ids */
3359         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3360         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3361                         RTE_CACHE_LINE_SIZE);
3362         if (vnic_ids == NULL) {
3363                 rc = -ENOMEM;
3364                 return rc;
3365         }
3366         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3367                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3368
3369         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3370
3371         if (num_vnic_ids < 0)
3372                 return num_vnic_ids;
3373
3374         /* Retrieve VNIC, update bd_stall then update */
3375
3376         for (i = 0; i < num_vnic_ids; i++) {
3377                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3378                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3379                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3380                 if (rc)
3381                         break;
3382                 if (vnic.mru <= 4)      /* Indicates unallocated */
3383                         continue;
3384
3385                 vnic_cb(&vnic, cbdata);
3386
3387                 rc = hwrm_cb(bp, &vnic);
3388                 if (rc)
3389                         break;
3390         }
3391
3392         rte_free(vnic_ids);
3393
3394         return rc;
3395 }
3396
3397 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3398                                               bool on)
3399 {
3400         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3401         struct hwrm_func_cfg_input req = {0};
3402         int rc;
3403
3404         HWRM_PREP(req, FUNC_CFG);
3405
3406         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3407         req.enables |= rte_cpu_to_le_32(
3408                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3409         req.vlan_antispoof_mode = on ?
3410                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3411                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3412         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3413
3414         HWRM_CHECK_RESULT();
3415         HWRM_UNLOCK();
3416
3417         return rc;
3418 }
3419
3420 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3421 {
3422         struct bnxt_vnic_info vnic;
3423         uint16_t *vnic_ids;
3424         size_t vnic_id_sz;
3425         int num_vnic_ids, i;
3426         size_t sz;
3427         int rc;
3428
3429         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3430         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3431                         RTE_CACHE_LINE_SIZE);
3432         if (vnic_ids == NULL) {
3433                 rc = -ENOMEM;
3434                 return rc;
3435         }
3436
3437         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3438                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3439
3440         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3441         if (rc <= 0)
3442                 goto exit;
3443         num_vnic_ids = rc;
3444
3445         /*
3446          * Loop through to find the default VNIC ID.
3447          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3448          * by sending the hwrm_func_qcfg command to the firmware.
3449          */
3450         for (i = 0; i < num_vnic_ids; i++) {
3451                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3452                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3453                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3454                                         bp->pf.first_vf_id + vf);
3455                 if (rc)
3456                         goto exit;
3457                 if (vnic.func_default) {
3458                         rte_free(vnic_ids);
3459                         return vnic.fw_vnic_id;
3460                 }
3461         }
3462         /* Could not find a default VNIC. */
3463         PMD_DRV_LOG(ERR, "No default VNIC\n");
3464 exit:
3465         rte_free(vnic_ids);
3466         return -1;
3467 }
3468
3469 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3470                          uint16_t dst_id,
3471                          struct bnxt_filter_info *filter)
3472 {
3473         int rc = 0;
3474         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3475         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3476         uint32_t enables = 0;
3477
3478         if (filter->fw_em_filter_id != UINT64_MAX)
3479                 bnxt_hwrm_clear_em_filter(bp, filter);
3480
3481         HWRM_PREP(req, CFA_EM_FLOW_ALLOC);
3482
3483         req.flags = rte_cpu_to_le_32(filter->flags);
3484
3485         enables = filter->enables |
3486               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3487         req.dst_id = rte_cpu_to_le_16(dst_id);
3488
3489         if (filter->ip_addr_type) {
3490                 req.ip_addr_type = filter->ip_addr_type;
3491                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3492         }
3493         if (enables &
3494             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3495                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3496         if (enables &
3497             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3498                 memcpy(req.src_macaddr, filter->src_macaddr,
3499                        ETHER_ADDR_LEN);
3500         if (enables &
3501             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3502                 memcpy(req.dst_macaddr, filter->dst_macaddr,
3503                        ETHER_ADDR_LEN);
3504         if (enables &
3505             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3506                 req.ovlan_vid = filter->l2_ovlan;
3507         if (enables &
3508             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3509                 req.ivlan_vid = filter->l2_ivlan;
3510         if (enables &
3511             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3512                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3513         if (enables &
3514             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3515                 req.ip_protocol = filter->ip_protocol;
3516         if (enables &
3517             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3518                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3519         if (enables &
3520             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3521                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3522         if (enables &
3523             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3524                 req.src_port = rte_cpu_to_be_16(filter->src_port);
3525         if (enables &
3526             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3527                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3528         if (enables &
3529             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3530                 req.mirror_vnic_id = filter->mirror_vnic_id;
3531
3532         req.enables = rte_cpu_to_le_32(enables);
3533
3534         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3535
3536         HWRM_CHECK_RESULT();
3537
3538         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3539         HWRM_UNLOCK();
3540
3541         return rc;
3542 }
3543
3544 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3545 {
3546         int rc = 0;
3547         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3548         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3549
3550         if (filter->fw_em_filter_id == UINT64_MAX)
3551                 return 0;
3552
3553         PMD_DRV_LOG(ERR, "Clear EM filter\n");
3554         HWRM_PREP(req, CFA_EM_FLOW_FREE);
3555
3556         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
3557
3558         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3559
3560         HWRM_CHECK_RESULT();
3561         HWRM_UNLOCK();
3562
3563         filter->fw_em_filter_id = -1;
3564         filter->fw_l2_filter_id = -1;
3565
3566         return 0;
3567 }
3568
3569 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
3570                          uint16_t dst_id,
3571                          struct bnxt_filter_info *filter)
3572 {
3573         int rc = 0;
3574         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
3575         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3576                                                 bp->hwrm_cmd_resp_addr;
3577         uint32_t enables = 0;
3578
3579         if (filter->fw_ntuple_filter_id != UINT64_MAX)
3580                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
3581
3582         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC);
3583
3584         req.flags = rte_cpu_to_le_32(filter->flags);
3585
3586         enables = filter->enables |
3587               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
3588         req.dst_id = rte_cpu_to_le_16(dst_id);
3589
3590
3591         if (filter->ip_addr_type) {
3592                 req.ip_addr_type = filter->ip_addr_type;
3593                 enables |=
3594                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3595         }
3596         if (enables &
3597             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3598                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3599         if (enables &
3600             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3601                 memcpy(req.src_macaddr, filter->src_macaddr,
3602                        ETHER_ADDR_LEN);
3603         //if (enables &
3604             //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
3605                 //memcpy(req.dst_macaddr, filter->dst_macaddr,
3606                        //ETHER_ADDR_LEN);
3607         if (enables &
3608             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
3609                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3610         if (enables &
3611             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3612                 req.ip_protocol = filter->ip_protocol;
3613         if (enables &
3614             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3615                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
3616         if (enables &
3617             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
3618                 req.src_ipaddr_mask[0] =
3619                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
3620         if (enables &
3621             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
3622                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
3623         if (enables &
3624             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
3625                 req.dst_ipaddr_mask[0] =
3626                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
3627         if (enables &
3628             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
3629                 req.src_port = rte_cpu_to_le_16(filter->src_port);
3630         if (enables &
3631             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
3632                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
3633         if (enables &
3634             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
3635                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
3636         if (enables &
3637             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
3638                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
3639         if (enables &
3640             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3641                 req.mirror_vnic_id = filter->mirror_vnic_id;
3642
3643         req.enables = rte_cpu_to_le_32(enables);
3644
3645         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3646
3647         HWRM_CHECK_RESULT();
3648
3649         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
3650         HWRM_UNLOCK();
3651
3652         return rc;
3653 }
3654
3655 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
3656                                 struct bnxt_filter_info *filter)
3657 {
3658         int rc = 0;
3659         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
3660         struct hwrm_cfa_ntuple_filter_free_output *resp =
3661                                                 bp->hwrm_cmd_resp_addr;
3662
3663         if (filter->fw_ntuple_filter_id == UINT64_MAX)
3664                 return 0;
3665
3666         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE);
3667
3668         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
3669
3670         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3671
3672         HWRM_CHECK_RESULT();
3673         HWRM_UNLOCK();
3674
3675         filter->fw_ntuple_filter_id = -1;
3676
3677         return 0;
3678 }
3679
3680 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3681 {
3682         unsigned int rss_idx, fw_idx, i;
3683
3684         if (vnic->rss_table && vnic->hash_type) {
3685                 /*
3686                  * Fill the RSS hash & redirection table with
3687                  * ring group ids for all VNICs
3688                  */
3689                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
3690                         rss_idx++, fw_idx++) {
3691                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
3692                                 fw_idx %= bp->rx_cp_nr_rings;
3693                                 if (vnic->fw_grp_ids[fw_idx] !=
3694                                     INVALID_HW_RING_ID)
3695                                         break;
3696                                 fw_idx++;
3697                         }
3698                         if (i == bp->rx_cp_nr_rings)
3699                                 return 0;
3700                         vnic->rss_table[rss_idx] =
3701                                 vnic->fw_grp_ids[fw_idx];
3702                 }
3703                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
3704         }
3705         return 0;
3706 }