drivers/net/bnxt/bnxt_rxr.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_bitmap.h>
  10 #include <rte_byteorder.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memory.h>
  13 #include <rte_alarm.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_reps.h"
  17 #include "bnxt_ring.h"
  18 #include "bnxt_rxr.h"
  19 #include "bnxt_rxq.h"
  20 #include "hsi_struct_def_dpdk.h"
  21 #include "bnxt_hwrm.h"
  22
  23 #include <bnxt_tf_common.h>
  24 #include <ulp_mark_mgr.h>
  25
  26 /*
  27  * RX Ring handling
  28  */
  29
  30 static inline struct rte_mbuf *__bnxt_alloc_rx_data(struct rte_mempool *mb)
  31 {
  32         struct rte_mbuf *data;
  33
  34         data = rte_mbuf_raw_alloc(mb);
  35
  36         return data;
  37 }
  38
  39 static inline int bnxt_alloc_rx_data(struct bnxt_rx_queue *rxq,
  40                                      struct bnxt_rx_ring_info *rxr,
  41                                      uint16_t raw_prod)
  42 {
  43         uint16_t prod = RING_IDX(rxr->rx_ring_struct, raw_prod);
  44         struct rx_prod_pkt_bd *rxbd;
  45         struct rte_mbuf **rx_buf;
  46         struct rte_mbuf *mbuf;
  47
  48         rxbd = &rxr->rx_desc_ring[prod];
  49         rx_buf = &rxr->rx_buf_ring[prod];
  50         mbuf = __bnxt_alloc_rx_data(rxq->mb_pool);
  51         if (!mbuf) {
  52                 rte_atomic64_inc(&rxq->rx_mbuf_alloc_fail);
  53                 return -ENOMEM;
  54         }
  55
  56         *rx_buf = mbuf;
  57         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
  58
  59         rxbd->address = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
  60
  61         return 0;
  62 }
  63
  64 static inline int bnxt_alloc_ag_data(struct bnxt_rx_queue *rxq,
  65                                      struct bnxt_rx_ring_info *rxr,
  66                                      uint16_t raw_prod)
  67 {
  68         uint16_t prod = RING_IDX(rxr->ag_ring_struct, raw_prod);
  69         struct rx_prod_pkt_bd *rxbd;
  70         struct rte_mbuf **rx_buf;
  71         struct rte_mbuf *mbuf;
  72
  73         rxbd = &rxr->ag_desc_ring[prod];
  74         rx_buf = &rxr->ag_buf_ring[prod];
  75         if (rxbd == NULL) {
  76                 PMD_DRV_LOG(ERR, "Jumbo Frame. rxbd is NULL\n");
  77                 return -EINVAL;
  78         }
  79
  80         if (rx_buf == NULL) {
  81                 PMD_DRV_LOG(ERR, "Jumbo Frame. rx_buf is NULL\n");
  82                 return -EINVAL;
  83         }
  84
  85         mbuf = __bnxt_alloc_rx_data(rxq->mb_pool);
  86         if (!mbuf) {
  87                 rte_atomic64_inc(&rxq->rx_mbuf_alloc_fail);
  88                 return -ENOMEM;
  89         }
  90
  91         *rx_buf = mbuf;
  92         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
  93
  94         rxbd->address = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
  95
  96         return 0;
  97 }
  98
  99 static inline void bnxt_reuse_rx_mbuf(struct bnxt_rx_ring_info *rxr,
 100                                struct rte_mbuf *mbuf)
 101 {
 102         uint16_t prod, raw_prod = RING_NEXT(rxr->rx_raw_prod);
 103         struct rte_mbuf **prod_rx_buf;
 104         struct rx_prod_pkt_bd *prod_bd;
 105
 106         prod = RING_IDX(rxr->rx_ring_struct, raw_prod);
 107         prod_rx_buf = &rxr->rx_buf_ring[prod];
 108
 109         RTE_ASSERT(*prod_rx_buf == NULL);
 110         RTE_ASSERT(mbuf != NULL);
 111
 112         *prod_rx_buf = mbuf;
 113
 114         prod_bd = &rxr->rx_desc_ring[prod];
 115
 116         prod_bd->address = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 117
 118         rxr->rx_raw_prod = raw_prod;
 119 }
 120
 121 static inline
 122 struct rte_mbuf *bnxt_consume_rx_buf(struct bnxt_rx_ring_info *rxr,
 123                                      uint16_t cons)
 124 {
 125         struct rte_mbuf **cons_rx_buf;
 126         struct rte_mbuf *mbuf;
 127
 128         cons_rx_buf = &rxr->rx_buf_ring[RING_IDX(rxr->rx_ring_struct, cons)];
 129         RTE_ASSERT(*cons_rx_buf != NULL);
 130         mbuf = *cons_rx_buf;
 131         *cons_rx_buf = NULL;
 132
 133         return mbuf;
 134 }
 135
 136 static void bnxt_rx_ring_reset(void *arg)
 137 {
 138         struct bnxt *bp = arg;
 139         int i, rc = 0;
 140         struct bnxt_rx_queue *rxq;
 141
 142
 143         for (i = 0; i < (int)bp->rx_nr_rings; i++) {
 144                 struct bnxt_rx_ring_info *rxr;
 145
 146                 rxq = bp->rx_queues[i];
 147                 if (!rxq || !rxq->in_reset)
 148                         continue;
 149
 150                 rxr = rxq->rx_ring;
 151                 /* Disable and flush TPA before resetting the RX ring */
 152                 if (rxr->tpa_info)
 153                         bnxt_hwrm_vnic_tpa_cfg(bp, rxq->vnic, false);
 154                 rc = bnxt_hwrm_rx_ring_reset(bp, i);
 155                 if (rc) {
 156                         PMD_DRV_LOG(ERR, "Rx ring%d reset failed\n", i);
 157                         continue;
 158                 }
 159
 160                 bnxt_rx_queue_release_mbufs(rxq);
 161                 rxr->rx_raw_prod = 0;
 162                 rxr->ag_raw_prod = 0;
 163                 rxr->rx_next_cons = 0;
 164                 bnxt_init_one_rx_ring(rxq);
 165                 bnxt_db_write(&rxr->rx_db, rxr->rx_raw_prod);
 166                 bnxt_db_write(&rxr->ag_db, rxr->ag_raw_prod);
 167                 if (rxr->tpa_info)
 168                         bnxt_hwrm_vnic_tpa_cfg(bp, rxq->vnic, true);
 169
 170                 rxq->in_reset = 0;
 171         }
 172 }
 173
 174
 175 static void bnxt_sched_ring_reset(struct bnxt_rx_queue *rxq)
 176 {
 177         rxq->in_reset = 1;
 178         rte_eal_alarm_set(1, bnxt_rx_ring_reset, (void *)rxq->bp);
 179 }
 180
 181 static void bnxt_tpa_get_metadata(struct bnxt *bp,
 182                                   struct bnxt_tpa_info *tpa_info,
 183                                   struct rx_tpa_start_cmpl *tpa_start,
 184                                   struct rx_tpa_start_cmpl_hi *tpa_start1)
 185 {
 186         tpa_info->cfa_code_valid = 0;
 187         tpa_info->vlan_valid = 0;
 188         tpa_info->hash_valid = 0;
 189         tpa_info->l4_csum_valid = 0;
 190
 191         if (likely(tpa_start->flags_type &
 192                    rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS_RSS_VALID))) {
 193                 tpa_info->hash_valid = 1;
 194                 tpa_info->rss_hash = rte_le_to_cpu_32(tpa_start->rss_hash);
 195         }
 196
 197         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
 198                 struct rx_tpa_start_v2_cmpl *v2_tpa_start = (void *)tpa_start;
 199                 struct rx_tpa_start_v2_cmpl_hi *v2_tpa_start1 =
 200                         (void *)tpa_start1;
 201
 202                 if (v2_tpa_start->agg_id &
 203                     RX_TPA_START_V2_CMPL_METADATA1_VALID) {
 204                         tpa_info->vlan_valid = 1;
 205                         tpa_info->vlan =
 206                                 rte_le_to_cpu_16(v2_tpa_start1->metadata0);
 207                 }
 208
 209                 if (v2_tpa_start1->flags2 & RX_CMP_FLAGS2_L4_CSUM_ALL_OK_MASK)
 210                         tpa_info->l4_csum_valid = 1;
 211
 212                 return;
 213         }
 214
 215         tpa_info->cfa_code_valid = 1;
 216         tpa_info->cfa_code = rte_le_to_cpu_16(tpa_start1->cfa_code);
 217         if (tpa_start1->flags2 &
 218             rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN)) {
 219                 tpa_info->vlan_valid = 1;
 220                 tpa_info->vlan = rte_le_to_cpu_32(tpa_start1->metadata);
 221         }
 222
 223         if (likely(tpa_start1->flags2 &
 224                    rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC)))
 225                 tpa_info->l4_csum_valid = 1;
 226 }
 227
 228 static void bnxt_tpa_start(struct bnxt_rx_queue *rxq,
 229                            struct rx_tpa_start_cmpl *tpa_start,
 230                            struct rx_tpa_start_cmpl_hi *tpa_start1)
 231 {
 232         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
 233         uint16_t agg_id;
 234         uint16_t data_cons;
 235         struct bnxt_tpa_info *tpa_info;
 236         struct rte_mbuf *mbuf;
 237
 238         agg_id = bnxt_tpa_start_agg_id(rxq->bp, tpa_start);
 239
 240         data_cons = tpa_start->opaque;
 241         tpa_info = &rxr->tpa_info[agg_id];
 242         if (unlikely(data_cons != rxr->rx_next_cons)) {
 243                 PMD_DRV_LOG(ERR, "TPA cons %x, expected cons %x\n",
 244                             data_cons, rxr->rx_next_cons);
 245                 bnxt_sched_ring_reset(rxq);
 246                 return;
 247         }
 248
 249         mbuf = bnxt_consume_rx_buf(rxr, data_cons);
 250
 251         bnxt_reuse_rx_mbuf(rxr, tpa_info->mbuf);
 252
 253         tpa_info->agg_count = 0;
 254         tpa_info->mbuf = mbuf;
 255         tpa_info->len = rte_le_to_cpu_32(tpa_start->len);
 256
 257         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 258         mbuf->nb_segs = 1;
 259         mbuf->next = NULL;
 260         mbuf->pkt_len = rte_le_to_cpu_32(tpa_start->len);
 261         mbuf->data_len = mbuf->pkt_len;
 262         mbuf->port = rxq->port_id;
 263         mbuf->ol_flags = RTE_MBUF_F_RX_LRO;
 264
 265         bnxt_tpa_get_metadata(rxq->bp, tpa_info, tpa_start, tpa_start1);
 266
 267         if (likely(tpa_info->hash_valid)) {
 268                 mbuf->hash.rss = tpa_info->rss_hash;
 269                 mbuf->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 270         } else if (tpa_info->cfa_code_valid) {
 271                 mbuf->hash.fdir.id = tpa_info->cfa_code;
 272                 mbuf->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 273         }
 274
 275         if (tpa_info->vlan_valid) {
 276                 mbuf->vlan_tci = tpa_info->vlan;
 277                 mbuf->ol_flags |= RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED;
 278         }
 279
 280         if (likely(tpa_info->l4_csum_valid))
 281                 mbuf->ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
 282
 283         /* recycle next mbuf */
 284         data_cons = RING_NEXT(data_cons);
 285         bnxt_reuse_rx_mbuf(rxr, bnxt_consume_rx_buf(rxr, data_cons));
 286
 287         rxr->rx_next_cons = RING_IDX(rxr->rx_ring_struct,
 288                                      RING_NEXT(data_cons));
 289 }
 290
 291 static int bnxt_agg_bufs_valid(struct bnxt_cp_ring_info *cpr,
 292                 uint8_t agg_bufs, uint32_t raw_cp_cons)
 293 {
 294         uint16_t last_cp_cons;
 295         struct rx_pkt_cmpl *agg_cmpl;
 296
 297         raw_cp_cons = ADV_RAW_CMP(raw_cp_cons, agg_bufs);
 298         last_cp_cons = RING_CMP(cpr->cp_ring_struct, raw_cp_cons);
 299         agg_cmpl = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[last_cp_cons];
 300         return bnxt_cpr_cmp_valid(agg_cmpl, raw_cp_cons,
 301                                   cpr->cp_ring_struct->ring_size);
 302 }
 303
 304 /* TPA consume agg buffer out of order, allocate connected data only */
 305 static int bnxt_prod_ag_mbuf(struct bnxt_rx_queue *rxq)
 306 {
 307         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
 308         uint16_t raw_next = RING_NEXT(rxr->ag_raw_prod);
 309         uint16_t bmap_next = RING_IDX(rxr->ag_ring_struct, raw_next);
 310
 311         /* TODO batch allocation for better performance */
 312         while (rte_bitmap_get(rxr->ag_bitmap, bmap_next)) {
 313                 if (unlikely(bnxt_alloc_ag_data(rxq, rxr, raw_next))) {
 314                         PMD_DRV_LOG(ERR, "agg mbuf alloc failed: prod=0x%x\n",
 315                                     raw_next);
 316                         break;
 317                 }
 318                 rte_bitmap_clear(rxr->ag_bitmap, bmap_next);
 319                 rxr->ag_raw_prod = raw_next;
 320                 raw_next = RING_NEXT(raw_next);
 321                 bmap_next = RING_IDX(rxr->ag_ring_struct, raw_next);
 322         }
 323
 324         return 0;
 325 }
 326
 327 static int bnxt_rx_pages(struct bnxt_rx_queue *rxq,
 328                          struct rte_mbuf *mbuf, uint32_t *tmp_raw_cons,
 329                          uint8_t agg_buf, struct bnxt_tpa_info *tpa_info)
 330 {
 331         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
 332         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
 333         int i;
 334         uint16_t cp_cons, ag_cons;
 335         struct rx_pkt_cmpl *rxcmp;
 336         struct rte_mbuf *last = mbuf;
 337         bool is_p5_tpa = tpa_info && BNXT_CHIP_P5(rxq->bp);
 338
 339         for (i = 0; i < agg_buf; i++) {
 340                 struct rte_mbuf **ag_buf;
 341                 struct rte_mbuf *ag_mbuf;
 342
 343                 if (is_p5_tpa) {
 344                         rxcmp = (void *)&tpa_info->agg_arr[i];
 345                 } else {
 346                         *tmp_raw_cons = NEXT_RAW_CMP(*tmp_raw_cons);
 347                         cp_cons = RING_CMP(cpr->cp_ring_struct, *tmp_raw_cons);
 348                         rxcmp = (struct rx_pkt_cmpl *)
 349                                         &cpr->cp_desc_ring[cp_cons];
 350                 }
 351
 352 #ifdef BNXT_DEBUG
 353                 bnxt_dump_cmpl(cp_cons, rxcmp);
 354 #endif
 355
 356                 ag_cons = rxcmp->opaque;
 357                 RTE_ASSERT(ag_cons <= rxr->ag_ring_struct->ring_mask);
 358                 ag_buf = &rxr->ag_buf_ring[ag_cons];
 359                 ag_mbuf = *ag_buf;
 360                 RTE_ASSERT(ag_mbuf != NULL);
 361
 362                 ag_mbuf->data_len = rte_le_to_cpu_16(rxcmp->len);
 363
 364                 mbuf->nb_segs++;
 365                 mbuf->pkt_len += ag_mbuf->data_len;
 366
 367                 last->next = ag_mbuf;
 368                 last = ag_mbuf;
 369
 370                 *ag_buf = NULL;
 371
 372                 /*
 373                  * As aggregation buffer consumed out of order in TPA module,
 374                  * use bitmap to track freed slots to be allocated and notified
 375                  * to NIC
 376                  */
 377                 rte_bitmap_set(rxr->ag_bitmap, ag_cons);
 378         }
 379         last->next = NULL;
 380         bnxt_prod_ag_mbuf(rxq);
 381         return 0;
 382 }
 383
 384 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
 385                            uint32_t *raw_cons, void *cmp)
 386 {
 387         struct rx_pkt_cmpl *rxcmp = cmp;
 388         uint32_t tmp_raw_cons = *raw_cons;
 389         uint8_t cmp_type, agg_bufs = 0;
 390
 391         cmp_type = CMP_TYPE(rxcmp);
 392
 393         if (cmp_type == CMPL_BASE_TYPE_RX_L2) {
 394                 agg_bufs = BNXT_RX_L2_AGG_BUFS(rxcmp);
 395         } else if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
 396                 struct rx_tpa_end_cmpl *tpa_end = cmp;
 397
 398                 if (BNXT_CHIP_P5(bp))
 399                         return 0;
 400
 401                 agg_bufs = BNXT_TPA_END_AGG_BUFS(tpa_end);
 402         }
 403
 404         if (agg_bufs) {
 405                 if (!bnxt_agg_bufs_valid(cpr, agg_bufs, tmp_raw_cons))
 406                         return -EBUSY;
 407         }
 408         *raw_cons = tmp_raw_cons;
 409         return 0;
 410 }
 411
 412 static inline struct rte_mbuf *bnxt_tpa_end(
 413                 struct bnxt_rx_queue *rxq,
 414                 uint32_t *raw_cp_cons,
 415                 struct rx_tpa_end_cmpl *tpa_end,
 416                 struct rx_tpa_end_cmpl_hi *tpa_end1)
 417 {
 418         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
 419         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
 420         uint16_t agg_id;
 421         struct rte_mbuf *mbuf;
 422         uint8_t agg_bufs;
 423         uint8_t payload_offset;
 424         struct bnxt_tpa_info *tpa_info;
 425
 426         if (unlikely(rxq->in_reset)) {
 427                 PMD_DRV_LOG(ERR, "rxq->in_reset: raw_cp_cons:%d\n",
 428                             *raw_cp_cons);
 429                 bnxt_discard_rx(rxq->bp, cpr, raw_cp_cons, tpa_end);
 430                 return NULL;
 431         }
 432
 433         if (BNXT_CHIP_P5(rxq->bp)) {
 434                 struct rx_tpa_v2_end_cmpl *th_tpa_end;
 435                 struct rx_tpa_v2_end_cmpl_hi *th_tpa_end1;
 436
 437                 th_tpa_end = (void *)tpa_end;
 438                 th_tpa_end1 = (void *)tpa_end1;
 439                 agg_id = BNXT_TPA_END_AGG_ID_TH(th_tpa_end);
 440                 agg_bufs = BNXT_TPA_END_AGG_BUFS_TH(th_tpa_end1);
 441                 payload_offset = th_tpa_end1->payload_offset;
 442         } else {
 443                 agg_id = BNXT_TPA_END_AGG_ID(tpa_end);
 444                 agg_bufs = BNXT_TPA_END_AGG_BUFS(tpa_end);
 445                 if (!bnxt_agg_bufs_valid(cpr, agg_bufs, *raw_cp_cons))
 446                         return NULL;
 447                 payload_offset = tpa_end->payload_offset;
 448         }
 449
 450         tpa_info = &rxr->tpa_info[agg_id];
 451         mbuf = tpa_info->mbuf;
 452         RTE_ASSERT(mbuf != NULL);
 453
 454         if (agg_bufs) {
 455                 bnxt_rx_pages(rxq, mbuf, raw_cp_cons, agg_bufs, tpa_info);
 456         }
 457         mbuf->l4_len = payload_offset;
 458
 459         struct rte_mbuf *new_data = __bnxt_alloc_rx_data(rxq->mb_pool);
 460         RTE_ASSERT(new_data != NULL);
 461         if (!new_data) {
 462                 rte_atomic64_inc(&rxq->rx_mbuf_alloc_fail);
 463                 return NULL;
 464         }
 465         tpa_info->mbuf = new_data;
 466
 467         return mbuf;
 468 }
 469
 470 uint32_t bnxt_ptype_table[BNXT_PTYPE_TBL_DIM] __rte_cache_aligned;
 471
 472 static void __rte_cold
 473 bnxt_init_ptype_table(void)
 474 {
 475         uint32_t *pt = bnxt_ptype_table;
 476         static bool initialized;
 477         int ip6, tun, type;
 478         uint32_t l3;
 479         int i;
 480
 481         if (initialized)
 482                 return;
 483
 484         for (i = 0; i < BNXT_PTYPE_TBL_DIM; i++) {
 485                 if (i & BNXT_PTYPE_TBL_VLAN_MSK)
 486                         pt[i] = RTE_PTYPE_L2_ETHER_VLAN;
 487                 else
 488                         pt[i] = RTE_PTYPE_L2_ETHER;
 489
 490                 ip6 = !!(i & BNXT_PTYPE_TBL_IP_VER_MSK);
 491                 tun = !!(i & BNXT_PTYPE_TBL_TUN_MSK);
 492                 type = (i & BNXT_PTYPE_TBL_TYPE_MSK) >> BNXT_PTYPE_TBL_TYPE_SFT;
 493
 494                 if (!tun && !ip6)
 495                         l3 = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
 496                 else if (!tun && ip6)
 497                         l3 = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
 498                 else if (tun && !ip6)
 499                         l3 = RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
 500                 else
 501                         l3 = RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
 502
 503                 switch (type) {
 504                 case BNXT_PTYPE_TBL_TYPE_ICMP:
 505                         if (tun)
 506                                 pt[i] |= l3 | RTE_PTYPE_INNER_L4_ICMP;
 507                         else
 508                                 pt[i] |= l3 | RTE_PTYPE_L4_ICMP;
 509                         break;
 510                 case BNXT_PTYPE_TBL_TYPE_TCP:
 511                         if (tun)
 512                                 pt[i] |= l3 | RTE_PTYPE_INNER_L4_TCP;
 513                         else
 514                                 pt[i] |= l3 | RTE_PTYPE_L4_TCP;
 515                         break;
 516                 case BNXT_PTYPE_TBL_TYPE_UDP:
 517                         if (tun)
 518                                 pt[i] |= l3 | RTE_PTYPE_INNER_L4_UDP;
 519                         else
 520                                 pt[i] |= l3 | RTE_PTYPE_L4_UDP;
 521                         break;
 522                 case BNXT_PTYPE_TBL_TYPE_IP:
 523                         pt[i] |= l3;
 524                         break;
 525                 }
 526         }
 527         initialized = true;
 528 }
 529
 530 static uint32_t
 531 bnxt_parse_pkt_type(struct rx_pkt_cmpl *rxcmp, struct rx_pkt_cmpl_hi *rxcmp1)
 532 {
 533         uint32_t flags_type, flags2;
 534         uint8_t index;
 535
 536         flags_type = rte_le_to_cpu_16(rxcmp->flags_type);
 537         flags2 = rte_le_to_cpu_32(rxcmp1->flags2);
 538
 539         /* Validate ptype table indexing at build time. */
 540         bnxt_check_ptype_constants();
 541
 542         /*
 543          * Index format:
 544          *     bit 0: Set if IP tunnel encapsulated packet.
 545          *     bit 1: Set if IPv6 packet, clear if IPv4.
 546          *     bit 2: Set if VLAN tag present.
 547          *     bits 3-6: Four-bit hardware packet type field.
 548          */
 549         index = BNXT_CMPL_ITYPE_TO_IDX(flags_type) |
 550                 BNXT_CMPL_VLAN_TUN_TO_IDX(flags2) |
 551                 BNXT_CMPL_IP_VER_TO_IDX(flags2);
 552
 553         return bnxt_ptype_table[index];
 554 }
 555
 556 static void __rte_cold
 557 bnxt_init_ol_flags_tables(struct bnxt_rx_queue *rxq)
 558 {
 559         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
 560         struct rte_eth_conf *dev_conf;
 561         bool outer_cksum_enabled;
 562         uint64_t offloads;
 563         uint32_t *pt;
 564         int i;
 565
 566         dev_conf = &rxq->bp->eth_dev->data->dev_conf;
 567         offloads = dev_conf->rxmode.offloads;
 568
 569         outer_cksum_enabled = !!(offloads & (DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 570                                              DEV_RX_OFFLOAD_OUTER_UDP_CKSUM));
 571
 572         /* Initialize ol_flags table. */
 573         pt = rxr->ol_flags_table;
 574         for (i = 0; i < BNXT_OL_FLAGS_TBL_DIM; i++) {
 575                 pt[i] = 0;
 576
 577                 if (i & RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN)
 578                         pt[i] |= RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED;
 579
 580                 if (i & (RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC << 3)) {
 581                         /* Tunnel case. */
 582                         if (outer_cksum_enabled) {
 583                                 if (i & RX_PKT_CMPL_FLAGS2_IP_CS_CALC)
 584                                         pt[i] |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
 585
 586                                 if (i & RX_PKT_CMPL_FLAGS2_L4_CS_CALC)
 587                                         pt[i] |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
 588
 589                                 if (i & RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC)
 590                                         pt[i] |= RTE_MBUF_F_RX_OUTER_L4_CKSUM_GOOD;
 591                         } else {
 592                                 if (i & RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC)
 593                                         pt[i] |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
 594
 595                                 if (i & RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC)
 596                                         pt[i] |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
 597                         }
 598                 } else {
 599                         /* Non-tunnel case. */
 600                         if (i & RX_PKT_CMPL_FLAGS2_IP_CS_CALC)
 601                                 pt[i] |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
 602
 603                         if (i & RX_PKT_CMPL_FLAGS2_L4_CS_CALC)
 604                                 pt[i] |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
 605                 }
 606         }
 607
 608         /* Initialize checksum error table. */
 609         pt = rxr->ol_flags_err_table;
 610         for (i = 0; i < BNXT_OL_FLAGS_ERR_TBL_DIM; i++) {
 611                 pt[i] = 0;
 612
 613                 if (i & (RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC << 2)) {
 614                         /* Tunnel case. */
 615                         if (outer_cksum_enabled) {
 616                                 if (i & (RX_PKT_CMPL_ERRORS_IP_CS_ERROR >> 4))
 617                                         pt[i] |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
 618
 619                                 if (i & (RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR >> 4))
 620                                         pt[i] |= RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD;
 621
 622                                 if (i & (RX_PKT_CMPL_ERRORS_L4_CS_ERROR >> 4))
 623                                         pt[i] |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
 624
 625                                 if (i & (RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR >> 4))
 626                                         pt[i] |= RTE_MBUF_F_RX_OUTER_L4_CKSUM_BAD;
 627                         } else {
 628                                 if (i & (RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR >> 4))
 629                                         pt[i] |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
 630
 631                                 if (i & (RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR >> 4))
 632                                         pt[i] |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
 633                         }
 634                 } else {
 635                         /* Non-tunnel case. */
 636                         if (i & (RX_PKT_CMPL_ERRORS_IP_CS_ERROR >> 4))
 637                                 pt[i] |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
 638
 639                         if (i & (RX_PKT_CMPL_ERRORS_L4_CS_ERROR >> 4))
 640                                 pt[i] |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
 641                 }
 642         }
 643 }
 644
 645 static void
 646 bnxt_set_ol_flags(struct bnxt_rx_ring_info *rxr, struct rx_pkt_cmpl *rxcmp,
 647                   struct rx_pkt_cmpl_hi *rxcmp1, struct rte_mbuf *mbuf)
 648 {
 649         uint16_t flags_type, errors, flags;
 650         uint64_t ol_flags;
 651
 652         flags_type = rte_le_to_cpu_16(rxcmp->flags_type);
 653
 654         flags = rte_le_to_cpu_32(rxcmp1->flags2) &
 655                                 (RX_PKT_CMPL_FLAGS2_IP_CS_CALC |
 656                                  RX_PKT_CMPL_FLAGS2_L4_CS_CALC |
 657                                  RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC |
 658                                  RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC |
 659                                  RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN);
 660
 661         flags |= (flags & RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC) << 3;
 662         errors = rte_le_to_cpu_16(rxcmp1->errors_v2) &
 663                                 (RX_PKT_CMPL_ERRORS_IP_CS_ERROR |
 664                                  RX_PKT_CMPL_ERRORS_L4_CS_ERROR |
 665                                  RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR |
 666                                  RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR);
 667         errors = (errors >> 4) & flags;
 668
 669         ol_flags = rxr->ol_flags_table[flags & ~errors];
 670
 671         if (unlikely(errors)) {
 672                 errors |= (flags & RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC) << 2;
 673                 ol_flags |= rxr->ol_flags_err_table[errors];
 674         }
 675
 676         if (flags_type & RX_PKT_CMPL_FLAGS_RSS_VALID) {
 677                 mbuf->hash.rss = rte_le_to_cpu_32(rxcmp->rss_hash);
 678                 ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 679         }
 680
 681 #ifdef RTE_LIBRTE_IEEE1588
 682         if (unlikely((flags_type & RX_PKT_CMPL_FLAGS_MASK) ==
 683                      RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP))
 684                 ol_flags |= RTE_MBUF_F_RX_IEEE1588_PTP | RTE_MBUF_F_RX_IEEE1588_TMST;
 685 #endif
 686
 687         mbuf->ol_flags = ol_flags;
 688 }
 689
 690 #ifdef RTE_LIBRTE_IEEE1588
 691 static void
 692 bnxt_get_rx_ts_p5(struct bnxt *bp, uint32_t rx_ts_cmpl)
 693 {
 694         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 695         uint64_t last_hwrm_time;
 696         uint64_t pkt_time = 0;
 697
 698         if (!BNXT_CHIP_P5(bp) || !ptp)
 699                 return;
 700
 701         /* On Thor, Rx timestamps are provided directly in the
 702          * Rx completion records to the driver. Only 32 bits of
 703          * the timestamp is present in the completion. Driver needs
 704          * to read the current 48 bit free running timer using the
 705          * HWRM_PORT_TS_QUERY command and combine the upper 16 bits
 706          * from the HWRM response with the lower 32 bits in the
 707          * Rx completion to produce the 48 bit timestamp for the Rx packet
 708          */
 709         last_hwrm_time = ptp->current_time;
 710         pkt_time = (last_hwrm_time & BNXT_PTP_CURRENT_TIME_MASK) | rx_ts_cmpl;
 711         if (rx_ts_cmpl < (uint32_t)last_hwrm_time) {
 712                 /* timer has rolled over */
 713                 pkt_time += (1ULL << 32);
 714         }
 715         ptp->rx_timestamp = pkt_time;
 716 }
 717 #endif
 718
 719 static uint32_t
 720 bnxt_ulp_set_mark_in_mbuf(struct bnxt *bp, struct rx_pkt_cmpl_hi *rxcmp1,
 721                           struct rte_mbuf *mbuf, uint32_t *vfr_flag)
 722 {
 723         uint32_t cfa_code;
 724         uint32_t meta_fmt;
 725         uint32_t meta;
 726         bool gfid = false;
 727         uint32_t mark_id;
 728         uint32_t flags2;
 729         uint32_t gfid_support = 0;
 730         int rc;
 731
 732         if (BNXT_GFID_ENABLED(bp))
 733                 gfid_support = 1;
 734
 735         cfa_code = rte_le_to_cpu_16(rxcmp1->cfa_code);
 736         flags2 = rte_le_to_cpu_32(rxcmp1->flags2);
 737         meta = rte_le_to_cpu_32(rxcmp1->metadata);
 738
 739         /*
 740          * The flags field holds extra bits of info from [6:4]
 741          * which indicate if the flow is in TCAM or EM or EEM
 742          */
 743         meta_fmt = (flags2 & BNXT_CFA_META_FMT_MASK) >>
 744                 BNXT_CFA_META_FMT_SHFT;
 745
 746         switch (meta_fmt) {
 747         case 0:
 748                 if (gfid_support) {
 749                         /* Not an LFID or GFID, a flush cmd. */
 750                         goto skip_mark;
 751                 } else {
 752                         /* LFID mode, no vlan scenario */
 753                         gfid = false;
 754                 }
 755                 break;
 756         case 4:
 757         case 5:
 758                 /*
 759                  * EM/TCAM case
 760                  * Assume that EM doesn't support Mark due to GFID
 761                  * collisions with EEM.  Simply return without setting the mark
 762                  * in the mbuf.
 763                  */
 764                 if (BNXT_CFA_META_EM_TEST(meta)) {
 765                         /*This is EM hit {EM(1), GFID[27:16], 19'd0 or vtag } */
 766                         gfid = true;
 767                         meta >>= BNXT_RX_META_CFA_CODE_SHIFT;
 768                         cfa_code |= meta << BNXT_CFA_CODE_META_SHIFT;
 769                 } else {
 770                         /*
 771                          * It is a TCAM entry, so it is an LFID.
 772                          * The TCAM IDX and Mode can also be determined
 773                          * by decoding the meta_data. We are not
 774                          * using these for now.
 775                          */
 776                 }
 777                 break;
 778         case 6:
 779         case 7:
 780                 /* EEM Case, only using gfid in EEM for now. */
 781                 gfid = true;
 782
 783                 /*
 784                  * For EEM flows, The first part of cfa_code is 16 bits.
 785                  * The second part is embedded in the
 786                  * metadata field from bit 19 onwards. The driver needs to
 787                  * ignore the first 19 bits of metadata and use the next 12
 788                  * bits as higher 12 bits of cfa_code.
 789                  */
 790                 meta >>= BNXT_RX_META_CFA_CODE_SHIFT;
 791                 cfa_code |= meta << BNXT_CFA_CODE_META_SHIFT;
 792                 break;
 793         default:
 794                 /* For other values, the cfa_code is assumed to be an LFID. */
 795                 break;
 796         }
 797
 798         rc = ulp_mark_db_mark_get(bp->ulp_ctx, gfid,
 799                                   cfa_code, vfr_flag, &mark_id);
 800         if (!rc) {
 801                 /* VF to VFR Rx path. So, skip mark_id injection in mbuf */
 802                 if (vfr_flag && *vfr_flag)
 803                         return mark_id;
 804                 /* Got the mark, write it to the mbuf and return */
 805                 mbuf->hash.fdir.hi = mark_id;
 806                 *bnxt_cfa_code_dynfield(mbuf) = cfa_code & 0xffffffffull;
 807                 mbuf->hash.fdir.id = rxcmp1->cfa_code;
 808                 mbuf->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 809                 return mark_id;
 810         }
 811
 812 skip_mark:
 813         mbuf->hash.fdir.hi = 0;
 814         mbuf->hash.fdir.id = 0;
 815
 816         return 0;
 817 }
 818
 819 void bnxt_set_mark_in_mbuf(struct bnxt *bp,
 820                            struct rx_pkt_cmpl_hi *rxcmp1,
 821                            struct rte_mbuf *mbuf)
 822 {
 823         uint32_t cfa_code = 0;
 824         uint8_t meta_fmt = 0;
 825         uint16_t flags2 = 0;
 826         uint32_t meta =  0;
 827
 828         cfa_code = rte_le_to_cpu_16(rxcmp1->cfa_code);
 829         if (!cfa_code)
 830                 return;
 831
 832         if (cfa_code && !bp->mark_table[cfa_code].valid)
 833                 return;
 834
 835         flags2 = rte_le_to_cpu_16(rxcmp1->flags2);
 836         meta = rte_le_to_cpu_32(rxcmp1->metadata);
 837         if (meta) {
 838                 meta >>= BNXT_RX_META_CFA_CODE_SHIFT;
 839
 840                 /* The flags field holds extra bits of info from [6:4]
 841                  * which indicate if the flow is in TCAM or EM or EEM
 842                  */
 843                 meta_fmt = (flags2 & BNXT_CFA_META_FMT_MASK) >>
 844                            BNXT_CFA_META_FMT_SHFT;
 845
 846                 /* meta_fmt == 4 => 'b100 => 'b10x => EM.
 847                  * meta_fmt == 5 => 'b101 => 'b10x => EM + VLAN
 848                  * meta_fmt == 6 => 'b110 => 'b11x => EEM
 849                  * meta_fmt == 7 => 'b111 => 'b11x => EEM + VLAN.
 850                  */
 851                 meta_fmt >>= BNXT_CFA_META_FMT_EM_EEM_SHFT;
 852         }
 853
 854         mbuf->hash.fdir.hi = bp->mark_table[cfa_code].mark_id;
 855         mbuf->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 856 }
 857
 858 static int bnxt_rx_pkt(struct rte_mbuf **rx_pkt,
 859                        struct bnxt_rx_queue *rxq, uint32_t *raw_cons)
 860 {
 861         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
 862         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
 863         struct rx_pkt_cmpl *rxcmp;
 864         struct rx_pkt_cmpl_hi *rxcmp1;
 865         uint32_t tmp_raw_cons = *raw_cons;
 866         uint16_t cons, raw_prod, cp_cons =
 867             RING_CMP(cpr->cp_ring_struct, tmp_raw_cons);
 868         struct rte_mbuf *mbuf;
 869         int rc = 0;
 870         uint8_t agg_buf = 0;
 871         uint16_t cmp_type;
 872         uint32_t vfr_flag = 0, mark_id = 0;
 873         struct bnxt *bp = rxq->bp;
 874
 875         rxcmp = (struct rx_pkt_cmpl *)
 876             &cpr->cp_desc_ring[cp_cons];
 877
 878         cmp_type = CMP_TYPE(rxcmp);
 879
 880         if (cmp_type == RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG) {
 881                 struct rx_tpa_v2_abuf_cmpl *rx_agg = (void *)rxcmp;
 882                 uint16_t agg_id = rte_cpu_to_le_16(rx_agg->agg_id);
 883                 struct bnxt_tpa_info *tpa_info;
 884
 885                 tpa_info = &rxr->tpa_info[agg_id];
 886                 RTE_ASSERT(tpa_info->agg_count < 16);
 887                 tpa_info->agg_arr[tpa_info->agg_count++] = *rx_agg;
 888                 rc = -EINVAL; /* Continue w/o new mbuf */
 889                 goto next_rx;
 890         }
 891
 892         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
 893         cp_cons = RING_CMP(cpr->cp_ring_struct, tmp_raw_cons);
 894         rxcmp1 = (struct rx_pkt_cmpl_hi *)&cpr->cp_desc_ring[cp_cons];
 895
 896         if (!bnxt_cpr_cmp_valid(rxcmp1, tmp_raw_cons,
 897                                 cpr->cp_ring_struct->ring_size))
 898                 return -EBUSY;
 899
 900         if (cmp_type == RX_TPA_START_CMPL_TYPE_RX_TPA_START ||
 901             cmp_type == RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2) {
 902                 bnxt_tpa_start(rxq, (struct rx_tpa_start_cmpl *)rxcmp,
 903                                (struct rx_tpa_start_cmpl_hi *)rxcmp1);
 904                 rc = -EINVAL; /* Continue w/o new mbuf */
 905                 goto next_rx;
 906         } else if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
 907                 mbuf = bnxt_tpa_end(rxq, &tmp_raw_cons,
 908                                    (struct rx_tpa_end_cmpl *)rxcmp,
 909                                    (struct rx_tpa_end_cmpl_hi *)rxcmp1);
 910                 if (unlikely(!mbuf))
 911                         return -EBUSY;
 912                 *rx_pkt = mbuf;
 913                 goto next_rx;
 914         } else if ((cmp_type != CMPL_BASE_TYPE_RX_L2) &&
 915                    (cmp_type != CMPL_BASE_TYPE_RX_L2_V2)) {
 916                 rc = -EINVAL;
 917                 goto next_rx;
 918         }
 919
 920         agg_buf = BNXT_RX_L2_AGG_BUFS(rxcmp);
 921         if (agg_buf && !bnxt_agg_bufs_valid(cpr, agg_buf, tmp_raw_cons))
 922                 return -EBUSY;
 923
 924         raw_prod = rxr->rx_raw_prod;
 925
 926         cons = rxcmp->opaque;
 927         if (unlikely(cons != rxr->rx_next_cons)) {
 928                 bnxt_discard_rx(bp, cpr, &tmp_raw_cons, rxcmp);
 929                 PMD_DRV_LOG(ERR, "RX cons %x != expected cons %x\n",
 930                             cons, rxr->rx_next_cons);
 931                 bnxt_sched_ring_reset(rxq);
 932                 rc = -EBUSY;
 933                 goto next_rx;
 934         }
 935         mbuf = bnxt_consume_rx_buf(rxr, cons);
 936         if (mbuf == NULL)
 937                 return -EBUSY;
 938
 939         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 940         mbuf->nb_segs = 1;
 941         mbuf->next = NULL;
 942         mbuf->pkt_len = rxcmp->len;
 943         mbuf->data_len = mbuf->pkt_len;
 944         mbuf->port = rxq->port_id;
 945
 946 #ifdef RTE_LIBRTE_IEEE1588
 947         if (unlikely((rte_le_to_cpu_16(rxcmp->flags_type) &
 948                       RX_PKT_CMPL_FLAGS_MASK) ==
 949                      RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP))
 950                 bnxt_get_rx_ts_p5(rxq->bp, rxcmp1->reorder);
 951 #endif
 952
 953         if (cmp_type == CMPL_BASE_TYPE_RX_L2_V2) {
 954                 bnxt_parse_csum_v2(mbuf, rxcmp1);
 955                 bnxt_parse_pkt_type_v2(mbuf, rxcmp, rxcmp1);
 956                 bnxt_rx_vlan_v2(mbuf, rxcmp, rxcmp1);
 957                 /* TODO Add support for cfa_code parsing */
 958                 goto reuse_rx_mbuf;
 959         }
 960
 961         bnxt_set_ol_flags(rxr, rxcmp, rxcmp1, mbuf);
 962
 963         mbuf->packet_type = bnxt_parse_pkt_type(rxcmp, rxcmp1);
 964
 965         if (BNXT_TRUFLOW_EN(bp))
 966                 mark_id = bnxt_ulp_set_mark_in_mbuf(rxq->bp, rxcmp1, mbuf,
 967                                                     &vfr_flag);
 968         else
 969                 bnxt_set_mark_in_mbuf(rxq->bp, rxcmp1, mbuf);
 970
 971 reuse_rx_mbuf:
 972         if (agg_buf)
 973                 bnxt_rx_pages(rxq, mbuf, &tmp_raw_cons, agg_buf, NULL);
 974
 975 #ifdef BNXT_DEBUG
 976         if (rxcmp1->errors_v2 & RX_CMP_L2_ERRORS) {
 977                 /* Re-install the mbuf back to the rx ring */
 978                 bnxt_reuse_rx_mbuf(rxr, cons, mbuf);
 979
 980                 rc = -EIO;
 981                 goto next_rx;
 982         }
 983 #endif
 984         /*
 985          * TODO: Redesign this....
 986          * If the allocation fails, the packet does not get received.
 987          * Simply returning this will result in slowly falling behind
 988          * on the producer ring buffers.
 989          * Instead, "filling up" the producer just before ringing the
 990          * doorbell could be a better solution since it will let the
 991          * producer ring starve until memory is available again pushing
 992          * the drops into hardware and getting them out of the driver
 993          * allowing recovery to a full producer ring.
 994          *
 995          * This could also help with cache usage by preventing per-packet
 996          * calls in favour of a tight loop with the same function being called
 997          * in it.
 998          */
 999         raw_prod = RING_NEXT(raw_prod);
1000         if (bnxt_alloc_rx_data(rxq, rxr, raw_prod)) {
1001                 PMD_DRV_LOG(ERR, "mbuf alloc failed with prod=0x%x\n",
1002                             raw_prod);
1003                 rc = -ENOMEM;
1004                 goto rx;
1005         }
1006         rxr->rx_raw_prod = raw_prod;
1007         rxr->rx_next_cons = RING_IDX(rxr->rx_ring_struct, RING_NEXT(cons));
1008
1009         if (BNXT_TRUFLOW_EN(bp) && (BNXT_VF_IS_TRUSTED(bp) || BNXT_PF(bp)) &&
1010             vfr_flag) {
1011                 bnxt_vfr_recv(mark_id, rxq->queue_id, mbuf);
1012                 /* Now return an error so that nb_rx_pkts is not
1013                  * incremented.
1014                  * This packet was meant to be given to the representor.
1015                  * So no need to account the packet and give it to
1016                  * parent Rx burst function.
1017                  */
1018                 rc = -ENODEV;
1019                 goto next_rx;
1020         }
1021         /*
1022          * All MBUFs are allocated with the same size under DPDK,
1023          * no optimization for rx_copy_thresh
1024          */
1025 rx:
1026         *rx_pkt = mbuf;
1027
1028 next_rx:
1029
1030         *raw_cons = tmp_raw_cons;
1031
1032         return rc;
1033 }
1034
1035 uint16_t bnxt_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1036                                uint16_t nb_pkts)
1037 {
1038         struct bnxt_rx_queue *rxq = rx_queue;
1039         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1040         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1041         uint16_t rx_raw_prod = rxr->rx_raw_prod;
1042         uint16_t ag_raw_prod = rxr->ag_raw_prod;
1043         uint32_t raw_cons = cpr->cp_raw_cons;
1044         bool alloc_failed = false;
1045         uint32_t cons;
1046         int nb_rx_pkts = 0;
1047         int nb_rep_rx_pkts = 0;
1048         struct rx_pkt_cmpl *rxcmp;
1049         int rc = 0;
1050         bool evt = false;
1051
1052         if (unlikely(is_bnxt_in_error(rxq->bp)))
1053                 return 0;
1054
1055         /* If Rx Q was stopped return */
1056         if (unlikely(!rxq->rx_started))
1057                 return 0;
1058
1059 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1060         /*
1061          * Replenish buffers if needed when a transition has been made from
1062          * vector- to non-vector- receive processing.
1063          */
1064         while (unlikely(rxq->rxrearm_nb)) {
1065                 if (!bnxt_alloc_rx_data(rxq, rxr, rxq->rxrearm_start)) {
1066                         rxr->rx_raw_prod = rxq->rxrearm_start;
1067                         bnxt_db_write(&rxr->rx_db, rxr->rx_raw_prod);
1068                         rxq->rxrearm_start++;
1069                         rxq->rxrearm_nb--;
1070                 } else {
1071                         /* Retry allocation on next call. */
1072                         break;
1073                 }
1074         }
1075 #endif
1076
1077         /* Handle RX burst request */
1078         while (1) {
1079                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1080                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1081
1082                 if (!bnxt_cpr_cmp_valid(rxcmp, raw_cons,
1083                                         cpr->cp_ring_struct->ring_size))
1084                         break;
1085                 if (CMP_TYPE(rxcmp) == CMPL_BASE_TYPE_HWRM_DONE) {
1086                         PMD_DRV_LOG(ERR, "Rx flush done\n");
1087                 } else if ((CMP_TYPE(rxcmp) >= CMPL_BASE_TYPE_RX_TPA_START_V2) &&
1088                      (CMP_TYPE(rxcmp) <= RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG)) {
1089                         rc = bnxt_rx_pkt(&rx_pkts[nb_rx_pkts], rxq, &raw_cons);
1090                         if (!rc)
1091                                 nb_rx_pkts++;
1092                         else if (rc == -EBUSY)  /* partial completion */
1093                                 break;
1094                         else if (rc == -ENODEV) /* completion for representor */
1095                                 nb_rep_rx_pkts++;
1096                         else if (rc == -ENOMEM) {
1097                                 nb_rx_pkts++;
1098                                 alloc_failed = true;
1099                         }
1100                 } else if (!BNXT_NUM_ASYNC_CPR(rxq->bp)) {
1101                         evt =
1102                         bnxt_event_hwrm_resp_handler(rxq->bp,
1103                                                      (struct cmpl_base *)rxcmp);
1104                         /* If the async event is Fatal error, return */
1105                         if (unlikely(is_bnxt_in_error(rxq->bp)))
1106                                 goto done;
1107                 }
1108
1109                 raw_cons = NEXT_RAW_CMP(raw_cons);
1110                 if (nb_rx_pkts == nb_pkts || nb_rep_rx_pkts == nb_pkts || evt)
1111                         break;
1112         }
1113
1114         cpr->cp_raw_cons = raw_cons;
1115         if (!nb_rx_pkts && !nb_rep_rx_pkts && !evt) {
1116                 /*
1117                  * For PMD, there is no need to keep on pushing to REARM
1118                  * the doorbell if there are no new completions
1119                  */
1120                 goto done;
1121         }
1122
1123         /* Ring the completion queue doorbell. */
1124         bnxt_db_cq(cpr);
1125
1126         /* Ring the receive descriptor doorbell. */
1127         if (rx_raw_prod != rxr->rx_raw_prod)
1128                 bnxt_db_write(&rxr->rx_db, rxr->rx_raw_prod);
1129
1130         /* Ring the AGG ring DB */
1131         if (ag_raw_prod != rxr->ag_raw_prod)
1132                 bnxt_db_write(&rxr->ag_db, rxr->ag_raw_prod);
1133
1134         /* Attempt to alloc Rx buf in case of a previous allocation failure. */
1135         if (alloc_failed) {
1136                 int cnt;
1137
1138                 rx_raw_prod = RING_NEXT(rx_raw_prod);
1139                 for (cnt = 0; cnt < nb_rx_pkts + nb_rep_rx_pkts; cnt++) {
1140                         struct rte_mbuf **rx_buf;
1141                         uint16_t ndx;
1142
1143                         ndx = RING_IDX(rxr->rx_ring_struct, rx_raw_prod + cnt);
1144                         rx_buf = &rxr->rx_buf_ring[ndx];
1145
1146                         /* Buffer already allocated for this index. */
1147                         if (*rx_buf != NULL && *rx_buf != &rxq->fake_mbuf)
1148                                 continue;
1149
1150                         /* This slot is empty. Alloc buffer for Rx */
1151                         if (!bnxt_alloc_rx_data(rxq, rxr, rx_raw_prod + cnt)) {
1152                                 rxr->rx_raw_prod = rx_raw_prod + cnt;
1153                                 bnxt_db_write(&rxr->rx_db, rxr->rx_raw_prod);
1154                         } else {
1155                                 PMD_DRV_LOG(ERR, "Alloc  mbuf failed\n");
1156                                 break;
1157                         }
1158                 }
1159         }
1160
1161 done:
1162         return nb_rx_pkts;
1163 }
1164
1165 /*
1166  * Dummy DPDK callback for RX.
1167  *
1168  * This function is used to temporarily replace the real callback during
1169  * unsafe control operations on the queue, or in case of error.
1170  */
1171 uint16_t
1172 bnxt_dummy_recv_pkts(void *rx_queue __rte_unused,
1173                      struct rte_mbuf **rx_pkts __rte_unused,
1174                      uint16_t nb_pkts __rte_unused)
1175 {
1176         return 0;
1177 }
1178
1179 void bnxt_free_rx_rings(struct bnxt *bp)
1180 {
1181         int i;
1182         struct bnxt_rx_queue *rxq;
1183
1184         if (!bp->rx_queues)
1185                 return;
1186
1187         for (i = 0; i < (int)bp->rx_nr_rings; i++) {
1188                 rxq = bp->rx_queues[i];
1189                 if (!rxq)
1190                         continue;
1191
1192                 bnxt_free_ring(rxq->rx_ring->rx_ring_struct);
1193                 rte_free(rxq->rx_ring->rx_ring_struct);
1194
1195                 /* Free the Aggregator ring */
1196                 bnxt_free_ring(rxq->rx_ring->ag_ring_struct);
1197                 rte_free(rxq->rx_ring->ag_ring_struct);
1198                 rxq->rx_ring->ag_ring_struct = NULL;
1199
1200                 rte_free(rxq->rx_ring);
1201
1202                 bnxt_free_ring(rxq->cp_ring->cp_ring_struct);
1203                 rte_free(rxq->cp_ring->cp_ring_struct);
1204                 rte_free(rxq->cp_ring);
1205
1206                 rte_free(rxq);
1207                 bp->rx_queues[i] = NULL;
1208         }
1209 }
1210
1211 int bnxt_init_rx_ring_struct(struct bnxt_rx_queue *rxq, unsigned int socket_id)
1212 {
1213         struct bnxt_cp_ring_info *cpr;
1214         struct bnxt_rx_ring_info *rxr;
1215         struct bnxt_ring *ring;
1216
1217         rxq->rx_buf_size = BNXT_MAX_PKT_LEN + sizeof(struct rte_mbuf);
1218
1219         rxr = rte_zmalloc_socket("bnxt_rx_ring",
1220                                  sizeof(struct bnxt_rx_ring_info),
1221                                  RTE_CACHE_LINE_SIZE, socket_id);
1222         if (rxr == NULL)
1223                 return -ENOMEM;
1224         rxq->rx_ring = rxr;
1225
1226         ring = rte_zmalloc_socket("bnxt_rx_ring_struct",
1227                                    sizeof(struct bnxt_ring),
1228                                    RTE_CACHE_LINE_SIZE, socket_id);
1229         if (ring == NULL)
1230                 return -ENOMEM;
1231         rxr->rx_ring_struct = ring;
1232         ring->ring_size = rte_align32pow2(rxq->nb_rx_desc);
1233         ring->ring_mask = ring->ring_size - 1;
1234         ring->bd = (void *)rxr->rx_desc_ring;
1235         ring->bd_dma = rxr->rx_desc_mapping;
1236
1237         /* Allocate extra rx ring entries for vector rx. */
1238         ring->vmem_size = sizeof(struct rte_mbuf *) *
1239                           (ring->ring_size + BNXT_RX_EXTRA_MBUF_ENTRIES);
1240
1241         ring->vmem = (void **)&rxr->rx_buf_ring;
1242         ring->fw_ring_id = INVALID_HW_RING_ID;
1243
1244         cpr = rte_zmalloc_socket("bnxt_rx_ring",
1245                                  sizeof(struct bnxt_cp_ring_info),
1246                                  RTE_CACHE_LINE_SIZE, socket_id);
1247         if (cpr == NULL)
1248                 return -ENOMEM;
1249         rxq->cp_ring = cpr;
1250
1251         ring = rte_zmalloc_socket("bnxt_rx_ring_struct",
1252                                    sizeof(struct bnxt_ring),
1253                                    RTE_CACHE_LINE_SIZE, socket_id);
1254         if (ring == NULL)
1255                 return -ENOMEM;
1256         cpr->cp_ring_struct = ring;
1257
1258         /* Allocate two completion slots per entry in desc ring. */
1259         ring->ring_size = rxr->rx_ring_struct->ring_size * 2;
1260         ring->ring_size *= AGG_RING_SIZE_FACTOR;
1261
1262         ring->ring_size = rte_align32pow2(ring->ring_size);
1263         ring->ring_mask = ring->ring_size - 1;
1264         ring->bd = (void *)cpr->cp_desc_ring;
1265         ring->bd_dma = cpr->cp_desc_mapping;
1266         ring->vmem_size = 0;
1267         ring->vmem = NULL;
1268         ring->fw_ring_id = INVALID_HW_RING_ID;
1269
1270         /* Allocate Aggregator rings */
1271         ring = rte_zmalloc_socket("bnxt_rx_ring_struct",
1272                                    sizeof(struct bnxt_ring),
1273                                    RTE_CACHE_LINE_SIZE, socket_id);
1274         if (ring == NULL)
1275                 return -ENOMEM;
1276         rxr->ag_ring_struct = ring;
1277         ring->ring_size = rte_align32pow2(rxq->nb_rx_desc *
1278                                           AGG_RING_SIZE_FACTOR);
1279         ring->ring_mask = ring->ring_size - 1;
1280         ring->bd = (void *)rxr->ag_desc_ring;
1281         ring->bd_dma = rxr->ag_desc_mapping;
1282         ring->vmem_size = ring->ring_size * sizeof(struct rte_mbuf *);
1283         ring->vmem = (void **)&rxr->ag_buf_ring;
1284         ring->fw_ring_id = INVALID_HW_RING_ID;
1285
1286         return 0;
1287 }
1288
1289 static void bnxt_init_rxbds(struct bnxt_ring *ring, uint32_t type,
1290                             uint16_t len)
1291 {
1292         uint32_t j;
1293         struct rx_prod_pkt_bd *rx_bd_ring = (struct rx_prod_pkt_bd *)ring->bd;
1294
1295         if (!rx_bd_ring)
1296                 return;
1297         for (j = 0; j < ring->ring_size; j++) {
1298                 rx_bd_ring[j].flags_type = rte_cpu_to_le_16(type);
1299                 rx_bd_ring[j].len = rte_cpu_to_le_16(len);
1300                 rx_bd_ring[j].opaque = j;
1301         }
1302 }
1303
1304 int bnxt_init_one_rx_ring(struct bnxt_rx_queue *rxq)
1305 {
1306         struct bnxt_rx_ring_info *rxr;
1307         struct bnxt_ring *ring;
1308         uint32_t raw_prod, type;
1309         unsigned int i;
1310         uint16_t size;
1311
1312         /* Initialize packet type table. */
1313         bnxt_init_ptype_table();
1314
1315         size = rte_pktmbuf_data_room_size(rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
1316         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
1317
1318         type = RX_PROD_PKT_BD_TYPE_RX_PROD_PKT;
1319
1320         rxr = rxq->rx_ring;
1321         ring = rxr->rx_ring_struct;
1322         bnxt_init_rxbds(ring, type, size);
1323
1324         /* Initialize offload flags parsing table. */
1325         bnxt_init_ol_flags_tables(rxq);
1326
1327         raw_prod = rxr->rx_raw_prod;
1328         for (i = 0; i < ring->ring_size; i++) {
1329                 if (unlikely(!rxr->rx_buf_ring[i])) {
1330                         if (bnxt_alloc_rx_data(rxq, rxr, raw_prod) != 0) {
1331                                 PMD_DRV_LOG(WARNING,
1332                                             "init'ed rx ring %d with %d/%d mbufs only\n",
1333                                             rxq->queue_id, i, ring->ring_size);
1334                                 break;
1335                         }
1336                 }
1337                 rxr->rx_raw_prod = raw_prod;
1338                 raw_prod = RING_NEXT(raw_prod);
1339         }
1340
1341         /* Initialize dummy mbuf pointers for vector mode rx. */
1342         for (i = ring->ring_size;
1343              i < ring->ring_size + BNXT_RX_EXTRA_MBUF_ENTRIES; i++) {
1344                 rxr->rx_buf_ring[i] = &rxq->fake_mbuf;
1345         }
1346
1347         ring = rxr->ag_ring_struct;
1348         type = RX_PROD_AGG_BD_TYPE_RX_PROD_AGG;
1349         bnxt_init_rxbds(ring, type, size);
1350         raw_prod = rxr->ag_raw_prod;
1351
1352         for (i = 0; i < ring->ring_size; i++) {
1353                 if (unlikely(!rxr->ag_buf_ring[i])) {
1354                         if (bnxt_alloc_ag_data(rxq, rxr, raw_prod) != 0) {
1355                                 PMD_DRV_LOG(WARNING,
1356                                             "init'ed AG ring %d with %d/%d mbufs only\n",
1357                                             rxq->queue_id, i, ring->ring_size);
1358                                 break;
1359                         }
1360                 }
1361                 rxr->ag_raw_prod = raw_prod;
1362                 raw_prod = RING_NEXT(raw_prod);
1363         }
1364         PMD_DRV_LOG(DEBUG, "AGG Done!\n");
1365
1366         if (rxr->tpa_info) {
1367                 unsigned int max_aggs = BNXT_TPA_MAX_AGGS(rxq->bp);
1368
1369                 for (i = 0; i < max_aggs; i++) {
1370                         if (unlikely(!rxr->tpa_info[i].mbuf)) {
1371                                 rxr->tpa_info[i].mbuf =
1372                                         __bnxt_alloc_rx_data(rxq->mb_pool);
1373                                 if (!rxr->tpa_info[i].mbuf) {
1374                                         rte_atomic64_inc(&rxq->rx_mbuf_alloc_fail);
1375                                         return -ENOMEM;
1376                                 }
1377                         }
1378                 }
1379         }
1380         PMD_DRV_LOG(DEBUG, "TPA alloc Done!\n");
1381
1382         return 0;
1383 }
1384
1385 /* Sweep the Rx completion queue till HWRM_DONE for ring flush is received.
1386  * The mbufs will not be freed in this call.
1387  * They will be freed during ring free as a part of mem cleanup.
1388  */
1389 int bnxt_flush_rx_cmp(struct bnxt_cp_ring_info *cpr)
1390 {
1391         struct bnxt_ring *cp_ring_struct = cpr->cp_ring_struct;
1392         uint32_t ring_mask = cp_ring_struct->ring_mask;
1393         uint32_t raw_cons = cpr->cp_raw_cons;
1394         struct rx_pkt_cmpl *rxcmp;
1395         uint32_t nb_rx = 0;
1396         uint32_t cons;
1397
1398         do {
1399                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1400                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1401
1402                 if (CMP_TYPE(rxcmp) == CMPL_BASE_TYPE_HWRM_DONE)
1403                         return 1;
1404
1405                 raw_cons = NEXT_RAW_CMP(raw_cons);
1406                 nb_rx++;
1407         } while (nb_rx < ring_mask);
1408
1409         cpr->cp_raw_cons = raw_cons;
1410
1411         /* Ring the completion queue doorbell. */
1412         bnxt_db_cq(cpr);
1413
1414         return 0;
1415 }