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34 #ifndef _HSI_STRUCT_DEF_EXTERNAL_H_
35 #define _HSI_STRUCT_DEF_EXTERNAL_H_
38 * per-context HW statistics -- chip view
41 struct ctx_hw_stats64 {
42 uint64_t rx_ucast_pkts;
43 uint64_t rx_mcast_pkts;
44 uint64_t rx_bcast_pkts;
45 uint64_t rx_drop_pkts;
47 uint64_t rx_ucast_bytes;
48 uint64_t rx_mcast_bytes;
49 uint64_t rx_bcast_bytes;
51 uint64_t tx_ucast_pkts;
52 uint64_t tx_mcast_pkts;
53 uint64_t tx_bcast_pkts;
54 uint64_t tx_drop_pkts;
56 uint64_t tx_ucast_bytes;
57 uint64_t tx_mcast_bytes;
58 uint64_t tx_bcast_bytes;
66 /* HW Resource Manager Specification 1.2.0 */
67 #define HWRM_VERSION_MAJOR 1
68 #define HWRM_VERSION_MINOR 2
69 #define HWRM_VERSION_UPDATE 0
72 * Following is the signature for HWRM message field that indicates not
73 * applicable (All F's). Need to cast it the size of the field if needed.
75 #define HWRM_NA_SIGNATURE ((uint32_t)(-1))
76 #define HWRM_MAX_REQ_LEN (128) /* hwrm_func_buf_rgtr */
77 #define HWRM_MAX_RESP_LEN (176) /* hwrm_func_qstats */
78 #define HW_HASH_INDEX_SIZE 0x80 /* 7 bit indirection table index. */
79 #define HW_HASH_KEY_SIZE 40
80 #define HWRM_RESP_VALID_KEY 1 /* valid key for HWRM response */
85 #define HWRM_VER_GET (UINT32_C(0x0))
86 #define HWRM_FUNC_QCAPS (UINT32_C(0x15))
87 #define HWRM_FUNC_DRV_UNRGTR (UINT32_C(0x1a))
88 #define HWRM_FUNC_DRV_RGTR (UINT32_C(0x1d))
89 #define HWRM_PORT_PHY_CFG (UINT32_C(0x20))
90 #define HWRM_QUEUE_QPORTCFG (UINT32_C(0x30))
91 #define HWRM_CFA_L2_FILTER_ALLOC (UINT32_C(0x90))
92 #define HWRM_CFA_L2_FILTER_FREE (UINT32_C(0x91))
93 #define HWRM_CFA_L2_FILTER_CFG (UINT32_C(0x92))
94 #define HWRM_CFA_L2_SET_RX_MASK (UINT32_C(0x93))
95 #define HWRM_STAT_CTX_CLR_STATS (UINT32_C(0xb3))
96 #define HWRM_EXEC_FWD_RESP (UINT32_C(0xd0))
99 #define HWRM_ERR_CODE_INVALID_PARAMS (UINT32_C(0x2))
100 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED (UINT32_C(0x3))
102 /* Short TX BD (16 bytes) */
105 * All bits in this field must be valid on the first BD of a packet.
106 * Only the packet_end bit must be valid for the remaining BDs of a
109 /* This value identifies the type of buffer descriptor. */
110 #define TX_BD_SHORT_TYPE_MASK UINT32_C(0x3f)
111 #define TX_BD_SHORT_TYPE_SFT 0
113 * Indicates that this BD is 16B long and is used for normal L2
114 * packet transmission.
116 #define TX_BD_SHORT_TYPE_TX_BD_SHORT (UINT32_C(0x0) << 0)
118 * If set to 1, the packet ends with the data in the buffer pointed to
119 * by this descriptor. This flag must be valid on every BD.
121 #define TX_BD_SHORT_FLAGS_PACKET_END UINT32_C(0x40)
123 * If set to 1, the device will not generate a completion for this
124 * transmit packet unless there is an error in it's processing. If this
125 * bit is set to 0, then the packet will be completed normally. This bit
126 * must be valid only on the first BD of a packet.
128 #define TX_BD_SHORT_FLAGS_NO_CMPL UINT32_C(0x80)
130 * This value indicates how many 16B BD locations are consumed in the
131 * ring by this packet. A value of 1 indicates that this BD is the only
132 * BD (and that the it is a short BD). A value of 3 indicates either 3
133 * short BDs or 1 long BD and one short BD in the packet. A value of 0
134 * indicates that there are 32 BD locations in the packet (the maximum).
135 * This field is valid only on the first BD of a packet.
137 #define TX_BD_SHORT_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
138 #define TX_BD_SHORT_FLAGS_BD_CNT_SFT 8
140 * This value is a hint for the length of the entire packet. It is used
141 * by the chip to optimize internal processing. The packet will be
142 * dropped if the hint is too short. This field is valid only on the
143 * first BD of a packet.
145 #define TX_BD_SHORT_FLAGS_LHINT_MASK UINT32_C(0x6000)
146 #define TX_BD_SHORT_FLAGS_LHINT_SFT 13
147 /* indicates packet length < 512B */
148 #define TX_BD_SHORT_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
149 /* indicates 512 <= packet length < 1KB */
150 #define TX_BD_SHORT_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
151 /* indicates 1KB <= packet length < 2KB */
152 #define TX_BD_SHORT_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
153 /* indicates packet length >= 2KB */
154 #define TX_BD_SHORT_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
155 #define TX_BD_SHORT_FLAGS_LHINT_LAST TX_BD_SHORT_FLAGS_LHINT_GTE2K
157 * If set to 1, the device immediately updates the Send Consumer Index
158 * after the buffer associated with this descriptor has been transferred
159 * via DMA to NIC memory from host memory. An interrupt may or may not
160 * be generated according to the state of the interrupt avoidance
161 * mechanisms. If this bit is set to 0, then the Consumer Index is only
162 * updated as soon as one of the host interrupt coalescing conditions
163 * has been met. This bit must be valid on the first BD of a packet.
165 #define TX_BD_SHORT_FLAGS_COAL_NOW UINT32_C(0x8000)
167 * All bits in this field must be valid on the first BD of a packet.
168 * Only the packet_end bit must be valid for the remaining BDs of a
171 #define TX_BD_SHORT_FLAGS_MASK UINT32_C(0xffc0)
172 #define TX_BD_SHORT_FLAGS_SFT 6
176 * This is the length of the host physical buffer this BD describes in
177 * bytes. This field must be valid on all BDs of a packet.
181 * The opaque data field is pass through to the completion and can be
182 * used for any data that the driver wants to associate with the
183 * transmit BD. This field must be valid on the first BD of a packet.
188 * This is the host physical address for the portion of the packet
189 * described by this TX BD. This value must be valid on all BDs of a
193 } __attribute__((packed));
195 /* Long TX BD (32 bytes split to 2 16-byte struct) */
198 * All bits in this field must be valid on the first BD of a packet.
199 * Only the packet_end bit must be valid for the remaining BDs of a
202 /* This value identifies the type of buffer descriptor. */
203 #define TX_BD_LONG_TYPE_MASK UINT32_C(0x3f)
204 #define TX_BD_LONG_TYPE_SFT 0
206 * Indicates that this BD is 32B long and is used for normal L2
207 * packet transmission.
209 #define TX_BD_LONG_TYPE_TX_BD_LONG (UINT32_C(0x10) << 0)
211 * If set to 1, the packet ends with the data in the buffer pointed to
212 * by this descriptor. This flag must be valid on every BD.
214 #define TX_BD_LONG_FLAGS_PACKET_END UINT32_C(0x40)
216 * If set to 1, the device will not generate a completion for this
217 * transmit packet unless there is an error in it's processing. If this
218 * bit is set to 0, then the packet will be completed normally. This bit
219 * must be valid only on the first BD of a packet.
221 #define TX_BD_LONG_FLAGS_NO_CMPL UINT32_C(0x80)
223 * This value indicates how many 16B BD locations are consumed in the
224 * ring by this packet. A value of 1 indicates that this BD is the only
225 * BD (and that the it is a short BD). A value of 3 indicates either 3
226 * short BDs or 1 long BD and one short BD in the packet. A value of 0
227 * indicates that there are 32 BD locations in the packet (the maximum).
228 * This field is valid only on the first BD of a packet.
230 #define TX_BD_LONG_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
231 #define TX_BD_LONG_FLAGS_BD_CNT_SFT 8
233 * This value is a hint for the length of the entire packet. It is used
234 * by the chip to optimize internal processing. The packet will be
235 * dropped if the hint is too short. This field is valid only on the
236 * first BD of a packet.
238 #define TX_BD_LONG_FLAGS_LHINT_MASK UINT32_C(0x6000)
239 #define TX_BD_LONG_FLAGS_LHINT_SFT 13
240 /* indicates packet length < 512B */
241 #define TX_BD_LONG_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
242 /* indicates 512 <= packet length < 1KB */
243 #define TX_BD_LONG_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
244 /* indicates 1KB <= packet length < 2KB */
245 #define TX_BD_LONG_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
246 /* indicates packet length >= 2KB */
247 #define TX_BD_LONG_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
248 #define TX_BD_LONG_FLAGS_LHINT_LAST TX_BD_LONG_FLAGS_LHINT_GTE2K
250 * If set to 1, the device immediately updates the Send Consumer Index
251 * after the buffer associated with this descriptor has been transferred
252 * via DMA to NIC memory from host memory. An interrupt may or may not
253 * be generated according to the state of the interrupt avoidance
254 * mechanisms. If this bit is set to 0, then the Consumer Index is only
255 * updated as soon as one of the host interrupt coalescing conditions
256 * has been met. This bit must be valid on the first BD of a packet.
258 #define TX_BD_LONG_FLAGS_COAL_NOW UINT32_C(0x8000)
260 * All bits in this field must be valid on the first BD of a packet.
261 * Only the packet_end bit must be valid for the remaining BDs of a
264 #define TX_BD_LONG_FLAGS_MASK UINT32_C(0xffc0)
265 #define TX_BD_LONG_FLAGS_SFT 6
269 * This is the length of the host physical buffer this BD describes in
270 * bytes. This field must be valid on all BDs of a packet.
275 * The opaque data field is pass through to the completion and can be
276 * used for any data that the driver wants to associate with the
277 * transmit BD. This field must be valid on the first BD of a packet.
282 * This is the host physical address for the portion of the packet
283 * described by this TX BD. This value must be valid on all BDs of a
287 } __attribute__((packed));
289 /* last 16 bytes of Long TX BD */
291 struct tx_bd_long_hi {
293 * All bits in this field must be valid on the first BD of a packet.
294 * Their value on other BDs of the packet will be ignored.
297 * If set to 1, the controller replaces the TCP/UPD checksum fields of
298 * normal TCP/UPD checksum, or the inner TCP/UDP checksum field of the
299 * encapsulated TCP/UDP packets with the hardware calculated TCP/UDP
300 * checksum for the packet associated with this descriptor. This bit
301 * must be valid on the first BD of a packet.
303 #define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
305 * If set to 1, the controller replaces the IP checksum of the normal
306 * packets, or the inner IP checksum of the encapsulated packets with
307 * the hardware calculated IP checksum for the packet associated with
308 * this descriptor. This bit must be valid on the first BD of a packet.
310 #define TX_BD_LONG_LFLAGS_IP_CHKSUM UINT32_C(0x2)
312 * If set to 1, the controller will not append an Ethernet CRC to the
313 * end of the frame. This bit must be valid on the first BD of a packet.
314 * Packet must be 64B or longer when this flag is set. It is not useful
315 * to use this bit with any form of TX offload such as CSO or LSO. The
316 * intent is that the packet from the host already has a valid Ethernet
319 #define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4)
321 * If set to 1, the device will record the time at which the packet was
322 * actually transmitted at the TX MAC. This bit must be valid on the
323 * first BD of a packet.
325 #define TX_BD_LONG_LFLAGS_STAMP UINT32_C(0x8)
327 * If set to 1, The controller replaces the tunnel IP checksum field
328 * with hardware calculated IP checksum for the IP header of the packet
329 * associated with this descriptor. In case of VXLAN, the controller
330 * also replaces the outer header UDP checksum with hardware calculated
331 * UDP checksum for the packet associated with this descriptor.
333 #define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
335 * If set to 1, the device will treat this packet with LSO(Large Send
336 * Offload) processing for both normal or encapsulated packets, which is
337 * a form of TCP segmentation. When this bit is 1, the hdr_size and mss
338 * fields must be valid. The driver doesn't need to set t_ip_chksum,
339 * ip_chksum, and tcp_udp_chksum flags since the controller will replace
340 * the appropriate checksum fields for segmented packets. When this bit
341 * is 1, the hdr_size and mss fields must be valid.
343 #define TX_BD_LONG_LFLAGS_LSO UINT32_C(0x20)
345 * If set to zero when LSO is '1', then the IPID will be treated as a
346 * 16b number and will be wrapped if it exceeds a value of 0xffff. If
347 * set to one when LSO is '1', then the IPID will be treated as a 15b
348 * number and will be wrapped if it exceeds a value 0f 0x7fff.
350 #define TX_BD_LONG_LFLAGS_IPID_FMT UINT32_C(0x40)
352 * If set to zero when LSO is '1', then the IPID of the tunnel IP header
353 * will not be modified during LSO operations. If set to one when LSO is
354 * '1', then the IPID of the tunnel IP header will be incremented for
355 * each subsequent segment of an LSO operation.
357 #define TX_BD_LONG_LFLAGS_T_IPID UINT32_C(0x80)
359 * If set to '1', then the RoCE ICRC will be appended to the packet.
360 * Packet must be a valid RoCE format packet.
362 #define TX_BD_LONG_LFLAGS_ROCE_CRC UINT32_C(0x100)
364 * If set to '1', then the FCoE CRC will be appended to the packet.
365 * Packet must be a valid FCoE format packet.
367 #define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200)
371 * When LSO is '1', this field must contain the offset of the TCP
372 * payload from the beginning of the packet in as 16b words. In case of
373 * encapsulated/tunneling packet, this field contains the offset of the
374 * inner TCP payload from beginning of the packet as 16-bit words. This
375 * value must be valid on the first BD of a packet.
377 #define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff)
378 #define TX_BD_LONG_HDR_SIZE_SFT 0
382 * This is the MSS value that will be used to do the LSO processing. The
383 * value is the length in bytes of the TCP payload for each segment
384 * generated by the LSO operation. This value must be valid on the first
387 #define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff)
388 #define TX_BD_LONG_MSS_SFT 0
394 * This value selects a CFA action to perform on the packet. Set this
395 * value to zero if no CFA action is desired. This value must be valid
396 * on the first BD of a packet.
401 * This value is action meta-data that defines CFA edit operations that
402 * are done in addition to any action editing.
404 /* When key=1, This is the VLAN tag VID value. */
405 #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
406 #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0
407 /* When key=1, This is the VLAN tag DE value. */
408 #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000)
409 /* When key=1, This is the VLAN tag PRI value. */
410 #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
411 #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13
412 /* When key=1, This is the VLAN tag TPID select value. */
413 #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
414 #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16
416 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
418 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
420 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
422 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
424 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
425 /* Value programmed in CFA VLANTPID register. */
426 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
427 #define TX_BD_LONG_CFA_META_VLAN_TPID_LAST \
428 TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG
429 /* When key=1, This is the VLAN tag TPID select value. */
430 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
431 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19
433 * This field identifies the type of edit to be performed on the packet.
434 * This value must be valid on the first BD of a packet.
436 #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000)
437 #define TX_BD_LONG_CFA_META_KEY_SFT 28
439 #define TX_BD_LONG_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
441 * - meta[17:16] - TPID select value (0 = 0x8100). - meta[15:12]
442 * - PRI/DE value. - meta[11:0] - VID value.
444 #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
445 #define TX_BD_LONG_CFA_META_KEY_LAST TX_BD_LONG_CFA_META_KEY_VLAN_TAG
447 } __attribute__((packed));
449 /* RX Producer Packet BD (16 bytes) */
450 struct rx_prod_pkt_bd {
451 /* This value identifies the type of buffer descriptor. */
452 #define RX_PROD_PKT_BD_TYPE_MASK UINT32_C(0x3f)
453 #define RX_PROD_PKT_BD_TYPE_SFT 0
455 * Indicates that this BD is 16B long and is an RX Producer (ie.
456 * empty) buffer descriptor.
458 #define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT (UINT32_C(0x4) << 0)
460 * If set to 1, the packet will be placed at the address plus 2B. The 2
461 * Bytes of padding will be written as zero.
464 * This is intended to be used when the host buffer is cache-line
465 * aligned to produce packets that are easy to parse in host memory
466 * while still allowing writes to be cache line aligned.
468 #define RX_PROD_PKT_BD_FLAGS_SOP_PAD UINT32_C(0x40)
470 * If set to 1, the packet write will be padded out to the nearest
471 * cache-line with zero value padding.
474 * If receive buffers start/end on cache-line boundaries, this feature
475 * will ensure that all data writes on the PCI bus start/end on cache
478 #define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80)
480 * This value is the number of additional buffers in the ring that
481 * describe the buffer space to be consumed for the this packet. If the
482 * value is zero, then the packet must fit within the space described by
483 * this BD. If this value is 1 or more, it indicates how many additional
484 * "buffer" BDs are in the ring immediately following this BD to be used
485 * for the same network packet. Even if the packet to be placed does not
486 * need all the additional buffers, they will be consumed anyway.
488 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300)
489 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT 8
490 #define RX_PROD_PKT_BD_FLAGS_MASK UINT32_C(0xffc0)
491 #define RX_PROD_PKT_BD_FLAGS_SFT 6
495 * This is the length in Bytes of the host physical buffer where data
496 * for the packet may be placed in host memory.
499 * While this is a Byte resolution value, it is often advantageous to
500 * ensure that the buffers provided end on a host cache line.
505 * The opaque data field is pass through to the completion and can be
506 * used for any data that the driver wants to associate with this
507 * receive buffer set.
512 * This is the host physical address where data for the packet may by
513 * placed in host memory.
516 * While this is a Byte resolution value, it is often advantageous to
517 * ensure that the buffers provide start on a host cache line.
520 } __attribute__((packed));
522 /* Completion Ring Structures */
523 /* Note: This structure is used by the HWRM to communicate HWRM Error. */
524 /* Base Completion Record (16 bytes) */
528 * This field indicates the exact type of the completion. By convention,
529 * the LSB identifies the length of the record in 16B units. Even values
530 * indicate 16B records. Odd values indicate 32B records.
532 #define CMPL_BASE_TYPE_MASK UINT32_C(0x3f)
533 #define CMPL_BASE_TYPE_SFT 0
534 /* TX L2 completion: Completion of TX packet. Length = 16B */
535 #define CMPL_BASE_TYPE_TX_L2 (UINT32_C(0x0) << 0)
537 * RX L2 completion: Completion of and L2 RX packet.
540 #define CMPL_BASE_TYPE_RX_L2 (UINT32_C(0x11) << 0)
542 * RX Aggregation Buffer completion : Completion of an L2
543 * aggregation buffer in support of TPA, HDS, or Jumbo packet
544 * completion. Length = 16B
546 #define CMPL_BASE_TYPE_RX_AGG (UINT32_C(0x12) << 0)
548 * RX L2 TPA Start Completion: Completion at the beginning of a
549 * TPA operation. Length = 32B
551 #define CMPL_BASE_TYPE_RX_TPA_START (UINT32_C(0x13) << 0)
553 * RX L2 TPA End Completion: Completion at the end of a TPA
554 * operation. Length = 32B
556 #define CMPL_BASE_TYPE_RX_TPA_END (UINT32_C(0x15) << 0)
558 * Statistics Ejection Completion: Completion of statistics data
559 * ejection buffer. Length = 16B
561 #define CMPL_BASE_TYPE_STAT_EJECT (UINT32_C(0x1a) << 0)
562 /* HWRM Command Completion: Completion of an HWRM command. */
563 #define CMPL_BASE_TYPE_HWRM_DONE (UINT32_C(0x20) << 0)
564 /* Forwarded HWRM Request */
565 #define CMPL_BASE_TYPE_HWRM_FWD_REQ (UINT32_C(0x22) << 0)
566 /* Forwarded HWRM Response */
567 #define CMPL_BASE_TYPE_HWRM_FWD_RESP (UINT32_C(0x24) << 0)
568 /* HWRM Asynchronous Event Information */
569 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT (UINT32_C(0x2e) << 0)
570 /* CQ Notification */
571 #define CMPL_BASE_TYPE_CQ_NOTIFICATION (UINT32_C(0x30) << 0)
572 /* SRQ Threshold Event */
573 #define CMPL_BASE_TYPE_SRQ_EVENT (UINT32_C(0x32) << 0)
574 /* DBQ Threshold Event */
575 #define CMPL_BASE_TYPE_DBQ_EVENT (UINT32_C(0x34) << 0)
576 /* QP Async Notification */
577 #define CMPL_BASE_TYPE_QP_EVENT (UINT32_C(0x38) << 0)
578 /* Function Async Notification */
579 #define CMPL_BASE_TYPE_FUNC_EVENT (UINT32_C(0x3a) << 0)
586 * This value is written by the NIC such that it will be different for
587 * each pass through the completion queue. The even passes will write 1.
588 * The odd passes will write 0.
590 #define CMPL_BASE_V UINT32_C(0x1)
592 #define CMPL_BASE_INFO3_MASK UINT32_C(0xfffffffe)
593 #define CMPL_BASE_INFO3_SFT 1
597 } __attribute__((packed));
599 /* TX Completion Record (16 bytes) */
602 * This field indicates the exact type of the completion. By convention,
603 * the LSB identifies the length of the record in 16B units. Even values
604 * indicate 16B records. Odd values indicate 32B records.
606 #define TX_CMPL_TYPE_MASK UINT32_C(0x3f)
607 #define TX_CMPL_TYPE_SFT 0
608 /* TX L2 completion: Completion of TX packet. Length = 16B */
609 #define TX_CMPL_TYPE_TX_L2 (UINT32_C(0x0) << 0)
611 * When this bit is '1', it indicates a packet that has an error of some
612 * type. Type of error is indicated in error_flags.
614 #define TX_CMPL_FLAGS_ERROR UINT32_C(0x40)
616 * When this bit is '1', it indicates that the packet completed was
617 * transmitted using the push acceleration data provided by the driver.
618 * When this bit is '0', it indicates that the packet had not push
619 * acceleration data written or was executed as a normal packet even
620 * though push data was provided.
622 #define TX_CMPL_FLAGS_PUSH UINT32_C(0x80)
623 #define TX_CMPL_FLAGS_MASK UINT32_C(0xffc0)
624 #define TX_CMPL_FLAGS_SFT 6
630 * This is a copy of the opaque field from the first TX BD of this
631 * transmitted packet.
636 * This value is written by the NIC such that it will be different for
637 * each pass through the completion queue. The even passes will write 1.
638 * The odd passes will write 0.
640 #define TX_CMPL_V UINT32_C(0x1)
642 * This error indicates that there was some sort of problem with the BDs
645 #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
646 #define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1
648 #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR (UINT32_C(0x0) << 1)
649 /* Bad Format: BDs were not formatted correctly. */
650 #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT (UINT32_C(0x2) << 1)
651 #define TX_CMPL_ERRORS_BUFFER_ERROR_LAST \
652 TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT
654 * When this bit is '1', it indicates that the length of the packet was
655 * zero. No packet was transmitted.
657 #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
659 * When this bit is '1', it indicates that the packet was longer than
660 * the programmed limit in TDI. No packet was transmitted.
662 #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
664 * When this bit is '1', it indicates that one or more of the BDs
665 * associated with this packet generated a PCI error. This probably
666 * means the address was not valid.
668 #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40)
670 * When this bit is '1', it indicates that the packet was longer than
671 * indicated by the hint. No packet was transmitted.
673 #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
675 * When this bit is '1', it indicates that the packet was dropped due to
676 * Poison TLP error on one or more of the TLPs in the PXP completion.
678 #define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
679 #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe)
680 #define TX_CMPL_ERRORS_SFT 1
685 } __attribute__((packed)) tx_cmpl_t, *ptx_cmpl_t;
687 /* RX Packet Completion Record (32 bytes split to 2 16-byte struct) */
690 * This field indicates the exact type of the completion. By convention,
691 * the LSB identifies the length of the record in 16B units. Even values
692 * indicate 16B records. Odd values indicate 32B records.
694 #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f)
695 #define RX_PKT_CMPL_TYPE_SFT 0
697 * RX L2 completion: Completion of and L2 RX packet.
700 #define RX_PKT_CMPL_TYPE_RX_L2 (UINT32_C(0x11) << 0)
702 * When this bit is '1', it indicates a packet that has an error of some
703 * type. Type of error is indicated in error_flags.
705 #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40)
706 /* This field indicates how the packet was placed in the buffer. */
707 #define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
708 #define RX_PKT_CMPL_FLAGS_PLACEMENT_SFT 7
709 /* Normal: Packet was placed using normal algorithm. */
710 #define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7)
711 /* Jumbo: Packet was placed using jumbo algorithm. */
712 #define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
714 * Header/Data Separation: Packet was placed using Header/Data
715 * separation algorithm. The separation location is indicated by
718 #define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
719 #define RX_PKT_CMPL_FLAGS_PLACEMENT_LAST \
720 RX_PKT_CMPL_FLAGS_PLACEMENT_HDS
721 /* This bit is '1' if the RSS field in this completion is valid. */
722 #define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
724 * This value indicates what the inner packet determined for the packet
727 #define RX_PKT_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
728 #define RX_PKT_CMPL_FLAGS_ITYPE_SFT 12
729 /* Not Known: Indicates that the packet type was not known. */
730 #define RX_PKT_CMPL_FLAGS_ITYPE_NOT_KNOWN (UINT32_C(0x0) << 12)
732 * IP Packet: Indicates that the packet was an IP packet, but
733 * further classification was not possible.
735 #define RX_PKT_CMPL_FLAGS_ITYPE_IP (UINT32_C(0x1) << 12)
737 * TCP Packet: Indicates that the packet was IP and TCP. This
738 * indicates that the payload_offset field is valid.
740 #define RX_PKT_CMPL_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 12)
742 * UDP Packet: Indicates that the packet was IP and UDP. This
743 * indicates that the payload_offset field is valid.
745 #define RX_PKT_CMPL_FLAGS_ITYPE_UDP (UINT32_C(0x3) << 12)
747 * FCoE Packet: Indicates that the packet was recognized as a
748 * FCoE. This also indicates that the payload_offset field is
751 #define RX_PKT_CMPL_FLAGS_ITYPE_FCOE (UINT32_C(0x4) << 12)
753 * RoCE Packet: Indicates that the packet was recognized as a
754 * RoCE. This also indicates that the payload_offset field is
757 #define RX_PKT_CMPL_FLAGS_ITYPE_ROCE (UINT32_C(0x5) << 12)
759 * ICMP Packet: Indicates that the packet was recognized as
760 * ICMP. This indicates that the payload_offset field is valid.
762 #define RX_PKT_CMPL_FLAGS_ITYPE_ICMP (UINT32_C(0x7) << 12)
764 * PtP packet wo/timestamp: Indicates that the packet was
765 * recognized as a PtP packet.
767 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
768 (UINT32_C(0x8) << 12)
770 * PtP packet w/timestamp: Indicates that the packet was
771 * recognized as a PtP packet and that a timestamp was taken for
774 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP (UINT32_C(0x9) << 12)
775 #define RX_PKT_CMPL_FLAGS_ITYPE_LAST \
776 RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
777 #define RX_PKT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
778 #define RX_PKT_CMPL_FLAGS_SFT 6
782 * This is the length of the data for the packet stored in the buffer(s)
783 * identified by the opaque value. This includes the packet BD and any
784 * associated buffer BDs. This does not include the the length of any
785 * data places in aggregation BDs.
790 * This is a copy of the opaque field from the RX BD this completion
796 * This value is written by the NIC such that it will be different for
797 * each pass through the completion queue. The even passes will write 1.
798 * The odd passes will write 0.
800 #define RX_PKT_CMPL_V1 UINT32_C(0x1)
802 * This value is the number of aggregation buffers that follow this
803 * entry in the completion ring that are a part of this packet. If the
804 * value is zero, then the packet is completely contained in the buffer
805 * space provided for the packet in the RX ring.
807 #define RX_PKT_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
808 #define RX_PKT_CMPL_AGG_BUFS_SFT 1
812 * This is the RSS hash type for the packet. The value is packed
813 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
815 uint8_t rss_hash_type;
818 * This value indicates the offset from the beginning of the packet
819 * where the inner payload starts. This value is valid for TCP, UDP,
820 * FCoE, and RoCE packets.
822 uint8_t payload_offset;
827 * This value is the RSS hash value calculated for the packet based on
828 * the mode bits and key value in the VNIC.
831 } __attribute__((packed));
833 /* last 16 bytes of RX Packet Completion Record */
834 struct rx_pkt_cmpl_hi {
836 * This indicates that the ip checksum was calculated for the inner
837 * packet and that the ip_cs_error field indicates if there was an
840 #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
842 * This indicates that the TCP, UDP or ICMP checksum was calculated for
843 * the inner packet and that the l4_cs_error field indicates if there
846 #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
848 * This indicates that the ip checksum was calculated for the tunnel
849 * header and that the t_ip_cs_error field indicates if there was an
852 #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
854 * This indicates that the UDP checksum was calculated for the tunnel
855 * packet and that the t_l4_cs_error field indicates if there was an
858 #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
859 /* This value indicates what format the metadata field is. */
860 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
861 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
862 /* No metadata informtaion. Value is zero. */
863 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
865 * The metadata field contains the VLAN tag and TPID value. -
866 * metadata[11:0] contains the vlan VID value. - metadata[12]
867 * contains the vlan DE value. - metadata[15:13] contains the
868 * vlan PRI value. - metadata[31:16] contains the vlan TPID
871 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN (UINT32_C(0x1) << 4)
872 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST \
873 RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN
875 * This field indicates the IP type for the inner-most IP header. A
876 * value of '0' indicates IPv4. A value of '1' indicates IPv6. This
877 * value is only valid if itype indicates a packet with an IP header.
879 #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
883 * This is data from the CFA block as indicated by the meta_format
886 /* When meta_format=1, this value is the VLAN VID. */
887 #define RX_PKT_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
888 #define RX_PKT_CMPL_METADATA_VID_SFT 0
889 /* When meta_format=1, this value is the VLAN DE. */
890 #define RX_PKT_CMPL_METADATA_DE UINT32_C(0x1000)
891 /* When meta_format=1, this value is the VLAN PRI. */
892 #define RX_PKT_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
893 #define RX_PKT_CMPL_METADATA_PRI_SFT 13
894 /* When meta_format=1, this value is the VLAN TPID. */
895 #define RX_PKT_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
896 #define RX_PKT_CMPL_METADATA_TPID_SFT 16
900 * This value is written by the NIC such that it will be different for
901 * each pass through the completion queue. The even passes will write 1.
902 * The odd passes will write 0.
904 #define RX_PKT_CMPL_V2 UINT32_C(0x1)
906 * This error indicates that there was some sort of problem with the BDs
907 * for the packet that was found after part of the packet was already
908 * placed. The packet should be treated as invalid.
910 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
911 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
912 /* No buffer error */
913 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
916 * Did Not Fit: Packet did not fit into packet buffer provided.
917 * For regular placement, this means the packet did not fit in
918 * the buffer provided. For HDS and jumbo placement, this means
919 * that the packet could not be placed into 7 physical buffers
922 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
925 * Not On Chip: All BDs needed for the packet were not on-chip
926 * when the packet arrived.
928 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
930 /* Bad Format: BDs were not formatted correctly. */
931 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
933 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST \
934 RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT
935 /* This indicates that there was an error in the IP header checksum. */
936 #define RX_PKT_CMPL_ERRORS_IP_CS_ERROR UINT32_C(0x10)
938 * This indicates that there was an error in the TCP, UDP or ICMP
941 #define RX_PKT_CMPL_ERRORS_L4_CS_ERROR UINT32_C(0x20)
943 * This indicates that there was an error in the tunnel IP header
946 #define RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR UINT32_C(0x40)
947 /* This indicates that there was an error in the tunnel UDP checksum. */
948 #define RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR UINT32_C(0x80)
950 * This indicates that there was a CRC error on either an FCoE or RoCE
951 * packet. The itype indicates the packet type.
953 #define RX_PKT_CMPL_ERRORS_CRC_ERROR UINT32_C(0x100)
955 * This indicates that there was an error in the tunnel portion of the
956 * packet when this field is non-zero.
958 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_MASK UINT32_C(0xe00)
959 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT 9
961 * No additional error occurred on the tunnel portion of the
962 * packet of the packet does not have a tunnel.
964 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 9)
966 * Indicates that IP header version does not match expectation
967 * from L2 Ethertype for IPv4 and IPv6 in the tunnel header.
969 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
972 * Indicates that header length is out of range in the tunnel
973 * header. Valid for IPv4.
975 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
978 * Indicates that the physical packet is shorter than that
979 * claimed by the PPPoE header length for a tunnel PPPoE packet.
981 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR \
984 * Indicates that physical packet is shorter than that claimed
985 * by the tunnel l3 header length. Valid for IPv4, or IPv6
986 * tunnel packet packets.
988 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
991 * Indicates that the physical packet is shorter than that
992 * claimed by the tunnel UDP header length for a tunnel UDP
993 * packet that is not fragmented.
995 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
998 * indicates that the IPv4 TTL or IPv6 hop limit check have
999 * failed (e.g. TTL = 0) in the tunnel header. Valid for IPv4,
1002 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
1003 (UINT32_C(0x6) << 9)
1004 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_LAST \
1005 RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
1007 * This indicates that there was an error in the inner portion of the
1008 * packet when this field is non-zero.
1010 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_MASK UINT32_C(0xf000)
1011 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT 12
1013 * No additional error occurred on the tunnel portion of the
1014 * packet of the packet does not have a tunnel.
1016 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 12)
1018 * Indicates that IP header version does not match expectation
1019 * from L2 Ethertype for IPv4 and IPv6 or that option other than
1020 * VFT was parsed on FCoE packet.
1022 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION \
1023 (UINT32_C(0x1) << 12)
1025 * indicates that header length is out of range. Valid for IPv4
1028 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
1029 (UINT32_C(0x2) << 12)
1031 * indicates that the IPv4 TTL or IPv6 hop limit check have
1032 * failed (e.g. TTL = 0). Valid for IPv4, and IPv6
1034 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (UINT32_C(0x3) << 12)
1036 * Indicates that physical packet is shorter than that claimed
1037 * by the l3 header length. Valid for IPv4, IPv6 packet or RoCE
1040 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
1041 (UINT32_C(0x4) << 12)
1043 * Indicates that the physical packet is shorter than that
1044 * claimed by the UDP header length for a UDP packet that is not
1047 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
1048 (UINT32_C(0x5) << 12)
1050 * Indicates that TCP header length > IP payload. Valid for TCP
1053 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
1054 (UINT32_C(0x6) << 12)
1055 /* Indicates that TCP header length < 5. Valid for TCP. */
1056 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
1057 (UINT32_C(0x7) << 12)
1059 * Indicates that TCP option headers result in a TCP header size
1060 * that does not match data offset in TCP header. Valid for TCP.
1062 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
1063 (UINT32_C(0x8) << 12)
1064 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_LAST \
1065 RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
1066 #define RX_PKT_CMPL_ERRORS_MASK UINT32_C(0xfffe)
1067 #define RX_PKT_CMPL_ERRORS_SFT 1
1071 * This field identifies the CFA action rule that was used for this
1077 * This value holds the reordering sequence number for the packet. If
1078 * the reordering sequence is not valid, then this value is zero. The
1079 * reordering domain for the packet is in the bottom 8 to 10b of the
1080 * rss_hash value. The bottom 20b of this value contain the ordering
1081 * domain value for the packet.
1083 #define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff)
1084 #define RX_PKT_CMPL_REORDER_SFT 0
1086 } __attribute__((packed));
1088 /* HWRM Forwarded Request (16 bytes) */
1089 struct hwrm_fwd_req_cmpl {
1090 /* Length of forwarded request in bytes. */
1092 * This field indicates the exact type of the completion. By convention,
1093 * the LSB identifies the length of the record in 16B units. Even values
1094 * indicate 16B records. Odd values indicate 32B records.
1096 #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f)
1097 #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0
1098 /* Forwarded HWRM Request */
1099 #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ (UINT32_C(0x22) << 0)
1100 /* Length of forwarded request in bytes. */
1101 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0)
1102 #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6
1103 uint16_t req_len_type;
1106 * Source ID of this request. Typically used in forwarding requests and
1107 * responses. 0x0 - 0xFFF8 - Used for function ids 0xFFF8 - 0xFFFE -
1108 * Reserved for internal processors 0xFFFF - HWRM
1114 /* Address of forwarded request. */
1116 * This value is written by the NIC such that it will be different for
1117 * each pass through the completion queue. The even passes will write 1.
1118 * The odd passes will write 0.
1120 #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1)
1121 /* Address of forwarded request. */
1122 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe)
1123 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
1124 uint64_t req_buf_addr_v;
1125 } __attribute__((packed));
1127 /* HWRM Asynchronous Event Completion Record (16 bytes) */
1128 struct hwrm_async_event_cmpl {
1130 * This field indicates the exact type of the completion. By convention,
1131 * the LSB identifies the length of the record in 16B units. Even values
1132 * indicate 16B records. Odd values indicate 32B records.
1134 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f)
1135 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0
1136 /* HWRM Asynchronous Event Information */
1137 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT \
1138 (UINT32_C(0x2e) << 0)
1141 /* Identifiers of events. */
1142 /* Link status changed */
1143 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE \
1144 (UINT32_C(0x0) << 0)
1145 /* Link MTU changed */
1146 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE \
1147 (UINT32_C(0x1) << 0)
1148 /* Link speed changed */
1149 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE \
1150 (UINT32_C(0x2) << 0)
1151 /* DCB Configuration changed */
1152 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE \
1153 (UINT32_C(0x3) << 0)
1154 /* Port connection not allowed */
1155 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED \
1156 (UINT32_C(0x4) << 0)
1157 /* Link speed configuration was not allowed */
1158 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
1159 (UINT32_C(0x5) << 0)
1160 /* Function driver unloaded */
1161 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \
1162 (UINT32_C(0x10) << 0)
1163 /* Function driver loaded */
1164 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD \
1165 (UINT32_C(0x11) << 0)
1166 /* PF driver unloaded */
1167 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD \
1168 (UINT32_C(0x20) << 0)
1169 /* PF driver loaded */
1170 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD \
1171 (UINT32_C(0x21) << 0)
1172 /* VF Function Level Reset (FLR) */
1173 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR (UINT32_C(0x30) << 0)
1174 /* VF MAC Address Change */
1175 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE \
1176 (UINT32_C(0x31) << 0)
1177 /* PF-VF communication channel status change. */
1178 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
1179 (UINT32_C(0x32) << 0)
1181 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \
1182 (UINT32_C(0xff) << 0)
1185 /* Event specific data */
1186 uint32_t event_data2;
1190 * This value is written by the NIC such that it will be different for
1191 * each pass through the completion queue. The even passes will write 1.
1192 * The odd passes will write 0.
1194 #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1)
1196 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK UINT32_C(0xfe)
1197 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1
1200 /* 8-lsb timestamp from POR (100-msec resolution) */
1201 uint8_t timestamp_lo;
1203 /* 16-lsb timestamp from POR (100-msec resolution) */
1204 uint16_t timestamp_hi;
1206 /* Event specific data */
1207 uint32_t event_data1;
1208 } __attribute__((packed));
1211 * Note: The Hardware Resource Manager (HWRM) manages various hardware resources
1212 * inside the chip. The HWRM is implemented in firmware, and runs on embedded
1213 * processors inside the chip. This firmware is vital part of the chip's
1214 * hardware. The chip can not be used by driver without it.
1217 /* Input (16 bytes) */
1220 * This value indicates what type of request this is. The format for the
1221 * rest of the command is determined by this field.
1226 * This value indicates the what completion ring the request will be
1227 * optionally completed on. If the value is -1, then no CR completion
1228 * will be generated. Any other value must be a valid CR ring_id value
1229 * for this function.
1233 /* This value indicates the command sequence number. */
1237 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
1238 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
1243 * This is the host address where the response will be written when the
1244 * request is complete. This area must be 16B aligned and must be
1245 * cleared to zero before the request is made.
1248 } __attribute__((packed));
1250 /* Output (8 bytes) */
1253 * Pass/Fail or error type Note: receiver to verify the in parameters,
1254 * and fail the call with an error when appropriate
1256 uint16_t error_code;
1258 /* This field returns the type of original request. */
1261 /* This field provides original sequence number of the command. */
1265 * This field is the length of the response in bytes. The last byte of
1266 * the response is a valid flag that will read as '1' when the command
1267 * has been completely written to memory.
1270 } __attribute__((packed));
1272 /* hwrm_cfa_l2_filter_alloc */
1274 * A filter is used to identify traffic that contains a matching set of
1275 * parameters like unicast or broadcast MAC address or a VLAN tag amongst
1276 * other things which then allows the ASIC to direct the incoming traffic
1277 * to an appropriate VNIC or Rx ring.
1280 /* Input (96 bytes) */
1281 struct hwrm_cfa_l2_filter_alloc_input {
1283 * This value indicates what type of request this is. The format for the
1284 * rest of the command is determined by this field.
1289 * This value indicates the what completion ring the request will be
1290 * optionally completed on. If the value is -1, then no CR completion
1291 * will be generated. Any other value must be a valid CR ring_id value
1292 * for this function.
1296 /* This value indicates the command sequence number. */
1300 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
1301 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
1306 * This is the host address where the response will be written when the
1307 * request is complete. This area must be 16B aligned and must be
1308 * cleared to zero before the request is made.
1313 * Enumeration denoting the RX, TX type of the resource. This
1314 * enumeration is used for resources that are similar for both TX and RX
1315 * paths of the chip.
1317 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \
1320 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \
1321 (UINT32_C(0x0) << 0)
1323 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \
1324 (UINT32_C(0x1) << 0)
1325 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \
1326 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX
1328 * Setting of this flag indicates the applicability to the loopback
1331 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
1334 * Setting of this flag indicates drop action. If this flag is not set,
1335 * then it should be considered accept action.
1337 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \
1340 * If this flag is set, all t_l2_* fields are invalid and they should
1341 * not be specified. If this flag is set, then l2_* fields refer to
1342 * fields of outermost L2 header.
1344 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \
1348 /* This bit must be '1' for the l2_addr field to be configured. */
1349 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
1351 /* This bit must be '1' for the l2_addr_mask field to be configured. */
1352 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \
1354 /* This bit must be '1' for the l2_ovlan field to be configured. */
1355 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \
1357 /* This bit must be '1' for the l2_ovlan_mask field to be configured. */
1358 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \
1360 /* This bit must be '1' for the l2_ivlan field to be configured. */
1361 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
1363 /* This bit must be '1' for the l2_ivlan_mask field to be configured. */
1364 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \
1366 /* This bit must be '1' for the t_l2_addr field to be configured. */
1367 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \
1370 * This bit must be '1' for the t_l2_addr_mask field to be configured.
1372 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \
1374 /* This bit must be '1' for the t_l2_ovlan field to be configured. */
1375 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \
1378 * This bit must be '1' for the t_l2_ovlan_mask field to be configured.
1380 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \
1382 /* This bit must be '1' for the t_l2_ivlan field to be configured. */
1383 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \
1386 * This bit must be '1' for the t_l2_ivlan_mask field to be configured.
1388 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \
1390 /* This bit must be '1' for the src_type field to be configured. */
1391 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \
1393 /* This bit must be '1' for the src_id field to be configured. */
1394 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \
1396 /* This bit must be '1' for the tunnel_type field to be configured. */
1397 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
1399 /* This bit must be '1' for the dst_id field to be configured. */
1400 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
1403 * This bit must be '1' for the mirror_vnic_id field to be configured.
1405 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
1410 * This value sets the match value for the L2 MAC address. Destination
1411 * MAC address for RX path. Source MAC address for TX path.
1419 * This value sets the mask value for the L2 address. A value of 0 will
1420 * mask the corresponding bit from compare.
1422 uint8_t l2_addr_mask[6];
1424 /* This value sets VLAN ID value for outer VLAN. */
1428 * This value sets the mask value for the ovlan id. A value of 0 will
1429 * mask the corresponding bit from compare.
1431 uint16_t l2_ovlan_mask;
1433 /* This value sets VLAN ID value for inner VLAN. */
1437 * This value sets the mask value for the ivlan id. A value of 0 will
1438 * mask the corresponding bit from compare.
1440 uint16_t l2_ivlan_mask;
1446 * This value sets the match value for the tunnel L2 MAC address.
1447 * Destination MAC address for RX path. Source MAC address for TX path.
1449 uint8_t t_l2_addr[6];
1455 * This value sets the mask value for the tunnel L2 address. A value of
1456 * 0 will mask the corresponding bit from compare.
1458 uint8_t t_l2_addr_mask[6];
1460 /* This value sets VLAN ID value for tunnel outer VLAN. */
1461 uint16_t t_l2_ovlan;
1464 * This value sets the mask value for the tunnel ovlan id. A value of 0
1465 * will mask the corresponding bit from compare.
1467 uint16_t t_l2_ovlan_mask;
1469 /* This value sets VLAN ID value for tunnel inner VLAN. */
1470 uint16_t t_l2_ivlan;
1473 * This value sets the mask value for the tunnel ivlan id. A value of 0
1474 * will mask the corresponding bit from compare.
1476 uint16_t t_l2_ivlan_mask;
1478 /* This value identifies the type of source of the packet. */
1480 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT \
1481 (UINT32_C(0x0) << 0)
1482 /* Physical function */
1483 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF \
1484 (UINT32_C(0x1) << 0)
1485 /* Virtual function */
1486 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF \
1487 (UINT32_C(0x2) << 0)
1488 /* Virtual NIC of a function */
1489 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC \
1490 (UINT32_C(0x3) << 0)
1491 /* Embedded processor for CFA management */
1492 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG \
1493 (UINT32_C(0x4) << 0)
1494 /* Embedded processor for OOB management */
1495 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE \
1496 (UINT32_C(0x5) << 0)
1497 /* Embedded processor for RoCE */
1498 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO \
1499 (UINT32_C(0x6) << 0)
1500 /* Embedded processor for network proxy functions */
1501 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG \
1502 (UINT32_C(0x7) << 0)
1507 * This value is the id of the source. For a network port, it represents
1508 * port_id. For a physical function, it represents fid. For a virtual
1509 * function, it represents vf_id. For a vnic, it represents vnic_id. For
1510 * embedded processors, this id is not valid. Notes: 1. The function ID
1511 * is implied if it src_id is not provided for a src_type that is either
1517 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
1518 (UINT32_C(0x0) << 0)
1519 /* Virtual eXtensible Local Area Network (VXLAN) */
1520 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
1521 (UINT32_C(0x1) << 0)
1523 * Network Virtualization Generic Routing Encapsulation (NVGRE)
1525 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
1526 (UINT32_C(0x2) << 0)
1528 * Generic Routing Encapsulation (GRE) inside Ethernet payload
1530 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
1531 (UINT32_C(0x3) << 0)
1533 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
1534 (UINT32_C(0x4) << 0)
1535 /* Generic Network Virtualization Encapsulation (Geneve) */
1536 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
1537 (UINT32_C(0x5) << 0)
1538 /* Multi-Protocol Lable Switching (MPLS) */
1539 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
1540 (UINT32_C(0x6) << 0)
1541 /* Stateless Transport Tunnel (STT) */
1542 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
1543 (UINT32_C(0x7) << 0)
1545 * Generic Routing Encapsulation (GRE) inside IP datagram
1548 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
1549 (UINT32_C(0x8) << 0)
1550 /* Any tunneled traffic */
1551 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
1552 (UINT32_C(0xff) << 0)
1553 uint8_t tunnel_type;
1558 * If set, this value shall represent the Logical VNIC ID of the
1559 * destination VNIC for the RX path and network port id of the
1560 * destination port for the TX path.
1564 /* Logical VNIC ID of the VNIC where traffic is mirrored. */
1565 uint16_t mirror_vnic_id;
1568 * This hint is provided to help in placing the filter in the filter
1572 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
1573 (UINT32_C(0x0) << 0)
1574 /* Above the given filter */
1575 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \
1576 (UINT32_C(0x1) << 0)
1577 /* Below the given filter */
1578 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \
1579 (UINT32_C(0x2) << 0)
1580 /* As high as possible */
1581 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \
1582 (UINT32_C(0x3) << 0)
1583 /* As low as possible */
1584 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \
1585 (UINT32_C(0x4) << 0)
1592 * This is the ID of the filter that goes along with the pri_hint. This
1593 * field is valid only for the following values. 1 - Above the given
1594 * filter 2 - Below the given filter
1596 uint64_t l2_filter_id_hint;
1597 } __attribute__((packed));
1599 /* Output (24 bytes) */
1600 struct hwrm_cfa_l2_filter_alloc_output {
1602 * Pass/Fail or error type Note: receiver to verify the in parameters,
1603 * and fail the call with an error when appropriate
1605 uint16_t error_code;
1607 /* This field returns the type of original request. */
1610 /* This field provides original sequence number of the command. */
1614 * This field is the length of the response in bytes. The last byte of
1615 * the response is a valid flag that will read as '1' when the command
1616 * has been completely written to memory.
1621 * This value identifies a set of CFA data structures used for an L2
1624 uint64_t l2_filter_id;
1627 * This is the ID of the flow associated with this filter. This value
1628 * shall be used to match and associate the flow identifier returned in
1629 * completion records. A value of 0xFFFFFFFF shall indicate no flow id.
1638 * This field is used in Output records to indicate that the output is
1639 * completely written to RAM. This field should be read as '1' to
1640 * indicate that the output has been completely written. When writing a
1641 * command completion or response to an internal processor, the order of
1642 * writes has to be such that this field is written last.
1645 } __attribute__((packed));
1647 /* hwrm_cfa_l2_filter_free */
1649 * Description: Free a L2 filter. The HWRM shall free all associated filter
1650 * resources with the L2 filter.
1653 /* Input (24 bytes) */
1654 struct hwrm_cfa_l2_filter_free_input {
1656 * This value indicates what type of request this is. The format for the
1657 * rest of the command is determined by this field.
1662 * This value indicates the what completion ring the request will be
1663 * optionally completed on. If the value is -1, then no CR completion
1664 * will be generated. Any other value must be a valid CR ring_id value
1665 * for this function.
1669 /* This value indicates the command sequence number. */
1673 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
1674 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
1679 * This is the host address where the response will be written when the
1680 * request is complete. This area must be 16B aligned and must be
1681 * cleared to zero before the request is made.
1686 * This value identifies a set of CFA data structures used for an L2
1689 uint64_t l2_filter_id;
1690 } __attribute__((packed));
1692 /* Output (16 bytes) */
1693 struct hwrm_cfa_l2_filter_free_output {
1695 * Pass/Fail or error type Note: receiver to verify the in parameters,
1696 * and fail the call with an error when appropriate
1698 uint16_t error_code;
1700 /* This field returns the type of original request. */
1703 /* This field provides original sequence number of the command. */
1707 * This field is the length of the response in bytes. The last byte of
1708 * the response is a valid flag that will read as '1' when the command
1709 * has been completely written to memory.
1719 * This field is used in Output records to indicate that the output is
1720 * completely written to RAM. This field should be read as '1' to
1721 * indicate that the output has been completely written. When writing a
1722 * command completion or response to an internal processor, the order of
1723 * writes has to be such that this field is written last.
1726 } __attribute__((packed));
1728 /* hwrm_exec_fwd_resp */
1730 * Description: This command is used to send an encapsulated request to the
1731 * HWRM. This command instructs the HWRM to execute the request and forward the
1732 * response of the encapsulated request to the location specified in the
1733 * original request that is encapsulated. The target id of this command shall be
1734 * set to 0xFFFF (HWRM). The response location in this command shall be used to
1735 * acknowledge the receipt of the encapsulated request and forwarding of the
1739 /* Input (128 bytes) */
1740 struct hwrm_exec_fwd_resp_input {
1742 * This value indicates what type of request this is. The format for the
1743 * rest of the command is determined by this field.
1748 * This value indicates the what completion ring the request will be
1749 * optionally completed on. If the value is -1, then no CR completion
1750 * will be generated. Any other value must be a valid CR ring_id value
1751 * for this function.
1755 /* This value indicates the command sequence number. */
1759 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
1760 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
1765 * This is the host address where the response will be written when the
1766 * request is complete. This area must be 16B aligned and must be
1767 * cleared to zero before the request is made.
1772 * This is an encapsulated request. This request should be executed by
1773 * the HWRM and the response should be provided in the response buffer
1774 * inside the encapsulated request.
1776 uint32_t encap_request[26];
1779 * This value indicates the target id of the response to the
1780 * encapsulated request. 0x0 - 0xFFF8 - Used for function ids 0xFFF8 -
1781 * 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
1783 uint16_t encap_resp_target_id;
1785 uint16_t unused_0[3];
1786 } __attribute__((packed));
1788 /* Output (16 bytes) */
1789 struct hwrm_exec_fwd_resp_output {
1791 * Pass/Fail or error type Note: receiver to verify the in parameters,
1792 * and fail the call with an error when appropriate
1794 uint16_t error_code;
1796 /* This field returns the type of original request. */
1799 /* This field provides original sequence number of the command. */
1803 * This field is the length of the response in bytes. The last byte of
1804 * the response is a valid flag that will read as '1' when the command
1805 * has been completely written to memory.
1815 * This field is used in Output records to indicate that the output is
1816 * completely written to RAM. This field should be read as '1' to
1817 * indicate that the output has been completely written. When writing a
1818 * command completion or response to an internal processor, the order of
1819 * writes has to be such that this field is written last.
1822 } __attribute__((packed));
1824 /* hwrm_func_qcaps */
1826 * Description: This command returns capabilities of a function. The input FID
1827 * value is used to indicate what function is being queried. This allows a
1828 * physical function driver to query virtual functions that are children of the
1829 * physical function. The output FID value is needed to configure Rings and
1830 * MSI-X vectors so their DMA operations appear correctly on the PCI bus.
1833 /* Input (24 bytes) */
1834 struct hwrm_func_qcaps_input {
1836 * This value indicates what type of request this is. The format for the
1837 * rest of the command is determined by this field.
1842 * This value indicates the what completion ring the request will be
1843 * optionally completed on. If the value is -1, then no CR completion
1844 * will be generated. Any other value must be a valid CR ring_id value
1845 * for this function.
1849 /* This value indicates the command sequence number. */
1853 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
1854 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
1859 * This is the host address where the response will be written when the
1860 * request is complete. This area must be 16B aligned and must be
1861 * cleared to zero before the request is made.
1866 * Function ID of the function that is being queried. 0xFF... (All Fs)
1867 * if the query is for the requesting function.
1871 uint16_t unused_0[3];
1872 } __attribute__((packed));
1874 /* Output (80 bytes) */
1875 struct hwrm_func_qcaps_output {
1877 * Pass/Fail or error type Note: receiver to verify the in parameters,
1878 * and fail the call with an error when appropriate
1880 uint16_t error_code;
1882 /* This field returns the type of original request. */
1885 /* This field provides original sequence number of the command. */
1889 * This field is the length of the response in bytes. The last byte of
1890 * the response is a valid flag that will read as '1' when the command
1891 * has been completely written to memory.
1896 * FID value. This value is used to identify operations on the PCI bus
1897 * as belonging to a particular PCI function.
1902 * Port ID of port that this function is associated with. Valid only for
1903 * the PF. 0xFF... (All Fs) if this function is not associated with any
1904 * port. 0xFF... (All Fs) if this function is called from a VF.
1908 /* If 1, then Push mode is supported on this function. */
1909 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED UINT32_C(0x1)
1911 * If 1, then the global MSI-X auto-masking is enabled for the device.
1913 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING \
1916 * If 1, then the Precision Time Protocol (PTP) processing is supported
1917 * on this function. The HWRM should enable PTP on only a single
1918 * Physical Function (PF) per port.
1920 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED UINT32_C(0x4)
1924 * This value is current MAC address configured for this function. A
1925 * value of 00-00-00-00-00-00 indicates no MAC address is currently
1928 uint8_t perm_mac_address[6];
1931 * The maximum number of RSS/COS contexts that can be allocated to the
1934 uint16_t max_rsscos_ctx;
1937 * The maximum number of completion rings that can be allocated to the
1940 uint16_t max_cmpl_rings;
1943 * The maximum number of transmit rings that can be allocated to the
1946 uint16_t max_tx_rings;
1949 * The maximum number of receive rings that can be allocated to the
1952 uint16_t max_rx_rings;
1955 * The maximum number of L2 contexts that can be allocated to the
1958 uint16_t max_l2_ctxs;
1960 /* The maximum number of VNICs that can be allocated to the function. */
1964 * The identifier for the first VF enabled on a PF. This is valid only
1965 * on the PF with SR-IOV enabled. 0xFF... (All Fs) if this command is
1966 * called on a PF with SR-IOV disabled or on a VF.
1968 uint16_t first_vf_id;
1971 * The maximum number of VFs that can be allocated to the function. This
1972 * is valid only on the PF with SR-IOV enabled. 0xFF... (All Fs) if this
1973 * command is called on a PF with SR-IOV disabled or on a VF.
1978 * The maximum number of statistic contexts that can be allocated to the
1981 uint16_t max_stat_ctx;
1984 * The maximum number of Encapsulation records that can be offloaded by
1987 uint32_t max_encap_records;
1990 * The maximum number of decapsulation records that can be offloaded by
1993 uint32_t max_decap_records;
1996 * The maximum number of Exact Match (EM) flows that can be offloaded by
1997 * this function on the TX side.
1999 uint32_t max_tx_em_flows;
2002 * The maximum number of Wildcard Match (WM) flows that can be offloaded
2003 * by this function on the TX side.
2005 uint32_t max_tx_wm_flows;
2008 * The maximum number of Exact Match (EM) flows that can be offloaded by
2009 * this function on the RX side.
2011 uint32_t max_rx_em_flows;
2014 * The maximum number of Wildcard Match (WM) flows that can be offloaded
2015 * by this function on the RX side.
2017 uint32_t max_rx_wm_flows;
2020 * The maximum number of multicast filters that can be supported by this
2021 * function on the RX side.
2023 uint32_t max_mcast_filters;
2026 * The maximum value of flow_id that can be supported in completion
2029 uint32_t max_flow_id;
2032 * The maximum number of HW ring groups that can be supported on this
2035 uint32_t max_hw_ring_grps;
2042 * This field is used in Output records to indicate that the output is
2043 * completely written to RAM. This field should be read as '1' to
2044 * indicate that the output has been completely written. When writing a
2045 * command completion or response to an internal processor, the order of
2046 * writes has to be such that this field is written last.
2049 } __attribute__((packed));
2051 /* hwrm_port_phy_cfg */
2053 * Description: This command configures the PHY device for the port. It allows
2054 * setting of the most generic settings for the PHY. The HWRM shall complete
2055 * this command as soon as PHY settings are configured. They may not be applied
2056 * when the command response is provided. A VF driver shall not be allowed to
2057 * configure PHY using this command. In a network partition mode, a PF driver
2058 * shall not be allowed to configure PHY using this command.
2061 /* Input (56 bytes) */
2062 struct hwrm_port_phy_cfg_input {
2064 * This value indicates what type of request this is. The format for the
2065 * rest of the command is determined by this field.
2070 * This value indicates the what completion ring the request will be
2071 * optionally completed on. If the value is -1, then no CR completion
2072 * will be generated. Any other value must be a valid CR ring_id value
2073 * for this function.
2077 /* This value indicates the command sequence number. */
2081 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
2082 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
2087 * This is the host address where the response will be written when the
2088 * request is complete. This area must be 16B aligned and must be
2089 * cleared to zero before the request is made.
2094 * When this bit is set to '1', the PHY for the port shall be reset. #
2095 * If this bit is set to 1, then the HWRM shall reset the PHY after
2096 * applying PHY configuration changes specified in this command. # In
2097 * order to guarantee that PHY configuration changes specified in this
2098 * command take effect, the HWRM client should set this flag to 1. # If
2099 * this bit is not set to 1, then the HWRM may reset the PHY depending
2100 * on the current PHY configuration and settings specified in this
2103 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY UINT32_C(0x1)
2105 * When this bit is set to '1', the link shall be forced to be taken
2106 * down. # When this bit is set to '1", all other command input settings
2107 * related to the link speed shall be ignored. Once the link state is
2108 * forced down, it can be explicitly cleared from that state by setting
2109 * this flag to '0'. # If this flag is set to '0', then the link shall
2110 * be cleared from forced down state if the link is in forced down
2111 * state. There may be conditions (e.g. out-of-band or sideband
2112 * configuration changes for the link) outside the scope of the HWRM
2113 * implementation that may clear forced down link state.
2115 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DOWN UINT32_C(0x2)
2117 * When this bit is set to '1', the link shall be forced to the
2118 * force_link_speed value. When this bit is set to '1', the HWRM client
2119 * should not enable any of the auto negotiation related fields
2120 * represented by auto_XXX fields in this command. When this bit is set
2121 * to '1' and the HWRM client has enabled a auto_XXX field in this
2122 * command, then the HWRM shall ignore the enabled auto_XXX field. When
2123 * this bit is set to zero, the link shall be allowed to autoneg.
2125 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE UINT32_C(0x4)
2127 * When this bit is set to '1', the auto-negotiation process shall be
2128 * restarted on the link.
2130 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG UINT32_C(0x8)
2132 * When this bit is set to '1', Energy Efficient Ethernet (EEE) is
2133 * requested to be enabled on this link. If EEE is not supported on this
2134 * port, then this flag shall be ignored by the HWRM.
2136 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE UINT32_C(0x10)
2138 * When this bit is set to '1', Energy Efficient Ethernet (EEE) is
2139 * requested to be disabled on this link. If EEE is not supported on
2140 * this port, then this flag shall be ignored by the HWRM.
2142 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE UINT32_C(0x20)
2144 * When this bit is set to '1' and EEE is enabled on this link, then TX
2145 * LPI is requested to be enabled on the link. If EEE is not supported
2146 * on this port, then this flag shall be ignored by the HWRM. If EEE is
2147 * disabled on this port, then this flag shall be ignored by the HWRM.
2149 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI UINT32_C(0x40)
2152 /* This bit must be '1' for the auto_mode field to be configured. */
2153 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE UINT32_C(0x1)
2154 /* This bit must be '1' for the auto_duplex field to be configured. */
2155 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX UINT32_C(0x2)
2156 /* This bit must be '1' for the auto_pause field to be configured. */
2157 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE UINT32_C(0x4)
2159 * This bit must be '1' for the auto_link_speed field to be configured.
2161 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED UINT32_C(0x8)
2163 * This bit must be '1' for the auto_link_speed_mask field to be
2166 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK \
2168 /* This bit must be '1' for the wirespeed field to be configured. */
2169 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED UINT32_C(0x20)
2170 /* This bit must be '1' for the lpbk field to be configured. */
2171 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK UINT32_C(0x40)
2172 /* This bit must be '1' for the preemphasis field to be configured. */
2173 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS UINT32_C(0x80)
2174 /* This bit must be '1' for the force_pause field to be configured. */
2175 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE UINT32_C(0x100)
2177 * This bit must be '1' for the eee_link_speed_mask field to be
2180 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK \
2182 /* This bit must be '1' for the tx_lpi_timer field to be configured. */
2183 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER UINT32_C(0x400)
2186 /* Port ID of port that is to be configured. */
2190 * This is the speed that will be used if the force bit is '1'. If
2191 * unsupported speed is selected, an error will be generated.
2193 /* 100Mb link speed */
2194 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB \
2195 (UINT32_C(0x1) << 0)
2196 /* 1Gb link speed */
2197 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB \
2198 (UINT32_C(0xa) << 0)
2199 /* 2Gb link speed */
2200 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB \
2201 (UINT32_C(0x14) << 0)
2202 /* 2.5Gb link speed */
2203 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB \
2204 (UINT32_C(0x19) << 0)
2205 /* 10Gb link speed */
2206 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB \
2207 (UINT32_C(0x64) << 0)
2208 /* 20Mb link speed */
2209 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB \
2210 (UINT32_C(0xc8) << 0)
2211 /* 25Gb link speed */
2212 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB \
2213 (UINT32_C(0xfa) << 0)
2214 /* 40Gb link speed */
2215 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB \
2216 (UINT32_C(0x190) << 0)
2217 /* 50Gb link speed */
2218 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB \
2219 (UINT32_C(0x1f4) << 0)
2220 /* 100Gb link speed */
2221 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB \
2222 (UINT32_C(0x3e8) << 0)
2223 /* 10Mb link speed */
2224 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB \
2225 (UINT32_C(0xffff) << 0)
2226 uint16_t force_link_speed;
2229 * This value is used to identify what autoneg mode is used when the
2230 * link speed is not being forced.
2233 * Disable autoneg or autoneg disabled. No speeds are selected.
2235 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE (UINT32_C(0x0) << 0)
2236 /* Select all possible speeds for autoneg mode. */
2237 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS \
2238 (UINT32_C(0x1) << 0)
2240 * Select only the auto_link_speed speed for autoneg mode. This
2241 * mode has been DEPRECATED. An HWRM client should not use this
2244 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED \
2245 (UINT32_C(0x2) << 0)
2247 * Select the auto_link_speed or any speed below that speed for
2248 * autoneg. This mode has been DEPRECATED. An HWRM client should
2249 * not use this mode.
2251 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW \
2252 (UINT32_C(0x3) << 0)
2254 * Select the speeds based on the corresponding link speed mask
2255 * value that is provided.
2257 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK \
2258 (UINT32_C(0x4) << 0)
2262 * This is the duplex setting that will be used if the autoneg_mode is
2263 * "one_speed" or "one_or_below".
2265 /* Half Duplex will be requested. */
2266 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF \
2267 (UINT32_C(0x0) << 0)
2268 /* Full duplex will be requested. */
2269 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL \
2270 (UINT32_C(0x1) << 0)
2271 /* Both Half and Full dupex will be requested. */
2272 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH \
2273 (UINT32_C(0x2) << 0)
2274 uint8_t auto_duplex;
2277 * This value is used to configure the pause that will be used for
2278 * autonegotiation. Add text on the usage of auto_pause and force_pause.
2281 * When this bit is '1', Generation of tx pause messages has been
2282 * requested. Disabled otherwise.
2284 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX UINT32_C(0x1)
2286 * When this bit is '1', Reception of rx pause messages has been
2287 * requested. Disabled otherwise.
2289 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX UINT32_C(0x2)
2291 * When set to 1, the advertisement of pause is enabled. # When the
2292 * auto_mode is not set to none and this flag is set to 1, then the
2293 * auto_pause bits on this port are being advertised and autoneg pause
2294 * results are being interpreted. # When the auto_mode is not set to
2295 * none and this flag is set to 0, the pause is forced as indicated in
2296 * force_pause, and also advertised as auto_pause bits, but the autoneg
2297 * results are not interpreted since the pause configuration is being
2298 * forced. # When the auto_mode is set to none and this flag is set to
2299 * 1, auto_pause bits should be ignored and should be set to 0.
2301 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE UINT32_C(0x4)
2307 * This is the speed that will be used if the autoneg_mode is
2308 * "one_speed" or "one_or_below". If an unsupported speed is selected,
2309 * an error will be generated.
2311 /* 100Mb link speed */
2312 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB \
2313 (UINT32_C(0x1) << 0)
2314 /* 1Gb link speed */
2315 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB \
2316 (UINT32_C(0xa) << 0)
2317 /* 2Gb link speed */
2318 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB \
2319 (UINT32_C(0x14) << 0)
2320 /* 2.5Gb link speed */
2321 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB \
2322 (UINT32_C(0x19) << 0)
2323 /* 10Gb link speed */
2324 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB \
2325 (UINT32_C(0x64) << 0)
2326 /* 20Mb link speed */
2327 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB \
2328 (UINT32_C(0xc8) << 0)
2329 /* 25Gb link speed */
2330 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB \
2331 (UINT32_C(0xfa) << 0)
2332 /* 40Gb link speed */
2333 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB \
2334 (UINT32_C(0x190) << 0)
2335 /* 50Gb link speed */
2336 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB \
2337 (UINT32_C(0x1f4) << 0)
2338 /* 100Gb link speed */
2339 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB \
2340 (UINT32_C(0x3e8) << 0)
2341 /* 10Mb link speed */
2342 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB \
2343 (UINT32_C(0xffff) << 0)
2344 uint16_t auto_link_speed;
2347 * This is a mask of link speeds that will be used if autoneg_mode is
2348 * "mask". If unsupported speed is enabled an error will be generated.
2350 /* 100Mb link speed (Half-duplex) */
2351 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD \
2353 /* 100Mb link speed (Full-duplex) */
2354 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB \
2356 /* 1Gb link speed (Half-duplex) */
2357 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD \
2359 /* 1Gb link speed (Full-duplex) */
2360 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB \
2362 /* 2Gb link speed */
2363 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB \
2365 /* 2.5Gb link speed */
2366 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB \
2368 /* 10Gb link speed */
2369 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB \
2371 /* 20Gb link speed */
2372 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB \
2374 /* 25Gb link speed */
2375 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB \
2377 /* 40Gb link speed */
2378 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB \
2380 /* 50Gb link speed */
2381 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB \
2383 /* 100Gb link speed */
2384 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB \
2386 /* 10Mb link speed (Half-duplex) */
2387 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD \
2389 /* 10Mb link speed (Full-duplex) */
2390 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
2392 uint16_t auto_link_speed_mask;
2394 /* This value controls the wirespeed feature. */
2395 /* Wirespeed feature is disabled. */
2396 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF (UINT32_C(0x0) << 0)
2397 /* Wirespeed feature is enabled. */
2398 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON (UINT32_C(0x1) << 0)
2401 /* This value controls the loopback setting for the PHY. */
2402 /* No loopback is selected. Normal operation. */
2403 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE (UINT32_C(0x0) << 0)
2405 * The HW will be configured with local loopback such that host
2406 * data is sent back to the host without modification.
2408 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL (UINT32_C(0x1) << 0)
2410 * The HW will be configured with remote loopback such that port
2411 * logic will send packets back out the transmitter that are
2414 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE (UINT32_C(0x2) << 0)
2418 * This value is used to configure the pause that will be used for force
2422 * When this bit is '1', Generation of tx pause messages is supported.
2423 * Disabled otherwise.
2425 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)
2427 * When this bit is '1', Reception of rx pause messages is supported.
2428 * Disabled otherwise.
2430 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)
2431 uint8_t force_pause;
2436 * This value controls the pre-emphasis to be used for the link. Driver
2437 * should not set this value (use enable.preemphasis = 0) unless driver
2438 * is sure of setting. Normally HWRM FW will determine proper pre-
2441 uint32_t preemphasis;
2444 * Setting for link speed mask that is used to advertise speeds during
2445 * autonegotiation when EEE is enabled. This field is valid only when
2446 * EEE is enabled. The speeds specified in this field shall be a subset
2447 * of speeds specified in auto_link_speed_mask. If EEE is enabled,then
2448 * at least one speed shall be provided in this mask.
2451 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 UINT32_C(0x1)
2452 /* 100Mb link speed (Full-duplex) */
2453 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB UINT32_C(0x2)
2455 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 UINT32_C(0x4)
2456 /* 1Gb link speed (Full-duplex) */
2457 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB UINT32_C(0x8)
2459 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 \
2462 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 \
2464 /* 10Gb link speed */
2465 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \
2467 uint16_t eee_link_speed_mask;
2473 * Reuested setting of TX LPI timer in microseconds. This field is valid
2474 * only when EEE is enabled and TX LPI is enabled.
2476 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK \
2478 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0
2479 uint32_t tx_lpi_timer;
2482 } __attribute__((packed));
2484 /* Output (16 bytes) */
2485 struct hwrm_port_phy_cfg_output {
2487 * Pass/Fail or error type Note: receiver to verify the in parameters,
2488 * and fail the call with an error when appropriate
2490 uint16_t error_code;
2492 /* This field returns the type of original request. */
2495 /* This field provides original sequence number of the command. */
2499 * This field is the length of the response in bytes. The last byte of
2500 * the response is a valid flag that will read as '1' when the command
2501 * has been completely written to memory.
2511 * This field is used in Output records to indicate that the output is
2512 * completely written to RAM. This field should be read as '1' to
2513 * indicate that the output has been completely written. When writing a
2514 * command completion or response to an internal processor, the order of
2515 * writes has to be such that this field is written last.
2518 } __attribute__((packed));
2522 * Description: This function is called by a driver to determine the HWRM
2523 * interface version supported by the HWRM firmware, the version of HWRM
2524 * firmware implementation, the name of HWRM firmware, the versions of other
2525 * embedded firmwares, and the names of other embedded firmwares, etc. Any
2526 * interface or firmware version with major = 0, minor = 0, and update = 0 shall
2527 * be considered an invalid version.
2530 /* Input (24 bytes) */
2531 struct hwrm_ver_get_input {
2533 * This value indicates what type of request this is. The format for the
2534 * rest of the command is determined by this field.
2539 * This value indicates the what completion ring the request will be
2540 * optionally completed on. If the value is -1, then no CR completion
2541 * will be generated. Any other value must be a valid CR ring_id value
2542 * for this function.
2546 /* This value indicates the command sequence number. */
2550 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
2551 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
2556 * This is the host address where the response will be written when the
2557 * request is complete. This area must be 16B aligned and must be
2558 * cleared to zero before the request is made.
2563 * This field represents the major version of HWRM interface
2564 * specification supported by the driver HWRM implementation. The
2565 * interface major version is intended to change only when non backward
2566 * compatible changes are made to the HWRM interface specification.
2568 uint8_t hwrm_intf_maj;
2571 * This field represents the minor version of HWRM interface
2572 * specification supported by the driver HWRM implementation. A change
2573 * in interface minor version is used to reflect significant backward
2574 * compatible modification to HWRM interface specification. This can be
2575 * due to addition or removal of functionality. HWRM interface
2576 * specifications with the same major version but different minor
2577 * versions are compatible.
2579 uint8_t hwrm_intf_min;
2582 * This field represents the update version of HWRM interface
2583 * specification supported by the driver HWRM implementation. The
2584 * interface update version is used to reflect minor changes or bug
2585 * fixes to a released HWRM interface specification.
2587 uint8_t hwrm_intf_upd;
2589 uint8_t unused_0[5];
2590 } __attribute__((packed));
2592 /* Output (128 bytes) */
2593 struct hwrm_ver_get_output {
2595 * Pass/Fail or error type Note: receiver to verify the in parameters,
2596 * and fail the call with an error when appropriate
2598 uint16_t error_code;
2600 /* This field returns the type of original request. */
2603 /* This field provides original sequence number of the command. */
2607 * This field is the length of the response in bytes. The last byte of
2608 * the response is a valid flag that will read as '1' when the command
2609 * has been completely written to memory.
2614 * This field represents the major version of HWRM interface
2615 * specification supported by the HWRM implementation. The interface
2616 * major version is intended to change only when non backward compatible
2617 * changes are made to the HWRM interface specification. A HWRM
2618 * implementation that is compliant with this specification shall
2619 * provide value of 1 in this field.
2621 uint8_t hwrm_intf_maj;
2624 * This field represents the minor version of HWRM interface
2625 * specification supported by the HWRM implementation. A change in
2626 * interface minor version is used to reflect significant backward
2627 * compatible modification to HWRM interface specification. This can be
2628 * due to addition or removal of functionality. HWRM interface
2629 * specifications with the same major version but different minor
2630 * versions are compatible. A HWRM implementation that is compliant with
2631 * this specification shall provide value of 0 in this field.
2633 uint8_t hwrm_intf_min;
2636 * This field represents the update version of HWRM interface
2637 * specification supported by the HWRM implementation. The interface
2638 * update version is used to reflect minor changes or bug fixes to a
2639 * released HWRM interface specification. A HWRM implementation that is
2640 * compliant with this specification shall provide value of 1 in this
2643 uint8_t hwrm_intf_upd;
2645 uint8_t hwrm_intf_rsvd;
2648 * This field represents the major version of HWRM firmware. A change in
2649 * firmware major version represents a major firmware release.
2651 uint8_t hwrm_fw_maj;
2654 * This field represents the minor version of HWRM firmware. A change in
2655 * firmware minor version represents significant firmware functionality
2658 uint8_t hwrm_fw_min;
2661 * This field represents the build version of HWRM firmware. A change in
2662 * firmware build version represents bug fixes to a released firmware.
2664 uint8_t hwrm_fw_bld;
2667 * This field is a reserved field. This field can be used to represent
2668 * firmware branches or customer specific releases tied to a specific
2669 * (major,minor,update) version of the HWRM firmware.
2671 uint8_t hwrm_fw_rsvd;
2674 * This field represents the major version of mgmt firmware. A change in
2675 * major version represents a major release.
2677 uint8_t mgmt_fw_maj;
2680 * This field represents the minor version of mgmt firmware. A change in
2681 * minor version represents significant functionality changes.
2683 uint8_t mgmt_fw_min;
2686 * This field represents the build version of mgmt firmware. A change in
2687 * update version represents bug fixes.
2689 uint8_t mgmt_fw_bld;
2692 * This field is a reserved field. This field can be used to represent
2693 * firmware branches or customer specific releases tied to a specific
2694 * (major,minor,update) version
2696 uint8_t mgmt_fw_rsvd;
2699 * This field represents the major version of network control firmware.
2700 * A change in major version represents a major release.
2702 uint8_t netctrl_fw_maj;
2705 * This field represents the minor version of network control firmware.
2706 * A change in minor version represents significant functionality
2709 uint8_t netctrl_fw_min;
2712 * This field represents the build version of network control firmware.
2713 * A change in update version represents bug fixes.
2715 uint8_t netctrl_fw_bld;
2718 * This field is a reserved field. This field can be used to represent
2719 * firmware branches or customer specific releases tied to a specific
2720 * (major,minor,update) version
2722 uint8_t netctrl_fw_rsvd;
2725 * This field is reserved for future use. The responder should set it to
2726 * 0. The requester should ignore this field.
2731 * This field represents the major version of RoCE firmware. A change in
2732 * major version represents a major release.
2734 uint8_t roce_fw_maj;
2737 * This field represents the minor version of RoCE firmware. A change in
2738 * minor version represents significant functionality changes.
2740 uint8_t roce_fw_min;
2743 * This field represents the build version of RoCE firmware. A change in
2744 * update version represents bug fixes.
2746 uint8_t roce_fw_bld;
2749 * This field is a reserved field. This field can be used to represent
2750 * firmware branches or customer specific releases tied to a specific
2751 * (major,minor,update) version
2753 uint8_t roce_fw_rsvd;
2756 * This field represents the name of HWRM FW (ASCII chars without NULL
2759 char hwrm_fw_name[16];
2762 * This field represents the name of mgmt FW (ASCII chars without NULL
2765 char mgmt_fw_name[16];
2768 * This field represents the name of network control firmware (ASCII
2769 * chars without NULL at the end).
2771 char netctrl_fw_name[16];
2774 * This field is reserved for future use. The responder should set it to
2775 * 0. The requester should ignore this field.
2777 uint32_t reserved2[4];
2780 * This field represents the name of RoCE FW (ASCII chars without NULL
2783 char roce_fw_name[16];
2785 /* This field returns the chip number. */
2788 /* This field returns the revision of chip. */
2791 /* This field returns the chip metal number. */
2794 /* This field returns the bond id of the chip. */
2795 uint8_t chip_bond_id;
2798 * This value indicates the type of platform used for chip
2802 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC \
2803 (UINT32_C(0x0) << 0)
2804 /* FPGA platform of the chip. */
2805 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_FPGA \
2806 (UINT32_C(0x1) << 0)
2807 /* Palladium platform of the chip. */
2808 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM \
2809 (UINT32_C(0x2) << 0)
2810 uint8_t chip_platform_type;
2813 * This field returns the maximum value of request window that is
2814 * supported by the HWRM. The request window is mapped into device
2815 * address space using MMIO.
2817 uint16_t max_req_win_len;
2820 * This field returns the maximum value of response buffer in bytes. If
2821 * a request specifies the response buffer length that is greater than
2822 * this value, then the HWRM should fail it. The value of this field
2823 * shall be 4KB or more.
2825 uint16_t max_resp_len;
2828 * This field returns the default request timeout value in milliseconds.
2830 uint16_t def_req_timeout;
2837 * This field is used in Output records to indicate that the output is
2838 * completely written to RAM. This field should be read as '1' to
2839 * indicate that the output has been completely written. When writing a
2840 * command completion or response to an internal processor, the order of
2841 * writes has to be such that this field is written last.
2844 } __attribute__((packed));
2846 /* hwrm_queue_qportcfg */
2848 * Description: This function is called by a driver to query queue configuration
2849 * of a port. # The HWRM shall at least advertise one queue with lossy service
2850 * profile. # The driver shall use this command to query queue ids before
2851 * configuring or using any queues. # If a service profile is not set for a
2852 * queue, then the driver shall not use that queue without configuring a service
2853 * profile for it. # If the driver is not allowed to configure service profiles,
2854 * then the driver shall only use queues for which service profiles are pre-
2858 /* Input (24 bytes) */
2859 struct hwrm_queue_qportcfg_input {
2861 * This value indicates what type of request this is. The format for the
2862 * rest of the command is determined by this field.
2867 * This value indicates the what completion ring the request will be
2868 * optionally completed on. If the value is -1, then no CR completion
2869 * will be generated. Any other value must be a valid CR ring_id value
2870 * for this function.
2874 /* This value indicates the command sequence number. */
2878 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
2879 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
2884 * This is the host address where the response will be written when the
2885 * request is complete. This area must be 16B aligned and must be
2886 * cleared to zero before the request is made.
2891 * Enumeration denoting the RX, TX type of the resource. This
2892 * enumeration is used for resources that are similar for both TX and RX
2893 * paths of the chip.
2895 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH \
2898 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX \
2899 (UINT32_C(0x0) << 0)
2901 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX \
2902 (UINT32_C(0x1) << 0)
2903 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \
2904 HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX
2908 * Port ID of port for which the queue configuration is being queried.
2909 * This field is only required when sent by IPC.
2914 } __attribute__((packed));
2916 /* hwrm_stat_ctx_clr_stats */
2917 /* Description: This command clears statistics of a context. */
2919 /* Input (24 bytes) */
2920 struct hwrm_stat_ctx_clr_stats_input {
2922 * This value indicates what type of request this is. The format for the
2923 * rest of the command is determined by this field.
2928 * This value indicates the what completion ring the request will be
2929 * optionally completed on. If the value is -1, then no CR completion
2930 * will be generated. Any other value must be a valid CR ring_id value
2931 * for this function.
2935 /* This value indicates the command sequence number. */
2939 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
2940 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
2945 * This is the host address where the response will be written when the
2946 * request is complete. This area must be 16B aligned and must be
2947 * cleared to zero before the request is made.
2951 /* ID of the statistics context that is being queried. */
2952 uint32_t stat_ctx_id;
2955 } __attribute__((packed));
2957 /* Output (16 bytes) */
2958 struct hwrm_stat_ctx_clr_stats_output {
2960 * Pass/Fail or error type Note: receiver to verify the in parameters,
2961 * and fail the call with an error when appropriate
2963 uint16_t error_code;
2965 /* This field returns the type of original request. */
2968 /* This field provides original sequence number of the command. */
2972 * This field is the length of the response in bytes. The last byte of
2973 * the response is a valid flag that will read as '1' when the command
2974 * has been completely written to memory.
2984 * This field is used in Output records to indicate that the output is
2985 * completely written to RAM. This field should be read as '1' to
2986 * indicate that the output has been completely written. When writing a
2987 * command completion or response to an internal processor, the order of
2988 * writes has to be such that this field is written last.
2991 } __attribute__((packed));
2993 /* hwrm_vnic_rss_cfg */
2994 /* Description: This function is used to enable RSS configuration. */
2996 /* Input (48 bytes) */
2997 struct hwrm_vnic_rss_cfg_input {
2999 * This value indicates what type of request this is. The format for the
3000 * rest of the command is determined by this field.
3005 * This value indicates the what completion ring the request will be
3006 * optionally completed on. If the value is -1, then no CR completion
3007 * will be generated. Any other value must be a valid CR ring_id value
3008 * for this function.
3012 /* This value indicates the command sequence number. */
3016 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
3017 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
3022 * This is the host address where the response will be written when the
3023 * request is complete. This area must be 16B aligned and must be
3024 * cleared to zero before the request is made.
3029 * When this bit is '1', the RSS hash shall be computed over source and
3030 * destination IPv4 addresses of IPv4 packets.
3032 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
3034 * When this bit is '1', the RSS hash shall be computed over
3035 * source/destination IPv4 addresses and source/destination ports of
3038 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
3040 * When this bit is '1', the RSS hash shall be computed over
3041 * source/destination IPv4 addresses and source/destination ports of
3044 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
3046 * When this bit is '1', the RSS hash shall be computed over source and
3047 * destination IPv4 addresses of IPv6 packets.
3049 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
3051 * When this bit is '1', the RSS hash shall be computed over
3052 * source/destination IPv6 addresses and source/destination ports of
3055 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
3057 * When this bit is '1', the RSS hash shall be computed over
3058 * source/destination IPv6 addresses and source/destination ports of
3061 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
3066 /* This is the address for rss ring group table */
3067 uint64_t ring_grp_tbl_addr;
3069 /* This is the address for rss hash key table */
3070 uint64_t hash_key_tbl_addr;
3072 /* Index to the rss indirection table. */
3073 uint16_t rss_ctx_idx;
3075 uint16_t unused_1[3];
3076 } __attribute__((packed));
3078 /* Output (16 bytes) */
3079 struct hwrm_vnic_rss_cfg_output {
3081 * Pass/Fail or error type Note: receiver to verify the in parameters,
3082 * and fail the call with an error when appropriate
3084 uint16_t error_code;
3086 /* This field returns the type of original request. */
3089 /* This field provides original sequence number of the command. */
3093 * This field is the length of the response in bytes. The last byte of
3094 * the response is a valid flag that will read as '1' when the command
3095 * has been completely written to memory.
3105 * This field is used in Output records to indicate that the output is
3106 * completely written to RAM. This field should be read as '1' to
3107 * indicate that the output has been completely written. When writing a
3108 * command completion or response to an internal processor, the order of
3109 * writes has to be such that this field is written last.
3112 } __attribute__((packed));
3114 /* Output (32 bytes) */
3115 struct hwrm_queue_qportcfg_output {
3117 * Pass/Fail or error type Note: receiver to verify the in parameters,
3118 * and fail the call with an error when appropriate
3120 uint16_t error_code;
3122 /* This field returns the type of original request. */
3125 /* This field provides original sequence number of the command. */
3129 * This field is the length of the response in bytes. The last byte of
3130 * the response is a valid flag that will read as '1' when the command
3131 * has been completely written to memory.
3135 /* The maximum number of queues that can be configured. */
3136 uint8_t max_configurable_queues;
3138 /* The maximum number of lossless queues that can be configured. */
3139 uint8_t max_configurable_lossless_queues;
3142 * 0 - Not allowed. Non-zero - Allowed. If this value is non-zero, then
3143 * the HWRM shall allow the host SW driver to configure queues using
3146 uint8_t queue_cfg_allowed;
3149 * 0 - Not allowed. Non-zero - Allowed If this value is non-zero, then
3150 * the HWRM shall allow the host SW driver to configure queue buffers
3151 * using hwrm_queue_buffers_cfg.
3153 uint8_t queue_buffers_cfg_allowed;
3156 * 0 - Not allowed. Non-zero - Allowed If this value is non-zero, then
3157 * the HWRM shall allow the host SW driver to configure PFC using
3158 * hwrm_queue_pfcenable_cfg.
3160 uint8_t queue_pfcenable_cfg_allowed;
3163 * 0 - Not allowed. Non-zero - Allowed If this value is non-zero, then
3164 * the HWRM shall allow the host SW driver to configure Priority to CoS
3165 * mapping using hwrm_queue_pri2cos_cfg.
3167 uint8_t queue_pri2cos_cfg_allowed;
3170 * 0 - Not allowed. Non-zero - Allowed If this value is non-zero, then
3171 * the HWRM shall allow the host SW driver to configure CoS Bandwidth
3172 * configuration using hwrm_queue_cos2bw_cfg.
3174 uint8_t queue_cos2bw_cfg_allowed;
3176 /* ID of CoS Queue 0. FF - Invalid id */
3179 /* This value is applicable to CoS queues only. */
3180 /* Lossy (best-effort) */
3181 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \
3182 (UINT32_C(0x0) << 0)
3184 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \
3185 (UINT32_C(0x1) << 0)
3187 * Set to 0xFF... (All Fs) if there is no service profile
3190 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN \
3191 (UINT32_C(0xff) << 0)
3192 uint8_t queue_id0_service_profile;
3194 /* ID of CoS Queue 1. FF - Invalid id */
3196 /* This value is applicable to CoS queues only. */
3197 /* Lossy (best-effort) */
3198 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \
3199 (UINT32_C(0x0) << 0)
3201 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \
3202 (UINT32_C(0x1) << 0)
3204 * Set to 0xFF... (All Fs) if there is no service profile
3207 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN \
3208 (UINT32_C(0xff) << 0)
3209 uint8_t queue_id1_service_profile;
3211 /* ID of CoS Queue 2. FF - Invalid id */
3213 /* This value is applicable to CoS queues only. */
3214 /* Lossy (best-effort) */
3215 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \
3216 (UINT32_C(0x0) << 0)
3218 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \
3219 (UINT32_C(0x1) << 0)
3221 * Set to 0xFF... (All Fs) if there is no service profile
3224 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN \
3225 (UINT32_C(0xff) << 0)
3226 uint8_t queue_id2_service_profile;
3228 /* ID of CoS Queue 3. FF - Invalid id */
3231 /* This value is applicable to CoS queues only. */
3232 /* Lossy (best-effort) */
3233 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \
3234 (UINT32_C(0x0) << 0)
3236 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \
3237 (UINT32_C(0x1) << 0)
3239 * Set to 0xFF... (All Fs) if there is no service profile
3242 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN \
3243 (UINT32_C(0xff) << 0)
3244 uint8_t queue_id3_service_profile;
3246 /* ID of CoS Queue 4. FF - Invalid id */
3248 /* This value is applicable to CoS queues only. */
3249 /* Lossy (best-effort) */
3250 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \
3251 (UINT32_C(0x0) << 0)
3253 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \
3254 (UINT32_C(0x1) << 0)
3256 * Set to 0xFF... (All Fs) if there is no service profile
3259 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN \
3260 (UINT32_C(0xff) << 0)
3261 uint8_t queue_id4_service_profile;
3263 /* ID of CoS Queue 5. FF - Invalid id */
3266 /* This value is applicable to CoS queues only. */
3267 /* Lossy (best-effort) */
3268 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \
3269 (UINT32_C(0x0) << 0)
3271 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \
3272 (UINT32_C(0x1) << 0)
3274 * Set to 0xFF... (All Fs) if there is no service profile
3277 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN \
3278 (UINT32_C(0xff) << 0)
3279 uint8_t queue_id5_service_profile;
3281 /* ID of CoS Queue 6. FF - Invalid id */
3282 uint8_t queue_id6_service_profile;
3283 /* This value is applicable to CoS queues only. */
3284 /* Lossy (best-effort) */
3285 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \
3286 (UINT32_C(0x0) << 0)
3288 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \
3289 (UINT32_C(0x1) << 0)
3291 * Set to 0xFF... (All Fs) if there is no service profile
3294 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN \
3295 (UINT32_C(0xff) << 0)
3298 /* ID of CoS Queue 7. FF - Invalid id */
3301 /* This value is applicable to CoS queues only. */
3302 /* Lossy (best-effort) */
3303 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \
3304 (UINT32_C(0x0) << 0)
3306 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \
3307 (UINT32_C(0x1) << 0)
3309 * Set to 0xFF... (All Fs) if there is no service profile
3312 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \
3313 (UINT32_C(0xff) << 0)
3314 uint8_t queue_id7_service_profile;
3317 * This field is used in Output records to indicate that the output is
3318 * completely written to RAM. This field should be read as '1' to
3319 * indicate that the output has been completely written. When writing a
3320 * command completion or response to an internal processor, the order of
3321 * writes has to be such that this field is written last.
3324 } __attribute__((packed));
3326 /* hwrm_func_drv_rgtr */
3328 * Description: This command is used by the function driver to register its
3329 * information with the HWRM. A function driver shall implement this command. A
3330 * function driver shall use this command during the driver initialization right
3331 * after the HWRM version discovery and default ring resources allocation.
3334 /* Input (80 bytes) */
3335 struct hwrm_func_drv_rgtr_input {
3337 * This value indicates what type of request this is. The format for the
3338 * rest of the command is determined by this field.
3343 * This value indicates the what completion ring the request will be
3344 * optionally completed on. If the value is -1, then no CR completion
3345 * will be generated. Any other value must be a valid CR ring_id value
3346 * for this function.
3350 /* This value indicates the command sequence number. */
3354 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
3355 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
3360 * This is the host address where the response will be written when the
3361 * request is complete. This area must be 16B aligned and must be
3362 * cleared to zero before the request is made.
3367 * When this bit is '1', the function driver is requesting all requests
3368 * from its children VF drivers to be forwarded to itself. This flag can
3369 * only be set by the PF driver. If a VF driver sets this flag, it
3370 * should be ignored by the HWRM.
3372 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE UINT32_C(0x1)
3374 * When this bit is '1', the function is requesting none of the requests
3375 * from its children VF drivers to be forwarded to itself. This flag can
3376 * only be set by the PF driver. If a VF driver sets this flag, it
3377 * should be ignored by the HWRM.
3379 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE UINT32_C(0x2)
3382 /* This bit must be '1' for the os_type field to be configured. */
3383 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE UINT32_C(0x1)
3384 /* This bit must be '1' for the ver field to be configured. */
3385 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER UINT32_C(0x2)
3386 /* This bit must be '1' for the timestamp field to be configured. */
3387 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP UINT32_C(0x4)
3388 /* This bit must be '1' for the vf_req_fwd field to be configured. */
3389 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD UINT32_C(0x8)
3391 * This bit must be '1' for the async_event_fwd field to be configured.
3393 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD \
3397 /* This value indicates the type of OS. */
3399 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN \
3400 (UINT32_C(0x0) << 0)
3401 /* Other OS not listed below. */
3402 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER \
3403 (UINT32_C(0x1) << 0)
3405 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS \
3406 (UINT32_C(0xe) << 0)
3408 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS \
3409 (UINT32_C(0x12) << 0)
3411 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS \
3412 (UINT32_C(0x1d) << 0)
3414 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX \
3415 (UINT32_C(0x24) << 0)
3417 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD \
3418 (UINT32_C(0x2a) << 0)
3419 /* VMware ESXi OS. */
3420 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI \
3421 (UINT32_C(0x68) << 0)
3422 /* Microsoft Windows 8 64-bit OS. */
3423 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 \
3424 (UINT32_C(0x73) << 0)
3425 /* Microsoft Windows Server 2012 R2 OS. */
3426 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 \
3427 (UINT32_C(0x74) << 0)
3430 /* This is the major version of the driver. */
3433 /* This is the minor version of the driver. */
3436 /* This is the update version of the driver. */
3443 * This is a 32-bit timestamp provided by the driver for keep alive. The
3444 * timestamp is in multiples of 1ms.
3451 * This is a 256-bit bit mask provided by the PF driver for letting the
3452 * HWRM know what commands issued by the VF driver to the HWRM should be
3453 * forwarded to the PF driver. Nth bit refers to the Nth req_type.
3454 * Setting Nth bit to 1 indicates that requests from the VF driver with
3455 * req_type equal to N shall be forwarded to the parent PF driver. This
3456 * field is not valid for the VF driver.
3458 uint32_t vf_req_fwd[8];
3461 * This is a 256-bit bit mask provided by the function driver (PF or VF
3462 * driver) to indicate the list of asynchronous event completions to be
3463 * forwarded. Nth bit refers to the Nth event_id. Setting Nth bit to 1
3464 * by the function driver shall result in the HWRM forwarding
3465 * asynchronous event completion with event_id equal to N. If all bits
3466 * are set to 0 (value of 0), then the HWRM shall not forward any
3467 * asynchronous event completion to this function driver.
3469 uint32_t async_event_fwd[8];
3470 } __attribute__((packed));
3472 /* Output (16 bytes) */
3474 struct hwrm_func_drv_rgtr_output {
3476 * Pass/Fail or error type Note: receiver to verify the in parameters,
3477 * and fail the call with an error when appropriate
3479 uint16_t error_code;
3481 /* This field returns the type of original request. */
3484 /* This field provides original sequence number of the command. */
3488 * This field is the length of the response in bytes. The last byte of
3489 * the response is a valid flag that will read as '1' when the command
3490 * has been completely written to memory.
3500 * This field is used in Output records to indicate that the output is
3501 * completely written to RAM. This field should be read as '1' to
3502 * indicate that the output has been completely written. When writing a
3503 * command completion or response to an internal processor, the order of
3504 * writes has to be such that this field is written last.
3507 } __attribute__((packed));
3509 /* hwrm_func_drv_unrgtr */
3511 * Description: This command is used by the function driver to un register with
3512 * the HWRM. A function driver shall implement this command. A function driver
3513 * shall use this command during the driver unloading.
3515 /* Input (24 bytes) */
3517 struct hwrm_func_drv_unrgtr_input {
3519 * This value indicates what type of request this is. The format for the
3520 * rest of the command is determined by this field.
3525 * This value indicates the what completion ring the request will be
3526 * optionally completed on. If the value is -1, then no CR completion
3527 * will be generated. Any other value must be a valid CR ring_id value
3528 * for this function.
3532 /* This value indicates the command sequence number. */
3536 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
3537 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
3542 * This is the host address where the response will be written when the
3543 * request is complete. This area must be 16B aligned and must be
3544 * cleared to zero before the request is made.
3549 * When this bit is '1', the function driver is notifying the HWRM to
3550 * prepare for the shutdown.
3552 #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN \
3557 } __attribute__((packed));
3559 /* Output (16 bytes) */
3560 struct hwrm_func_drv_unrgtr_output {
3562 * Pass/Fail or error type Note: receiver to verify the in parameters,
3563 * and fail the call with an error when appropriate
3565 uint16_t error_code;
3567 /* This field returns the type of original request. */
3570 /* This field provides original sequence number of the command. */
3574 * This field is the length of the response in bytes. The last byte of
3575 * the response is a valid flag that will read as '1' when the command
3576 * has been completely written to memory.
3586 * This field is used in Output records to indicate that the output is
3587 * completely written to RAM. This field should be read as '1' to
3588 * indicate that the output has been completely written. When writing a
3589 * command completion or response to an internal processor, the order of
3590 * writes has to be such that this field is written last.
3593 } __attribute__((packed));