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34 #ifndef _HSI_STRUCT_DEF_EXTERNAL_H_
35 #define _HSI_STRUCT_DEF_EXTERNAL_H_
38 * per-context HW statistics -- chip view
41 struct ctx_hw_stats64 {
42 uint64_t rx_ucast_pkts;
43 uint64_t rx_mcast_pkts;
44 uint64_t rx_bcast_pkts;
45 uint64_t rx_drop_pkts;
47 uint64_t rx_ucast_bytes;
48 uint64_t rx_mcast_bytes;
49 uint64_t rx_bcast_bytes;
51 uint64_t tx_ucast_pkts;
52 uint64_t tx_mcast_pkts;
53 uint64_t tx_bcast_pkts;
54 uint64_t tx_drop_pkts;
56 uint64_t tx_ucast_bytes;
57 uint64_t tx_mcast_bytes;
58 uint64_t tx_bcast_bytes;
66 /* HW Resource Manager Specification 1.2.0 */
67 #define HWRM_VERSION_MAJOR 1
68 #define HWRM_VERSION_MINOR 2
69 #define HWRM_VERSION_UPDATE 0
72 * Following is the signature for HWRM message field that indicates not
73 * applicable (All F's). Need to cast it the size of the field if needed.
75 #define HWRM_NA_SIGNATURE ((uint32_t)(-1))
76 #define HWRM_MAX_REQ_LEN (128) /* hwrm_func_buf_rgtr */
77 #define HWRM_MAX_RESP_LEN (176) /* hwrm_func_qstats */
78 #define HW_HASH_INDEX_SIZE 0x80 /* 7 bit indirection table index. */
79 #define HW_HASH_KEY_SIZE 40
80 #define HWRM_RESP_VALID_KEY 1 /* valid key for HWRM response */
85 #define HWRM_VER_GET (UINT32_C(0x0))
86 #define HWRM_FUNC_RESET (UINT32_C(0x11))
87 #define HWRM_FUNC_QCAPS (UINT32_C(0x15))
88 #define HWRM_FUNC_DRV_UNRGTR (UINT32_C(0x1a))
89 #define HWRM_FUNC_DRV_RGTR (UINT32_C(0x1d))
90 #define HWRM_PORT_PHY_CFG (UINT32_C(0x20))
91 #define HWRM_QUEUE_QPORTCFG (UINT32_C(0x30))
92 #define HWRM_CFA_L2_FILTER_ALLOC (UINT32_C(0x90))
93 #define HWRM_CFA_L2_FILTER_FREE (UINT32_C(0x91))
94 #define HWRM_CFA_L2_FILTER_CFG (UINT32_C(0x92))
95 #define HWRM_CFA_L2_SET_RX_MASK (UINT32_C(0x93))
96 #define HWRM_STAT_CTX_CLR_STATS (UINT32_C(0xb3))
97 #define HWRM_EXEC_FWD_RESP (UINT32_C(0xd0))
100 #define HWRM_ERR_CODE_INVALID_PARAMS (UINT32_C(0x2))
101 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED (UINT32_C(0x3))
103 /* Short TX BD (16 bytes) */
106 * All bits in this field must be valid on the first BD of a packet.
107 * Only the packet_end bit must be valid for the remaining BDs of a
110 /* This value identifies the type of buffer descriptor. */
111 #define TX_BD_SHORT_TYPE_MASK UINT32_C(0x3f)
112 #define TX_BD_SHORT_TYPE_SFT 0
114 * Indicates that this BD is 16B long and is used for normal L2
115 * packet transmission.
117 #define TX_BD_SHORT_TYPE_TX_BD_SHORT (UINT32_C(0x0) << 0)
119 * If set to 1, the packet ends with the data in the buffer pointed to
120 * by this descriptor. This flag must be valid on every BD.
122 #define TX_BD_SHORT_FLAGS_PACKET_END UINT32_C(0x40)
124 * If set to 1, the device will not generate a completion for this
125 * transmit packet unless there is an error in it's processing. If this
126 * bit is set to 0, then the packet will be completed normally. This bit
127 * must be valid only on the first BD of a packet.
129 #define TX_BD_SHORT_FLAGS_NO_CMPL UINT32_C(0x80)
131 * This value indicates how many 16B BD locations are consumed in the
132 * ring by this packet. A value of 1 indicates that this BD is the only
133 * BD (and that the it is a short BD). A value of 3 indicates either 3
134 * short BDs or 1 long BD and one short BD in the packet. A value of 0
135 * indicates that there are 32 BD locations in the packet (the maximum).
136 * This field is valid only on the first BD of a packet.
138 #define TX_BD_SHORT_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
139 #define TX_BD_SHORT_FLAGS_BD_CNT_SFT 8
141 * This value is a hint for the length of the entire packet. It is used
142 * by the chip to optimize internal processing. The packet will be
143 * dropped if the hint is too short. This field is valid only on the
144 * first BD of a packet.
146 #define TX_BD_SHORT_FLAGS_LHINT_MASK UINT32_C(0x6000)
147 #define TX_BD_SHORT_FLAGS_LHINT_SFT 13
148 /* indicates packet length < 512B */
149 #define TX_BD_SHORT_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
150 /* indicates 512 <= packet length < 1KB */
151 #define TX_BD_SHORT_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
152 /* indicates 1KB <= packet length < 2KB */
153 #define TX_BD_SHORT_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
154 /* indicates packet length >= 2KB */
155 #define TX_BD_SHORT_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
156 #define TX_BD_SHORT_FLAGS_LHINT_LAST TX_BD_SHORT_FLAGS_LHINT_GTE2K
158 * If set to 1, the device immediately updates the Send Consumer Index
159 * after the buffer associated with this descriptor has been transferred
160 * via DMA to NIC memory from host memory. An interrupt may or may not
161 * be generated according to the state of the interrupt avoidance
162 * mechanisms. If this bit is set to 0, then the Consumer Index is only
163 * updated as soon as one of the host interrupt coalescing conditions
164 * has been met. This bit must be valid on the first BD of a packet.
166 #define TX_BD_SHORT_FLAGS_COAL_NOW UINT32_C(0x8000)
168 * All bits in this field must be valid on the first BD of a packet.
169 * Only the packet_end bit must be valid for the remaining BDs of a
172 #define TX_BD_SHORT_FLAGS_MASK UINT32_C(0xffc0)
173 #define TX_BD_SHORT_FLAGS_SFT 6
177 * This is the length of the host physical buffer this BD describes in
178 * bytes. This field must be valid on all BDs of a packet.
182 * The opaque data field is pass through to the completion and can be
183 * used for any data that the driver wants to associate with the
184 * transmit BD. This field must be valid on the first BD of a packet.
189 * This is the host physical address for the portion of the packet
190 * described by this TX BD. This value must be valid on all BDs of a
194 } __attribute__((packed));
196 /* Long TX BD (32 bytes split to 2 16-byte struct) */
199 * All bits in this field must be valid on the first BD of a packet.
200 * Only the packet_end bit must be valid for the remaining BDs of a
203 /* This value identifies the type of buffer descriptor. */
204 #define TX_BD_LONG_TYPE_MASK UINT32_C(0x3f)
205 #define TX_BD_LONG_TYPE_SFT 0
207 * Indicates that this BD is 32B long and is used for normal L2
208 * packet transmission.
210 #define TX_BD_LONG_TYPE_TX_BD_LONG (UINT32_C(0x10) << 0)
212 * If set to 1, the packet ends with the data in the buffer pointed to
213 * by this descriptor. This flag must be valid on every BD.
215 #define TX_BD_LONG_FLAGS_PACKET_END UINT32_C(0x40)
217 * If set to 1, the device will not generate a completion for this
218 * transmit packet unless there is an error in it's processing. If this
219 * bit is set to 0, then the packet will be completed normally. This bit
220 * must be valid only on the first BD of a packet.
222 #define TX_BD_LONG_FLAGS_NO_CMPL UINT32_C(0x80)
224 * This value indicates how many 16B BD locations are consumed in the
225 * ring by this packet. A value of 1 indicates that this BD is the only
226 * BD (and that the it is a short BD). A value of 3 indicates either 3
227 * short BDs or 1 long BD and one short BD in the packet. A value of 0
228 * indicates that there are 32 BD locations in the packet (the maximum).
229 * This field is valid only on the first BD of a packet.
231 #define TX_BD_LONG_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
232 #define TX_BD_LONG_FLAGS_BD_CNT_SFT 8
234 * This value is a hint for the length of the entire packet. It is used
235 * by the chip to optimize internal processing. The packet will be
236 * dropped if the hint is too short. This field is valid only on the
237 * first BD of a packet.
239 #define TX_BD_LONG_FLAGS_LHINT_MASK UINT32_C(0x6000)
240 #define TX_BD_LONG_FLAGS_LHINT_SFT 13
241 /* indicates packet length < 512B */
242 #define TX_BD_LONG_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
243 /* indicates 512 <= packet length < 1KB */
244 #define TX_BD_LONG_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
245 /* indicates 1KB <= packet length < 2KB */
246 #define TX_BD_LONG_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
247 /* indicates packet length >= 2KB */
248 #define TX_BD_LONG_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
249 #define TX_BD_LONG_FLAGS_LHINT_LAST TX_BD_LONG_FLAGS_LHINT_GTE2K
251 * If set to 1, the device immediately updates the Send Consumer Index
252 * after the buffer associated with this descriptor has been transferred
253 * via DMA to NIC memory from host memory. An interrupt may or may not
254 * be generated according to the state of the interrupt avoidance
255 * mechanisms. If this bit is set to 0, then the Consumer Index is only
256 * updated as soon as one of the host interrupt coalescing conditions
257 * has been met. This bit must be valid on the first BD of a packet.
259 #define TX_BD_LONG_FLAGS_COAL_NOW UINT32_C(0x8000)
261 * All bits in this field must be valid on the first BD of a packet.
262 * Only the packet_end bit must be valid for the remaining BDs of a
265 #define TX_BD_LONG_FLAGS_MASK UINT32_C(0xffc0)
266 #define TX_BD_LONG_FLAGS_SFT 6
270 * This is the length of the host physical buffer this BD describes in
271 * bytes. This field must be valid on all BDs of a packet.
276 * The opaque data field is pass through to the completion and can be
277 * used for any data that the driver wants to associate with the
278 * transmit BD. This field must be valid on the first BD of a packet.
283 * This is the host physical address for the portion of the packet
284 * described by this TX BD. This value must be valid on all BDs of a
288 } __attribute__((packed));
290 /* last 16 bytes of Long TX BD */
292 struct tx_bd_long_hi {
294 * All bits in this field must be valid on the first BD of a packet.
295 * Their value on other BDs of the packet will be ignored.
298 * If set to 1, the controller replaces the TCP/UPD checksum fields of
299 * normal TCP/UPD checksum, or the inner TCP/UDP checksum field of the
300 * encapsulated TCP/UDP packets with the hardware calculated TCP/UDP
301 * checksum for the packet associated with this descriptor. This bit
302 * must be valid on the first BD of a packet.
304 #define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
306 * If set to 1, the controller replaces the IP checksum of the normal
307 * packets, or the inner IP checksum of the encapsulated packets with
308 * the hardware calculated IP checksum for the packet associated with
309 * this descriptor. This bit must be valid on the first BD of a packet.
311 #define TX_BD_LONG_LFLAGS_IP_CHKSUM UINT32_C(0x2)
313 * If set to 1, the controller will not append an Ethernet CRC to the
314 * end of the frame. This bit must be valid on the first BD of a packet.
315 * Packet must be 64B or longer when this flag is set. It is not useful
316 * to use this bit with any form of TX offload such as CSO or LSO. The
317 * intent is that the packet from the host already has a valid Ethernet
320 #define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4)
322 * If set to 1, the device will record the time at which the packet was
323 * actually transmitted at the TX MAC. This bit must be valid on the
324 * first BD of a packet.
326 #define TX_BD_LONG_LFLAGS_STAMP UINT32_C(0x8)
328 * If set to 1, The controller replaces the tunnel IP checksum field
329 * with hardware calculated IP checksum for the IP header of the packet
330 * associated with this descriptor. In case of VXLAN, the controller
331 * also replaces the outer header UDP checksum with hardware calculated
332 * UDP checksum for the packet associated with this descriptor.
334 #define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
336 * If set to 1, the device will treat this packet with LSO(Large Send
337 * Offload) processing for both normal or encapsulated packets, which is
338 * a form of TCP segmentation. When this bit is 1, the hdr_size and mss
339 * fields must be valid. The driver doesn't need to set t_ip_chksum,
340 * ip_chksum, and tcp_udp_chksum flags since the controller will replace
341 * the appropriate checksum fields for segmented packets. When this bit
342 * is 1, the hdr_size and mss fields must be valid.
344 #define TX_BD_LONG_LFLAGS_LSO UINT32_C(0x20)
346 * If set to zero when LSO is '1', then the IPID will be treated as a
347 * 16b number and will be wrapped if it exceeds a value of 0xffff. If
348 * set to one when LSO is '1', then the IPID will be treated as a 15b
349 * number and will be wrapped if it exceeds a value 0f 0x7fff.
351 #define TX_BD_LONG_LFLAGS_IPID_FMT UINT32_C(0x40)
353 * If set to zero when LSO is '1', then the IPID of the tunnel IP header
354 * will not be modified during LSO operations. If set to one when LSO is
355 * '1', then the IPID of the tunnel IP header will be incremented for
356 * each subsequent segment of an LSO operation.
358 #define TX_BD_LONG_LFLAGS_T_IPID UINT32_C(0x80)
360 * If set to '1', then the RoCE ICRC will be appended to the packet.
361 * Packet must be a valid RoCE format packet.
363 #define TX_BD_LONG_LFLAGS_ROCE_CRC UINT32_C(0x100)
365 * If set to '1', then the FCoE CRC will be appended to the packet.
366 * Packet must be a valid FCoE format packet.
368 #define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200)
372 * When LSO is '1', this field must contain the offset of the TCP
373 * payload from the beginning of the packet in as 16b words. In case of
374 * encapsulated/tunneling packet, this field contains the offset of the
375 * inner TCP payload from beginning of the packet as 16-bit words. This
376 * value must be valid on the first BD of a packet.
378 #define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff)
379 #define TX_BD_LONG_HDR_SIZE_SFT 0
383 * This is the MSS value that will be used to do the LSO processing. The
384 * value is the length in bytes of the TCP payload for each segment
385 * generated by the LSO operation. This value must be valid on the first
388 #define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff)
389 #define TX_BD_LONG_MSS_SFT 0
395 * This value selects a CFA action to perform on the packet. Set this
396 * value to zero if no CFA action is desired. This value must be valid
397 * on the first BD of a packet.
402 * This value is action meta-data that defines CFA edit operations that
403 * are done in addition to any action editing.
405 /* When key=1, This is the VLAN tag VID value. */
406 #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
407 #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0
408 /* When key=1, This is the VLAN tag DE value. */
409 #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000)
410 /* When key=1, This is the VLAN tag PRI value. */
411 #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
412 #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13
413 /* When key=1, This is the VLAN tag TPID select value. */
414 #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
415 #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16
417 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
419 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
421 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
423 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
425 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
426 /* Value programmed in CFA VLANTPID register. */
427 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
428 #define TX_BD_LONG_CFA_META_VLAN_TPID_LAST \
429 TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG
430 /* When key=1, This is the VLAN tag TPID select value. */
431 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
432 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19
434 * This field identifies the type of edit to be performed on the packet.
435 * This value must be valid on the first BD of a packet.
437 #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000)
438 #define TX_BD_LONG_CFA_META_KEY_SFT 28
440 #define TX_BD_LONG_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
442 * - meta[17:16] - TPID select value (0 = 0x8100). - meta[15:12]
443 * - PRI/DE value. - meta[11:0] - VID value.
445 #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
446 #define TX_BD_LONG_CFA_META_KEY_LAST TX_BD_LONG_CFA_META_KEY_VLAN_TAG
448 } __attribute__((packed));
450 /* RX Producer Packet BD (16 bytes) */
451 struct rx_prod_pkt_bd {
452 /* This value identifies the type of buffer descriptor. */
453 #define RX_PROD_PKT_BD_TYPE_MASK UINT32_C(0x3f)
454 #define RX_PROD_PKT_BD_TYPE_SFT 0
456 * Indicates that this BD is 16B long and is an RX Producer (ie.
457 * empty) buffer descriptor.
459 #define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT (UINT32_C(0x4) << 0)
461 * If set to 1, the packet will be placed at the address plus 2B. The 2
462 * Bytes of padding will be written as zero.
465 * This is intended to be used when the host buffer is cache-line
466 * aligned to produce packets that are easy to parse in host memory
467 * while still allowing writes to be cache line aligned.
469 #define RX_PROD_PKT_BD_FLAGS_SOP_PAD UINT32_C(0x40)
471 * If set to 1, the packet write will be padded out to the nearest
472 * cache-line with zero value padding.
475 * If receive buffers start/end on cache-line boundaries, this feature
476 * will ensure that all data writes on the PCI bus start/end on cache
479 #define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80)
481 * This value is the number of additional buffers in the ring that
482 * describe the buffer space to be consumed for the this packet. If the
483 * value is zero, then the packet must fit within the space described by
484 * this BD. If this value is 1 or more, it indicates how many additional
485 * "buffer" BDs are in the ring immediately following this BD to be used
486 * for the same network packet. Even if the packet to be placed does not
487 * need all the additional buffers, they will be consumed anyway.
489 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300)
490 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT 8
491 #define RX_PROD_PKT_BD_FLAGS_MASK UINT32_C(0xffc0)
492 #define RX_PROD_PKT_BD_FLAGS_SFT 6
496 * This is the length in Bytes of the host physical buffer where data
497 * for the packet may be placed in host memory.
500 * While this is a Byte resolution value, it is often advantageous to
501 * ensure that the buffers provided end on a host cache line.
506 * The opaque data field is pass through to the completion and can be
507 * used for any data that the driver wants to associate with this
508 * receive buffer set.
513 * This is the host physical address where data for the packet may by
514 * placed in host memory.
517 * While this is a Byte resolution value, it is often advantageous to
518 * ensure that the buffers provide start on a host cache line.
521 } __attribute__((packed));
523 /* Completion Ring Structures */
524 /* Note: This structure is used by the HWRM to communicate HWRM Error. */
525 /* Base Completion Record (16 bytes) */
529 * This field indicates the exact type of the completion. By convention,
530 * the LSB identifies the length of the record in 16B units. Even values
531 * indicate 16B records. Odd values indicate 32B records.
533 #define CMPL_BASE_TYPE_MASK UINT32_C(0x3f)
534 #define CMPL_BASE_TYPE_SFT 0
535 /* TX L2 completion: Completion of TX packet. Length = 16B */
536 #define CMPL_BASE_TYPE_TX_L2 (UINT32_C(0x0) << 0)
538 * RX L2 completion: Completion of and L2 RX packet.
541 #define CMPL_BASE_TYPE_RX_L2 (UINT32_C(0x11) << 0)
543 * RX Aggregation Buffer completion : Completion of an L2
544 * aggregation buffer in support of TPA, HDS, or Jumbo packet
545 * completion. Length = 16B
547 #define CMPL_BASE_TYPE_RX_AGG (UINT32_C(0x12) << 0)
549 * RX L2 TPA Start Completion: Completion at the beginning of a
550 * TPA operation. Length = 32B
552 #define CMPL_BASE_TYPE_RX_TPA_START (UINT32_C(0x13) << 0)
554 * RX L2 TPA End Completion: Completion at the end of a TPA
555 * operation. Length = 32B
557 #define CMPL_BASE_TYPE_RX_TPA_END (UINT32_C(0x15) << 0)
559 * Statistics Ejection Completion: Completion of statistics data
560 * ejection buffer. Length = 16B
562 #define CMPL_BASE_TYPE_STAT_EJECT (UINT32_C(0x1a) << 0)
563 /* HWRM Command Completion: Completion of an HWRM command. */
564 #define CMPL_BASE_TYPE_HWRM_DONE (UINT32_C(0x20) << 0)
565 /* Forwarded HWRM Request */
566 #define CMPL_BASE_TYPE_HWRM_FWD_REQ (UINT32_C(0x22) << 0)
567 /* Forwarded HWRM Response */
568 #define CMPL_BASE_TYPE_HWRM_FWD_RESP (UINT32_C(0x24) << 0)
569 /* HWRM Asynchronous Event Information */
570 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT (UINT32_C(0x2e) << 0)
571 /* CQ Notification */
572 #define CMPL_BASE_TYPE_CQ_NOTIFICATION (UINT32_C(0x30) << 0)
573 /* SRQ Threshold Event */
574 #define CMPL_BASE_TYPE_SRQ_EVENT (UINT32_C(0x32) << 0)
575 /* DBQ Threshold Event */
576 #define CMPL_BASE_TYPE_DBQ_EVENT (UINT32_C(0x34) << 0)
577 /* QP Async Notification */
578 #define CMPL_BASE_TYPE_QP_EVENT (UINT32_C(0x38) << 0)
579 /* Function Async Notification */
580 #define CMPL_BASE_TYPE_FUNC_EVENT (UINT32_C(0x3a) << 0)
587 * This value is written by the NIC such that it will be different for
588 * each pass through the completion queue. The even passes will write 1.
589 * The odd passes will write 0.
591 #define CMPL_BASE_V UINT32_C(0x1)
593 #define CMPL_BASE_INFO3_MASK UINT32_C(0xfffffffe)
594 #define CMPL_BASE_INFO3_SFT 1
598 } __attribute__((packed));
600 /* TX Completion Record (16 bytes) */
603 * This field indicates the exact type of the completion. By convention,
604 * the LSB identifies the length of the record in 16B units. Even values
605 * indicate 16B records. Odd values indicate 32B records.
607 #define TX_CMPL_TYPE_MASK UINT32_C(0x3f)
608 #define TX_CMPL_TYPE_SFT 0
609 /* TX L2 completion: Completion of TX packet. Length = 16B */
610 #define TX_CMPL_TYPE_TX_L2 (UINT32_C(0x0) << 0)
612 * When this bit is '1', it indicates a packet that has an error of some
613 * type. Type of error is indicated in error_flags.
615 #define TX_CMPL_FLAGS_ERROR UINT32_C(0x40)
617 * When this bit is '1', it indicates that the packet completed was
618 * transmitted using the push acceleration data provided by the driver.
619 * When this bit is '0', it indicates that the packet had not push
620 * acceleration data written or was executed as a normal packet even
621 * though push data was provided.
623 #define TX_CMPL_FLAGS_PUSH UINT32_C(0x80)
624 #define TX_CMPL_FLAGS_MASK UINT32_C(0xffc0)
625 #define TX_CMPL_FLAGS_SFT 6
631 * This is a copy of the opaque field from the first TX BD of this
632 * transmitted packet.
637 * This value is written by the NIC such that it will be different for
638 * each pass through the completion queue. The even passes will write 1.
639 * The odd passes will write 0.
641 #define TX_CMPL_V UINT32_C(0x1)
643 * This error indicates that there was some sort of problem with the BDs
646 #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
647 #define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1
649 #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR (UINT32_C(0x0) << 1)
650 /* Bad Format: BDs were not formatted correctly. */
651 #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT (UINT32_C(0x2) << 1)
652 #define TX_CMPL_ERRORS_BUFFER_ERROR_LAST \
653 TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT
655 * When this bit is '1', it indicates that the length of the packet was
656 * zero. No packet was transmitted.
658 #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
660 * When this bit is '1', it indicates that the packet was longer than
661 * the programmed limit in TDI. No packet was transmitted.
663 #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
665 * When this bit is '1', it indicates that one or more of the BDs
666 * associated with this packet generated a PCI error. This probably
667 * means the address was not valid.
669 #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40)
671 * When this bit is '1', it indicates that the packet was longer than
672 * indicated by the hint. No packet was transmitted.
674 #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
676 * When this bit is '1', it indicates that the packet was dropped due to
677 * Poison TLP error on one or more of the TLPs in the PXP completion.
679 #define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
680 #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe)
681 #define TX_CMPL_ERRORS_SFT 1
686 } __attribute__((packed)) tx_cmpl_t, *ptx_cmpl_t;
688 /* RX Packet Completion Record (32 bytes split to 2 16-byte struct) */
691 * This field indicates the exact type of the completion. By convention,
692 * the LSB identifies the length of the record in 16B units. Even values
693 * indicate 16B records. Odd values indicate 32B records.
695 #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f)
696 #define RX_PKT_CMPL_TYPE_SFT 0
698 * RX L2 completion: Completion of and L2 RX packet.
701 #define RX_PKT_CMPL_TYPE_RX_L2 (UINT32_C(0x11) << 0)
703 * When this bit is '1', it indicates a packet that has an error of some
704 * type. Type of error is indicated in error_flags.
706 #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40)
707 /* This field indicates how the packet was placed in the buffer. */
708 #define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
709 #define RX_PKT_CMPL_FLAGS_PLACEMENT_SFT 7
710 /* Normal: Packet was placed using normal algorithm. */
711 #define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7)
712 /* Jumbo: Packet was placed using jumbo algorithm. */
713 #define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
715 * Header/Data Separation: Packet was placed using Header/Data
716 * separation algorithm. The separation location is indicated by
719 #define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
720 #define RX_PKT_CMPL_FLAGS_PLACEMENT_LAST \
721 RX_PKT_CMPL_FLAGS_PLACEMENT_HDS
722 /* This bit is '1' if the RSS field in this completion is valid. */
723 #define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
725 * This value indicates what the inner packet determined for the packet
728 #define RX_PKT_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
729 #define RX_PKT_CMPL_FLAGS_ITYPE_SFT 12
730 /* Not Known: Indicates that the packet type was not known. */
731 #define RX_PKT_CMPL_FLAGS_ITYPE_NOT_KNOWN (UINT32_C(0x0) << 12)
733 * IP Packet: Indicates that the packet was an IP packet, but
734 * further classification was not possible.
736 #define RX_PKT_CMPL_FLAGS_ITYPE_IP (UINT32_C(0x1) << 12)
738 * TCP Packet: Indicates that the packet was IP and TCP. This
739 * indicates that the payload_offset field is valid.
741 #define RX_PKT_CMPL_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 12)
743 * UDP Packet: Indicates that the packet was IP and UDP. This
744 * indicates that the payload_offset field is valid.
746 #define RX_PKT_CMPL_FLAGS_ITYPE_UDP (UINT32_C(0x3) << 12)
748 * FCoE Packet: Indicates that the packet was recognized as a
749 * FCoE. This also indicates that the payload_offset field is
752 #define RX_PKT_CMPL_FLAGS_ITYPE_FCOE (UINT32_C(0x4) << 12)
754 * RoCE Packet: Indicates that the packet was recognized as a
755 * RoCE. This also indicates that the payload_offset field is
758 #define RX_PKT_CMPL_FLAGS_ITYPE_ROCE (UINT32_C(0x5) << 12)
760 * ICMP Packet: Indicates that the packet was recognized as
761 * ICMP. This indicates that the payload_offset field is valid.
763 #define RX_PKT_CMPL_FLAGS_ITYPE_ICMP (UINT32_C(0x7) << 12)
765 * PtP packet wo/timestamp: Indicates that the packet was
766 * recognized as a PtP packet.
768 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
769 (UINT32_C(0x8) << 12)
771 * PtP packet w/timestamp: Indicates that the packet was
772 * recognized as a PtP packet and that a timestamp was taken for
775 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP (UINT32_C(0x9) << 12)
776 #define RX_PKT_CMPL_FLAGS_ITYPE_LAST \
777 RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
778 #define RX_PKT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
779 #define RX_PKT_CMPL_FLAGS_SFT 6
783 * This is the length of the data for the packet stored in the buffer(s)
784 * identified by the opaque value. This includes the packet BD and any
785 * associated buffer BDs. This does not include the the length of any
786 * data places in aggregation BDs.
791 * This is a copy of the opaque field from the RX BD this completion
797 * This value is written by the NIC such that it will be different for
798 * each pass through the completion queue. The even passes will write 1.
799 * The odd passes will write 0.
801 #define RX_PKT_CMPL_V1 UINT32_C(0x1)
803 * This value is the number of aggregation buffers that follow this
804 * entry in the completion ring that are a part of this packet. If the
805 * value is zero, then the packet is completely contained in the buffer
806 * space provided for the packet in the RX ring.
808 #define RX_PKT_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
809 #define RX_PKT_CMPL_AGG_BUFS_SFT 1
813 * This is the RSS hash type for the packet. The value is packed
814 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
816 uint8_t rss_hash_type;
819 * This value indicates the offset from the beginning of the packet
820 * where the inner payload starts. This value is valid for TCP, UDP,
821 * FCoE, and RoCE packets.
823 uint8_t payload_offset;
828 * This value is the RSS hash value calculated for the packet based on
829 * the mode bits and key value in the VNIC.
832 } __attribute__((packed));
834 /* last 16 bytes of RX Packet Completion Record */
835 struct rx_pkt_cmpl_hi {
837 * This indicates that the ip checksum was calculated for the inner
838 * packet and that the ip_cs_error field indicates if there was an
841 #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
843 * This indicates that the TCP, UDP or ICMP checksum was calculated for
844 * the inner packet and that the l4_cs_error field indicates if there
847 #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
849 * This indicates that the ip checksum was calculated for the tunnel
850 * header and that the t_ip_cs_error field indicates if there was an
853 #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
855 * This indicates that the UDP checksum was calculated for the tunnel
856 * packet and that the t_l4_cs_error field indicates if there was an
859 #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
860 /* This value indicates what format the metadata field is. */
861 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
862 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
863 /* No metadata informtaion. Value is zero. */
864 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
866 * The metadata field contains the VLAN tag and TPID value. -
867 * metadata[11:0] contains the vlan VID value. - metadata[12]
868 * contains the vlan DE value. - metadata[15:13] contains the
869 * vlan PRI value. - metadata[31:16] contains the vlan TPID
872 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN (UINT32_C(0x1) << 4)
873 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST \
874 RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN
876 * This field indicates the IP type for the inner-most IP header. A
877 * value of '0' indicates IPv4. A value of '1' indicates IPv6. This
878 * value is only valid if itype indicates a packet with an IP header.
880 #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
884 * This is data from the CFA block as indicated by the meta_format
887 /* When meta_format=1, this value is the VLAN VID. */
888 #define RX_PKT_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
889 #define RX_PKT_CMPL_METADATA_VID_SFT 0
890 /* When meta_format=1, this value is the VLAN DE. */
891 #define RX_PKT_CMPL_METADATA_DE UINT32_C(0x1000)
892 /* When meta_format=1, this value is the VLAN PRI. */
893 #define RX_PKT_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
894 #define RX_PKT_CMPL_METADATA_PRI_SFT 13
895 /* When meta_format=1, this value is the VLAN TPID. */
896 #define RX_PKT_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
897 #define RX_PKT_CMPL_METADATA_TPID_SFT 16
901 * This value is written by the NIC such that it will be different for
902 * each pass through the completion queue. The even passes will write 1.
903 * The odd passes will write 0.
905 #define RX_PKT_CMPL_V2 UINT32_C(0x1)
907 * This error indicates that there was some sort of problem with the BDs
908 * for the packet that was found after part of the packet was already
909 * placed. The packet should be treated as invalid.
911 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
912 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
913 /* No buffer error */
914 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
917 * Did Not Fit: Packet did not fit into packet buffer provided.
918 * For regular placement, this means the packet did not fit in
919 * the buffer provided. For HDS and jumbo placement, this means
920 * that the packet could not be placed into 7 physical buffers
923 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
926 * Not On Chip: All BDs needed for the packet were not on-chip
927 * when the packet arrived.
929 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
931 /* Bad Format: BDs were not formatted correctly. */
932 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
934 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST \
935 RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT
936 /* This indicates that there was an error in the IP header checksum. */
937 #define RX_PKT_CMPL_ERRORS_IP_CS_ERROR UINT32_C(0x10)
939 * This indicates that there was an error in the TCP, UDP or ICMP
942 #define RX_PKT_CMPL_ERRORS_L4_CS_ERROR UINT32_C(0x20)
944 * This indicates that there was an error in the tunnel IP header
947 #define RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR UINT32_C(0x40)
948 /* This indicates that there was an error in the tunnel UDP checksum. */
949 #define RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR UINT32_C(0x80)
951 * This indicates that there was a CRC error on either an FCoE or RoCE
952 * packet. The itype indicates the packet type.
954 #define RX_PKT_CMPL_ERRORS_CRC_ERROR UINT32_C(0x100)
956 * This indicates that there was an error in the tunnel portion of the
957 * packet when this field is non-zero.
959 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_MASK UINT32_C(0xe00)
960 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT 9
962 * No additional error occurred on the tunnel portion of the
963 * packet of the packet does not have a tunnel.
965 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 9)
967 * Indicates that IP header version does not match expectation
968 * from L2 Ethertype for IPv4 and IPv6 in the tunnel header.
970 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
973 * Indicates that header length is out of range in the tunnel
974 * header. Valid for IPv4.
976 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
979 * Indicates that the physical packet is shorter than that
980 * claimed by the PPPoE header length for a tunnel PPPoE packet.
982 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR \
985 * Indicates that physical packet is shorter than that claimed
986 * by the tunnel l3 header length. Valid for IPv4, or IPv6
987 * tunnel packet packets.
989 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
992 * Indicates that the physical packet is shorter than that
993 * claimed by the tunnel UDP header length for a tunnel UDP
994 * packet that is not fragmented.
996 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
999 * indicates that the IPv4 TTL or IPv6 hop limit check have
1000 * failed (e.g. TTL = 0) in the tunnel header. Valid for IPv4,
1003 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
1004 (UINT32_C(0x6) << 9)
1005 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_LAST \
1006 RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
1008 * This indicates that there was an error in the inner portion of the
1009 * packet when this field is non-zero.
1011 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_MASK UINT32_C(0xf000)
1012 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT 12
1014 * No additional error occurred on the tunnel portion of the
1015 * packet of the packet does not have a tunnel.
1017 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 12)
1019 * Indicates that IP header version does not match expectation
1020 * from L2 Ethertype for IPv4 and IPv6 or that option other than
1021 * VFT was parsed on FCoE packet.
1023 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION \
1024 (UINT32_C(0x1) << 12)
1026 * indicates that header length is out of range. Valid for IPv4
1029 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
1030 (UINT32_C(0x2) << 12)
1032 * indicates that the IPv4 TTL or IPv6 hop limit check have
1033 * failed (e.g. TTL = 0). Valid for IPv4, and IPv6
1035 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (UINT32_C(0x3) << 12)
1037 * Indicates that physical packet is shorter than that claimed
1038 * by the l3 header length. Valid for IPv4, IPv6 packet or RoCE
1041 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
1042 (UINT32_C(0x4) << 12)
1044 * Indicates that the physical packet is shorter than that
1045 * claimed by the UDP header length for a UDP packet that is not
1048 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
1049 (UINT32_C(0x5) << 12)
1051 * Indicates that TCP header length > IP payload. Valid for TCP
1054 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
1055 (UINT32_C(0x6) << 12)
1056 /* Indicates that TCP header length < 5. Valid for TCP. */
1057 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
1058 (UINT32_C(0x7) << 12)
1060 * Indicates that TCP option headers result in a TCP header size
1061 * that does not match data offset in TCP header. Valid for TCP.
1063 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
1064 (UINT32_C(0x8) << 12)
1065 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_LAST \
1066 RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
1067 #define RX_PKT_CMPL_ERRORS_MASK UINT32_C(0xfffe)
1068 #define RX_PKT_CMPL_ERRORS_SFT 1
1072 * This field identifies the CFA action rule that was used for this
1078 * This value holds the reordering sequence number for the packet. If
1079 * the reordering sequence is not valid, then this value is zero. The
1080 * reordering domain for the packet is in the bottom 8 to 10b of the
1081 * rss_hash value. The bottom 20b of this value contain the ordering
1082 * domain value for the packet.
1084 #define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff)
1085 #define RX_PKT_CMPL_REORDER_SFT 0
1087 } __attribute__((packed));
1089 /* HWRM Forwarded Request (16 bytes) */
1090 struct hwrm_fwd_req_cmpl {
1091 /* Length of forwarded request in bytes. */
1093 * This field indicates the exact type of the completion. By convention,
1094 * the LSB identifies the length of the record in 16B units. Even values
1095 * indicate 16B records. Odd values indicate 32B records.
1097 #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f)
1098 #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0
1099 /* Forwarded HWRM Request */
1100 #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ (UINT32_C(0x22) << 0)
1101 /* Length of forwarded request in bytes. */
1102 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0)
1103 #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6
1104 uint16_t req_len_type;
1107 * Source ID of this request. Typically used in forwarding requests and
1108 * responses. 0x0 - 0xFFF8 - Used for function ids 0xFFF8 - 0xFFFE -
1109 * Reserved for internal processors 0xFFFF - HWRM
1115 /* Address of forwarded request. */
1117 * This value is written by the NIC such that it will be different for
1118 * each pass through the completion queue. The even passes will write 1.
1119 * The odd passes will write 0.
1121 #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1)
1122 /* Address of forwarded request. */
1123 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe)
1124 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
1125 uint64_t req_buf_addr_v;
1126 } __attribute__((packed));
1128 /* HWRM Asynchronous Event Completion Record (16 bytes) */
1129 struct hwrm_async_event_cmpl {
1131 * This field indicates the exact type of the completion. By convention,
1132 * the LSB identifies the length of the record in 16B units. Even values
1133 * indicate 16B records. Odd values indicate 32B records.
1135 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f)
1136 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0
1137 /* HWRM Asynchronous Event Information */
1138 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT \
1139 (UINT32_C(0x2e) << 0)
1142 /* Identifiers of events. */
1143 /* Link status changed */
1144 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE \
1145 (UINT32_C(0x0) << 0)
1146 /* Link MTU changed */
1147 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE \
1148 (UINT32_C(0x1) << 0)
1149 /* Link speed changed */
1150 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE \
1151 (UINT32_C(0x2) << 0)
1152 /* DCB Configuration changed */
1153 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE \
1154 (UINT32_C(0x3) << 0)
1155 /* Port connection not allowed */
1156 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED \
1157 (UINT32_C(0x4) << 0)
1158 /* Link speed configuration was not allowed */
1159 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
1160 (UINT32_C(0x5) << 0)
1161 /* Function driver unloaded */
1162 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \
1163 (UINT32_C(0x10) << 0)
1164 /* Function driver loaded */
1165 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD \
1166 (UINT32_C(0x11) << 0)
1167 /* PF driver unloaded */
1168 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD \
1169 (UINT32_C(0x20) << 0)
1170 /* PF driver loaded */
1171 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD \
1172 (UINT32_C(0x21) << 0)
1173 /* VF Function Level Reset (FLR) */
1174 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR (UINT32_C(0x30) << 0)
1175 /* VF MAC Address Change */
1176 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE \
1177 (UINT32_C(0x31) << 0)
1178 /* PF-VF communication channel status change. */
1179 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
1180 (UINT32_C(0x32) << 0)
1182 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \
1183 (UINT32_C(0xff) << 0)
1186 /* Event specific data */
1187 uint32_t event_data2;
1191 * This value is written by the NIC such that it will be different for
1192 * each pass through the completion queue. The even passes will write 1.
1193 * The odd passes will write 0.
1195 #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1)
1197 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK UINT32_C(0xfe)
1198 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1
1201 /* 8-lsb timestamp from POR (100-msec resolution) */
1202 uint8_t timestamp_lo;
1204 /* 16-lsb timestamp from POR (100-msec resolution) */
1205 uint16_t timestamp_hi;
1207 /* Event specific data */
1208 uint32_t event_data1;
1209 } __attribute__((packed));
1212 * Note: The Hardware Resource Manager (HWRM) manages various hardware resources
1213 * inside the chip. The HWRM is implemented in firmware, and runs on embedded
1214 * processors inside the chip. This firmware is vital part of the chip's
1215 * hardware. The chip can not be used by driver without it.
1218 /* Input (16 bytes) */
1221 * This value indicates what type of request this is. The format for the
1222 * rest of the command is determined by this field.
1227 * This value indicates the what completion ring the request will be
1228 * optionally completed on. If the value is -1, then no CR completion
1229 * will be generated. Any other value must be a valid CR ring_id value
1230 * for this function.
1234 /* This value indicates the command sequence number. */
1238 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
1239 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
1244 * This is the host address where the response will be written when the
1245 * request is complete. This area must be 16B aligned and must be
1246 * cleared to zero before the request is made.
1249 } __attribute__((packed));
1251 /* Output (8 bytes) */
1254 * Pass/Fail or error type Note: receiver to verify the in parameters,
1255 * and fail the call with an error when appropriate
1257 uint16_t error_code;
1259 /* This field returns the type of original request. */
1262 /* This field provides original sequence number of the command. */
1266 * This field is the length of the response in bytes. The last byte of
1267 * the response is a valid flag that will read as '1' when the command
1268 * has been completely written to memory.
1271 } __attribute__((packed));
1273 /* hwrm_cfa_l2_filter_alloc */
1275 * A filter is used to identify traffic that contains a matching set of
1276 * parameters like unicast or broadcast MAC address or a VLAN tag amongst
1277 * other things which then allows the ASIC to direct the incoming traffic
1278 * to an appropriate VNIC or Rx ring.
1281 /* Input (96 bytes) */
1282 struct hwrm_cfa_l2_filter_alloc_input {
1284 * This value indicates what type of request this is. The format for the
1285 * rest of the command is determined by this field.
1290 * This value indicates the what completion ring the request will be
1291 * optionally completed on. If the value is -1, then no CR completion
1292 * will be generated. Any other value must be a valid CR ring_id value
1293 * for this function.
1297 /* This value indicates the command sequence number. */
1301 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
1302 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
1307 * This is the host address where the response will be written when the
1308 * request is complete. This area must be 16B aligned and must be
1309 * cleared to zero before the request is made.
1314 * Enumeration denoting the RX, TX type of the resource. This
1315 * enumeration is used for resources that are similar for both TX and RX
1316 * paths of the chip.
1318 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \
1321 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \
1322 (UINT32_C(0x0) << 0)
1324 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \
1325 (UINT32_C(0x1) << 0)
1326 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \
1327 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX
1329 * Setting of this flag indicates the applicability to the loopback
1332 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
1335 * Setting of this flag indicates drop action. If this flag is not set,
1336 * then it should be considered accept action.
1338 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \
1341 * If this flag is set, all t_l2_* fields are invalid and they should
1342 * not be specified. If this flag is set, then l2_* fields refer to
1343 * fields of outermost L2 header.
1345 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \
1349 /* This bit must be '1' for the l2_addr field to be configured. */
1350 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
1352 /* This bit must be '1' for the l2_addr_mask field to be configured. */
1353 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \
1355 /* This bit must be '1' for the l2_ovlan field to be configured. */
1356 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \
1358 /* This bit must be '1' for the l2_ovlan_mask field to be configured. */
1359 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \
1361 /* This bit must be '1' for the l2_ivlan field to be configured. */
1362 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
1364 /* This bit must be '1' for the l2_ivlan_mask field to be configured. */
1365 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \
1367 /* This bit must be '1' for the t_l2_addr field to be configured. */
1368 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \
1371 * This bit must be '1' for the t_l2_addr_mask field to be configured.
1373 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \
1375 /* This bit must be '1' for the t_l2_ovlan field to be configured. */
1376 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \
1379 * This bit must be '1' for the t_l2_ovlan_mask field to be configured.
1381 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \
1383 /* This bit must be '1' for the t_l2_ivlan field to be configured. */
1384 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \
1387 * This bit must be '1' for the t_l2_ivlan_mask field to be configured.
1389 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \
1391 /* This bit must be '1' for the src_type field to be configured. */
1392 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \
1394 /* This bit must be '1' for the src_id field to be configured. */
1395 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \
1397 /* This bit must be '1' for the tunnel_type field to be configured. */
1398 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
1400 /* This bit must be '1' for the dst_id field to be configured. */
1401 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
1404 * This bit must be '1' for the mirror_vnic_id field to be configured.
1406 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
1411 * This value sets the match value for the L2 MAC address. Destination
1412 * MAC address for RX path. Source MAC address for TX path.
1420 * This value sets the mask value for the L2 address. A value of 0 will
1421 * mask the corresponding bit from compare.
1423 uint8_t l2_addr_mask[6];
1425 /* This value sets VLAN ID value for outer VLAN. */
1429 * This value sets the mask value for the ovlan id. A value of 0 will
1430 * mask the corresponding bit from compare.
1432 uint16_t l2_ovlan_mask;
1434 /* This value sets VLAN ID value for inner VLAN. */
1438 * This value sets the mask value for the ivlan id. A value of 0 will
1439 * mask the corresponding bit from compare.
1441 uint16_t l2_ivlan_mask;
1447 * This value sets the match value for the tunnel L2 MAC address.
1448 * Destination MAC address for RX path. Source MAC address for TX path.
1450 uint8_t t_l2_addr[6];
1456 * This value sets the mask value for the tunnel L2 address. A value of
1457 * 0 will mask the corresponding bit from compare.
1459 uint8_t t_l2_addr_mask[6];
1461 /* This value sets VLAN ID value for tunnel outer VLAN. */
1462 uint16_t t_l2_ovlan;
1465 * This value sets the mask value for the tunnel ovlan id. A value of 0
1466 * will mask the corresponding bit from compare.
1468 uint16_t t_l2_ovlan_mask;
1470 /* This value sets VLAN ID value for tunnel inner VLAN. */
1471 uint16_t t_l2_ivlan;
1474 * This value sets the mask value for the tunnel ivlan id. A value of 0
1475 * will mask the corresponding bit from compare.
1477 uint16_t t_l2_ivlan_mask;
1479 /* This value identifies the type of source of the packet. */
1481 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT \
1482 (UINT32_C(0x0) << 0)
1483 /* Physical function */
1484 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF \
1485 (UINT32_C(0x1) << 0)
1486 /* Virtual function */
1487 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF \
1488 (UINT32_C(0x2) << 0)
1489 /* Virtual NIC of a function */
1490 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC \
1491 (UINT32_C(0x3) << 0)
1492 /* Embedded processor for CFA management */
1493 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG \
1494 (UINT32_C(0x4) << 0)
1495 /* Embedded processor for OOB management */
1496 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE \
1497 (UINT32_C(0x5) << 0)
1498 /* Embedded processor for RoCE */
1499 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO \
1500 (UINT32_C(0x6) << 0)
1501 /* Embedded processor for network proxy functions */
1502 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG \
1503 (UINT32_C(0x7) << 0)
1508 * This value is the id of the source. For a network port, it represents
1509 * port_id. For a physical function, it represents fid. For a virtual
1510 * function, it represents vf_id. For a vnic, it represents vnic_id. For
1511 * embedded processors, this id is not valid. Notes: 1. The function ID
1512 * is implied if it src_id is not provided for a src_type that is either
1518 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
1519 (UINT32_C(0x0) << 0)
1520 /* Virtual eXtensible Local Area Network (VXLAN) */
1521 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
1522 (UINT32_C(0x1) << 0)
1524 * Network Virtualization Generic Routing Encapsulation (NVGRE)
1526 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
1527 (UINT32_C(0x2) << 0)
1529 * Generic Routing Encapsulation (GRE) inside Ethernet payload
1531 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
1532 (UINT32_C(0x3) << 0)
1534 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
1535 (UINT32_C(0x4) << 0)
1536 /* Generic Network Virtualization Encapsulation (Geneve) */
1537 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
1538 (UINT32_C(0x5) << 0)
1539 /* Multi-Protocol Lable Switching (MPLS) */
1540 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
1541 (UINT32_C(0x6) << 0)
1542 /* Stateless Transport Tunnel (STT) */
1543 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
1544 (UINT32_C(0x7) << 0)
1546 * Generic Routing Encapsulation (GRE) inside IP datagram
1549 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
1550 (UINT32_C(0x8) << 0)
1551 /* Any tunneled traffic */
1552 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
1553 (UINT32_C(0xff) << 0)
1554 uint8_t tunnel_type;
1559 * If set, this value shall represent the Logical VNIC ID of the
1560 * destination VNIC for the RX path and network port id of the
1561 * destination port for the TX path.
1565 /* Logical VNIC ID of the VNIC where traffic is mirrored. */
1566 uint16_t mirror_vnic_id;
1569 * This hint is provided to help in placing the filter in the filter
1573 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
1574 (UINT32_C(0x0) << 0)
1575 /* Above the given filter */
1576 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \
1577 (UINT32_C(0x1) << 0)
1578 /* Below the given filter */
1579 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \
1580 (UINT32_C(0x2) << 0)
1581 /* As high as possible */
1582 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \
1583 (UINT32_C(0x3) << 0)
1584 /* As low as possible */
1585 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \
1586 (UINT32_C(0x4) << 0)
1593 * This is the ID of the filter that goes along with the pri_hint. This
1594 * field is valid only for the following values. 1 - Above the given
1595 * filter 2 - Below the given filter
1597 uint64_t l2_filter_id_hint;
1598 } __attribute__((packed));
1600 /* Output (24 bytes) */
1601 struct hwrm_cfa_l2_filter_alloc_output {
1603 * Pass/Fail or error type Note: receiver to verify the in parameters,
1604 * and fail the call with an error when appropriate
1606 uint16_t error_code;
1608 /* This field returns the type of original request. */
1611 /* This field provides original sequence number of the command. */
1615 * This field is the length of the response in bytes. The last byte of
1616 * the response is a valid flag that will read as '1' when the command
1617 * has been completely written to memory.
1622 * This value identifies a set of CFA data structures used for an L2
1625 uint64_t l2_filter_id;
1628 * This is the ID of the flow associated with this filter. This value
1629 * shall be used to match and associate the flow identifier returned in
1630 * completion records. A value of 0xFFFFFFFF shall indicate no flow id.
1639 * This field is used in Output records to indicate that the output is
1640 * completely written to RAM. This field should be read as '1' to
1641 * indicate that the output has been completely written. When writing a
1642 * command completion or response to an internal processor, the order of
1643 * writes has to be such that this field is written last.
1646 } __attribute__((packed));
1648 /* hwrm_cfa_l2_filter_free */
1650 * Description: Free a L2 filter. The HWRM shall free all associated filter
1651 * resources with the L2 filter.
1654 /* Input (24 bytes) */
1655 struct hwrm_cfa_l2_filter_free_input {
1657 * This value indicates what type of request this is. The format for the
1658 * rest of the command is determined by this field.
1663 * This value indicates the what completion ring the request will be
1664 * optionally completed on. If the value is -1, then no CR completion
1665 * will be generated. Any other value must be a valid CR ring_id value
1666 * for this function.
1670 /* This value indicates the command sequence number. */
1674 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
1675 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
1680 * This is the host address where the response will be written when the
1681 * request is complete. This area must be 16B aligned and must be
1682 * cleared to zero before the request is made.
1687 * This value identifies a set of CFA data structures used for an L2
1690 uint64_t l2_filter_id;
1691 } __attribute__((packed));
1693 /* Output (16 bytes) */
1694 struct hwrm_cfa_l2_filter_free_output {
1696 * Pass/Fail or error type Note: receiver to verify the in parameters,
1697 * and fail the call with an error when appropriate
1699 uint16_t error_code;
1701 /* This field returns the type of original request. */
1704 /* This field provides original sequence number of the command. */
1708 * This field is the length of the response in bytes. The last byte of
1709 * the response is a valid flag that will read as '1' when the command
1710 * has been completely written to memory.
1720 * This field is used in Output records to indicate that the output is
1721 * completely written to RAM. This field should be read as '1' to
1722 * indicate that the output has been completely written. When writing a
1723 * command completion or response to an internal processor, the order of
1724 * writes has to be such that this field is written last.
1727 } __attribute__((packed));
1729 /* hwrm_exec_fwd_resp */
1731 * Description: This command is used to send an encapsulated request to the
1732 * HWRM. This command instructs the HWRM to execute the request and forward the
1733 * response of the encapsulated request to the location specified in the
1734 * original request that is encapsulated. The target id of this command shall be
1735 * set to 0xFFFF (HWRM). The response location in this command shall be used to
1736 * acknowledge the receipt of the encapsulated request and forwarding of the
1740 /* Input (128 bytes) */
1741 struct hwrm_exec_fwd_resp_input {
1743 * This value indicates what type of request this is. The format for the
1744 * rest of the command is determined by this field.
1749 * This value indicates the what completion ring the request will be
1750 * optionally completed on. If the value is -1, then no CR completion
1751 * will be generated. Any other value must be a valid CR ring_id value
1752 * for this function.
1756 /* This value indicates the command sequence number. */
1760 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
1761 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
1766 * This is the host address where the response will be written when the
1767 * request is complete. This area must be 16B aligned and must be
1768 * cleared to zero before the request is made.
1773 * This is an encapsulated request. This request should be executed by
1774 * the HWRM and the response should be provided in the response buffer
1775 * inside the encapsulated request.
1777 uint32_t encap_request[26];
1780 * This value indicates the target id of the response to the
1781 * encapsulated request. 0x0 - 0xFFF8 - Used for function ids 0xFFF8 -
1782 * 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
1784 uint16_t encap_resp_target_id;
1786 uint16_t unused_0[3];
1787 } __attribute__((packed));
1789 /* Output (16 bytes) */
1790 struct hwrm_exec_fwd_resp_output {
1792 * Pass/Fail or error type Note: receiver to verify the in parameters,
1793 * and fail the call with an error when appropriate
1795 uint16_t error_code;
1797 /* This field returns the type of original request. */
1800 /* This field provides original sequence number of the command. */
1804 * This field is the length of the response in bytes. The last byte of
1805 * the response is a valid flag that will read as '1' when the command
1806 * has been completely written to memory.
1816 * This field is used in Output records to indicate that the output is
1817 * completely written to RAM. This field should be read as '1' to
1818 * indicate that the output has been completely written. When writing a
1819 * command completion or response to an internal processor, the order of
1820 * writes has to be such that this field is written last.
1823 } __attribute__((packed));
1825 /* hwrm_func_qcaps */
1827 * Description: This command returns capabilities of a function. The input FID
1828 * value is used to indicate what function is being queried. This allows a
1829 * physical function driver to query virtual functions that are children of the
1830 * physical function. The output FID value is needed to configure Rings and
1831 * MSI-X vectors so their DMA operations appear correctly on the PCI bus.
1834 /* Input (24 bytes) */
1835 struct hwrm_func_qcaps_input {
1837 * This value indicates what type of request this is. The format for the
1838 * rest of the command is determined by this field.
1843 * This value indicates the what completion ring the request will be
1844 * optionally completed on. If the value is -1, then no CR completion
1845 * will be generated. Any other value must be a valid CR ring_id value
1846 * for this function.
1850 /* This value indicates the command sequence number. */
1854 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
1855 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
1860 * This is the host address where the response will be written when the
1861 * request is complete. This area must be 16B aligned and must be
1862 * cleared to zero before the request is made.
1867 * Function ID of the function that is being queried. 0xFF... (All Fs)
1868 * if the query is for the requesting function.
1872 uint16_t unused_0[3];
1873 } __attribute__((packed));
1875 /* Output (80 bytes) */
1876 struct hwrm_func_qcaps_output {
1878 * Pass/Fail or error type Note: receiver to verify the in parameters,
1879 * and fail the call with an error when appropriate
1881 uint16_t error_code;
1883 /* This field returns the type of original request. */
1886 /* This field provides original sequence number of the command. */
1890 * This field is the length of the response in bytes. The last byte of
1891 * the response is a valid flag that will read as '1' when the command
1892 * has been completely written to memory.
1897 * FID value. This value is used to identify operations on the PCI bus
1898 * as belonging to a particular PCI function.
1903 * Port ID of port that this function is associated with. Valid only for
1904 * the PF. 0xFF... (All Fs) if this function is not associated with any
1905 * port. 0xFF... (All Fs) if this function is called from a VF.
1909 /* If 1, then Push mode is supported on this function. */
1910 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED UINT32_C(0x1)
1912 * If 1, then the global MSI-X auto-masking is enabled for the device.
1914 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING \
1917 * If 1, then the Precision Time Protocol (PTP) processing is supported
1918 * on this function. The HWRM should enable PTP on only a single
1919 * Physical Function (PF) per port.
1921 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED UINT32_C(0x4)
1925 * This value is current MAC address configured for this function. A
1926 * value of 00-00-00-00-00-00 indicates no MAC address is currently
1929 uint8_t perm_mac_address[6];
1932 * The maximum number of RSS/COS contexts that can be allocated to the
1935 uint16_t max_rsscos_ctx;
1938 * The maximum number of completion rings that can be allocated to the
1941 uint16_t max_cmpl_rings;
1944 * The maximum number of transmit rings that can be allocated to the
1947 uint16_t max_tx_rings;
1950 * The maximum number of receive rings that can be allocated to the
1953 uint16_t max_rx_rings;
1956 * The maximum number of L2 contexts that can be allocated to the
1959 uint16_t max_l2_ctxs;
1961 /* The maximum number of VNICs that can be allocated to the function. */
1965 * The identifier for the first VF enabled on a PF. This is valid only
1966 * on the PF with SR-IOV enabled. 0xFF... (All Fs) if this command is
1967 * called on a PF with SR-IOV disabled or on a VF.
1969 uint16_t first_vf_id;
1972 * The maximum number of VFs that can be allocated to the function. This
1973 * is valid only on the PF with SR-IOV enabled. 0xFF... (All Fs) if this
1974 * command is called on a PF with SR-IOV disabled or on a VF.
1979 * The maximum number of statistic contexts that can be allocated to the
1982 uint16_t max_stat_ctx;
1985 * The maximum number of Encapsulation records that can be offloaded by
1988 uint32_t max_encap_records;
1991 * The maximum number of decapsulation records that can be offloaded by
1994 uint32_t max_decap_records;
1997 * The maximum number of Exact Match (EM) flows that can be offloaded by
1998 * this function on the TX side.
2000 uint32_t max_tx_em_flows;
2003 * The maximum number of Wildcard Match (WM) flows that can be offloaded
2004 * by this function on the TX side.
2006 uint32_t max_tx_wm_flows;
2009 * The maximum number of Exact Match (EM) flows that can be offloaded by
2010 * this function on the RX side.
2012 uint32_t max_rx_em_flows;
2015 * The maximum number of Wildcard Match (WM) flows that can be offloaded
2016 * by this function on the RX side.
2018 uint32_t max_rx_wm_flows;
2021 * The maximum number of multicast filters that can be supported by this
2022 * function on the RX side.
2024 uint32_t max_mcast_filters;
2027 * The maximum value of flow_id that can be supported in completion
2030 uint32_t max_flow_id;
2033 * The maximum number of HW ring groups that can be supported on this
2036 uint32_t max_hw_ring_grps;
2043 * This field is used in Output records to indicate that the output is
2044 * completely written to RAM. This field should be read as '1' to
2045 * indicate that the output has been completely written. When writing a
2046 * command completion or response to an internal processor, the order of
2047 * writes has to be such that this field is written last.
2050 } __attribute__((packed));
2052 /* hwrm_func_reset */
2054 * Description: This command resets a hardware function (PCIe function) and
2055 * frees any resources used by the function. This command shall be initiated by
2056 * the driver after an FLR has occurred to prepare the function for re-use. This
2057 * command may also be initiated by a driver prior to doing it's own
2058 * configuration. This command puts the function into the reset state. In the
2059 * reset state, global and port related features of the chip are not available.
2062 * Note: This command will reset a function that has already been disabled or
2063 * idled. The command returns all the resources owned by the function so a new
2064 * driver may allocate and configure resources normally.
2067 /* Input (24 bytes) */
2068 struct hwrm_func_reset_input {
2070 * This value indicates what type of request this is. The format for the
2071 * rest of the command is determined by this field.
2076 * This value indicates the what completion ring the request will be
2077 * optionally completed on. If the value is -1, then no CR completion
2078 * will be generated. Any other value must be a valid CR ring_id value
2079 * for this function.
2083 /* This value indicates the command sequence number. */
2087 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
2088 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
2093 * This is the host address where the response will be written when the
2094 * request is complete. This area must be 16B aligned and must be
2095 * cleared to zero before the request is made.
2099 /* This bit must be '1' for the vf_id_valid field to be configured. */
2100 #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID \
2105 * The ID of the VF that this PF is trying to reset. Only the parent PF
2106 * shall be allowed to reset a child VF. A parent PF driver shall use
2107 * this field only when a specific child VF is requested to be reset.
2111 /* This value indicates the level of a function reset. */
2113 * Reset the caller function and its children VFs (if any). If
2114 * no children functions exist, then reset the caller function
2117 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \
2118 (UINT32_C(0x0) << 0)
2119 /* Reset the caller function only */
2120 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \
2121 (UINT32_C(0x1) << 0)
2123 * Reset all children VFs of the caller function driver if the
2124 * caller is a PF driver. It is an error to specify this level
2125 * by a VF driver. It is an error to specify this level by a PF
2126 * driver with no children VFs.
2128 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \
2129 (UINT32_C(0x2) << 0)
2131 * Reset a specific VF of the caller function driver if the
2132 * caller is the parent PF driver. It is an error to specify
2133 * this level by a VF driver. It is an error to specify this
2134 * level by a PF driver that is not the parent of the VF that is
2135 * being requested to reset.
2137 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \
2138 (UINT32_C(0x3) << 0)
2139 uint8_t func_reset_level;
2142 } __attribute__((packed));
2144 /* Output (16 bytes) */
2145 struct hwrm_func_reset_output {
2147 * Pass/Fail or error type Note: receiver to verify the in parameters,
2148 * and fail the call with an error when appropriate
2150 uint16_t error_code;
2152 /* This field returns the type of original request. */
2155 /* This field provides original sequence number of the command. */
2159 * This field is the length of the response in bytes. The last byte of
2160 * the response is a valid flag that will read as '1' when the command
2161 * has been completely written to memory.
2171 * This field is used in Output records to indicate that the output is
2172 * completely written to RAM. This field should be read as '1' to
2173 * indicate that the output has been completely written. When writing a
2174 * command completion or response to an internal processor, the order of
2175 * writes has to be such that this field is written last.
2178 } __attribute__((packed));
2180 /* hwrm_port_phy_cfg */
2182 * Description: This command configures the PHY device for the port. It allows
2183 * setting of the most generic settings for the PHY. The HWRM shall complete
2184 * this command as soon as PHY settings are configured. They may not be applied
2185 * when the command response is provided. A VF driver shall not be allowed to
2186 * configure PHY using this command. In a network partition mode, a PF driver
2187 * shall not be allowed to configure PHY using this command.
2190 /* Input (56 bytes) */
2191 struct hwrm_port_phy_cfg_input {
2193 * This value indicates what type of request this is. The format for the
2194 * rest of the command is determined by this field.
2199 * This value indicates the what completion ring the request will be
2200 * optionally completed on. If the value is -1, then no CR completion
2201 * will be generated. Any other value must be a valid CR ring_id value
2202 * for this function.
2206 /* This value indicates the command sequence number. */
2210 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
2211 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
2216 * This is the host address where the response will be written when the
2217 * request is complete. This area must be 16B aligned and must be
2218 * cleared to zero before the request is made.
2223 * When this bit is set to '1', the PHY for the port shall be reset. #
2224 * If this bit is set to 1, then the HWRM shall reset the PHY after
2225 * applying PHY configuration changes specified in this command. # In
2226 * order to guarantee that PHY configuration changes specified in this
2227 * command take effect, the HWRM client should set this flag to 1. # If
2228 * this bit is not set to 1, then the HWRM may reset the PHY depending
2229 * on the current PHY configuration and settings specified in this
2232 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY UINT32_C(0x1)
2234 * When this bit is set to '1', the link shall be forced to be taken
2235 * down. # When this bit is set to '1", all other command input settings
2236 * related to the link speed shall be ignored. Once the link state is
2237 * forced down, it can be explicitly cleared from that state by setting
2238 * this flag to '0'. # If this flag is set to '0', then the link shall
2239 * be cleared from forced down state if the link is in forced down
2240 * state. There may be conditions (e.g. out-of-band or sideband
2241 * configuration changes for the link) outside the scope of the HWRM
2242 * implementation that may clear forced down link state.
2244 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DOWN UINT32_C(0x2)
2246 * When this bit is set to '1', the link shall be forced to the
2247 * force_link_speed value. When this bit is set to '1', the HWRM client
2248 * should not enable any of the auto negotiation related fields
2249 * represented by auto_XXX fields in this command. When this bit is set
2250 * to '1' and the HWRM client has enabled a auto_XXX field in this
2251 * command, then the HWRM shall ignore the enabled auto_XXX field. When
2252 * this bit is set to zero, the link shall be allowed to autoneg.
2254 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE UINT32_C(0x4)
2256 * When this bit is set to '1', the auto-negotiation process shall be
2257 * restarted on the link.
2259 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG UINT32_C(0x8)
2261 * When this bit is set to '1', Energy Efficient Ethernet (EEE) is
2262 * requested to be enabled on this link. If EEE is not supported on this
2263 * port, then this flag shall be ignored by the HWRM.
2265 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE UINT32_C(0x10)
2267 * When this bit is set to '1', Energy Efficient Ethernet (EEE) is
2268 * requested to be disabled on this link. If EEE is not supported on
2269 * this port, then this flag shall be ignored by the HWRM.
2271 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE UINT32_C(0x20)
2273 * When this bit is set to '1' and EEE is enabled on this link, then TX
2274 * LPI is requested to be enabled on the link. If EEE is not supported
2275 * on this port, then this flag shall be ignored by the HWRM. If EEE is
2276 * disabled on this port, then this flag shall be ignored by the HWRM.
2278 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI UINT32_C(0x40)
2281 /* This bit must be '1' for the auto_mode field to be configured. */
2282 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE UINT32_C(0x1)
2283 /* This bit must be '1' for the auto_duplex field to be configured. */
2284 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX UINT32_C(0x2)
2285 /* This bit must be '1' for the auto_pause field to be configured. */
2286 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE UINT32_C(0x4)
2288 * This bit must be '1' for the auto_link_speed field to be configured.
2290 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED UINT32_C(0x8)
2292 * This bit must be '1' for the auto_link_speed_mask field to be
2295 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK \
2297 /* This bit must be '1' for the wirespeed field to be configured. */
2298 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED UINT32_C(0x20)
2299 /* This bit must be '1' for the lpbk field to be configured. */
2300 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK UINT32_C(0x40)
2301 /* This bit must be '1' for the preemphasis field to be configured. */
2302 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS UINT32_C(0x80)
2303 /* This bit must be '1' for the force_pause field to be configured. */
2304 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE UINT32_C(0x100)
2306 * This bit must be '1' for the eee_link_speed_mask field to be
2309 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK \
2311 /* This bit must be '1' for the tx_lpi_timer field to be configured. */
2312 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER UINT32_C(0x400)
2315 /* Port ID of port that is to be configured. */
2319 * This is the speed that will be used if the force bit is '1'. If
2320 * unsupported speed is selected, an error will be generated.
2322 /* 100Mb link speed */
2323 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB \
2324 (UINT32_C(0x1) << 0)
2325 /* 1Gb link speed */
2326 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB \
2327 (UINT32_C(0xa) << 0)
2328 /* 2Gb link speed */
2329 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB \
2330 (UINT32_C(0x14) << 0)
2331 /* 2.5Gb link speed */
2332 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB \
2333 (UINT32_C(0x19) << 0)
2334 /* 10Gb link speed */
2335 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB \
2336 (UINT32_C(0x64) << 0)
2337 /* 20Mb link speed */
2338 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB \
2339 (UINT32_C(0xc8) << 0)
2340 /* 25Gb link speed */
2341 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB \
2342 (UINT32_C(0xfa) << 0)
2343 /* 40Gb link speed */
2344 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB \
2345 (UINT32_C(0x190) << 0)
2346 /* 50Gb link speed */
2347 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB \
2348 (UINT32_C(0x1f4) << 0)
2349 /* 100Gb link speed */
2350 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB \
2351 (UINT32_C(0x3e8) << 0)
2352 /* 10Mb link speed */
2353 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB \
2354 (UINT32_C(0xffff) << 0)
2355 uint16_t force_link_speed;
2358 * This value is used to identify what autoneg mode is used when the
2359 * link speed is not being forced.
2362 * Disable autoneg or autoneg disabled. No speeds are selected.
2364 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE (UINT32_C(0x0) << 0)
2365 /* Select all possible speeds for autoneg mode. */
2366 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS \
2367 (UINT32_C(0x1) << 0)
2369 * Select only the auto_link_speed speed for autoneg mode. This
2370 * mode has been DEPRECATED. An HWRM client should not use this
2373 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED \
2374 (UINT32_C(0x2) << 0)
2376 * Select the auto_link_speed or any speed below that speed for
2377 * autoneg. This mode has been DEPRECATED. An HWRM client should
2378 * not use this mode.
2380 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW \
2381 (UINT32_C(0x3) << 0)
2383 * Select the speeds based on the corresponding link speed mask
2384 * value that is provided.
2386 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK \
2387 (UINT32_C(0x4) << 0)
2391 * This is the duplex setting that will be used if the autoneg_mode is
2392 * "one_speed" or "one_or_below".
2394 /* Half Duplex will be requested. */
2395 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF \
2396 (UINT32_C(0x0) << 0)
2397 /* Full duplex will be requested. */
2398 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL \
2399 (UINT32_C(0x1) << 0)
2400 /* Both Half and Full dupex will be requested. */
2401 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH \
2402 (UINT32_C(0x2) << 0)
2403 uint8_t auto_duplex;
2406 * This value is used to configure the pause that will be used for
2407 * autonegotiation. Add text on the usage of auto_pause and force_pause.
2410 * When this bit is '1', Generation of tx pause messages has been
2411 * requested. Disabled otherwise.
2413 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX UINT32_C(0x1)
2415 * When this bit is '1', Reception of rx pause messages has been
2416 * requested. Disabled otherwise.
2418 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX UINT32_C(0x2)
2420 * When set to 1, the advertisement of pause is enabled. # When the
2421 * auto_mode is not set to none and this flag is set to 1, then the
2422 * auto_pause bits on this port are being advertised and autoneg pause
2423 * results are being interpreted. # When the auto_mode is not set to
2424 * none and this flag is set to 0, the pause is forced as indicated in
2425 * force_pause, and also advertised as auto_pause bits, but the autoneg
2426 * results are not interpreted since the pause configuration is being
2427 * forced. # When the auto_mode is set to none and this flag is set to
2428 * 1, auto_pause bits should be ignored and should be set to 0.
2430 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE UINT32_C(0x4)
2436 * This is the speed that will be used if the autoneg_mode is
2437 * "one_speed" or "one_or_below". If an unsupported speed is selected,
2438 * an error will be generated.
2440 /* 100Mb link speed */
2441 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB \
2442 (UINT32_C(0x1) << 0)
2443 /* 1Gb link speed */
2444 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB \
2445 (UINT32_C(0xa) << 0)
2446 /* 2Gb link speed */
2447 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB \
2448 (UINT32_C(0x14) << 0)
2449 /* 2.5Gb link speed */
2450 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB \
2451 (UINT32_C(0x19) << 0)
2452 /* 10Gb link speed */
2453 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB \
2454 (UINT32_C(0x64) << 0)
2455 /* 20Mb link speed */
2456 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB \
2457 (UINT32_C(0xc8) << 0)
2458 /* 25Gb link speed */
2459 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB \
2460 (UINT32_C(0xfa) << 0)
2461 /* 40Gb link speed */
2462 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB \
2463 (UINT32_C(0x190) << 0)
2464 /* 50Gb link speed */
2465 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB \
2466 (UINT32_C(0x1f4) << 0)
2467 /* 100Gb link speed */
2468 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB \
2469 (UINT32_C(0x3e8) << 0)
2470 /* 10Mb link speed */
2471 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB \
2472 (UINT32_C(0xffff) << 0)
2473 uint16_t auto_link_speed;
2476 * This is a mask of link speeds that will be used if autoneg_mode is
2477 * "mask". If unsupported speed is enabled an error will be generated.
2479 /* 100Mb link speed (Half-duplex) */
2480 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD \
2482 /* 100Mb link speed (Full-duplex) */
2483 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB \
2485 /* 1Gb link speed (Half-duplex) */
2486 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD \
2488 /* 1Gb link speed (Full-duplex) */
2489 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB \
2491 /* 2Gb link speed */
2492 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB \
2494 /* 2.5Gb link speed */
2495 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB \
2497 /* 10Gb link speed */
2498 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB \
2500 /* 20Gb link speed */
2501 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB \
2503 /* 25Gb link speed */
2504 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB \
2506 /* 40Gb link speed */
2507 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB \
2509 /* 50Gb link speed */
2510 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB \
2512 /* 100Gb link speed */
2513 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB \
2515 /* 10Mb link speed (Half-duplex) */
2516 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD \
2518 /* 10Mb link speed (Full-duplex) */
2519 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
2521 uint16_t auto_link_speed_mask;
2523 /* This value controls the wirespeed feature. */
2524 /* Wirespeed feature is disabled. */
2525 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF (UINT32_C(0x0) << 0)
2526 /* Wirespeed feature is enabled. */
2527 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON (UINT32_C(0x1) << 0)
2530 /* This value controls the loopback setting for the PHY. */
2531 /* No loopback is selected. Normal operation. */
2532 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE (UINT32_C(0x0) << 0)
2534 * The HW will be configured with local loopback such that host
2535 * data is sent back to the host without modification.
2537 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL (UINT32_C(0x1) << 0)
2539 * The HW will be configured with remote loopback such that port
2540 * logic will send packets back out the transmitter that are
2543 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE (UINT32_C(0x2) << 0)
2547 * This value is used to configure the pause that will be used for force
2551 * When this bit is '1', Generation of tx pause messages is supported.
2552 * Disabled otherwise.
2554 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)
2556 * When this bit is '1', Reception of rx pause messages is supported.
2557 * Disabled otherwise.
2559 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)
2560 uint8_t force_pause;
2565 * This value controls the pre-emphasis to be used for the link. Driver
2566 * should not set this value (use enable.preemphasis = 0) unless driver
2567 * is sure of setting. Normally HWRM FW will determine proper pre-
2570 uint32_t preemphasis;
2573 * Setting for link speed mask that is used to advertise speeds during
2574 * autonegotiation when EEE is enabled. This field is valid only when
2575 * EEE is enabled. The speeds specified in this field shall be a subset
2576 * of speeds specified in auto_link_speed_mask. If EEE is enabled,then
2577 * at least one speed shall be provided in this mask.
2580 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 UINT32_C(0x1)
2581 /* 100Mb link speed (Full-duplex) */
2582 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB UINT32_C(0x2)
2584 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 UINT32_C(0x4)
2585 /* 1Gb link speed (Full-duplex) */
2586 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB UINT32_C(0x8)
2588 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 \
2591 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 \
2593 /* 10Gb link speed */
2594 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \
2596 uint16_t eee_link_speed_mask;
2602 * Reuested setting of TX LPI timer in microseconds. This field is valid
2603 * only when EEE is enabled and TX LPI is enabled.
2605 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK \
2607 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0
2608 uint32_t tx_lpi_timer;
2611 } __attribute__((packed));
2613 /* Output (16 bytes) */
2614 struct hwrm_port_phy_cfg_output {
2616 * Pass/Fail or error type Note: receiver to verify the in parameters,
2617 * and fail the call with an error when appropriate
2619 uint16_t error_code;
2621 /* This field returns the type of original request. */
2624 /* This field provides original sequence number of the command. */
2628 * This field is the length of the response in bytes. The last byte of
2629 * the response is a valid flag that will read as '1' when the command
2630 * has been completely written to memory.
2640 * This field is used in Output records to indicate that the output is
2641 * completely written to RAM. This field should be read as '1' to
2642 * indicate that the output has been completely written. When writing a
2643 * command completion or response to an internal processor, the order of
2644 * writes has to be such that this field is written last.
2647 } __attribute__((packed));
2651 * Description: This function is called by a driver to determine the HWRM
2652 * interface version supported by the HWRM firmware, the version of HWRM
2653 * firmware implementation, the name of HWRM firmware, the versions of other
2654 * embedded firmwares, and the names of other embedded firmwares, etc. Any
2655 * interface or firmware version with major = 0, minor = 0, and update = 0 shall
2656 * be considered an invalid version.
2659 /* Input (24 bytes) */
2660 struct hwrm_ver_get_input {
2662 * This value indicates what type of request this is. The format for the
2663 * rest of the command is determined by this field.
2668 * This value indicates the what completion ring the request will be
2669 * optionally completed on. If the value is -1, then no CR completion
2670 * will be generated. Any other value must be a valid CR ring_id value
2671 * for this function.
2675 /* This value indicates the command sequence number. */
2679 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
2680 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
2685 * This is the host address where the response will be written when the
2686 * request is complete. This area must be 16B aligned and must be
2687 * cleared to zero before the request is made.
2692 * This field represents the major version of HWRM interface
2693 * specification supported by the driver HWRM implementation. The
2694 * interface major version is intended to change only when non backward
2695 * compatible changes are made to the HWRM interface specification.
2697 uint8_t hwrm_intf_maj;
2700 * This field represents the minor version of HWRM interface
2701 * specification supported by the driver HWRM implementation. A change
2702 * in interface minor version is used to reflect significant backward
2703 * compatible modification to HWRM interface specification. This can be
2704 * due to addition or removal of functionality. HWRM interface
2705 * specifications with the same major version but different minor
2706 * versions are compatible.
2708 uint8_t hwrm_intf_min;
2711 * This field represents the update version of HWRM interface
2712 * specification supported by the driver HWRM implementation. The
2713 * interface update version is used to reflect minor changes or bug
2714 * fixes to a released HWRM interface specification.
2716 uint8_t hwrm_intf_upd;
2718 uint8_t unused_0[5];
2719 } __attribute__((packed));
2721 /* Output (128 bytes) */
2722 struct hwrm_ver_get_output {
2724 * Pass/Fail or error type Note: receiver to verify the in parameters,
2725 * and fail the call with an error when appropriate
2727 uint16_t error_code;
2729 /* This field returns the type of original request. */
2732 /* This field provides original sequence number of the command. */
2736 * This field is the length of the response in bytes. The last byte of
2737 * the response is a valid flag that will read as '1' when the command
2738 * has been completely written to memory.
2743 * This field represents the major version of HWRM interface
2744 * specification supported by the HWRM implementation. The interface
2745 * major version is intended to change only when non backward compatible
2746 * changes are made to the HWRM interface specification. A HWRM
2747 * implementation that is compliant with this specification shall
2748 * provide value of 1 in this field.
2750 uint8_t hwrm_intf_maj;
2753 * This field represents the minor version of HWRM interface
2754 * specification supported by the HWRM implementation. A change in
2755 * interface minor version is used to reflect significant backward
2756 * compatible modification to HWRM interface specification. This can be
2757 * due to addition or removal of functionality. HWRM interface
2758 * specifications with the same major version but different minor
2759 * versions are compatible. A HWRM implementation that is compliant with
2760 * this specification shall provide value of 0 in this field.
2762 uint8_t hwrm_intf_min;
2765 * This field represents the update version of HWRM interface
2766 * specification supported by the HWRM implementation. The interface
2767 * update version is used to reflect minor changes or bug fixes to a
2768 * released HWRM interface specification. A HWRM implementation that is
2769 * compliant with this specification shall provide value of 1 in this
2772 uint8_t hwrm_intf_upd;
2774 uint8_t hwrm_intf_rsvd;
2777 * This field represents the major version of HWRM firmware. A change in
2778 * firmware major version represents a major firmware release.
2780 uint8_t hwrm_fw_maj;
2783 * This field represents the minor version of HWRM firmware. A change in
2784 * firmware minor version represents significant firmware functionality
2787 uint8_t hwrm_fw_min;
2790 * This field represents the build version of HWRM firmware. A change in
2791 * firmware build version represents bug fixes to a released firmware.
2793 uint8_t hwrm_fw_bld;
2796 * This field is a reserved field. This field can be used to represent
2797 * firmware branches or customer specific releases tied to a specific
2798 * (major,minor,update) version of the HWRM firmware.
2800 uint8_t hwrm_fw_rsvd;
2803 * This field represents the major version of mgmt firmware. A change in
2804 * major version represents a major release.
2806 uint8_t mgmt_fw_maj;
2809 * This field represents the minor version of mgmt firmware. A change in
2810 * minor version represents significant functionality changes.
2812 uint8_t mgmt_fw_min;
2815 * This field represents the build version of mgmt firmware. A change in
2816 * update version represents bug fixes.
2818 uint8_t mgmt_fw_bld;
2821 * This field is a reserved field. This field can be used to represent
2822 * firmware branches or customer specific releases tied to a specific
2823 * (major,minor,update) version
2825 uint8_t mgmt_fw_rsvd;
2828 * This field represents the major version of network control firmware.
2829 * A change in major version represents a major release.
2831 uint8_t netctrl_fw_maj;
2834 * This field represents the minor version of network control firmware.
2835 * A change in minor version represents significant functionality
2838 uint8_t netctrl_fw_min;
2841 * This field represents the build version of network control firmware.
2842 * A change in update version represents bug fixes.
2844 uint8_t netctrl_fw_bld;
2847 * This field is a reserved field. This field can be used to represent
2848 * firmware branches or customer specific releases tied to a specific
2849 * (major,minor,update) version
2851 uint8_t netctrl_fw_rsvd;
2854 * This field is reserved for future use. The responder should set it to
2855 * 0. The requester should ignore this field.
2860 * This field represents the major version of RoCE firmware. A change in
2861 * major version represents a major release.
2863 uint8_t roce_fw_maj;
2866 * This field represents the minor version of RoCE firmware. A change in
2867 * minor version represents significant functionality changes.
2869 uint8_t roce_fw_min;
2872 * This field represents the build version of RoCE firmware. A change in
2873 * update version represents bug fixes.
2875 uint8_t roce_fw_bld;
2878 * This field is a reserved field. This field can be used to represent
2879 * firmware branches or customer specific releases tied to a specific
2880 * (major,minor,update) version
2882 uint8_t roce_fw_rsvd;
2885 * This field represents the name of HWRM FW (ASCII chars without NULL
2888 char hwrm_fw_name[16];
2891 * This field represents the name of mgmt FW (ASCII chars without NULL
2894 char mgmt_fw_name[16];
2897 * This field represents the name of network control firmware (ASCII
2898 * chars without NULL at the end).
2900 char netctrl_fw_name[16];
2903 * This field is reserved for future use. The responder should set it to
2904 * 0. The requester should ignore this field.
2906 uint32_t reserved2[4];
2909 * This field represents the name of RoCE FW (ASCII chars without NULL
2912 char roce_fw_name[16];
2914 /* This field returns the chip number. */
2917 /* This field returns the revision of chip. */
2920 /* This field returns the chip metal number. */
2923 /* This field returns the bond id of the chip. */
2924 uint8_t chip_bond_id;
2927 * This value indicates the type of platform used for chip
2931 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC \
2932 (UINT32_C(0x0) << 0)
2933 /* FPGA platform of the chip. */
2934 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_FPGA \
2935 (UINT32_C(0x1) << 0)
2936 /* Palladium platform of the chip. */
2937 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM \
2938 (UINT32_C(0x2) << 0)
2939 uint8_t chip_platform_type;
2942 * This field returns the maximum value of request window that is
2943 * supported by the HWRM. The request window is mapped into device
2944 * address space using MMIO.
2946 uint16_t max_req_win_len;
2949 * This field returns the maximum value of response buffer in bytes. If
2950 * a request specifies the response buffer length that is greater than
2951 * this value, then the HWRM should fail it. The value of this field
2952 * shall be 4KB or more.
2954 uint16_t max_resp_len;
2957 * This field returns the default request timeout value in milliseconds.
2959 uint16_t def_req_timeout;
2966 * This field is used in Output records to indicate that the output is
2967 * completely written to RAM. This field should be read as '1' to
2968 * indicate that the output has been completely written. When writing a
2969 * command completion or response to an internal processor, the order of
2970 * writes has to be such that this field is written last.
2973 } __attribute__((packed));
2975 /* hwrm_queue_qportcfg */
2977 * Description: This function is called by a driver to query queue configuration
2978 * of a port. # The HWRM shall at least advertise one queue with lossy service
2979 * profile. # The driver shall use this command to query queue ids before
2980 * configuring or using any queues. # If a service profile is not set for a
2981 * queue, then the driver shall not use that queue without configuring a service
2982 * profile for it. # If the driver is not allowed to configure service profiles,
2983 * then the driver shall only use queues for which service profiles are pre-
2987 /* Input (24 bytes) */
2988 struct hwrm_queue_qportcfg_input {
2990 * This value indicates what type of request this is. The format for the
2991 * rest of the command is determined by this field.
2996 * This value indicates the what completion ring the request will be
2997 * optionally completed on. If the value is -1, then no CR completion
2998 * will be generated. Any other value must be a valid CR ring_id value
2999 * for this function.
3003 /* This value indicates the command sequence number. */
3007 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
3008 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
3013 * This is the host address where the response will be written when the
3014 * request is complete. This area must be 16B aligned and must be
3015 * cleared to zero before the request is made.
3020 * Enumeration denoting the RX, TX type of the resource. This
3021 * enumeration is used for resources that are similar for both TX and RX
3022 * paths of the chip.
3024 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH \
3027 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX \
3028 (UINT32_C(0x0) << 0)
3030 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX \
3031 (UINT32_C(0x1) << 0)
3032 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \
3033 HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX
3037 * Port ID of port for which the queue configuration is being queried.
3038 * This field is only required when sent by IPC.
3043 } __attribute__((packed));
3045 /* hwrm_stat_ctx_clr_stats */
3046 /* Description: This command clears statistics of a context. */
3048 /* Input (24 bytes) */
3049 struct hwrm_stat_ctx_clr_stats_input {
3051 * This value indicates what type of request this is. The format for the
3052 * rest of the command is determined by this field.
3057 * This value indicates the what completion ring the request will be
3058 * optionally completed on. If the value is -1, then no CR completion
3059 * will be generated. Any other value must be a valid CR ring_id value
3060 * for this function.
3064 /* This value indicates the command sequence number. */
3068 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
3069 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
3074 * This is the host address where the response will be written when the
3075 * request is complete. This area must be 16B aligned and must be
3076 * cleared to zero before the request is made.
3080 /* ID of the statistics context that is being queried. */
3081 uint32_t stat_ctx_id;
3084 } __attribute__((packed));
3086 /* Output (16 bytes) */
3087 struct hwrm_stat_ctx_clr_stats_output {
3089 * Pass/Fail or error type Note: receiver to verify the in parameters,
3090 * and fail the call with an error when appropriate
3092 uint16_t error_code;
3094 /* This field returns the type of original request. */
3097 /* This field provides original sequence number of the command. */
3101 * This field is the length of the response in bytes. The last byte of
3102 * the response is a valid flag that will read as '1' when the command
3103 * has been completely written to memory.
3113 * This field is used in Output records to indicate that the output is
3114 * completely written to RAM. This field should be read as '1' to
3115 * indicate that the output has been completely written. When writing a
3116 * command completion or response to an internal processor, the order of
3117 * writes has to be such that this field is written last.
3120 } __attribute__((packed));
3122 /* hwrm_vnic_rss_cfg */
3123 /* Description: This function is used to enable RSS configuration. */
3125 /* Input (48 bytes) */
3126 struct hwrm_vnic_rss_cfg_input {
3128 * This value indicates what type of request this is. The format for the
3129 * rest of the command is determined by this field.
3134 * This value indicates the what completion ring the request will be
3135 * optionally completed on. If the value is -1, then no CR completion
3136 * will be generated. Any other value must be a valid CR ring_id value
3137 * for this function.
3141 /* This value indicates the command sequence number. */
3145 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
3146 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
3151 * This is the host address where the response will be written when the
3152 * request is complete. This area must be 16B aligned and must be
3153 * cleared to zero before the request is made.
3158 * When this bit is '1', the RSS hash shall be computed over source and
3159 * destination IPv4 addresses of IPv4 packets.
3161 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
3163 * When this bit is '1', the RSS hash shall be computed over
3164 * source/destination IPv4 addresses and source/destination ports of
3167 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
3169 * When this bit is '1', the RSS hash shall be computed over
3170 * source/destination IPv4 addresses and source/destination ports of
3173 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
3175 * When this bit is '1', the RSS hash shall be computed over source and
3176 * destination IPv4 addresses of IPv6 packets.
3178 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
3180 * When this bit is '1', the RSS hash shall be computed over
3181 * source/destination IPv6 addresses and source/destination ports of
3184 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
3186 * When this bit is '1', the RSS hash shall be computed over
3187 * source/destination IPv6 addresses and source/destination ports of
3190 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
3195 /* This is the address for rss ring group table */
3196 uint64_t ring_grp_tbl_addr;
3198 /* This is the address for rss hash key table */
3199 uint64_t hash_key_tbl_addr;
3201 /* Index to the rss indirection table. */
3202 uint16_t rss_ctx_idx;
3204 uint16_t unused_1[3];
3205 } __attribute__((packed));
3207 /* Output (16 bytes) */
3208 struct hwrm_vnic_rss_cfg_output {
3210 * Pass/Fail or error type Note: receiver to verify the in parameters,
3211 * and fail the call with an error when appropriate
3213 uint16_t error_code;
3215 /* This field returns the type of original request. */
3218 /* This field provides original sequence number of the command. */
3222 * This field is the length of the response in bytes. The last byte of
3223 * the response is a valid flag that will read as '1' when the command
3224 * has been completely written to memory.
3234 * This field is used in Output records to indicate that the output is
3235 * completely written to RAM. This field should be read as '1' to
3236 * indicate that the output has been completely written. When writing a
3237 * command completion or response to an internal processor, the order of
3238 * writes has to be such that this field is written last.
3241 } __attribute__((packed));
3243 /* Output (32 bytes) */
3244 struct hwrm_queue_qportcfg_output {
3246 * Pass/Fail or error type Note: receiver to verify the in parameters,
3247 * and fail the call with an error when appropriate
3249 uint16_t error_code;
3251 /* This field returns the type of original request. */
3254 /* This field provides original sequence number of the command. */
3258 * This field is the length of the response in bytes. The last byte of
3259 * the response is a valid flag that will read as '1' when the command
3260 * has been completely written to memory.
3264 /* The maximum number of queues that can be configured. */
3265 uint8_t max_configurable_queues;
3267 /* The maximum number of lossless queues that can be configured. */
3268 uint8_t max_configurable_lossless_queues;
3271 * 0 - Not allowed. Non-zero - Allowed. If this value is non-zero, then
3272 * the HWRM shall allow the host SW driver to configure queues using
3275 uint8_t queue_cfg_allowed;
3278 * 0 - Not allowed. Non-zero - Allowed If this value is non-zero, then
3279 * the HWRM shall allow the host SW driver to configure queue buffers
3280 * using hwrm_queue_buffers_cfg.
3282 uint8_t queue_buffers_cfg_allowed;
3285 * 0 - Not allowed. Non-zero - Allowed If this value is non-zero, then
3286 * the HWRM shall allow the host SW driver to configure PFC using
3287 * hwrm_queue_pfcenable_cfg.
3289 uint8_t queue_pfcenable_cfg_allowed;
3292 * 0 - Not allowed. Non-zero - Allowed If this value is non-zero, then
3293 * the HWRM shall allow the host SW driver to configure Priority to CoS
3294 * mapping using hwrm_queue_pri2cos_cfg.
3296 uint8_t queue_pri2cos_cfg_allowed;
3299 * 0 - Not allowed. Non-zero - Allowed If this value is non-zero, then
3300 * the HWRM shall allow the host SW driver to configure CoS Bandwidth
3301 * configuration using hwrm_queue_cos2bw_cfg.
3303 uint8_t queue_cos2bw_cfg_allowed;
3305 /* ID of CoS Queue 0. FF - Invalid id */
3308 /* This value is applicable to CoS queues only. */
3309 /* Lossy (best-effort) */
3310 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \
3311 (UINT32_C(0x0) << 0)
3313 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \
3314 (UINT32_C(0x1) << 0)
3316 * Set to 0xFF... (All Fs) if there is no service profile
3319 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN \
3320 (UINT32_C(0xff) << 0)
3321 uint8_t queue_id0_service_profile;
3323 /* ID of CoS Queue 1. FF - Invalid id */
3325 /* This value is applicable to CoS queues only. */
3326 /* Lossy (best-effort) */
3327 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \
3328 (UINT32_C(0x0) << 0)
3330 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \
3331 (UINT32_C(0x1) << 0)
3333 * Set to 0xFF... (All Fs) if there is no service profile
3336 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN \
3337 (UINT32_C(0xff) << 0)
3338 uint8_t queue_id1_service_profile;
3340 /* ID of CoS Queue 2. FF - Invalid id */
3342 /* This value is applicable to CoS queues only. */
3343 /* Lossy (best-effort) */
3344 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \
3345 (UINT32_C(0x0) << 0)
3347 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \
3348 (UINT32_C(0x1) << 0)
3350 * Set to 0xFF... (All Fs) if there is no service profile
3353 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN \
3354 (UINT32_C(0xff) << 0)
3355 uint8_t queue_id2_service_profile;
3357 /* ID of CoS Queue 3. FF - Invalid id */
3360 /* This value is applicable to CoS queues only. */
3361 /* Lossy (best-effort) */
3362 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \
3363 (UINT32_C(0x0) << 0)
3365 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \
3366 (UINT32_C(0x1) << 0)
3368 * Set to 0xFF... (All Fs) if there is no service profile
3371 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN \
3372 (UINT32_C(0xff) << 0)
3373 uint8_t queue_id3_service_profile;
3375 /* ID of CoS Queue 4. FF - Invalid id */
3377 /* This value is applicable to CoS queues only. */
3378 /* Lossy (best-effort) */
3379 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \
3380 (UINT32_C(0x0) << 0)
3382 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \
3383 (UINT32_C(0x1) << 0)
3385 * Set to 0xFF... (All Fs) if there is no service profile
3388 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN \
3389 (UINT32_C(0xff) << 0)
3390 uint8_t queue_id4_service_profile;
3392 /* ID of CoS Queue 5. FF - Invalid id */
3395 /* This value is applicable to CoS queues only. */
3396 /* Lossy (best-effort) */
3397 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \
3398 (UINT32_C(0x0) << 0)
3400 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \
3401 (UINT32_C(0x1) << 0)
3403 * Set to 0xFF... (All Fs) if there is no service profile
3406 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN \
3407 (UINT32_C(0xff) << 0)
3408 uint8_t queue_id5_service_profile;
3410 /* ID of CoS Queue 6. FF - Invalid id */
3411 uint8_t queue_id6_service_profile;
3412 /* This value is applicable to CoS queues only. */
3413 /* Lossy (best-effort) */
3414 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \
3415 (UINT32_C(0x0) << 0)
3417 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \
3418 (UINT32_C(0x1) << 0)
3420 * Set to 0xFF... (All Fs) if there is no service profile
3423 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN \
3424 (UINT32_C(0xff) << 0)
3427 /* ID of CoS Queue 7. FF - Invalid id */
3430 /* This value is applicable to CoS queues only. */
3431 /* Lossy (best-effort) */
3432 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \
3433 (UINT32_C(0x0) << 0)
3435 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \
3436 (UINT32_C(0x1) << 0)
3438 * Set to 0xFF... (All Fs) if there is no service profile
3441 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \
3442 (UINT32_C(0xff) << 0)
3443 uint8_t queue_id7_service_profile;
3446 * This field is used in Output records to indicate that the output is
3447 * completely written to RAM. This field should be read as '1' to
3448 * indicate that the output has been completely written. When writing a
3449 * command completion or response to an internal processor, the order of
3450 * writes has to be such that this field is written last.
3453 } __attribute__((packed));
3455 /* hwrm_func_drv_rgtr */
3457 * Description: This command is used by the function driver to register its
3458 * information with the HWRM. A function driver shall implement this command. A
3459 * function driver shall use this command during the driver initialization right
3460 * after the HWRM version discovery and default ring resources allocation.
3463 /* Input (80 bytes) */
3464 struct hwrm_func_drv_rgtr_input {
3466 * This value indicates what type of request this is. The format for the
3467 * rest of the command is determined by this field.
3472 * This value indicates the what completion ring the request will be
3473 * optionally completed on. If the value is -1, then no CR completion
3474 * will be generated. Any other value must be a valid CR ring_id value
3475 * for this function.
3479 /* This value indicates the command sequence number. */
3483 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
3484 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
3489 * This is the host address where the response will be written when the
3490 * request is complete. This area must be 16B aligned and must be
3491 * cleared to zero before the request is made.
3496 * When this bit is '1', the function driver is requesting all requests
3497 * from its children VF drivers to be forwarded to itself. This flag can
3498 * only be set by the PF driver. If a VF driver sets this flag, it
3499 * should be ignored by the HWRM.
3501 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE UINT32_C(0x1)
3503 * When this bit is '1', the function is requesting none of the requests
3504 * from its children VF drivers to be forwarded to itself. This flag can
3505 * only be set by the PF driver. If a VF driver sets this flag, it
3506 * should be ignored by the HWRM.
3508 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE UINT32_C(0x2)
3511 /* This bit must be '1' for the os_type field to be configured. */
3512 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE UINT32_C(0x1)
3513 /* This bit must be '1' for the ver field to be configured. */
3514 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER UINT32_C(0x2)
3515 /* This bit must be '1' for the timestamp field to be configured. */
3516 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP UINT32_C(0x4)
3517 /* This bit must be '1' for the vf_req_fwd field to be configured. */
3518 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD UINT32_C(0x8)
3520 * This bit must be '1' for the async_event_fwd field to be configured.
3522 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD \
3526 /* This value indicates the type of OS. */
3528 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN \
3529 (UINT32_C(0x0) << 0)
3530 /* Other OS not listed below. */
3531 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER \
3532 (UINT32_C(0x1) << 0)
3534 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS \
3535 (UINT32_C(0xe) << 0)
3537 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS \
3538 (UINT32_C(0x12) << 0)
3540 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS \
3541 (UINT32_C(0x1d) << 0)
3543 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX \
3544 (UINT32_C(0x24) << 0)
3546 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD \
3547 (UINT32_C(0x2a) << 0)
3548 /* VMware ESXi OS. */
3549 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI \
3550 (UINT32_C(0x68) << 0)
3551 /* Microsoft Windows 8 64-bit OS. */
3552 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 \
3553 (UINT32_C(0x73) << 0)
3554 /* Microsoft Windows Server 2012 R2 OS. */
3555 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 \
3556 (UINT32_C(0x74) << 0)
3559 /* This is the major version of the driver. */
3562 /* This is the minor version of the driver. */
3565 /* This is the update version of the driver. */
3572 * This is a 32-bit timestamp provided by the driver for keep alive. The
3573 * timestamp is in multiples of 1ms.
3580 * This is a 256-bit bit mask provided by the PF driver for letting the
3581 * HWRM know what commands issued by the VF driver to the HWRM should be
3582 * forwarded to the PF driver. Nth bit refers to the Nth req_type.
3583 * Setting Nth bit to 1 indicates that requests from the VF driver with
3584 * req_type equal to N shall be forwarded to the parent PF driver. This
3585 * field is not valid for the VF driver.
3587 uint32_t vf_req_fwd[8];
3590 * This is a 256-bit bit mask provided by the function driver (PF or VF
3591 * driver) to indicate the list of asynchronous event completions to be
3592 * forwarded. Nth bit refers to the Nth event_id. Setting Nth bit to 1
3593 * by the function driver shall result in the HWRM forwarding
3594 * asynchronous event completion with event_id equal to N. If all bits
3595 * are set to 0 (value of 0), then the HWRM shall not forward any
3596 * asynchronous event completion to this function driver.
3598 uint32_t async_event_fwd[8];
3599 } __attribute__((packed));
3601 /* Output (16 bytes) */
3603 struct hwrm_func_drv_rgtr_output {
3605 * Pass/Fail or error type Note: receiver to verify the in parameters,
3606 * and fail the call with an error when appropriate
3608 uint16_t error_code;
3610 /* This field returns the type of original request. */
3613 /* This field provides original sequence number of the command. */
3617 * This field is the length of the response in bytes. The last byte of
3618 * the response is a valid flag that will read as '1' when the command
3619 * has been completely written to memory.
3629 * This field is used in Output records to indicate that the output is
3630 * completely written to RAM. This field should be read as '1' to
3631 * indicate that the output has been completely written. When writing a
3632 * command completion or response to an internal processor, the order of
3633 * writes has to be such that this field is written last.
3636 } __attribute__((packed));
3638 /* hwrm_func_drv_unrgtr */
3640 * Description: This command is used by the function driver to un register with
3641 * the HWRM. A function driver shall implement this command. A function driver
3642 * shall use this command during the driver unloading.
3644 /* Input (24 bytes) */
3646 struct hwrm_func_drv_unrgtr_input {
3648 * This value indicates what type of request this is. The format for the
3649 * rest of the command is determined by this field.
3654 * This value indicates the what completion ring the request will be
3655 * optionally completed on. If the value is -1, then no CR completion
3656 * will be generated. Any other value must be a valid CR ring_id value
3657 * for this function.
3661 /* This value indicates the command sequence number. */
3665 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
3666 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
3671 * This is the host address where the response will be written when the
3672 * request is complete. This area must be 16B aligned and must be
3673 * cleared to zero before the request is made.
3678 * When this bit is '1', the function driver is notifying the HWRM to
3679 * prepare for the shutdown.
3681 #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN \
3686 } __attribute__((packed));
3688 /* Output (16 bytes) */
3689 struct hwrm_func_drv_unrgtr_output {
3691 * Pass/Fail or error type Note: receiver to verify the in parameters,
3692 * and fail the call with an error when appropriate
3694 uint16_t error_code;
3696 /* This field returns the type of original request. */
3699 /* This field provides original sequence number of the command. */
3703 * This field is the length of the response in bytes. The last byte of
3704 * the response is a valid flag that will read as '1' when the command
3705 * has been completely written to memory.
3715 * This field is used in Output records to indicate that the output is
3716 * completely written to RAM. This field should be read as '1' to
3717 * indicate that the output has been completely written. When writing a
3718 * command completion or response to an internal processor, the order of
3719 * writes has to be such that this field is written last.
3722 } __attribute__((packed));