drivers/net/bnxt/tf_core/tf_device_p4.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2019-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <rte_common.h>
   7
   8 #include "cfa_resource_types.h"
   9 #include "tf_device.h"
  10 #include "tf_identifier.h"
  11 #include "tf_tbl.h"
  12 #include "tf_tcam.h"
  13 #ifdef TF_TCAM_SHARED
  14 #include "tf_tcam_shared.h"
  15 #endif /* TF_TCAM_SHARED */
  16 #include "tf_em.h"
  17 #include "tf_if_tbl.h"
  18 #include "tfp.h"
  19 #include "tf_msg_common.h"
  20
  21 #define TF_DEV_P4_PARIF_MAX 16
  22 #define TF_DEV_P4_PF_MASK 0xfUL
  23
  24 const char *tf_resource_str_p4[CFA_RESOURCE_TYPE_P4_LAST + 1] = {
  25         [CFA_RESOURCE_TYPE_P4_MCG] = "mc_group",
  26         [CFA_RESOURCE_TYPE_P4_ENCAP_8B] = "encap_8 ",
  27         [CFA_RESOURCE_TYPE_P4_ENCAP_16B] = "encap_16",
  28         [CFA_RESOURCE_TYPE_P4_ENCAP_64B] = "encap_64",
  29         [CFA_RESOURCE_TYPE_P4_SP_MAC] = "sp_mac  ",
  30         [CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4] = "sp_macv4",
  31         [CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6] = "sp_macv6",
  32         [CFA_RESOURCE_TYPE_P4_COUNTER_64B] = "ctr_64b ",
  33         [CFA_RESOURCE_TYPE_P4_NAT_PORT] = "nat_port",
  34         [CFA_RESOURCE_TYPE_P4_NAT_IPV4] = "nat_ipv4",
  35         [CFA_RESOURCE_TYPE_P4_METER] = "meter   ",
  36         [CFA_RESOURCE_TYPE_P4_FLOW_STATE] = "flow_st ",
  37         [CFA_RESOURCE_TYPE_P4_FULL_ACTION] = "full_act",
  38         [CFA_RESOURCE_TYPE_P4_FORMAT_0_ACTION] = "fmt0_act",
  39         [CFA_RESOURCE_TYPE_P4_EXT_FORMAT_0_ACTION] = "ext0_act",
  40         [CFA_RESOURCE_TYPE_P4_FORMAT_1_ACTION] = "fmt1_act",
  41         [CFA_RESOURCE_TYPE_P4_FORMAT_2_ACTION] = "fmt2_act",
  42         [CFA_RESOURCE_TYPE_P4_FORMAT_3_ACTION] = "fmt3_act",
  43         [CFA_RESOURCE_TYPE_P4_FORMAT_4_ACTION] = "fmt4_act",
  44         [CFA_RESOURCE_TYPE_P4_FORMAT_5_ACTION] = "fmt5_act",
  45         [CFA_RESOURCE_TYPE_P4_FORMAT_6_ACTION] = "fmt6_act",
  46         [CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH] = "l2ctx_hi",
  47         [CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW] = "l2ctx_lo",
  48         [CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH] = "l2ctr_hi",
  49         [CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW] = "l2ctr_lo",
  50         [CFA_RESOURCE_TYPE_P4_PROF_FUNC] = "prf_func",
  51         [CFA_RESOURCE_TYPE_P4_PROF_TCAM] = "prf_tcam",
  52         [CFA_RESOURCE_TYPE_P4_EM_PROF_ID] = "em_prof ",
  53         [CFA_RESOURCE_TYPE_P4_EM_REC] = "em_rec  ",
  54         [CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID] = "wc_prof ",
  55         [CFA_RESOURCE_TYPE_P4_WC_TCAM] = "wc_tcam ",
  56         [CFA_RESOURCE_TYPE_P4_METER_PROF] = "mtr_prof",
  57         [CFA_RESOURCE_TYPE_P4_MIRROR] = "mirror  ",
  58         [CFA_RESOURCE_TYPE_P4_SP_TCAM] = "sp_tcam ",
  59         [CFA_RESOURCE_TYPE_P4_TBL_SCOPE] = "tb_scope",
  60 };
  61
  62 struct tf_rm_element_cfg tf_tbl_p4[TF_DIR_MAX][TF_TBL_TYPE_MAX] = {
  63         [TF_DIR_RX][TF_TBL_TYPE_FULL_ACT_RECORD] = {
  64                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION,
  65                 0, 0
  66         },
  67         [TF_DIR_RX][TF_TBL_TYPE_MCAST_GROUPS] = {
  68                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG,
  69                 0, 0
  70         },
  71         [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_8B] = {
  72                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B,
  73                 0, 0
  74         },
  75         [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_16B] = {
  76                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B,
  77                 0, 0
  78         },
  79         [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_64B] = {
  80                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B,
  81                 0, 0
  82         },
  83         [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC] = {
  84                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC,
  85                 0, 0
  86         },
  87         [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {
  88                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4,
  89                 0, 0
  90         },
  91         [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {
  92                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6,
  93                 0, 0
  94         },
  95         [TF_DIR_RX][TF_TBL_TYPE_ACT_STATS_64] = {
  96                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B,
  97                 0, 0
  98         },
  99         [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_IPV4] = {
 100                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4,
 101                 0, 0
 102         },
 103         [TF_DIR_RX][TF_TBL_TYPE_METER_PROF] = {
 104                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF,
 105                 0, 0
 106         },
 107         [TF_DIR_RX][TF_TBL_TYPE_METER_INST] = {
 108                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER,
 109                 0, 0
 110         },
 111         [TF_DIR_RX][TF_TBL_TYPE_MIRROR_CONFIG] = {
 112                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR,
 113                 0, 0
 114         },
 115         [TF_DIR_TX][TF_TBL_TYPE_FULL_ACT_RECORD] = {
 116                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION,
 117                 0, 0
 118         },
 119         [TF_DIR_TX][TF_TBL_TYPE_MCAST_GROUPS] = {
 120                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG,
 121                 0, 0
 122         },
 123         [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_8B] = {
 124                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B,
 125                 0, 0
 126         },
 127         [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_16B] = {
 128                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B,
 129                 0, 0
 130         },
 131         [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_64B] = {
 132                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B,
 133                 0, 0
 134         },
 135         [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC] = {
 136                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC,
 137                 0, 0
 138         },
 139         [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {
 140                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4,
 141                 0, 0
 142         },
 143         [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {
 144                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6,
 145                 0, 0
 146         },
 147         [TF_DIR_TX][TF_TBL_TYPE_ACT_STATS_64] = {
 148                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B,
 149                 0, 0
 150         },
 151         [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_IPV4] = {
 152                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4,
 153                 0, 0
 154         },
 155         [TF_DIR_TX][TF_TBL_TYPE_METER_PROF] = {
 156                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF,
 157                 0, 0
 158         },
 159         [TF_DIR_TX][TF_TBL_TYPE_METER_INST] = {
 160                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER,
 161                 0, 0
 162         },
 163         [TF_DIR_TX][TF_TBL_TYPE_MIRROR_CONFIG] = {
 164                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR,
 165                 0, 0
 166         },
 167 };
 168
 169 /**
 170  * Device specific function that retrieves the MAX number of HCAPI
 171  * types the device supports.
 172  *
 173  * [in] tfp
 174  *   Pointer to TF handle
 175  *
 176  * [out] max_types
 177  *   Pointer to the MAX number of CFA resource types supported
 178  *
 179  * Returns
 180  *   - (0) if successful.
 181  *   - (-EINVAL) on failure.
 182  */
 183 static int
 184 tf_dev_p4_get_max_types(struct tf *tfp,
 185                         uint16_t *max_types)
 186 {
 187         if (max_types == NULL || tfp == NULL)
 188                 return -EINVAL;
 189
 190         *max_types = CFA_RESOURCE_TYPE_P4_LAST + 1;
 191
 192         return 0;
 193 }
 194 /**
 195  * Device specific function that retrieves a human readable
 196  * string to identify a CFA resource type.
 197  *
 198  * [in] tfp
 199  *   Pointer to TF handle
 200  *
 201  * [in] resource_id
 202  *   HCAPI CFA resource id
 203  *
 204  * [out] resource_str
 205  *   Resource string
 206  *
 207  * Returns
 208  *   - (0) if successful.
 209  *   - (-EINVAL) on failure.
 210  */
 211 static int
 212 tf_dev_p4_get_resource_str(struct tf *tfp __rte_unused,
 213                            uint16_t resource_id,
 214                            const char **resource_str)
 215 {
 216         if (resource_str == NULL)
 217                 return -EINVAL;
 218
 219         if (resource_id > CFA_RESOURCE_TYPE_P4_LAST)
 220                 return -EINVAL;
 221
 222         *resource_str = tf_resource_str_p4[resource_id];
 223
 224         return 0;
 225 }
 226
 227 /**
 228  * Device specific function that set the WC TCAM slices the
 229  * device supports.
 230  *
 231  * [in] tfp
 232  *   Pointer to TF handle
 233  *
 234  * [in] num_slices_per_row
 235  *   The WC TCAM row slice configuration
 236  *
 237  * Returns
 238  *   - (0) if successful.
 239  *   - (-EINVAL) on failure.
 240  */
 241 static int
 242 tf_dev_p4_set_tcam_slice_info(struct tf *tfp __rte_unused,
 243                               enum tf_wc_num_slice num_slices_per_row)
 244 {
 245         switch (num_slices_per_row) {
 246         case TF_WC_TCAM_1_SLICE_PER_ROW:
 247         case TF_WC_TCAM_2_SLICE_PER_ROW:
 248         case TF_WC_TCAM_4_SLICE_PER_ROW:
 249                 g_wc_num_slices_per_row = num_slices_per_row;
 250         break;
 251         default:
 252                 return -EINVAL;
 253         }
 254
 255         return 0;
 256 }
 257
 258 /**
 259  * Device specific function that retrieves the TCAM slices the
 260  * device supports.
 261  *
 262  * [in] tfp
 263  *   Pointer to TF handle
 264  *
 265  * [in] type
 266  *   TF TCAM type
 267  *
 268  * [in] key_sz
 269  *   The key size
 270  *
 271  * [out] num_slices_per_row
 272  *   Pointer to the WC TCAM row slice configuration
 273  *
 274  * Returns
 275  *   - (0) if successful.
 276  *   - (-EINVAL) on failure.
 277  */
 278 static int
 279 tf_dev_p4_get_tcam_slice_info(struct tf *tfp __rte_unused,
 280                               enum tf_tcam_tbl_type type,
 281                               uint16_t key_sz,
 282                               uint16_t *num_slices_per_row)
 283 {
 284 /* Single slice support */
 285 #define CFA_P4_WC_TCAM_SLICE_SIZE     12
 286
 287         if (type == TF_TCAM_TBL_TYPE_WC_TCAM) {
 288                 *num_slices_per_row = g_wc_num_slices_per_row;
 289                 if (key_sz > *num_slices_per_row * CFA_P4_WC_TCAM_SLICE_SIZE)
 290                         return -ENOTSUP;
 291         } else { /* for other type of tcam */
 292                 *num_slices_per_row = 1;
 293         }
 294
 295         return 0;
 296 }
 297
 298 static int
 299 tf_dev_p4_map_parif(struct tf *tfp __rte_unused,
 300                     uint16_t parif_bitmask,
 301                     uint16_t pf,
 302                     uint8_t *data,
 303                     uint8_t *mask,
 304                     uint16_t sz_in_bytes)
 305 {
 306         uint32_t parif_pf[2] = { 0 };
 307         uint32_t parif_pf_mask[2] = { 0 };
 308         uint32_t parif;
 309         uint32_t shift;
 310
 311         if (sz_in_bytes != sizeof(uint64_t))
 312                 return -ENOTSUP;
 313
 314         for (parif = 0; parif < TF_DEV_P4_PARIF_MAX; parif++) {
 315                 if (parif_bitmask & (1UL << parif)) {
 316                         if (parif < 8) {
 317                                 shift = 4 * parif;
 318                                 parif_pf_mask[0] |= TF_DEV_P4_PF_MASK << shift;
 319                                 parif_pf[0] |= pf << shift;
 320                         } else {
 321                                 shift = 4 * (parif - 8);
 322                                 parif_pf_mask[1] |= TF_DEV_P4_PF_MASK << shift;
 323                                 parif_pf[1] |= pf << shift;
 324                         }
 325                 }
 326         }
 327         tfp_memcpy(data, parif_pf, sz_in_bytes);
 328         tfp_memcpy(mask, parif_pf_mask, sz_in_bytes);
 329
 330         return 0;
 331 }
 332
 333 /**
 334  * Device specific function that retrieves the increment
 335  * required for certain table types in a shared session
 336  *
 337  * [in] tfp
 338  *  tf handle
 339  *
 340  * [in/out] parms
 341  *   pointer to parms structure
 342  *
 343  * Returns
 344  *   - (0) if successful.
 345  *   - (-EINVAL) on failure.
 346  */
 347 static int tf_dev_p4_get_shared_tbl_increment(struct tf *tfp __rte_unused,
 348                                 struct tf_get_shared_tbl_increment_parms *parms)
 349 {
 350         parms->increment_cnt = 1;
 351         return 0;
 352 }
 353 static int tf_dev_p4_get_mailbox(void)
 354 {
 355         return TF_KONG_MB;
 356 }
 357
 358 static int tf_dev_p4_word_align(uint16_t size)
 359 {
 360         return ((((size) + 31) >> 5) * 4);
 361 }
 362
 363 /**
 364  * Indicates whether the index table type is SRAM managed
 365  *
 366  * [in] tfp
 367  *   Pointer to TF handle
 368  *
 369  * [in] type
 370  *   Truflow index table type, e.g. TF_TYPE_FULL_ACT_RECORD
 371  *
 372  * Returns
 373  *   - (0) if the table is not managed by the SRAM manager
 374  *   - (1) if the table is managed by the SRAM manager
 375  */
 376 static bool tf_dev_p4_is_sram_managed(struct tf *tfp __rte_unused,
 377                                       enum tf_tbl_type type __rte_unused)
 378 {
 379         return false;
 380 }
 381
 382 /**
 383  * Device specific function that maps the hcapi resource types
 384  * to Truflow type.
 385  *
 386  * [in] hcapi_caps
 387  *   CFA resource type bitmap
 388  *
 389  * [out] ident_caps
 390  *   Pointer to identifier type bitmap
 391  *
 392  * [out] tcam_caps
 393  *   Pointer to tcam type bitmap
 394  *
 395  * [out] tbl_caps
 396  *   Pointer to table type bitmap
 397  *
 398  * [out] em_caps
 399  *   Pointer to em type bitmap
 400  *
 401  * Returns
 402  *   - (0) if successful.
 403  *   - (-EINVAL) on failure.
 404  */
 405 static int tf_dev_p4_map_hcapi_caps(uint64_t hcapi_caps,
 406                                     uint32_t *ident_caps,
 407                                     uint32_t *tcam_caps,
 408                                     uint32_t *tbl_caps,
 409                                     uint32_t *em_caps)
 410 {
 411         uint32_t i;
 412
 413         *ident_caps = 0;
 414         *tcam_caps = 0;
 415         *tbl_caps = 0;
 416         *em_caps = 0;
 417
 418         for (i = 0; i <= CFA_RESOURCE_TYPE_P4_LAST; i++) {
 419                 if (hcapi_caps & 1ULL << i) {
 420                         switch (tf_hcapi_res_map_p4[i].module_type) {
 421                         case TF_MODULE_TYPE_IDENTIFIER:
 422                                 *ident_caps |= tf_hcapi_res_map_p4[i].type_caps;
 423                                 break;
 424                         case TF_MODULE_TYPE_TABLE:
 425                                 *tbl_caps |= tf_hcapi_res_map_p4[i].type_caps;
 426                                 break;
 427                         case TF_MODULE_TYPE_TCAM:
 428                                 *tcam_caps |= tf_hcapi_res_map_p4[i].type_caps;
 429                                 break;
 430                         case TF_MODULE_TYPE_EM:
 431                                 *em_caps |= tf_hcapi_res_map_p4[i].type_caps;
 432                                 break;
 433                         default:
 434                                 return -EINVAL;
 435                         }
 436                 }
 437         }
 438
 439         return 0;
 440 }
 441
 442 /**
 443  * Truflow P4 device specific functions
 444  */
 445 const struct tf_dev_ops tf_dev_ops_p4_init = {
 446         .tf_dev_get_max_types = tf_dev_p4_get_max_types,
 447         .tf_dev_get_resource_str = tf_dev_p4_get_resource_str,
 448         .tf_dev_set_tcam_slice_info = tf_dev_p4_set_tcam_slice_info,
 449         .tf_dev_get_tcam_slice_info = tf_dev_p4_get_tcam_slice_info,
 450         .tf_dev_alloc_ident = NULL,
 451         .tf_dev_free_ident = NULL,
 452         .tf_dev_search_ident = NULL,
 453         .tf_dev_get_ident_resc_info = NULL,
 454         .tf_dev_get_tbl_info = NULL,
 455         .tf_dev_is_sram_managed = tf_dev_p4_is_sram_managed,
 456         .tf_dev_alloc_ext_tbl = NULL,
 457         .tf_dev_alloc_tbl = NULL,
 458         .tf_dev_alloc_sram_tbl = NULL,
 459         .tf_dev_free_ext_tbl = NULL,
 460         .tf_dev_free_tbl = NULL,
 461         .tf_dev_free_sram_tbl = NULL,
 462         .tf_dev_set_tbl = NULL,
 463         .tf_dev_set_ext_tbl = NULL,
 464         .tf_dev_set_sram_tbl = NULL,
 465         .tf_dev_get_tbl = NULL,
 466         .tf_dev_get_sram_tbl = NULL,
 467         .tf_dev_get_bulk_tbl = NULL,
 468         .tf_dev_get_bulk_sram_tbl = NULL,
 469         .tf_dev_get_shared_tbl_increment = tf_dev_p4_get_shared_tbl_increment,
 470         .tf_dev_get_tbl_resc_info = NULL,
 471         .tf_dev_alloc_tcam = NULL,
 472         .tf_dev_free_tcam = NULL,
 473         .tf_dev_alloc_search_tcam = NULL,
 474         .tf_dev_set_tcam = NULL,
 475         .tf_dev_get_tcam = NULL,
 476         .tf_dev_get_tcam_resc_info = NULL,
 477         .tf_dev_insert_int_em_entry = NULL,
 478         .tf_dev_delete_int_em_entry = NULL,
 479         .tf_dev_insert_ext_em_entry = NULL,
 480         .tf_dev_delete_ext_em_entry = NULL,
 481         .tf_dev_get_em_resc_info = NULL,
 482         .tf_dev_alloc_tbl_scope = NULL,
 483         .tf_dev_map_tbl_scope = NULL,
 484         .tf_dev_map_parif = NULL,
 485         .tf_dev_free_tbl_scope = NULL,
 486         .tf_dev_set_if_tbl = NULL,
 487         .tf_dev_get_if_tbl = NULL,
 488         .tf_dev_set_global_cfg = NULL,
 489         .tf_dev_get_global_cfg = NULL,
 490         .tf_dev_get_mailbox = tf_dev_p4_get_mailbox,
 491         .tf_dev_word_align = NULL,
 492         .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps,
 493         .tf_dev_get_sram_resources = NULL,
 494         .tf_dev_set_sram_policy = NULL,
 495         .tf_dev_get_sram_policy = NULL,
 496 };
 497
 498 /**
 499  * Truflow P4 device specific functions
 500  */
 501 const struct tf_dev_ops tf_dev_ops_p4 = {
 502         .tf_dev_get_max_types = tf_dev_p4_get_max_types,
 503         .tf_dev_get_resource_str = tf_dev_p4_get_resource_str,
 504         .tf_dev_set_tcam_slice_info = tf_dev_p4_set_tcam_slice_info,
 505         .tf_dev_get_tcam_slice_info = tf_dev_p4_get_tcam_slice_info,
 506         .tf_dev_alloc_ident = tf_ident_alloc,
 507         .tf_dev_free_ident = tf_ident_free,
 508         .tf_dev_search_ident = tf_ident_search,
 509         .tf_dev_get_ident_resc_info = tf_ident_get_resc_info,
 510         .tf_dev_get_tbl_info = NULL,
 511         .tf_dev_is_sram_managed = tf_dev_p4_is_sram_managed,
 512         .tf_dev_alloc_tbl = tf_tbl_alloc,
 513         .tf_dev_alloc_ext_tbl = tf_tbl_ext_alloc,
 514         .tf_dev_alloc_sram_tbl = tf_tbl_alloc,
 515         .tf_dev_free_tbl = tf_tbl_free,
 516         .tf_dev_free_ext_tbl = tf_tbl_ext_free,
 517         .tf_dev_free_sram_tbl = tf_tbl_free,
 518         .tf_dev_set_tbl = tf_tbl_set,
 519         .tf_dev_set_ext_tbl = tf_tbl_ext_common_set,
 520         .tf_dev_set_sram_tbl = NULL,
 521         .tf_dev_get_tbl = tf_tbl_get,
 522         .tf_dev_get_sram_tbl = NULL,
 523         .tf_dev_get_bulk_tbl = tf_tbl_bulk_get,
 524         .tf_dev_get_bulk_sram_tbl = NULL,
 525         .tf_dev_get_shared_tbl_increment = tf_dev_p4_get_shared_tbl_increment,
 526         .tf_dev_get_tbl_resc_info = tf_tbl_get_resc_info,
 527 #ifdef TF_TCAM_SHARED
 528         .tf_dev_alloc_tcam = tf_tcam_shared_alloc,
 529         .tf_dev_free_tcam = tf_tcam_shared_free,
 530         .tf_dev_set_tcam = tf_tcam_shared_set,
 531         .tf_dev_get_tcam = tf_tcam_shared_get,
 532         .tf_dev_move_tcam = tf_tcam_shared_move_p4,
 533         .tf_dev_clear_tcam = tf_tcam_shared_clear,
 534 #else /* !TF_TCAM_SHARED */
 535         .tf_dev_alloc_tcam = tf_tcam_alloc,
 536         .tf_dev_free_tcam = tf_tcam_free,
 537         .tf_dev_set_tcam = tf_tcam_set,
 538         .tf_dev_get_tcam = tf_tcam_get,
 539 #endif
 540         .tf_dev_alloc_search_tcam = tf_tcam_alloc_search,
 541         .tf_dev_get_tcam_resc_info = tf_tcam_get_resc_info,
 542         .tf_dev_insert_int_em_entry = tf_em_insert_int_entry,
 543         .tf_dev_delete_int_em_entry = tf_em_delete_int_entry,
 544         .tf_dev_insert_ext_em_entry = tf_em_insert_ext_entry,
 545         .tf_dev_delete_ext_em_entry = tf_em_delete_ext_entry,
 546         .tf_dev_get_em_resc_info = tf_em_get_resc_info,
 547         .tf_dev_alloc_tbl_scope = tf_em_ext_common_alloc,
 548         .tf_dev_map_tbl_scope = tf_em_ext_map_tbl_scope,
 549         .tf_dev_map_parif = tf_dev_p4_map_parif,
 550         .tf_dev_free_tbl_scope = tf_em_ext_common_free,
 551         .tf_dev_set_if_tbl = tf_if_tbl_set,
 552         .tf_dev_get_if_tbl = tf_if_tbl_get,
 553         .tf_dev_set_global_cfg = tf_global_cfg_set,
 554         .tf_dev_get_global_cfg = tf_global_cfg_get,
 555         .tf_dev_get_mailbox = tf_dev_p4_get_mailbox,
 556         .tf_dev_word_align = tf_dev_p4_word_align,
 557         .tf_dev_cfa_key_hash = hcapi_cfa_p4_key_hash,
 558         .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps,
 559         .tf_dev_get_sram_resources = NULL,
 560         .tf_dev_set_sram_policy = NULL,
 561         .tf_dev_get_sram_policy = NULL,
 562 };