drivers/net/bnxt/tf_core/tf_device_p4.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2019-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <rte_common.h>
   7
   8 #include "cfa_resource_types.h"
   9 #include "tf_device.h"
  10 #include "tf_identifier.h"
  11 #include "tf_tbl.h"
  12 #include "tf_tcam.h"
  13 #ifdef TF_TCAM_SHARED
  14 #include "tf_tcam_shared.h"
  15 #endif /* TF_TCAM_SHARED */
  16 #include "tf_em.h"
  17 #include "tf_if_tbl.h"
  18 #include "tfp.h"
  19 #include "tf_msg_common.h"
  20
  21 #define TF_DEV_P4_PARIF_MAX 16
  22 #define TF_DEV_P4_PF_MASK 0xfUL
  23
  24 const char *tf_resource_str_p4[CFA_RESOURCE_TYPE_P4_LAST + 1] = {
  25         [CFA_RESOURCE_TYPE_P4_MCG] = "mc_group",
  26         [CFA_RESOURCE_TYPE_P4_ENCAP_8B] = "encap_8 ",
  27         [CFA_RESOURCE_TYPE_P4_ENCAP_16B] = "encap_16",
  28         [CFA_RESOURCE_TYPE_P4_ENCAP_64B] = "encap_64",
  29         [CFA_RESOURCE_TYPE_P4_SP_MAC] = "sp_mac  ",
  30         [CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4] = "sp_macv4",
  31         [CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6] = "sp_macv6",
  32         [CFA_RESOURCE_TYPE_P4_COUNTER_64B] = "ctr_64b ",
  33         [CFA_RESOURCE_TYPE_P4_NAT_PORT] = "nat_port",
  34         [CFA_RESOURCE_TYPE_P4_NAT_IPV4] = "nat_ipv4",
  35         [CFA_RESOURCE_TYPE_P4_METER] = "meter   ",
  36         [CFA_RESOURCE_TYPE_P4_FLOW_STATE] = "flow_st ",
  37         [CFA_RESOURCE_TYPE_P4_FULL_ACTION] = "full_act",
  38         [CFA_RESOURCE_TYPE_P4_FORMAT_0_ACTION] = "fmt0_act",
  39         [CFA_RESOURCE_TYPE_P4_EXT_FORMAT_0_ACTION] = "ext0_act",
  40         [CFA_RESOURCE_TYPE_P4_FORMAT_1_ACTION] = "fmt1_act",
  41         [CFA_RESOURCE_TYPE_P4_FORMAT_2_ACTION] = "fmt2_act",
  42         [CFA_RESOURCE_TYPE_P4_FORMAT_3_ACTION] = "fmt3_act",
  43         [CFA_RESOURCE_TYPE_P4_FORMAT_4_ACTION] = "fmt4_act",
  44         [CFA_RESOURCE_TYPE_P4_FORMAT_5_ACTION] = "fmt5_act",
  45         [CFA_RESOURCE_TYPE_P4_FORMAT_6_ACTION] = "fmt6_act",
  46         [CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH] = "l2ctx_hi",
  47         [CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW] = "l2ctx_lo",
  48         [CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH] = "l2ctr_hi",
  49         [CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW] = "l2ctr_lo",
  50         [CFA_RESOURCE_TYPE_P4_PROF_FUNC] = "prf_func",
  51         [CFA_RESOURCE_TYPE_P4_PROF_TCAM] = "prf_tcam",
  52         [CFA_RESOURCE_TYPE_P4_EM_PROF_ID] = "em_prof ",
  53         [CFA_RESOURCE_TYPE_P4_EM_REC] = "em_rec  ",
  54         [CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID] = "wc_prof ",
  55         [CFA_RESOURCE_TYPE_P4_WC_TCAM] = "wc_tcam ",
  56         [CFA_RESOURCE_TYPE_P4_METER_PROF] = "mtr_prof",
  57         [CFA_RESOURCE_TYPE_P4_MIRROR] = "mirror  ",
  58         [CFA_RESOURCE_TYPE_P4_SP_TCAM] = "sp_tcam ",
  59         [CFA_RESOURCE_TYPE_P4_TBL_SCOPE] = "tb_scope",
  60 };
  61
  62 struct tf_rm_element_cfg tf_tbl_p4[TF_DIR_MAX][TF_TBL_TYPE_MAX] = {
  63         [TF_DIR_RX][TF_TBL_TYPE_FULL_ACT_RECORD] = {
  64                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION,
  65                 0, 0
  66         },
  67         [TF_DIR_RX][TF_TBL_TYPE_MCAST_GROUPS] = {
  68                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG,
  69                 0, 0
  70         },
  71         [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_8B] = {
  72                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B,
  73                 0, 0
  74         },
  75         [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_16B] = {
  76                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B,
  77                 0, 0
  78         },
  79         [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_64B] = {
  80                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B,
  81                 0, 0
  82         },
  83         [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC] = {
  84                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC,
  85                 0, 0
  86         },
  87         [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {
  88                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4,
  89                 0, 0
  90         },
  91         [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {
  92                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6,
  93                 0, 0
  94         },
  95         [TF_DIR_RX][TF_TBL_TYPE_ACT_STATS_64] = {
  96                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B,
  97                 0, 0
  98         },
  99         [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_IPV4] = {
 100                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4,
 101                 0, 0
 102         },
 103         [TF_DIR_RX][TF_TBL_TYPE_METER_PROF] = {
 104                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF,
 105                 0, 0
 106         },
 107         [TF_DIR_RX][TF_TBL_TYPE_METER_INST] = {
 108                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER,
 109                 0, 0
 110         },
 111         [TF_DIR_RX][TF_TBL_TYPE_MIRROR_CONFIG] = {
 112                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR,
 113                 0, 0
 114         },
 115         [TF_DIR_TX][TF_TBL_TYPE_FULL_ACT_RECORD] = {
 116                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION,
 117                 0, 0
 118         },
 119         [TF_DIR_TX][TF_TBL_TYPE_MCAST_GROUPS] = {
 120                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG,
 121                 0, 0
 122         },
 123         [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_8B] = {
 124                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B,
 125                 0, 0
 126         },
 127         [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_16B] = {
 128                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B,
 129                 0, 0
 130         },
 131         [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_64B] = {
 132                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B,
 133                 0, 0
 134         },
 135         [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC] = {
 136                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC,
 137                 0, 0
 138         },
 139         [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {
 140                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4,
 141                 0, 0
 142         },
 143         [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {
 144                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6,
 145                 0, 0
 146         },
 147         [TF_DIR_TX][TF_TBL_TYPE_ACT_STATS_64] = {
 148                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B,
 149                 0, 0
 150         },
 151         [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_IPV4] = {
 152                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4,
 153                 0, 0
 154         },
 155         [TF_DIR_TX][TF_TBL_TYPE_METER_PROF] = {
 156                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF,
 157                 0, 0
 158         },
 159         [TF_DIR_TX][TF_TBL_TYPE_METER_INST] = {
 160                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER,
 161                 0, 0
 162         },
 163         [TF_DIR_TX][TF_TBL_TYPE_MIRROR_CONFIG] = {
 164                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR,
 165                 0, 0
 166         },
 167 };
 168
 169 /**
 170  * Device specific function that retrieves the MAX number of HCAPI
 171  * types the device supports.
 172  *
 173  * [in] tfp
 174  *   Pointer to TF handle
 175  *
 176  * [out] max_types
 177  *   Pointer to the MAX number of CFA resource types supported
 178  *
 179  * Returns
 180  *   - (0) if successful.
 181  *   - (-EINVAL) on failure.
 182  */
 183 static int
 184 tf_dev_p4_get_max_types(struct tf *tfp,
 185                         uint16_t *max_types)
 186 {
 187         if (max_types == NULL || tfp == NULL)
 188                 return -EINVAL;
 189
 190         *max_types = CFA_RESOURCE_TYPE_P4_LAST + 1;
 191
 192         return 0;
 193 }
 194 /**
 195  * Device specific function that retrieves a human readable
 196  * string to identify a CFA resource type.
 197  *
 198  * [in] tfp
 199  *   Pointer to TF handle
 200  *
 201  * [in] resource_id
 202  *   HCAPI CFA resource id
 203  *
 204  * [out] resource_str
 205  *   Resource string
 206  *
 207  * Returns
 208  *   - (0) if successful.
 209  *   - (-EINVAL) on failure.
 210  */
 211 static int
 212 tf_dev_p4_get_resource_str(struct tf *tfp __rte_unused,
 213                            uint16_t resource_id,
 214                            const char **resource_str)
 215 {
 216         if (resource_str == NULL)
 217                 return -EINVAL;
 218
 219         if (resource_id > CFA_RESOURCE_TYPE_P4_LAST)
 220                 return -EINVAL;
 221
 222         *resource_str = tf_resource_str_p4[resource_id];
 223
 224         return 0;
 225 }
 226
 227 /**
 228  * Device specific function that set the WC TCAM slices the
 229  * device supports.
 230  *
 231  * [in] tfp
 232  *   Pointer to TF handle
 233  *
 234  * [in] num_slices_per_row
 235  *   The WC TCAM row slice configuration
 236  *
 237  * Returns
 238  *   - (0) if successful.
 239  *   - (-EINVAL) on failure.
 240  */
 241 static int
 242 tf_dev_p4_set_tcam_slice_info(struct tf *tfp,
 243                               enum tf_wc_num_slice num_slices_per_row)
 244 {
 245         int rc;
 246         struct tf_session *tfs;
 247
 248         /* Retrieve the session information */
 249         rc = tf_session_get_session_internal(tfp, &tfs);
 250         if (rc)
 251                 return rc;
 252
 253         switch (num_slices_per_row) {
 254         case TF_WC_TCAM_1_SLICE_PER_ROW:
 255         case TF_WC_TCAM_2_SLICE_PER_ROW:
 256         case TF_WC_TCAM_4_SLICE_PER_ROW:
 257                 tfs->wc_num_slices_per_row = num_slices_per_row;
 258         break;
 259         default:
 260                 return -EINVAL;
 261         }
 262
 263         return 0;
 264 }
 265
 266 /**
 267  * Device specific function that retrieves the TCAM slices the
 268  * device supports.
 269  *
 270  * [in] tfp
 271  *   Pointer to TF handle
 272  *
 273  * [in] type
 274  *   TF TCAM type
 275  *
 276  * [in] key_sz
 277  *   The key size
 278  *
 279  * [out] num_slices_per_row
 280  *   Pointer to the WC TCAM row slice configuration
 281  *
 282  * Returns
 283  *   - (0) if successful.
 284  *   - (-EINVAL) on failure.
 285  */
 286 static int
 287 tf_dev_p4_get_tcam_slice_info(struct tf *tfp,
 288                               enum tf_tcam_tbl_type type,
 289                               uint16_t key_sz,
 290                               uint16_t *num_slices_per_row)
 291 {
 292         int rc;
 293         struct tf_session *tfs;
 294
 295         /* Retrieve the session information */
 296         rc = tf_session_get_session_internal(tfp, &tfs);
 297         if (rc)
 298                 return rc;
 299
 300 /* Single slice support */
 301 #define CFA_P4_WC_TCAM_SLICE_SIZE     12
 302
 303         if (type == TF_TCAM_TBL_TYPE_WC_TCAM) {
 304                 *num_slices_per_row = tfs->wc_num_slices_per_row;
 305                 if (key_sz > *num_slices_per_row * CFA_P4_WC_TCAM_SLICE_SIZE)
 306                         return -ENOTSUP;
 307         } else { /* for other type of tcam */
 308                 *num_slices_per_row = 1;
 309         }
 310
 311         return 0;
 312 }
 313
 314 static int
 315 tf_dev_p4_map_parif(struct tf *tfp __rte_unused,
 316                     uint16_t parif_bitmask,
 317                     uint16_t pf,
 318                     uint8_t *data,
 319                     uint8_t *mask,
 320                     uint16_t sz_in_bytes)
 321 {
 322         uint32_t parif_pf[2] = { 0 };
 323         uint32_t parif_pf_mask[2] = { 0 };
 324         uint32_t parif;
 325         uint32_t shift;
 326
 327         if (sz_in_bytes != sizeof(uint64_t))
 328                 return -ENOTSUP;
 329
 330         for (parif = 0; parif < TF_DEV_P4_PARIF_MAX; parif++) {
 331                 if (parif_bitmask & (1UL << parif)) {
 332                         if (parif < 8) {
 333                                 shift = 4 * parif;
 334                                 parif_pf_mask[0] |= TF_DEV_P4_PF_MASK << shift;
 335                                 parif_pf[0] |= pf << shift;
 336                         } else {
 337                                 shift = 4 * (parif - 8);
 338                                 parif_pf_mask[1] |= TF_DEV_P4_PF_MASK << shift;
 339                                 parif_pf[1] |= pf << shift;
 340                         }
 341                 }
 342         }
 343         tfp_memcpy(data, parif_pf, sz_in_bytes);
 344         tfp_memcpy(mask, parif_pf_mask, sz_in_bytes);
 345
 346         return 0;
 347 }
 348
 349 /**
 350  * Device specific function that retrieves the increment
 351  * required for certain table types in a shared session
 352  *
 353  * [in] tfp
 354  *  tf handle
 355  *
 356  * [in/out] parms
 357  *   pointer to parms structure
 358  *
 359  * Returns
 360  *   - (0) if successful.
 361  *   - (-EINVAL) on failure.
 362  */
 363 static int tf_dev_p4_get_shared_tbl_increment(struct tf *tfp __rte_unused,
 364                                 struct tf_get_shared_tbl_increment_parms *parms)
 365 {
 366         parms->increment_cnt = 1;
 367         return 0;
 368 }
 369 static int tf_dev_p4_get_mailbox(void)
 370 {
 371         return TF_KONG_MB;
 372 }
 373
 374 static int tf_dev_p4_word_align(uint16_t size)
 375 {
 376         return ((((size) + 31) >> 5) * 4);
 377 }
 378
 379 /**
 380  * Indicates whether the index table type is SRAM managed
 381  *
 382  * [in] tfp
 383  *   Pointer to TF handle
 384  *
 385  * [in] type
 386  *   Truflow index table type, e.g. TF_TYPE_FULL_ACT_RECORD
 387  *
 388  * Returns
 389  *   - (0) if the table is not managed by the SRAM manager
 390  *   - (1) if the table is managed by the SRAM manager
 391  */
 392 static bool tf_dev_p4_is_sram_managed(struct tf *tfp __rte_unused,
 393                                       enum tf_tbl_type type __rte_unused)
 394 {
 395         return false;
 396 }
 397
 398 /**
 399  * Device specific function that maps the hcapi resource types
 400  * to Truflow type.
 401  *
 402  * [in] hcapi_caps
 403  *   CFA resource type bitmap
 404  *
 405  * [out] ident_caps
 406  *   Pointer to identifier type bitmap
 407  *
 408  * [out] tcam_caps
 409  *   Pointer to tcam type bitmap
 410  *
 411  * [out] tbl_caps
 412  *   Pointer to table type bitmap
 413  *
 414  * [out] em_caps
 415  *   Pointer to em type bitmap
 416  *
 417  * Returns
 418  *   - (0) if successful.
 419  *   - (-EINVAL) on failure.
 420  */
 421 static int tf_dev_p4_map_hcapi_caps(uint64_t hcapi_caps,
 422                                     uint32_t *ident_caps,
 423                                     uint32_t *tcam_caps,
 424                                     uint32_t *tbl_caps,
 425                                     uint32_t *em_caps)
 426 {
 427         uint32_t i;
 428
 429         *ident_caps = 0;
 430         *tcam_caps = 0;
 431         *tbl_caps = 0;
 432         *em_caps = 0;
 433
 434         for (i = 0; i <= CFA_RESOURCE_TYPE_P4_LAST; i++) {
 435                 if (hcapi_caps & 1ULL << i) {
 436                         switch (tf_hcapi_res_map_p4[i].module_type) {
 437                         case TF_MODULE_TYPE_IDENTIFIER:
 438                                 *ident_caps |= tf_hcapi_res_map_p4[i].type_caps;
 439                                 break;
 440                         case TF_MODULE_TYPE_TABLE:
 441                                 *tbl_caps |= tf_hcapi_res_map_p4[i].type_caps;
 442                                 break;
 443                         case TF_MODULE_TYPE_TCAM:
 444                                 *tcam_caps |= tf_hcapi_res_map_p4[i].type_caps;
 445                                 break;
 446                         case TF_MODULE_TYPE_EM:
 447                                 *em_caps |= tf_hcapi_res_map_p4[i].type_caps;
 448                                 break;
 449                         default:
 450                                 return -EINVAL;
 451                         }
 452                 }
 453         }
 454
 455         return 0;
 456 }
 457
 458 /**
 459  * Truflow P4 device specific functions
 460  */
 461 const struct tf_dev_ops tf_dev_ops_p4_init = {
 462         .tf_dev_get_max_types = tf_dev_p4_get_max_types,
 463         .tf_dev_get_resource_str = tf_dev_p4_get_resource_str,
 464         .tf_dev_set_tcam_slice_info = tf_dev_p4_set_tcam_slice_info,
 465         .tf_dev_get_tcam_slice_info = tf_dev_p4_get_tcam_slice_info,
 466         .tf_dev_alloc_ident = NULL,
 467         .tf_dev_free_ident = NULL,
 468         .tf_dev_search_ident = NULL,
 469         .tf_dev_get_ident_resc_info = NULL,
 470         .tf_dev_get_tbl_info = NULL,
 471         .tf_dev_is_sram_managed = tf_dev_p4_is_sram_managed,
 472         .tf_dev_alloc_ext_tbl = NULL,
 473         .tf_dev_alloc_tbl = NULL,
 474         .tf_dev_alloc_sram_tbl = NULL,
 475         .tf_dev_free_ext_tbl = NULL,
 476         .tf_dev_free_tbl = NULL,
 477         .tf_dev_free_sram_tbl = NULL,
 478         .tf_dev_set_tbl = NULL,
 479         .tf_dev_set_ext_tbl = NULL,
 480         .tf_dev_set_sram_tbl = NULL,
 481         .tf_dev_get_tbl = NULL,
 482         .tf_dev_get_sram_tbl = NULL,
 483         .tf_dev_get_bulk_tbl = NULL,
 484         .tf_dev_get_bulk_sram_tbl = NULL,
 485         .tf_dev_get_shared_tbl_increment = tf_dev_p4_get_shared_tbl_increment,
 486         .tf_dev_get_tbl_resc_info = NULL,
 487         .tf_dev_alloc_tcam = NULL,
 488         .tf_dev_free_tcam = NULL,
 489         .tf_dev_alloc_search_tcam = NULL,
 490         .tf_dev_set_tcam = NULL,
 491         .tf_dev_get_tcam = NULL,
 492         .tf_dev_get_tcam_resc_info = NULL,
 493         .tf_dev_insert_int_em_entry = NULL,
 494         .tf_dev_delete_int_em_entry = NULL,
 495         .tf_dev_insert_ext_em_entry = NULL,
 496         .tf_dev_delete_ext_em_entry = NULL,
 497         .tf_dev_get_em_resc_info = NULL,
 498         .tf_dev_alloc_tbl_scope = NULL,
 499         .tf_dev_map_tbl_scope = NULL,
 500         .tf_dev_map_parif = NULL,
 501         .tf_dev_free_tbl_scope = NULL,
 502         .tf_dev_set_if_tbl = NULL,
 503         .tf_dev_get_if_tbl = NULL,
 504         .tf_dev_set_global_cfg = NULL,
 505         .tf_dev_get_global_cfg = NULL,
 506         .tf_dev_get_mailbox = tf_dev_p4_get_mailbox,
 507         .tf_dev_word_align = NULL,
 508         .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps,
 509         .tf_dev_get_sram_resources = NULL,
 510         .tf_dev_set_sram_policy = NULL,
 511         .tf_dev_get_sram_policy = NULL,
 512 };
 513
 514 /**
 515  * Truflow P4 device specific functions
 516  */
 517 const struct tf_dev_ops tf_dev_ops_p4 = {
 518         .tf_dev_get_max_types = tf_dev_p4_get_max_types,
 519         .tf_dev_get_resource_str = tf_dev_p4_get_resource_str,
 520         .tf_dev_set_tcam_slice_info = tf_dev_p4_set_tcam_slice_info,
 521         .tf_dev_get_tcam_slice_info = tf_dev_p4_get_tcam_slice_info,
 522         .tf_dev_alloc_ident = tf_ident_alloc,
 523         .tf_dev_free_ident = tf_ident_free,
 524         .tf_dev_search_ident = tf_ident_search,
 525         .tf_dev_get_ident_resc_info = tf_ident_get_resc_info,
 526         .tf_dev_get_tbl_info = NULL,
 527         .tf_dev_is_sram_managed = tf_dev_p4_is_sram_managed,
 528         .tf_dev_alloc_tbl = tf_tbl_alloc,
 529         .tf_dev_alloc_ext_tbl = tf_tbl_ext_alloc,
 530         .tf_dev_alloc_sram_tbl = tf_tbl_alloc,
 531         .tf_dev_free_tbl = tf_tbl_free,
 532         .tf_dev_free_ext_tbl = tf_tbl_ext_free,
 533         .tf_dev_free_sram_tbl = tf_tbl_free,
 534         .tf_dev_set_tbl = tf_tbl_set,
 535         .tf_dev_set_ext_tbl = tf_tbl_ext_common_set,
 536         .tf_dev_set_sram_tbl = NULL,
 537         .tf_dev_get_tbl = tf_tbl_get,
 538         .tf_dev_get_sram_tbl = NULL,
 539         .tf_dev_get_bulk_tbl = tf_tbl_bulk_get,
 540         .tf_dev_get_bulk_sram_tbl = NULL,
 541         .tf_dev_get_shared_tbl_increment = tf_dev_p4_get_shared_tbl_increment,
 542         .tf_dev_get_tbl_resc_info = tf_tbl_get_resc_info,
 543 #ifdef TF_TCAM_SHARED
 544         .tf_dev_alloc_tcam = tf_tcam_shared_alloc,
 545         .tf_dev_free_tcam = tf_tcam_shared_free,
 546         .tf_dev_set_tcam = tf_tcam_shared_set,
 547         .tf_dev_get_tcam = tf_tcam_shared_get,
 548         .tf_dev_move_tcam = tf_tcam_shared_move_p4,
 549         .tf_dev_clear_tcam = tf_tcam_shared_clear,
 550 #else /* !TF_TCAM_SHARED */
 551         .tf_dev_alloc_tcam = tf_tcam_alloc,
 552         .tf_dev_free_tcam = tf_tcam_free,
 553         .tf_dev_set_tcam = tf_tcam_set,
 554         .tf_dev_get_tcam = tf_tcam_get,
 555 #endif
 556         .tf_dev_alloc_search_tcam = tf_tcam_alloc_search,
 557         .tf_dev_get_tcam_resc_info = tf_tcam_get_resc_info,
 558         .tf_dev_insert_int_em_entry = tf_em_insert_int_entry,
 559         .tf_dev_delete_int_em_entry = tf_em_delete_int_entry,
 560         .tf_dev_insert_ext_em_entry = tf_em_insert_ext_entry,
 561         .tf_dev_delete_ext_em_entry = tf_em_delete_ext_entry,
 562         .tf_dev_get_em_resc_info = tf_em_get_resc_info,
 563         .tf_dev_alloc_tbl_scope = tf_em_ext_common_alloc,
 564         .tf_dev_map_tbl_scope = tf_em_ext_map_tbl_scope,
 565         .tf_dev_map_parif = tf_dev_p4_map_parif,
 566         .tf_dev_free_tbl_scope = tf_em_ext_common_free,
 567         .tf_dev_set_if_tbl = tf_if_tbl_set,
 568         .tf_dev_get_if_tbl = tf_if_tbl_get,
 569         .tf_dev_set_global_cfg = tf_global_cfg_set,
 570         .tf_dev_get_global_cfg = tf_global_cfg_get,
 571         .tf_dev_get_mailbox = tf_dev_p4_get_mailbox,
 572         .tf_dev_word_align = tf_dev_p4_word_align,
 573         .tf_dev_cfa_key_hash = hcapi_cfa_p4_key_hash,
 574         .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps,
 575         .tf_dev_get_sram_resources = NULL,
 576         .tf_dev_set_sram_policy = NULL,
 577         .tf_dev_get_sram_policy = NULL,
 578 };