net/bnxt: update multi device design
[dpdk.git] / drivers / net / bnxt / tf_core / tf_device_p4.h
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2019-2020 Broadcom
3  * All rights reserved.
4  */
5
6 #ifndef _TF_DEVICE_P4_H_
7 #define _TF_DEVICE_P4_H_
8
9 #include <cfa_resource_types.h>
10
11 #include "tf_core.h"
12 #include "tf_rm_new.h"
13
14 struct tf_rm_element_cfg tf_ident_p4[TF_IDENT_TYPE_MAX] = {
15         { TF_RM_ELEM_CFG_PRIVATE, CFA_RESOURCE_TYPE_INVALID },
16         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_PROF_FUNC },
17         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID },
18         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_EM_PROF_ID },
19         /* CFA_RESOURCE_TYPE_P4_L2_FUNC */
20         { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }
21 };
22
23 struct tf_rm_element_cfg tf_tcam_p4[TF_TCAM_TBL_TYPE_MAX] = {
24         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM },
25         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_PROF_TCAM },
26         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_WC_TCAM },
27         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_SP_TCAM },
28         /* CFA_RESOURCE_TYPE_P4_CT_RULE_TCAM */
29         { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
30         /* CFA_RESOURCE_TYPE_P4_VEB_TCAM */
31         { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }
32 };
33
34 struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = {
35         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_FULL_ACTION },
36         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_MCG },
37         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_ENCAP_8B },
38         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_ENCAP_16B },
39         /* CFA_RESOURCE_TYPE_P4_SRAM_ENCAP_32B */
40         { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
41         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_ENCAP_64B },
42         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_SP_MAC },
43         /* CFA_RESOURCE_TYPE_P4_SRAM_SP_SMAC_IPV4 */
44         { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
45         /* CFA_RESOURCE_TYPE_P4_SRAM_SP_SMAC_IPV6 */
46         { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
47         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_COUNTER_64B },
48         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_NAT_SPORT },
49         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_NAT_DPORT },
50         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_NAT_S_IPV4 },
51         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_NAT_D_IPV4 },
52         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_NAT_S_IPV6 },
53         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_NAT_D_IPV6 },
54         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_METER_PROF },
55         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_METER },
56         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_MIRROR },
57         /* CFA_RESOURCE_TYPE_P4_UPAR */
58         { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
59         /* CFA_RESOURCE_TYPE_P4_EPOC */
60         { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
61         /* CFA_RESOURCE_TYPE_P4_METADATA */
62         { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
63         /* CFA_RESOURCE_TYPE_P4_CT_STATE */
64         { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
65         /* CFA_RESOURCE_TYPE_P4_RANGE_PROF */
66         { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
67         /* CFA_RESOURCE_TYPE_P4_RANGE_ENTRY */
68         { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
69         /* CFA_RESOURCE_TYPE_P4_LAG */
70         { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
71         /* CFA_RESOURCE_TYPE_P4_VNIC_SVIF */
72         { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
73         /* CFA_RESOURCE_TYPE_P4_EM_FBK */
74         { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
75         /* CFA_RESOURCE_TYPE_P4_WC_FKB */
76         { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
77         /* CFA_RESOURCE_TYPE_P4_EXT */
78         { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }
79 };
80
81 #endif /* _TF_DEVICE_P4_H_ */