drivers/net/bnxt/tf_core/tf_resources.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2019-2020 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #ifndef _TF_RESOURCES_H_
   7 #define _TF_RESOURCES_H_
   8
   9 /*
  10  * Hardware specific MAX values
  11  * NOTE: Should really come from the chip_cfg.h in some MAX form or HCAPI
  12  */
  13
  14 /* Common HW resources for all chip variants */
  15 #define TF_NUM_L2_CTXT_TCAM      1024      /* < Number of L2 context TCAM
  16                                             * entries
  17                                             */
  18 #define TF_NUM_PROF_FUNC          128      /* < Number prof_func ID */
  19 #define TF_NUM_PROF_TCAM         1024      /* < Number entries in profile
  20                                             * TCAM
  21                                             */
  22 #define TF_NUM_EM_PROF_ID          64      /* < Number software EM Profile
  23                                             * IDs
  24                                             */
  25 #define TF_NUM_WC_PROF_ID         256      /* < Number WC profile IDs */
  26 #define TF_NUM_WC_TCAM_ROW        256      /*  Number slices per row in WC
  27                                             * TCAM. A slices is a WC TCAM entry.
  28                                             */
  29 #define TF_NUM_METER_PROF         256      /* < Number of meter profiles */
  30 #define TF_NUM_METER             1024      /* < Number of meter instances */
  31 #define TF_NUM_MIRROR               2      /* < Number of mirror instances */
  32 #define TF_NUM_UPAR                 2      /* < Number of UPAR instances */
  33
  34 /* Wh+/Brd2 specific HW resources */
  35 #define TF_NUM_SP_TCAM            512      /* < Number of Source Property TCAM
  36                                             * entries
  37                                             */
  38
  39 /* Brd2/Brd4 specific HW resources */
  40 #define TF_NUM_L2_FUNC            256      /* < Number of L2 Func */
  41
  42
  43 /* Brd3, Brd4 common HW resources */
  44 #define TF_NUM_FKB                  1      /* < Number of Flexible Key Builder
  45                                             * templates
  46                                             */
  47
  48 /* Brd4 specific HW resources */
  49 #define TF_NUM_TBL_SCOPE           16      /* < Number of TBL scopes */
  50 #define TF_NUM_EPOCH0               1      /* < Number of Epoch0 */
  51 #define TF_NUM_EPOCH1               1      /* < Number of Epoch1 */
  52 #define TF_NUM_METADATA             8      /* < Number of MetaData Profiles */
  53 #define TF_NUM_CT_STATE            32      /* < Number of Connection Tracking
  54                                             * States
  55                                             */
  56 #define TF_NUM_RANGE_PROF          16      /* < Number of Range Profiles */
  57 #define TF_NUM_RANGE_ENTRY (64 * 1024)     /* < Number of Range Entries */
  58 #define TF_NUM_LAG_ENTRY          256      /* < Number of LAG Entries */
  59
  60 /*
  61  * Common for the Reserved Resource defines below:
  62  *
  63  * - HW Resources
  64  *   For resources where a priority level plays a role, i.e. l2 ctx
  65  *   tcam entries, both a number of resources and a begin/end pair is
  66  *   required. The begin/end is used to assure TFLIB gets the correct
  67  *   priority setting for that resource.
  68  *
  69  *   For EM records there is no priority required thus a number of
  70  *   resources is sufficient.
  71  *
  72  *   Example, TCAM:
  73  *     64 L2 CTXT TCAM entries would in a max 1024 pool be entry
  74  *     0-63 as HW presents 0 as the highest priority entry.
  75  *
  76  * - SRAM Resources
  77  *   Handled as regular resources as there is no priority required.
  78  *
  79  * Common for these resources is that they are handled per direction,
  80  * rx/tx.
  81  */
  82
  83 /* HW Resources */
  84
  85 /* L2 CTX */
  86 #define TF_RSVD_L2_CTXT_TCAM_RX                   64
  87 #define TF_RSVD_L2_CTXT_TCAM_BEGIN_IDX_RX         0
  88 #define TF_RSVD_L2_CTXT_TCAM_END_IDX_RX           (TF_RSVD_L2_CTXT_RX - 1)
  89 #define TF_RSVD_L2_CTXT_TCAM_TX                   960
  90 #define TF_RSVD_L2_CTXT_TCAM_BEGIN_IDX_TX         0
  91 #define TF_RSVD_L2_CTXT_TCAM_END_IDX_TX           (TF_RSVD_L2_CTXT_TX - 1)
  92
  93 /* Profiler */
  94 #define TF_RSVD_PROF_FUNC_RX                      64
  95 #define TF_RSVD_PROF_FUNC_BEGIN_IDX_RX            64
  96 #define TF_RSVD_PROF_FUNC_END_IDX_RX              127
  97 #define TF_RSVD_PROF_FUNC_TX                      64
  98 #define TF_RSVD_PROF_FUNC_BEGIN_IDX_TX            64
  99 #define TF_RSVD_PROF_FUNC_END_IDX_TX              127
 100
 101 #define TF_RSVD_PROF_TCAM_RX                      64
 102 #define TF_RSVD_PROF_TCAM_BEGIN_IDX_RX            960
 103 #define TF_RSVD_PROF_TCAM_END_IDX_RX              1023
 104 #define TF_RSVD_PROF_TCAM_TX                      64
 105 #define TF_RSVD_PROF_TCAM_BEGIN_IDX_TX            960
 106 #define TF_RSVD_PROF_TCAM_END_IDX_TX              1023
 107
 108 /* EM Profiles IDs */
 109 #define TF_RSVD_EM_PROF_ID_RX                     64
 110 #define TF_RSVD_EM_PROF_ID_BEGIN_IDX_RX           0
 111 #define TF_RSVD_EM_PROF_ID_END_IDX_RX             63  /* Less on CU+ then SR */
 112 #define TF_RSVD_EM_PROF_ID_TX                     64
 113 #define TF_RSVD_EM_PROF_ID_BEGIN_IDX_TX           0
 114 #define TF_RSVD_EM_PROF_ID_END_IDX_TX             63  /* Less on CU+ then SR */
 115
 116 /* EM Records */
 117 #define TF_RSVD_EM_REC_RX                         16000
 118 #define TF_RSVD_EM_REC_BEGIN_IDX_RX               0
 119 #define TF_RSVD_EM_REC_TX                         16000
 120 #define TF_RSVD_EM_REC_BEGIN_IDX_TX               0
 121
 122 /* Wildcard */
 123 #define TF_RSVD_WC_TCAM_PROF_ID_RX                128
 124 #define TF_RSVD_WC_TCAM_PROF_ID_BEGIN_IDX_RX      128
 125 #define TF_RSVD_WC_TCAM_PROF_ID_END_IDX_RX        255
 126 #define TF_RSVD_WC_TCAM_PROF_ID_TX                128
 127 #define TF_RSVD_WC_TCAM_PROF_ID_BEGIN_IDX_TX      128
 128 #define TF_RSVD_WC_TCAM_PROF_ID_END_IDX_TX        255
 129
 130 #define TF_RSVD_WC_TCAM_RX                        64
 131 #define TF_RSVD_WC_TCAM_BEGIN_IDX_RX              0
 132 #define TF_RSVD_WC_TCAM_END_IDX_RX                63
 133 #define TF_RSVD_WC_TCAM_TX                        64
 134 #define TF_RSVD_WC_TCAM_BEGIN_IDX_TX              0
 135 #define TF_RSVD_WC_TCAM_END_IDX_TX                63
 136
 137 #define TF_RSVD_METER_PROF_RX                     0
 138 #define TF_RSVD_METER_PROF_BEGIN_IDX_RX           0
 139 #define TF_RSVD_METER_PROF_END_IDX_RX             0
 140 #define TF_RSVD_METER_PROF_TX                     0
 141 #define TF_RSVD_METER_PROF_BEGIN_IDX_TX           0
 142 #define TF_RSVD_METER_PROF_END_IDX_TX             0
 143
 144 #define TF_RSVD_METER_INST_RX                     0
 145 #define TF_RSVD_METER_INST_BEGIN_IDX_RX           0
 146 #define TF_RSVD_METER_INST_END_IDX_RX             0
 147 #define TF_RSVD_METER_INST_TX                     0
 148 #define TF_RSVD_METER_INST_BEGIN_IDX_TX           0
 149 #define TF_RSVD_METER_INST_END_IDX_TX             0
 150
 151 /* Mirror */
 152 #define TF_RSVD_MIRROR_RX                         1
 153 #define TF_RSVD_MIRROR_BEGIN_IDX_RX               0
 154 #define TF_RSVD_MIRROR_END_IDX_RX                 0
 155 #define TF_RSVD_MIRROR_TX                         1
 156 #define TF_RSVD_MIRROR_BEGIN_IDX_TX               0
 157 #define TF_RSVD_MIRROR_END_IDX_TX                 0
 158
 159 /* UPAR */
 160 /* Not yet supported fully in the infra */
 161 #define TF_RSVD_UPAR_RX                           0
 162 #define TF_RSVD_UPAR_BEGIN_IDX_RX                 0
 163 #define TF_RSVD_UPAR_END_IDX_RX                   0
 164 #define TF_RSVD_UPAR_TX                           0
 165 #define TF_RSVD_UPAR_BEGIN_IDX_TX                 0
 166 #define TF_RSVD_UPAR_END_IDX_TX                   0
 167
 168 /* Source Properties */
 169 /* Not yet supported fully in the infra */
 170 #define TF_RSVD_SP_TCAM_RX                        0
 171 #define TF_RSVD_SP_TCAM_BEGIN_IDX_RX              0
 172 #define TF_RSVD_SP_TCAM_END_IDX_RX                0
 173 #define TF_RSVD_SP_TCAM_TX                        0
 174 #define TF_RSVD_SP_TCAM_BEGIN_IDX_TX              0
 175 #define TF_RSVD_SP_TCAM_END_IDX_TX                0
 176
 177 /* L2 Func */
 178 #define TF_RSVD_L2_FUNC_RX                        0
 179 #define TF_RSVD_L2_FUNC_BEGIN_IDX_RX              0
 180 #define TF_RSVD_L2_FUNC_END_IDX_RX                0
 181 #define TF_RSVD_L2_FUNC_TX                        0
 182 #define TF_RSVD_L2_FUNC_BEGIN_IDX_TX              0
 183 #define TF_RSVD_L2_FUNC_END_IDX_TX                0
 184
 185 /* FKB */
 186 #define TF_RSVD_FKB_RX                            0
 187 #define TF_RSVD_FKB_BEGIN_IDX_RX                  0
 188 #define TF_RSVD_FKB_END_IDX_RX                    0
 189 #define TF_RSVD_FKB_TX                            0
 190 #define TF_RSVD_FKB_BEGIN_IDX_TX                  0
 191 #define TF_RSVD_FKB_END_IDX_TX                    0
 192
 193 /* TBL Scope */
 194 #define TF_RSVD_TBL_SCOPE_RX                      1
 195 #define TF_RSVD_TBL_SCOPE_BEGIN_IDX_RX            0
 196 #define TF_RSVD_TBL_SCOPE_END_IDX_RX              1
 197 #define TF_RSVD_TBL_SCOPE_TX                      1
 198 #define TF_RSVD_TBL_SCOPE_BEGIN_IDX_TX            0
 199 #define TF_RSVD_TBL_SCOPE_END_IDX_TX              1
 200
 201 /* EPOCH0 */
 202 /* Not yet supported fully in the infra */
 203 #define TF_RSVD_EPOCH0_RX                         0
 204 #define TF_RSVD_EPOCH0_BEGIN_IDX_RX               0
 205 #define TF_RSVD_EPOCH0_END_IDX_RX                 0
 206 #define TF_RSVD_EPOCH0_TX                         0
 207 #define TF_RSVD_EPOCH0_BEGIN_IDX_TX               0
 208 #define TF_RSVD_EPOCH0_END_IDX_TX                 0
 209
 210 /* EPOCH1 */
 211 /* Not yet supported fully in the infra */
 212 #define TF_RSVD_EPOCH1_RX                         0
 213 #define TF_RSVD_EPOCH1_BEGIN_IDX_RX               0
 214 #define TF_RSVD_EPOCH1_END_IDX_RX                 0
 215 #define TF_RSVD_EPOCH1_TX                         0
 216 #define TF_RSVD_EPOCH1_BEGIN_IDX_TX               0
 217 #define TF_RSVD_EPOCH1_END_IDX_TX                 0
 218
 219 /* METADATA */
 220 /* Not yet supported fully in the infra */
 221 #define TF_RSVD_METADATA_RX                       0
 222 #define TF_RSVD_METADATA_BEGIN_IDX_RX             0
 223 #define TF_RSVD_METADATA_END_IDX_RX               0
 224 #define TF_RSVD_METADATA_TX                       0
 225 #define TF_RSVD_METADATA_BEGIN_IDX_TX             0
 226 #define TF_RSVD_METADATA_END_IDX_TX               0
 227
 228 /* CT_STATE */
 229 /* Not yet supported fully in the infra */
 230 #define TF_RSVD_CT_STATE_RX                       0
 231 #define TF_RSVD_CT_STATE_BEGIN_IDX_RX             0
 232 #define TF_RSVD_CT_STATE_END_IDX_RX               0
 233 #define TF_RSVD_CT_STATE_TX                       0
 234 #define TF_RSVD_CT_STATE_BEGIN_IDX_TX             0
 235 #define TF_RSVD_CT_STATE_END_IDX_TX               0
 236
 237 /* RANGE_PROF */
 238 /* Not yet supported fully in the infra */
 239 #define TF_RSVD_RANGE_PROF_RX                     0
 240 #define TF_RSVD_RANGE_PROF_BEGIN_IDX_RX           0
 241 #define TF_RSVD_RANGE_PROF_END_IDX_RX             0
 242 #define TF_RSVD_RANGE_PROF_TX                     0
 243 #define TF_RSVD_RANGE_PROF_BEGIN_IDX_TX           0
 244 #define TF_RSVD_RANGE_PROF_END_IDX_TX             0
 245
 246 /* RANGE_ENTRY */
 247 /* Not yet supported fully in the infra */
 248 #define TF_RSVD_RANGE_ENTRY_RX                    0
 249 #define TF_RSVD_RANGE_ENTRY_BEGIN_IDX_RX          0
 250 #define TF_RSVD_RANGE_ENTRY_END_IDX_RX            0
 251 #define TF_RSVD_RANGE_ENTRY_TX                    0
 252 #define TF_RSVD_RANGE_ENTRY_BEGIN_IDX_TX          0
 253 #define TF_RSVD_RANGE_ENTRY_END_IDX_TX            0
 254
 255 /* LAG_ENTRY */
 256 /* Not yet supported fully in the infra */
 257 #define TF_RSVD_LAG_ENTRY_RX                      0
 258 #define TF_RSVD_LAG_ENTRY_BEGIN_IDX_RX            0
 259 #define TF_RSVD_LAG_ENTRY_END_IDX_RX              0
 260 #define TF_RSVD_LAG_ENTRY_TX                      0
 261 #define TF_RSVD_LAG_ENTRY_BEGIN_IDX_TX            0
 262 #define TF_RSVD_LAG_ENTRY_END_IDX_TX              0
 263
 264
 265 /* SRAM - Resources
 266  * Limited to the types that CFA provides.
 267  */
 268 #define TF_RSVD_SRAM_FULL_ACTION_RX               8001
 269 #define TF_RSVD_SRAM_FULL_ACTION_BEGIN_IDX_RX     0
 270 #define TF_RSVD_SRAM_FULL_ACTION_TX               8001
 271 #define TF_RSVD_SRAM_FULL_ACTION_BEGIN_IDX_TX     0
 272
 273 /* Not yet supported fully in the infra */
 274 #define TF_RSVD_SRAM_MCG_RX                       0
 275 #define TF_RSVD_SRAM_MCG_BEGIN_IDX_RX             0
 276 /* Multicast Group on TX is not supported */
 277 #define TF_RSVD_SRAM_MCG_TX                       0
 278 #define TF_RSVD_SRAM_MCG_BEGIN_IDX_TX             0
 279
 280 /* First encap of 8B RX is reserved by CFA */
 281 #define TF_RSVD_SRAM_ENCAP_8B_RX                  32
 282 #define TF_RSVD_SRAM_ENCAP_8B_BEGIN_IDX_RX        0
 283 /* First encap of 8B TX is reserved by CFA */
 284 #define TF_RSVD_SRAM_ENCAP_8B_TX                  0
 285 #define TF_RSVD_SRAM_ENCAP_8B_BEGIN_IDX_TX        0
 286
 287 #define TF_RSVD_SRAM_ENCAP_16B_RX                 16
 288 #define TF_RSVD_SRAM_ENCAP_16B_BEGIN_IDX_RX       0
 289 /* First encap of 16B TX is reserved by CFA */
 290 #define TF_RSVD_SRAM_ENCAP_16B_TX                 20
 291 #define TF_RSVD_SRAM_ENCAP_16B_BEGIN_IDX_TX       0
 292
 293 /* Encap of 64B on RX is not supported */
 294 #define TF_RSVD_SRAM_ENCAP_64B_RX                 0
 295 #define TF_RSVD_SRAM_ENCAP_64B_BEGIN_IDX_RX       0
 296 /* First encap of 64B TX is reserved by CFA */
 297 #define TF_RSVD_SRAM_ENCAP_64B_TX                 1007
 298 #define TF_RSVD_SRAM_ENCAP_64B_BEGIN_IDX_TX       0
 299
 300 #define TF_RSVD_SRAM_SP_SMAC_RX                   0
 301 #define TF_RSVD_SRAM_SP_SMAC_BEGIN_IDX_RX         0
 302 #define TF_RSVD_SRAM_SP_SMAC_TX                   0
 303 #define TF_RSVD_SRAM_SP_SMAC_BEGIN_IDX_TX         0
 304
 305 /* SRAM SP IPV4 on RX is not supported */
 306 #define TF_RSVD_SRAM_SP_SMAC_IPV4_RX              0
 307 #define TF_RSVD_SRAM_SP_SMAC_IPV4_BEGIN_IDX_RX    0
 308 #define TF_RSVD_SRAM_SP_SMAC_IPV4_TX              511
 309 #define TF_RSVD_SRAM_SP_SMAC_IPV4_BEGIN_IDX_TX    0
 310
 311 /* SRAM SP IPV6 on RX is not supported */
 312 #define TF_RSVD_SRAM_SP_SMAC_IPV6_RX              0
 313 #define TF_RSVD_SRAM_SP_SMAC_IPV6_BEGIN_IDX_RX    0
 314 /* Not yet supported fully in infra */
 315 #define TF_RSVD_SRAM_SP_SMAC_IPV6_TX              0
 316 #define TF_RSVD_SRAM_SP_SMAC_IPV6_BEGIN_IDX_TX    0
 317
 318 #define TF_RSVD_SRAM_COUNTER_64B_RX               160
 319 #define TF_RSVD_SRAM_COUNTER_64B_BEGIN_IDX_RX     0
 320 #define TF_RSVD_SRAM_COUNTER_64B_TX               160
 321 #define TF_RSVD_SRAM_COUNTER_64B_BEGIN_IDX_TX     0
 322
 323 #define TF_RSVD_SRAM_NAT_SPORT_RX                 0
 324 #define TF_RSVD_SRAM_NAT_SPORT_BEGIN_IDX_RX       0
 325 #define TF_RSVD_SRAM_NAT_SPORT_TX                 0
 326 #define TF_RSVD_SRAM_NAT_SPORT_BEGIN_IDX_TX       0
 327
 328 #define TF_RSVD_SRAM_NAT_DPORT_RX                 0
 329 #define TF_RSVD_SRAM_NAT_DPORT_BEGIN_IDX_RX       0
 330 #define TF_RSVD_SRAM_NAT_DPORT_TX                 0
 331 #define TF_RSVD_SRAM_NAT_DPORT_BEGIN_IDX_TX       0
 332
 333 #define TF_RSVD_SRAM_NAT_S_IPV4_RX                0
 334 #define TF_RSVD_SRAM_NAT_S_IPV4_BEGIN_IDX_RX      0
 335 #define TF_RSVD_SRAM_NAT_S_IPV4_TX                0
 336 #define TF_RSVD_SRAM_NAT_S_IPV4_BEGIN_IDX_TX      0
 337
 338 #define TF_RSVD_SRAM_NAT_D_IPV4_RX                0
 339 #define TF_RSVD_SRAM_NAT_D_IPV4_BEGIN_IDX_RX      0
 340 #define TF_RSVD_SRAM_NAT_D_IPV4_TX                0
 341 #define TF_RSVD_SRAM_NAT_D_IPV4_BEGIN_IDX_TX      0
 342
 343 /* HW Resource Pool names */
 344
 345 #define TF_L2_CTXT_TCAM_POOL_NAME         l2_ctxt_tcam_pool
 346 #define TF_L2_CTXT_TCAM_POOL_NAME_RX      l2_ctxt_tcam_pool_rx
 347 #define TF_L2_CTXT_TCAM_POOL_NAME_TX      l2_ctxt_tcam_pool_tx
 348
 349 #define TF_PROF_FUNC_POOL_NAME            prof_func_pool
 350 #define TF_PROF_FUNC_POOL_NAME_RX         prof_func_pool_rx
 351 #define TF_PROF_FUNC_POOL_NAME_TX         prof_func_pool_tx
 352
 353 #define TF_PROF_TCAM_POOL_NAME            prof_tcam_pool
 354 #define TF_PROF_TCAM_POOL_NAME_RX         prof_tcam_pool_rx
 355 #define TF_PROF_TCAM_POOL_NAME_TX         prof_tcam_pool_tx
 356
 357 #define TF_EM_PROF_ID_POOL_NAME           em_prof_id_pool
 358 #define TF_EM_PROF_ID_POOL_NAME_RX        em_prof_id_pool_rx
 359 #define TF_EM_PROF_ID_POOL_NAME_TX        em_prof_id_pool_tx
 360
 361 #define TF_WC_TCAM_PROF_ID_POOL_NAME      wc_tcam_prof_id_pool
 362 #define TF_WC_TCAM_PROF_ID_POOL_NAME_RX   wc_tcam_prof_id_pool_rx
 363 #define TF_WC_TCAM_PROF_ID_POOL_NAME_TX   wc_tcam_prof_id_pool_tx
 364
 365 #define TF_WC_TCAM_POOL_NAME              wc_tcam_pool
 366 #define TF_WC_TCAM_POOL_NAME_RX           wc_tcam_pool_rx
 367 #define TF_WC_TCAM_POOL_NAME_TX           wc_tcam_pool_tx
 368
 369 #define TF_METER_PROF_POOL_NAME           meter_prof_pool
 370 #define TF_METER_PROF_POOL_NAME_RX        meter_prof_pool_rx
 371 #define TF_METER_PROF_POOL_NAME_TX        meter_prof_pool_tx
 372
 373 #define TF_METER_INST_POOL_NAME           meter_inst_pool
 374 #define TF_METER_INST_POOL_NAME_RX        meter_inst_pool_rx
 375 #define TF_METER_INST_POOL_NAME_TX        meter_inst_pool_tx
 376
 377 #define TF_MIRROR_POOL_NAME               mirror_pool
 378 #define TF_MIRROR_POOL_NAME_RX            mirror_pool_rx
 379 #define TF_MIRROR_POOL_NAME_TX            mirror_pool_tx
 380
 381 #define TF_UPAR_POOL_NAME                 upar_pool
 382 #define TF_UPAR_POOL_NAME_RX              upar_pool_rx
 383 #define TF_UPAR_POOL_NAME_TX              upar_pool_tx
 384
 385 #define TF_SP_TCAM_POOL_NAME              sp_tcam_pool
 386 #define TF_SP_TCAM_POOL_NAME_RX           sp_tcam_pool_rx
 387 #define TF_SP_TCAM_POOL_NAME_TX           sp_tcam_pool_tx
 388
 389 #define TF_FKB_POOL_NAME                  fkb_pool
 390 #define TF_FKB_POOL_NAME_RX               fkb_pool_rx
 391 #define TF_FKB_POOL_NAME_TX               fkb_pool_tx
 392
 393 #define TF_TBL_SCOPE_POOL_NAME            tbl_scope_pool
 394 #define TF_TBL_SCOPE_POOL_NAME_RX         tbl_scope_pool_rx
 395 #define TF_TBL_SCOPE_POOL_NAME_TX         tbl_scope_pool_tx
 396
 397 #define TF_L2_FUNC_POOL_NAME              l2_func_pool
 398 #define TF_L2_FUNC_POOL_NAME_RX           l2_func_pool_rx
 399 #define TF_L2_FUNC_POOL_NAME_TX           l2_func_pool_tx
 400
 401 #define TF_EPOCH0_POOL_NAME               epoch0_pool
 402 #define TF_EPOCH0_POOL_NAME_RX            epoch0_pool_rx
 403 #define TF_EPOCH0_POOL_NAME_TX            epoch0_pool_tx
 404
 405 #define TF_EPOCH1_POOL_NAME               epoch1_pool
 406 #define TF_EPOCH1_POOL_NAME_RX            epoch1_pool_rx
 407 #define TF_EPOCH1_POOL_NAME_TX            epoch1_pool_tx
 408
 409 #define TF_METADATA_POOL_NAME             metadata_pool
 410 #define TF_METADATA_POOL_NAME_RX          metadata_pool_rx
 411 #define TF_METADATA_POOL_NAME_TX          metadata_pool_tx
 412
 413 #define TF_CT_STATE_POOL_NAME             ct_state_pool
 414 #define TF_CT_STATE_POOL_NAME_RX          ct_state_pool_rx
 415 #define TF_CT_STATE_POOL_NAME_TX          ct_state_pool_tx
 416
 417 #define TF_RANGE_PROF_POOL_NAME           range_prof_pool
 418 #define TF_RANGE_PROF_POOL_NAME_RX        range_prof_pool_rx
 419 #define TF_RANGE_PROF_POOL_NAME_TX        range_prof_pool_tx
 420
 421 #define TF_RANGE_ENTRY_POOL_NAME          range_entry_pool
 422 #define TF_RANGE_ENTRY_POOL_NAME_RX       range_entry_pool_rx
 423 #define TF_RANGE_ENTRY_POOL_NAME_TX       range_entry_pool_tx
 424
 425 #define TF_LAG_ENTRY_POOL_NAME            lag_entry_pool
 426 #define TF_LAG_ENTRY_POOL_NAME_RX         lag_entry_pool_rx
 427 #define TF_LAG_ENTRY_POOL_NAME_TX         lag_entry_pool_tx
 428
 429 /* SRAM Resource Pool names */
 430 #define TF_SRAM_FULL_ACTION_POOL_NAME     sram_full_action_pool
 431 #define TF_SRAM_FULL_ACTION_POOL_NAME_RX  sram_full_action_pool_rx
 432 #define TF_SRAM_FULL_ACTION_POOL_NAME_TX  sram_full_action_pool_tx
 433
 434 #define TF_SRAM_MCG_POOL_NAME             sram_mcg_pool
 435 #define TF_SRAM_MCG_POOL_NAME_RX          sram_mcg_pool_rx
 436 #define TF_SRAM_MCG_POOL_NAME_TX          sram_mcg_pool_tx
 437
 438 #define TF_SRAM_ENCAP_8B_POOL_NAME        sram_encap_8b_pool
 439 #define TF_SRAM_ENCAP_8B_POOL_NAME_RX     sram_encap_8b_pool_rx
 440 #define TF_SRAM_ENCAP_8B_POOL_NAME_TX     sram_encap_8b_pool_tx
 441
 442 #define TF_SRAM_ENCAP_16B_POOL_NAME       sram_encap_16b_pool
 443 #define TF_SRAM_ENCAP_16B_POOL_NAME_RX    sram_encap_16b_pool_rx
 444 #define TF_SRAM_ENCAP_16B_POOL_NAME_TX    sram_encap_16b_pool_tx
 445
 446 #define TF_SRAM_ENCAP_64B_POOL_NAME       sram_encap_64b_pool
 447 #define TF_SRAM_ENCAP_64B_POOL_NAME_RX    sram_encap_64b_pool_rx
 448 #define TF_SRAM_ENCAP_64B_POOL_NAME_TX    sram_encap_64b_pool_tx
 449
 450 #define TF_SRAM_SP_SMAC_POOL_NAME         sram_sp_smac_pool
 451 #define TF_SRAM_SP_SMAC_POOL_NAME_RX      sram_sp_smac_pool_rx
 452 #define TF_SRAM_SP_SMAC_POOL_NAME_TX      sram_sp_smac_pool_tx
 453
 454 #define TF_SRAM_SP_SMAC_IPV4_POOL_NAME    sram_sp_smac_ipv4_pool
 455 #define TF_SRAM_SP_SMAC_IPV4_POOL_NAME_RX sram_sp_smac_ipv4_pool_rx
 456 #define TF_SRAM_SP_SMAC_IPV4_POOL_NAME_TX sram_sp_smac_ipv4_pool_tx
 457
 458 #define TF_SRAM_SP_SMAC_IPV6_POOL_NAME    sram_sp_smac_ipv6_pool
 459 #define TF_SRAM_SP_SMAC_IPV6_POOL_NAME_RX sram_sp_smac_ipv6_pool_rx
 460 #define TF_SRAM_SP_SMAC_IPV6_POOL_NAME_TX sram_sp_smac_ipv6_pool_tx
 461
 462 #define TF_SRAM_STATS_64B_POOL_NAME       sram_stats_64b_pool
 463 #define TF_SRAM_STATS_64B_POOL_NAME_RX    sram_stats_64b_pool_rx
 464 #define TF_SRAM_STATS_64B_POOL_NAME_TX    sram_stats_64b_pool_tx
 465
 466 #define TF_SRAM_NAT_SPORT_POOL_NAME       sram_nat_sport_pool
 467 #define TF_SRAM_NAT_SPORT_POOL_NAME_RX    sram_nat_sport_pool_rx
 468 #define TF_SRAM_NAT_SPORT_POOL_NAME_TX    sram_nat_sport_pool_tx
 469
 470 #define TF_SRAM_NAT_DPORT_POOL_NAME       sram_nat_dport_pool
 471 #define TF_SRAM_NAT_DPORT_POOL_NAME_RX    sram_nat_dport_pool_rx
 472 #define TF_SRAM_NAT_DPORT_POOL_NAME_TX    sram_nat_dport_pool_tx
 473
 474 #define TF_SRAM_NAT_S_IPV4_POOL_NAME      sram_nat_s_ipv4_pool
 475 #define TF_SRAM_NAT_S_IPV4_POOL_NAME_RX   sram_nat_s_ipv4_pool_rx
 476 #define TF_SRAM_NAT_S_IPV4_POOL_NAME_TX   sram_nat_s_ipv4_pool_tx
 477
 478 #define TF_SRAM_NAT_D_IPV4_POOL_NAME      sram_nat_d_ipv4_pool
 479 #define TF_SRAM_NAT_D_IPV4_POOL_NAME_RX   sram_nat_d_ipv4_pool_rx
 480 #define TF_SRAM_NAT_D_IPV4_POOL_NAME_TX   sram_nat_d_ipv4_pool_tx
 481
 482 /* Sw Resource Pool Names */
 483
 484 #define TF_L2_CTXT_REMAP_POOL_NAME         l2_ctxt_remap_pool
 485 #define TF_L2_CTXT_REMAP_POOL_NAME_RX      l2_ctxt_remap_pool_rx
 486 #define TF_L2_CTXT_REMAP_POOL_NAME_TX      l2_ctxt_remap_pool_tx
 487
 488
 489 /** HW Resource types
 490  */
 491 enum tf_resource_type_hw {
 492         /* Common HW resources for all chip variants */
 493         TF_RESC_TYPE_HW_L2_CTXT_TCAM,
 494         TF_RESC_TYPE_HW_PROF_FUNC,
 495         TF_RESC_TYPE_HW_PROF_TCAM,
 496         TF_RESC_TYPE_HW_EM_PROF_ID,
 497         TF_RESC_TYPE_HW_EM_REC,
 498         TF_RESC_TYPE_HW_WC_TCAM_PROF_ID,
 499         TF_RESC_TYPE_HW_WC_TCAM,
 500         TF_RESC_TYPE_HW_METER_PROF,
 501         TF_RESC_TYPE_HW_METER_INST,
 502         TF_RESC_TYPE_HW_MIRROR,
 503         TF_RESC_TYPE_HW_UPAR,
 504         /* Wh+/Brd2 specific HW resources */
 505         TF_RESC_TYPE_HW_SP_TCAM,
 506         /* Brd2/Brd4 specific HW resources */
 507         TF_RESC_TYPE_HW_L2_FUNC,
 508         /* Brd3, Brd4 common HW resources */
 509         TF_RESC_TYPE_HW_FKB,
 510         /* Brd4 specific HW resources */
 511         TF_RESC_TYPE_HW_TBL_SCOPE,
 512         TF_RESC_TYPE_HW_EPOCH0,
 513         TF_RESC_TYPE_HW_EPOCH1,
 514         TF_RESC_TYPE_HW_METADATA,
 515         TF_RESC_TYPE_HW_CT_STATE,
 516         TF_RESC_TYPE_HW_RANGE_PROF,
 517         TF_RESC_TYPE_HW_RANGE_ENTRY,
 518         TF_RESC_TYPE_HW_LAG_ENTRY,
 519         TF_RESC_TYPE_HW_MAX
 520 };
 521
 522 /** HW Resource types
 523  */
 524 enum tf_resource_type_sram {
 525         TF_RESC_TYPE_SRAM_FULL_ACTION,
 526         TF_RESC_TYPE_SRAM_MCG,
 527         TF_RESC_TYPE_SRAM_ENCAP_8B,
 528         TF_RESC_TYPE_SRAM_ENCAP_16B,
 529         TF_RESC_TYPE_SRAM_ENCAP_64B,
 530         TF_RESC_TYPE_SRAM_SP_SMAC,
 531         TF_RESC_TYPE_SRAM_SP_SMAC_IPV4,
 532         TF_RESC_TYPE_SRAM_SP_SMAC_IPV6,
 533         TF_RESC_TYPE_SRAM_COUNTER_64B,
 534         TF_RESC_TYPE_SRAM_NAT_SPORT,
 535         TF_RESC_TYPE_SRAM_NAT_DPORT,
 536         TF_RESC_TYPE_SRAM_NAT_S_IPV4,
 537         TF_RESC_TYPE_SRAM_NAT_D_IPV4,
 538         TF_RESC_TYPE_SRAM_MAX
 539 };
 540
 541 #endif /* _TF_RESOURCES_H_ */