net/bnxt: add VLAN tag count in computed field list
[dpdk.git] / drivers / net / bnxt / tf_ulp / ulp_template_db_enum.h
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2014-2020 Broadcom
3  * All rights reserved.
4  */
5
6 #ifndef ULP_TEMPLATE_DB_H_
7 #define ULP_TEMPLATE_DB_H_
8
9 #define BNXT_ULP_REGFILE_MAX_SZ 17
10 #define BNXT_ULP_MAX_NUM_DEVICES 4
11 #define BNXT_ULP_LOG2_MAX_NUM_DEV 2
12 #define BNXT_ULP_CACHE_TBL_MAX_SZ 4
13 #define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 256
14 #define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 4
15 #define BNXT_ULP_CLASS_HID_LOW_PRIME 7919
16 #define BNXT_ULP_CLASS_HID_HIGH_PRIME 7907
17 #define BNXT_ULP_CLASS_HID_SHFTR 16
18 #define BNXT_ULP_CLASS_HID_SHFTL 23
19 #define BNXT_ULP_CLASS_HID_MASK 255
20 #define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 256
21 #define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 24
22 #define BNXT_ULP_ACT_HID_LOW_PRIME 7919
23 #define BNXT_ULP_ACT_HID_HIGH_PRIME 7919
24 #define BNXT_ULP_ACT_HID_SHFTR 23
25 #define BNXT_ULP_ACT_HID_SHFTL 23
26 #define BNXT_ULP_ACT_HID_MASK 255
27 #define BNXT_ULP_CACHE_TBL_IDENT_MAX_NUM 2
28 #define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 5
29 #define BNXT_ULP_GLB_TEMPLATE_TBL_MAX_SZ 1
30
31 enum bnxt_ulp_action_bit {
32         BNXT_ULP_ACTION_BIT_MARK             = 0x0000000000000001,
33         BNXT_ULP_ACTION_BIT_DROP             = 0x0000000000000002,
34         BNXT_ULP_ACTION_BIT_COUNT            = 0x0000000000000004,
35         BNXT_ULP_ACTION_BIT_RSS              = 0x0000000000000008,
36         BNXT_ULP_ACTION_BIT_METER            = 0x0000000000000010,
37         BNXT_ULP_ACTION_BIT_VNIC             = 0x0000000000000020,
38         BNXT_ULP_ACTION_BIT_VPORT            = 0x0000000000000040,
39         BNXT_ULP_ACTION_BIT_VXLAN_DECAP      = 0x0000000000000080,
40         BNXT_ULP_ACTION_BIT_NVGRE_DECAP      = 0x0000000000000100,
41         BNXT_ULP_ACTION_BIT_POP_MPLS         = 0x0000000000000200,
42         BNXT_ULP_ACTION_BIT_PUSH_MPLS        = 0x0000000000000400,
43         BNXT_ULP_ACTION_BIT_MAC_SWAP         = 0x0000000000000800,
44         BNXT_ULP_ACTION_BIT_SET_MAC_SRC      = 0x0000000000001000,
45         BNXT_ULP_ACTION_BIT_SET_MAC_DST      = 0x0000000000002000,
46         BNXT_ULP_ACTION_BIT_POP_VLAN         = 0x0000000000004000,
47         BNXT_ULP_ACTION_BIT_PUSH_VLAN        = 0x0000000000008000,
48         BNXT_ULP_ACTION_BIT_SET_VLAN_PCP     = 0x0000000000010000,
49         BNXT_ULP_ACTION_BIT_SET_VLAN_VID     = 0x0000000000020000,
50         BNXT_ULP_ACTION_BIT_SET_IPV4_SRC     = 0x0000000000040000,
51         BNXT_ULP_ACTION_BIT_SET_IPV4_DST     = 0x0000000000080000,
52         BNXT_ULP_ACTION_BIT_SET_IPV6_SRC     = 0x0000000000100000,
53         BNXT_ULP_ACTION_BIT_SET_IPV6_DST     = 0x0000000000200000,
54         BNXT_ULP_ACTION_BIT_DEC_TTL          = 0x0000000000400000,
55         BNXT_ULP_ACTION_BIT_SET_TP_SRC       = 0x0000000000800000,
56         BNXT_ULP_ACTION_BIT_SET_TP_DST       = 0x0000000001000000,
57         BNXT_ULP_ACTION_BIT_VXLAN_ENCAP      = 0x0000000002000000,
58         BNXT_ULP_ACTION_BIT_NVGRE_ENCAP      = 0x0000000004000000,
59         BNXT_ULP_ACTION_BIT_LAST             = 0x0000000008000000
60 };
61
62 enum bnxt_ulp_hdr_bit {
63         BNXT_ULP_HDR_BIT_O_ETH               = 0x0000000000000001,
64         BNXT_ULP_HDR_BIT_OO_VLAN             = 0x0000000000000002,
65         BNXT_ULP_HDR_BIT_OI_VLAN             = 0x0000000000000004,
66         BNXT_ULP_HDR_BIT_O_IPV4              = 0x0000000000000008,
67         BNXT_ULP_HDR_BIT_O_IPV6              = 0x0000000000000010,
68         BNXT_ULP_HDR_BIT_O_TCP               = 0x0000000000000020,
69         BNXT_ULP_HDR_BIT_O_UDP               = 0x0000000000000040,
70         BNXT_ULP_HDR_BIT_T_VXLAN             = 0x0000000000000080,
71         BNXT_ULP_HDR_BIT_T_GRE               = 0x0000000000000100,
72         BNXT_ULP_HDR_BIT_I_ETH               = 0x0000000000000200,
73         BNXT_ULP_HDR_BIT_IO_VLAN             = 0x0000000000000400,
74         BNXT_ULP_HDR_BIT_II_VLAN             = 0x0000000000000800,
75         BNXT_ULP_HDR_BIT_I_IPV4              = 0x0000000000001000,
76         BNXT_ULP_HDR_BIT_I_IPV6              = 0x0000000000002000,
77         BNXT_ULP_HDR_BIT_I_TCP               = 0x0000000000004000,
78         BNXT_ULP_HDR_BIT_I_UDP               = 0x0000000000008000,
79         BNXT_ULP_HDR_BIT_LAST                = 0x0000000000010000
80 };
81
82 enum bnxt_ulp_act_type {
83         BNXT_ULP_ACT_TYPE_NOT_SUPPORTED = 0,
84         BNXT_ULP_ACT_TYPE_SUPPORTED = 1,
85         BNXT_ULP_ACT_TYPE_END = 2,
86         BNXT_ULP_ACT_TYPE_LAST = 3
87 };
88
89 enum bnxt_ulp_byte_order {
90         BNXT_ULP_BYTE_ORDER_BE = 0,
91         BNXT_ULP_BYTE_ORDER_LE = 1,
92         BNXT_ULP_BYTE_ORDER_LAST = 2
93 };
94
95 enum bnxt_ulp_cf_idx {
96         BNXT_ULP_CF_IDX_NOT_USED = 0,
97         BNXT_ULP_CF_IDX_MPLS_TAG_NUM = 1,
98         BNXT_ULP_CF_IDX_O_VTAG_NUM = 2,
99         BNXT_ULP_CF_IDX_O_NO_VTAG = 3,
100         BNXT_ULP_CF_IDX_O_ONE_VTAG = 4,
101         BNXT_ULP_CF_IDX_O_TWO_VTAGS = 5,
102         BNXT_ULP_CF_IDX_I_VTAG_NUM = 6,
103         BNXT_ULP_CF_IDX_I_NO_VTAG = 7,
104         BNXT_ULP_CF_IDX_I_ONE_VTAG = 8,
105         BNXT_ULP_CF_IDX_I_TWO_VTAGS = 9,
106         BNXT_ULP_CF_IDX_INCOMING_IF = 10,
107         BNXT_ULP_CF_IDX_DIRECTION = 11,
108         BNXT_ULP_CF_IDX_SVIF_FLAG = 12,
109         BNXT_ULP_CF_IDX_O_L3 = 13,
110         BNXT_ULP_CF_IDX_I_L3 = 14,
111         BNXT_ULP_CF_IDX_O_L4 = 15,
112         BNXT_ULP_CF_IDX_I_L4 = 16,
113         BNXT_ULP_CF_IDX_DEV_PORT_ID = 17,
114         BNXT_ULP_CF_IDX_DRV_FUNC_SVIF = 18,
115         BNXT_ULP_CF_IDX_DRV_FUNC_SPIF = 19,
116         BNXT_ULP_CF_IDX_DRV_FUNC_PARIF = 20,
117         BNXT_ULP_CF_IDX_DRV_FUNC_VNIC = 21,
118         BNXT_ULP_CF_IDX_DRV_FUNC_PHY_PORT = 22,
119         BNXT_ULP_CF_IDX_VF_FUNC_SVIF = 23,
120         BNXT_ULP_CF_IDX_VF_FUNC_SPIF = 24,
121         BNXT_ULP_CF_IDX_VF_FUNC_PARIF = 25,
122         BNXT_ULP_CF_IDX_VF_FUNC_VNIC = 26,
123         BNXT_ULP_CF_IDX_PHY_PORT_SVIF = 27,
124         BNXT_ULP_CF_IDX_PHY_PORT_SPIF = 28,
125         BNXT_ULP_CF_IDX_PHY_PORT_PARIF = 29,
126         BNXT_ULP_CF_IDX_PHY_PORT_VPORT = 30,
127         BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG = 31,
128         BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG = 32,
129         BNXT_ULP_CF_IDX_ACT_DEC_TTL = 33,
130         BNXT_ULP_CF_IDX_ACT_T_DEC_TTL = 34,
131         BNXT_ULP_CF_IDX_LAST = 35
132 };
133
134 enum bnxt_ulp_cond_opcode {
135         BNXT_ULP_COND_OPCODE_NOP = 0,
136         BNXT_ULP_COND_OPCODE_COMP_FIELD_IS_SET = 1,
137         BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET = 2,
138         BNXT_ULP_COND_OPCODE_HDR_BIT_IS_SET = 3,
139         BNXT_ULP_COND_OPCODE_COMP_FIELD_NOT_SET = 4,
140         BNXT_ULP_COND_OPCODE_ACTION_BIT_NOT_SET = 5,
141         BNXT_ULP_COND_OPCODE_HDR_BIT_NOT_SET = 6,
142         BNXT_ULP_COND_OPCODE_LAST = 7
143 };
144
145 enum bnxt_ulp_critical_resource {
146         BNXT_ULP_CRITICAL_RESOURCE_NO = 0,
147         BNXT_ULP_CRITICAL_RESOURCE_YES = 1,
148         BNXT_ULP_CRITICAL_RESOURCE_LAST = 2
149 };
150
151 enum bnxt_ulp_device_id {
152         BNXT_ULP_DEVICE_ID_WH_PLUS = 0,
153         BNXT_ULP_DEVICE_ID_THOR = 1,
154         BNXT_ULP_DEVICE_ID_STINGRAY = 2,
155         BNXT_ULP_DEVICE_ID_STINGRAY2 = 3,
156         BNXT_ULP_DEVICE_ID_LAST = 4
157 };
158
159 enum bnxt_ulp_df_param_type {
160         BNXT_ULP_DF_PARAM_TYPE_DEV_PORT_ID = 0,
161         BNXT_ULP_DF_PARAM_TYPE_LAST = 1
162 };
163
164 enum bnxt_ulp_direction {
165         BNXT_ULP_DIRECTION_INGRESS = 0,
166         BNXT_ULP_DIRECTION_EGRESS = 1,
167         BNXT_ULP_DIRECTION_LAST = 2
168 };
169
170 enum bnxt_ulp_flow_mem_type {
171         BNXT_ULP_FLOW_MEM_TYPE_INT = 0,
172         BNXT_ULP_FLOW_MEM_TYPE_EXT = 1,
173         BNXT_ULP_FLOW_MEM_TYPE_BOTH = 2,
174         BNXT_ULP_FLOW_MEM_TYPE_LAST = 3
175 };
176
177 enum bnxt_ulp_glb_regfile_index {
178         BNXT_ULP_GLB_REGFILE_INDEX_NOT_USED = 0,
179         BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID = 1,
180         BNXT_ULP_GLB_REGFILE_INDEX_GLB_L2_CNTXT_ID = 2,
181         BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR = 3,
182         BNXT_ULP_GLB_REGFILE_INDEX_LAST = 4
183 };
184
185 enum bnxt_ulp_hdr_type {
186         BNXT_ULP_HDR_TYPE_NOT_SUPPORTED = 0,
187         BNXT_ULP_HDR_TYPE_SUPPORTED = 1,
188         BNXT_ULP_HDR_TYPE_END = 2,
189         BNXT_ULP_HDR_TYPE_LAST = 3
190 };
191
192 enum bnxt_ulp_index_opcode {
193         BNXT_ULP_INDEX_OPCODE_NOT_USED = 0,
194         BNXT_ULP_INDEX_OPCODE_ALLOCATE = 1,
195         BNXT_ULP_INDEX_OPCODE_GLOBAL = 2,
196         BNXT_ULP_INDEX_OPCODE_COMP_FIELD = 3,
197         BNXT_ULP_INDEX_OPCODE_CONSTANT = 4,
198         BNXT_ULP_INDEX_OPCODE_LAST = 5
199 };
200
201 enum bnxt_ulp_mapper_opc {
202         BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT = 0,
203         BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD = 1,
204         BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD = 2,
205         BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE = 3,
206         BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE = 4,
207         BNXT_ULP_MAPPER_OPC_SET_TO_ZERO = 5,
208         BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT = 6,
209         BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP = 7,
210         BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ = 8,
211         BNXT_ULP_MAPPER_OPC_LAST = 9
212 };
213
214 enum bnxt_ulp_mark_db_opcode {
215         BNXT_ULP_MARK_DB_OPCODE_NOP = 0,
216         BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION = 1,
217         BNXT_ULP_MARK_DB_OPCODE_SET_VFR_FLAG = 2,
218         BNXT_ULP_MARK_DB_OPCODE_LAST = 3
219 };
220
221 enum bnxt_ulp_match_type {
222         BNXT_ULP_MATCH_TYPE_EM = 0,
223         BNXT_ULP_MATCH_TYPE_WM = 1,
224         BNXT_ULP_MATCH_TYPE_LAST = 2
225 };
226
227 enum bnxt_ulp_priority {
228         BNXT_ULP_PRIORITY_LEVEL_0 = 0,
229         BNXT_ULP_PRIORITY_LEVEL_1 = 1,
230         BNXT_ULP_PRIORITY_LEVEL_2 = 2,
231         BNXT_ULP_PRIORITY_LEVEL_3 = 3,
232         BNXT_ULP_PRIORITY_LEVEL_4 = 4,
233         BNXT_ULP_PRIORITY_LEVEL_5 = 5,
234         BNXT_ULP_PRIORITY_LEVEL_6 = 6,
235         BNXT_ULP_PRIORITY_LEVEL_7 = 7,
236         BNXT_ULP_PRIORITY_NOT_USED = 8,
237         BNXT_ULP_PRIORITY_LAST = 9
238 };
239
240 enum bnxt_ulp_regfile_index {
241         BNXT_ULP_REGFILE_INDEX_NOT_USED = 0,
242         BNXT_ULP_REGFILE_INDEX_CLASS_TID = 1,
243         BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 = 2,
244         BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_1 = 3,
245         BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_0 = 4,
246         BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_1 = 5,
247         BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 = 6,
248         BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_1 = 7,
249         BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 = 8,
250         BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_1 = 9,
251         BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR = 10,
252         BNXT_ULP_REGFILE_INDEX_ACTION_PTR_0 = 11,
253         BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 = 12,
254         BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_1 = 13,
255         BNXT_ULP_REGFILE_INDEX_CRITICAL_RESOURCE = 14,
256         BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 = 15,
257         BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR = 16,
258         BNXT_ULP_REGFILE_INDEX_LAST = 17
259 };
260
261 enum bnxt_ulp_search_before_alloc {
262         BNXT_ULP_SEARCH_BEFORE_ALLOC_NO = 0,
263         BNXT_ULP_SEARCH_BEFORE_ALLOC_YES = 1,
264         BNXT_ULP_SEARCH_BEFORE_ALLOC_LAST = 2
265 };
266
267 enum bnxt_ulp_fdb_resource_flags {
268         BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_INGR = 0x00,
269         BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_EGR = 0x01
270 };
271
272 enum bnxt_ulp_fdb_type {
273         BNXT_ULP_FDB_TYPE_REGULAR = 0,
274         BNXT_ULP_FDB_TYPE_DEFAULT = 1
275 };
276
277 enum bnxt_ulp_flow_dir_bitmask {
278         BNXT_ULP_FLOW_DIR_BITMASK_ING = 0x0000000000000000,
279         BNXT_ULP_FLOW_DIR_BITMASK_EGR = 0x8000000000000000
280 };
281
282 enum bnxt_ulp_match_type_bitmask {
283         BNXT_ULP_MATCH_TYPE_BITMASK_EM = 0x0000000000000000,
284         BNXT_ULP_MATCH_TYPE_BITMASK_WM = 0x0000000000000001
285 };
286
287 enum bnxt_ulp_resource_func {
288         BNXT_ULP_RESOURCE_FUNC_INVALID = 0x00,
289         BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE = 0x20,
290         BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE = 0x40,
291         BNXT_ULP_RESOURCE_FUNC_RSVD2 = 0x60,
292         BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE = 0x80,
293         BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE = 0x81,
294         BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE = 0x82,
295         BNXT_ULP_RESOURCE_FUNC_IDENTIFIER = 0x83,
296         BNXT_ULP_RESOURCE_FUNC_IF_TABLE = 0x84,
297         BNXT_ULP_RESOURCE_FUNC_HW_FID = 0x85
298 };
299
300 enum bnxt_ulp_resource_sub_type {
301         BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED = 0,
302         BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL = 0,
303         BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION = 1,
304         BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT = 2,
305         BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_EXT_COUNT = 3,
306         BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM = 0,
307         BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM = 1
308 };
309
310 enum bnxt_ulp_sym {
311         BNXT_ULP_SYM_PKT_TYPE_IGNORE = 0,
312         BNXT_ULP_SYM_PKT_TYPE_L2 = 0,
313         BNXT_ULP_SYM_RECYCLE_CNT_IGNORE = 0,
314         BNXT_ULP_SYM_RECYCLE_CNT_ZERO = 0,
315         BNXT_ULP_SYM_RECYCLE_CNT_ONE = 1,
316         BNXT_ULP_SYM_RECYCLE_CNT_TWO = 2,
317         BNXT_ULP_SYM_RECYCLE_CNT_THREE = 3,
318         BNXT_ULP_SYM_AGG_ERROR_IGNORE = 0,
319         BNXT_ULP_SYM_AGG_ERROR_NO = 0,
320         BNXT_ULP_SYM_AGG_ERROR_YES = 1,
321         BNXT_ULP_SYM_RESERVED_IGNORE = 0,
322         BNXT_ULP_SYM_HREC_NEXT_IGNORE = 0,
323         BNXT_ULP_SYM_HREC_NEXT_NO = 0,
324         BNXT_ULP_SYM_HREC_NEXT_YES = 1,
325         BNXT_ULP_SYM_TL2_HDR_VALID_IGNORE = 0,
326         BNXT_ULP_SYM_TL2_HDR_VALID_NO = 0,
327         BNXT_ULP_SYM_TL2_HDR_VALID_YES = 1,
328         BNXT_ULP_SYM_TL2_HDR_TYPE_IGNORE = 0,
329         BNXT_ULP_SYM_TL2_HDR_TYPE_DIX = 0,
330         BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE = 0,
331         BNXT_ULP_SYM_TL2_UC_MC_BC_UC = 0,
332         BNXT_ULP_SYM_TL2_UC_MC_BC_MC = 2,
333         BNXT_ULP_SYM_TL2_UC_MC_BC_BC = 3,
334         BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE = 0,
335         BNXT_ULP_SYM_TL2_VTAG_PRESENT_NO = 0,
336         BNXT_ULP_SYM_TL2_VTAG_PRESENT_YES = 1,
337         BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE = 0,
338         BNXT_ULP_SYM_TL2_TWO_VTAGS_NO = 0,
339         BNXT_ULP_SYM_TL2_TWO_VTAGS_YES = 1,
340         BNXT_ULP_SYM_TL3_HDR_VALID_IGNORE = 0,
341         BNXT_ULP_SYM_TL3_HDR_VALID_NO = 0,
342         BNXT_ULP_SYM_TL3_HDR_VALID_YES = 1,
343         BNXT_ULP_SYM_TL3_HDR_ERROR_IGNORE = 0,
344         BNXT_ULP_SYM_TL3_HDR_ERROR_NO = 0,
345         BNXT_ULP_SYM_TL3_HDR_ERROR_YES = 1,
346         BNXT_ULP_SYM_TL3_HDR_TYPE_IGNORE = 0,
347         BNXT_ULP_SYM_TL3_HDR_TYPE_IPV4 = 0,
348         BNXT_ULP_SYM_TL3_HDR_TYPE_IPV6 = 1,
349         BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE = 0,
350         BNXT_ULP_SYM_TL3_HDR_ISIP_NO = 0,
351         BNXT_ULP_SYM_TL3_HDR_ISIP_YES = 1,
352         BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE = 0,
353         BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_NO = 0,
354         BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_YES = 1,
355         BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE = 0,
356         BNXT_ULP_SYM_TL3_IPV6_CMP_DST_NO = 0,
357         BNXT_ULP_SYM_TL3_IPV6_CMP_DST_YES = 1,
358         BNXT_ULP_SYM_TL4_HDR_VALID_IGNORE = 0,
359         BNXT_ULP_SYM_TL4_HDR_VALID_NO = 0,
360         BNXT_ULP_SYM_TL4_HDR_VALID_YES = 1,
361         BNXT_ULP_SYM_TL4_HDR_ERROR_IGNORE = 0,
362         BNXT_ULP_SYM_TL4_HDR_ERROR_NO = 0,
363         BNXT_ULP_SYM_TL4_HDR_ERROR_YES = 1,
364         BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE = 0,
365         BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_NO = 0,
366         BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_YES = 1,
367         BNXT_ULP_SYM_TL4_HDR_TYPE_IGNORE = 0,
368         BNXT_ULP_SYM_TL4_HDR_TYPE_TCP = 0,
369         BNXT_ULP_SYM_TL4_HDR_TYPE_UDP = 1,
370         BNXT_ULP_SYM_TUN_HDR_VALID_IGNORE = 0,
371         BNXT_ULP_SYM_TUN_HDR_VALID_NO = 0,
372         BNXT_ULP_SYM_TUN_HDR_VALID_YES = 1,
373         BNXT_ULP_SYM_TUN_HDR_ERROR_IGNORE = 0,
374         BNXT_ULP_SYM_TUN_HDR_ERROR_NO = 0,
375         BNXT_ULP_SYM_TUN_HDR_ERROR_YES = 1,
376         BNXT_ULP_SYM_TUN_HDR_TYPE_IGNORE = 0,
377         BNXT_ULP_SYM_TUN_HDR_TYPE_VXLAN = 0,
378         BNXT_ULP_SYM_TUN_HDR_TYPE_GENEVE = 1,
379         BNXT_ULP_SYM_TUN_HDR_TYPE_NVGRE = 2,
380         BNXT_ULP_SYM_TUN_HDR_TYPE_GRE = 3,
381         BNXT_ULP_SYM_TUN_HDR_TYPE_IPV4 = 4,
382         BNXT_ULP_SYM_TUN_HDR_TYPE_IPV6 = 5,
383         BNXT_ULP_SYM_TUN_HDR_TYPE_PPPOE = 6,
384         BNXT_ULP_SYM_TUN_HDR_TYPE_MPLS = 7,
385         BNXT_ULP_SYM_TUN_HDR_TYPE_UPAR1 = 8,
386         BNXT_ULP_SYM_TUN_HDR_TYPE_UPAR2 = 9,
387         BNXT_ULP_SYM_TUN_HDR_TYPE_NONE = 15,
388         BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE = 0,
389         BNXT_ULP_SYM_L2_HDR_VALID_IGNORE = 0,
390         BNXT_ULP_SYM_L2_HDR_VALID_NO = 0,
391         BNXT_ULP_SYM_L2_HDR_VALID_YES = 1,
392         BNXT_ULP_SYM_L2_HDR_ERROR_IGNORE = 0,
393         BNXT_ULP_SYM_L2_HDR_ERROR_NO = 0,
394         BNXT_ULP_SYM_L2_HDR_ERROR_YES = 1,
395         BNXT_ULP_SYM_L2_HDR_TYPE_IGNORE = 0,
396         BNXT_ULP_SYM_L2_HDR_TYPE_DIX = 0,
397         BNXT_ULP_SYM_L2_HDR_TYPE_LLC_SNAP = 1,
398         BNXT_ULP_SYM_L2_HDR_TYPE_LLC = 2,
399         BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE = 0,
400         BNXT_ULP_SYM_L2_UC_MC_BC_UC = 0,
401         BNXT_ULP_SYM_L2_UC_MC_BC_MC = 2,
402         BNXT_ULP_SYM_L2_UC_MC_BC_BC = 3,
403         BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE = 0,
404         BNXT_ULP_SYM_L2_VTAG_PRESENT_NO = 0,
405         BNXT_ULP_SYM_L2_VTAG_PRESENT_YES = 1,
406         BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE = 0,
407         BNXT_ULP_SYM_L2_TWO_VTAGS_NO = 0,
408         BNXT_ULP_SYM_L2_TWO_VTAGS_YES = 1,
409         BNXT_ULP_SYM_L3_HDR_VALID_IGNORE = 0,
410         BNXT_ULP_SYM_L3_HDR_VALID_NO = 0,
411         BNXT_ULP_SYM_L3_HDR_VALID_YES = 1,
412         BNXT_ULP_SYM_L3_HDR_ERROR_IGNORE = 0,
413         BNXT_ULP_SYM_L3_HDR_ERROR_NO = 0,
414         BNXT_ULP_SYM_L3_HDR_ERROR_YES = 1,
415         BNXT_ULP_SYM_L3_HDR_TYPE_IGNORE = 0,
416         BNXT_ULP_SYM_L3_HDR_TYPE_IPV4 = 0,
417         BNXT_ULP_SYM_L3_HDR_TYPE_IPV6 = 1,
418         BNXT_ULP_SYM_L3_HDR_TYPE_ARP = 2,
419         BNXT_ULP_SYM_L3_HDR_TYPE_PTP = 3,
420         BNXT_ULP_SYM_L3_HDR_TYPE_EAPOL = 4,
421         BNXT_ULP_SYM_L3_HDR_TYPE_ROCE = 5,
422         BNXT_ULP_SYM_L3_HDR_TYPE_FCOE = 6,
423         BNXT_ULP_SYM_L3_HDR_TYPE_UPAR1 = 7,
424         BNXT_ULP_SYM_L3_HDR_TYPE_UPAR2 = 8,
425         BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE = 0,
426         BNXT_ULP_SYM_L3_HDR_ISIP_NO = 0,
427         BNXT_ULP_SYM_L3_HDR_ISIP_YES = 1,
428         BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE = 0,
429         BNXT_ULP_SYM_L3_IPV6_CMP_SRC_NO = 0,
430         BNXT_ULP_SYM_L3_IPV6_CMP_SRC_YES = 1,
431         BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE = 0,
432         BNXT_ULP_SYM_L3_IPV6_CMP_DST_NO = 0,
433         BNXT_ULP_SYM_L3_IPV6_CMP_DST_YES = 1,
434         BNXT_ULP_SYM_L4_HDR_VALID_IGNORE = 0,
435         BNXT_ULP_SYM_L4_HDR_VALID_NO = 0,
436         BNXT_ULP_SYM_L4_HDR_VALID_YES = 1,
437         BNXT_ULP_SYM_L4_HDR_ERROR_IGNORE = 0,
438         BNXT_ULP_SYM_L4_HDR_ERROR_NO = 0,
439         BNXT_ULP_SYM_L4_HDR_ERROR_YES = 1,
440         BNXT_ULP_SYM_L4_HDR_TYPE_IGNORE = 0,
441         BNXT_ULP_SYM_L4_HDR_TYPE_TCP = 0,
442         BNXT_ULP_SYM_L4_HDR_TYPE_UDP = 1,
443         BNXT_ULP_SYM_L4_HDR_TYPE_ICMP = 2,
444         BNXT_ULP_SYM_L4_HDR_TYPE_UPAR1 = 3,
445         BNXT_ULP_SYM_L4_HDR_TYPE_UPAR2 = 4,
446         BNXT_ULP_SYM_L4_HDR_TYPE_BTH_V1 = 5,
447         BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0,
448         BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_NO = 0,
449         BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_YES = 1,
450         BNXT_ULP_SYM_POP_VLAN_NO = 0,
451         BNXT_ULP_SYM_POP_VLAN_YES = 1,
452         BNXT_ULP_SYM_DECAP_FUNC_NONE = 0,
453         BNXT_ULP_SYM_DECAP_FUNC_THRU_TL2 = 3,
454         BNXT_ULP_SYM_DECAP_FUNC_THRU_TL3 = 8,
455         BNXT_ULP_SYM_DECAP_FUNC_THRU_TL4 = 9,
456         BNXT_ULP_SYM_DECAP_FUNC_THRU_TUN = 10,
457         BNXT_ULP_SYM_DECAP_FUNC_THRU_L2 = 11,
458         BNXT_ULP_SYM_DECAP_FUNC_THRU_L3 = 12,
459         BNXT_ULP_SYM_DECAP_FUNC_THRU_L4 = 13,
460         BNXT_ULP_SYM_ECV_VALID_NO = 0,
461         BNXT_ULP_SYM_ECV_VALID_YES = 1,
462         BNXT_ULP_SYM_ECV_CUSTOM_EN_NO = 0,
463         BNXT_ULP_SYM_ECV_CUSTOM_EN_YES = 1,
464         BNXT_ULP_SYM_ECV_L2_EN_NO = 0,
465         BNXT_ULP_SYM_ECV_L2_EN_YES = 1,
466         BNXT_ULP_SYM_ECV_VTAG_TYPE_NOP = 0,
467         BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI = 1,
468         BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_IVLAN_PRI = 2,
469         BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_REMAP_DIFFSERV = 3,
470         BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI = 4,
471         BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_REMAP_DIFFSERV = 5,
472         BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_ENCAP_PRI = 6,
473         BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_REMAP_DIFFSERV = 7,
474         BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_0 = 8,
475         BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_1 = 8,
476         BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_2 = 8,
477         BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_3 = 8,
478         BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_4 = 8,
479         BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_5 = 8,
480         BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_6 = 8,
481         BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_7 = 8,
482         BNXT_ULP_SYM_ECV_L3_TYPE_NONE = 0,
483         BNXT_ULP_SYM_ECV_L3_TYPE_IPV4 = 4,
484         BNXT_ULP_SYM_ECV_L3_TYPE_IPV6 = 5,
485         BNXT_ULP_SYM_ECV_L3_TYPE_MPLS_8847 = 6,
486         BNXT_ULP_SYM_ECV_L3_TYPE_MPLS_8848 = 7,
487         BNXT_ULP_SYM_ECV_L4_TYPE_NONE = 0,
488         BNXT_ULP_SYM_ECV_L4_TYPE_UDP = 4,
489         BNXT_ULP_SYM_ECV_L4_TYPE_UDP_CSUM = 5,
490         BNXT_ULP_SYM_ECV_L4_TYPE_UDP_ENTROPY = 6,
491         BNXT_ULP_SYM_ECV_L4_TYPE_UDP_ENTROPY_CSUM = 7,
492         BNXT_ULP_SYM_ECV_TUN_TYPE_NONE = 0,
493         BNXT_ULP_SYM_ECV_TUN_TYPE_GENERIC = 1,
494         BNXT_ULP_SYM_ECV_TUN_TYPE_VXLAN = 2,
495         BNXT_ULP_SYM_ECV_TUN_TYPE_NGE = 3,
496         BNXT_ULP_SYM_ECV_TUN_TYPE_NVGRE = 4,
497         BNXT_ULP_SYM_ECV_TUN_TYPE_GRE = 5,
498         BNXT_ULP_SYM_WH_PLUS_INT_ACT_REC = 1,
499         BNXT_ULP_SYM_WH_PLUS_EXT_ACT_REC = 0,
500         BNXT_ULP_SYM_WH_PLUS_UC_ACT_REC = 0,
501         BNXT_ULP_SYM_WH_PLUS_MC_ACT_REC = 1,
502         BNXT_ULP_SYM_ACT_REC_DROP_YES = 1,
503         BNXT_ULP_SYM_ACT_REC_DROP_NO = 0,
504         BNXT_ULP_SYM_ACT_REC_POP_VLAN_YES = 1,
505         BNXT_ULP_SYM_ACT_REC_POP_VLAN_NO = 0,
506         BNXT_ULP_SYM_ACT_REC_METER_EN_YES = 1,
507         BNXT_ULP_SYM_ACT_REC_METER_EN_NO = 0,
508         BNXT_ULP_SYM_WH_PLUS_LOOPBACK_PORT = 4,
509         BNXT_ULP_SYM_WH_PLUS_EXT_EM_MAX_KEY_SIZE = 448,
510         BNXT_ULP_SYM_STINGRAY_LOOPBACK_PORT = 16,
511         BNXT_ULP_SYM_STINGRAY_EXT_EM_MAX_KEY_SIZE = 448,
512         BNXT_ULP_SYM_STINGRAY2_LOOPBACK_PORT = 3,
513         BNXT_ULP_SYM_THOR_LOOPBACK_PORT = 3,
514         BNXT_ULP_SYM_MATCH_TYPE_EM = 0,
515         BNXT_ULP_SYM_MATCH_TYPE_WM = 1,
516         BNXT_ULP_SYM_IP_PROTO_ICMP = 1,
517         BNXT_ULP_SYM_IP_PROTO_IGMP = 2,
518         BNXT_ULP_SYM_IP_PROTO_IP_IN_IP = 4,
519         BNXT_ULP_SYM_IP_PROTO_TCP = 6,
520         BNXT_ULP_SYM_IP_PROTO_UDP = 17,
521         BNXT_ULP_SYM_VF_FUNC_PARIF = 15,
522         BNXT_ULP_SYM_NO = 0,
523         BNXT_ULP_SYM_YES = 1
524 };
525
526 enum bnxt_ulp_wh_plus {
527         BNXT_ULP_WH_PLUS_LOOPBACK_PORT = 4,
528         BNXT_ULP_WH_PLUS_EXT_EM_MAX_KEY_SIZE = 448
529 };
530
531 enum bnxt_ulp_act_prop_sz {
532         BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN_SZ = 4,
533         BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SZ = 4,
534         BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_SZ = 4,
535         BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_TYPE = 4,
536         BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_NUM = 4,
537         BNXT_ULP_ACT_PROP_SZ_ENCAP_L3_TYPE = 4,
538         BNXT_ULP_ACT_PROP_SZ_MPLS_POP_NUM = 4,
539         BNXT_ULP_ACT_PROP_SZ_MPLS_PUSH_NUM = 4,
540         BNXT_ULP_ACT_PROP_SZ_PORT_ID = 4,
541         BNXT_ULP_ACT_PROP_SZ_VNIC = 4,
542         BNXT_ULP_ACT_PROP_SZ_VPORT = 4,
543         BNXT_ULP_ACT_PROP_SZ_MARK = 4,
544         BNXT_ULP_ACT_PROP_SZ_COUNT = 4,
545         BNXT_ULP_ACT_PROP_SZ_METER = 4,
546         BNXT_ULP_ACT_PROP_SZ_SET_MAC_SRC = 8,
547         BNXT_ULP_ACT_PROP_SZ_SET_MAC_DST = 8,
548         BNXT_ULP_ACT_PROP_SZ_PUSH_VLAN = 2,
549         BNXT_ULP_ACT_PROP_SZ_SET_VLAN_PCP = 1,
550         BNXT_ULP_ACT_PROP_SZ_SET_VLAN_VID = 2,
551         BNXT_ULP_ACT_PROP_SZ_SET_IPV4_SRC = 4,
552         BNXT_ULP_ACT_PROP_SZ_SET_IPV4_DST = 4,
553         BNXT_ULP_ACT_PROP_SZ_SET_IPV6_SRC = 16,
554         BNXT_ULP_ACT_PROP_SZ_SET_IPV6_DST = 16,
555         BNXT_ULP_ACT_PROP_SZ_SET_TP_SRC = 4,
556         BNXT_ULP_ACT_PROP_SZ_SET_TP_DST = 4,
557         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_0 = 4,
558         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_1 = 4,
559         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_2 = 4,
560         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_3 = 4,
561         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_4 = 4,
562         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_5 = 4,
563         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_6 = 4,
564         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_7 = 4,
565         BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_DMAC = 6,
566         BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_SMAC = 6,
567         BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG = 8,
568         BNXT_ULP_ACT_PROP_SZ_ENCAP_IP = 32,
569         BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SRC = 16,
570         BNXT_ULP_ACT_PROP_SZ_ENCAP_UDP = 4,
571         BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN = 32,
572         BNXT_ULP_ACT_PROP_SZ_LAST = 4
573 };
574
575 enum bnxt_ulp_act_prop_idx {
576         BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ = 0,
577         BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ = 4,
578         BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ = 8,
579         BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE = 12,
580         BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_NUM = 16,
581         BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE = 20,
582         BNXT_ULP_ACT_PROP_IDX_MPLS_POP_NUM = 24,
583         BNXT_ULP_ACT_PROP_IDX_MPLS_PUSH_NUM = 28,
584         BNXT_ULP_ACT_PROP_IDX_PORT_ID = 32,
585         BNXT_ULP_ACT_PROP_IDX_VNIC = 36,
586         BNXT_ULP_ACT_PROP_IDX_VPORT = 40,
587         BNXT_ULP_ACT_PROP_IDX_MARK = 44,
588         BNXT_ULP_ACT_PROP_IDX_COUNT = 48,
589         BNXT_ULP_ACT_PROP_IDX_METER = 52,
590         BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC = 56,
591         BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST = 64,
592         BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN = 72,
593         BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP = 74,
594         BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID = 75,
595         BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC = 77,
596         BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST = 81,
597         BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC = 85,
598         BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST = 101,
599         BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC = 117,
600         BNXT_ULP_ACT_PROP_IDX_SET_TP_DST = 121,
601         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_0 = 125,
602         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_1 = 129,
603         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_2 = 133,
604         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_3 = 137,
605         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_4 = 141,
606         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_5 = 145,
607         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_6 = 149,
608         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_7 = 153,
609         BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC = 157,
610         BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC = 163,
611         BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG = 169,
612         BNXT_ULP_ACT_PROP_IDX_ENCAP_IP = 177,
613         BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC = 209,
614         BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP = 225,
615         BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN = 229,
616         BNXT_ULP_ACT_PROP_IDX_LAST = 261
617 };
618
619 enum bnxt_ulp_class_hid {
620         BNXT_ULP_CLASS_HID_0080 = 0x0080,
621         BNXT_ULP_CLASS_HID_0087 = 0x0087,
622         BNXT_ULP_CLASS_HID_0000 = 0x0000
623 };
624
625 enum bnxt_ulp_act_hid {
626         BNXT_ULP_ACT_HID_0002 = 0x0002,
627         BNXT_ULP_ACT_HID_0022 = 0x0022,
628         BNXT_ULP_ACT_HID_0026 = 0x0026,
629         BNXT_ULP_ACT_HID_0006 = 0x0006,
630         BNXT_ULP_ACT_HID_0009 = 0x0009,
631         BNXT_ULP_ACT_HID_0029 = 0x0029,
632         BNXT_ULP_ACT_HID_002d = 0x002d,
633         BNXT_ULP_ACT_HID_004b = 0x004b,
634         BNXT_ULP_ACT_HID_004a = 0x004a,
635         BNXT_ULP_ACT_HID_004f = 0x004f,
636         BNXT_ULP_ACT_HID_004e = 0x004e,
637         BNXT_ULP_ACT_HID_006c = 0x006c,
638         BNXT_ULP_ACT_HID_0070 = 0x0070,
639         BNXT_ULP_ACT_HID_0021 = 0x0021,
640         BNXT_ULP_ACT_HID_0025 = 0x0025,
641         BNXT_ULP_ACT_HID_0043 = 0x0043,
642         BNXT_ULP_ACT_HID_0042 = 0x0042,
643         BNXT_ULP_ACT_HID_0047 = 0x0047,
644         BNXT_ULP_ACT_HID_0046 = 0x0046,
645         BNXT_ULP_ACT_HID_0064 = 0x0064,
646         BNXT_ULP_ACT_HID_0068 = 0x0068,
647         BNXT_ULP_ACT_HID_00a1 = 0x00a1,
648         BNXT_ULP_ACT_HID_00df = 0x00df
649 };
650
651 enum bnxt_ulp_df_tpl {
652         BNXT_ULP_DF_TPL_PORT_TO_VS = 1,
653         BNXT_ULP_DF_TPL_VS_TO_PORT = 2,
654         BNXT_ULP_DF_TPL_VFREP_TO_VF = 3,
655         BNXT_ULP_DF_TPL_VF_TO_VFREP = 4,
656         BNXT_ULP_DF_TPL_DRV_FUNC_SVIF_PUSH_VLAN = 5,
657         BNXT_ULP_DF_TPL_PORT_SVIF_VID_VNIC_POP_VLAN = 6,
658         BNXT_ULP_DF_TPL_LOOPBACK_ACTION_REC = 7
659 };
660
661 #endif