drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2020 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #ifndef ULP_TEMPLATE_DB_H_
   7 #define ULP_TEMPLATE_DB_H_
   8
   9 #define BNXT_ULP_REGFILE_MAX_SZ 15
  10 #define BNXT_ULP_MAX_NUM_DEVICES 4
  11 #define BNXT_ULP_LOG2_MAX_NUM_DEV 2
  12 #define BNXT_ULP_CACHE_TBL_MAX_SZ 4
  13 #define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 256
  14 #define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 4
  15 #define BNXT_ULP_CLASS_HID_LOW_PRIME 7919
  16 #define BNXT_ULP_CLASS_HID_HIGH_PRIME 7907
  17 #define BNXT_ULP_CLASS_HID_SHFTR 16
  18 #define BNXT_ULP_CLASS_HID_SHFTL 23
  19 #define BNXT_ULP_CLASS_HID_MASK 255
  20 #define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 256
  21 #define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 4
  22 #define BNXT_ULP_ACT_HID_LOW_PRIME 7919
  23 #define BNXT_ULP_ACT_HID_HIGH_PRIME 7919
  24 #define BNXT_ULP_ACT_HID_SHFTR 0
  25 #define BNXT_ULP_ACT_HID_SHFTL 23
  26 #define BNXT_ULP_ACT_HID_MASK 255
  27 #define BNXT_ULP_CACHE_TBL_IDENT_MAX_NUM 2
  28 #define BNXT_ULP_GLB_RESOURCE_INFO_TBL_MAX_SZ 2
  29
  30 enum bnxt_ulp_action_bit {
  31         BNXT_ULP_ACTION_BIT_MARK             = 0x0000000000000001,
  32         BNXT_ULP_ACTION_BIT_DROP             = 0x0000000000000002,
  33         BNXT_ULP_ACTION_BIT_COUNT            = 0x0000000000000004,
  34         BNXT_ULP_ACTION_BIT_RSS              = 0x0000000000000008,
  35         BNXT_ULP_ACTION_BIT_METER            = 0x0000000000000010,
  36         BNXT_ULP_ACTION_BIT_VNIC             = 0x0000000000000020,
  37         BNXT_ULP_ACTION_BIT_VPORT            = 0x0000000000000040,
  38         BNXT_ULP_ACTION_BIT_VXLAN_DECAP      = 0x0000000000000080,
  39         BNXT_ULP_ACTION_BIT_NVGRE_DECAP      = 0x0000000000000100,
  40         BNXT_ULP_ACTION_BIT_POP_MPLS         = 0x0000000000000200,
  41         BNXT_ULP_ACTION_BIT_PUSH_MPLS        = 0x0000000000000400,
  42         BNXT_ULP_ACTION_BIT_MAC_SWAP         = 0x0000000000000800,
  43         BNXT_ULP_ACTION_BIT_SET_MAC_SRC      = 0x0000000000001000,
  44         BNXT_ULP_ACTION_BIT_SET_MAC_DST      = 0x0000000000002000,
  45         BNXT_ULP_ACTION_BIT_POP_VLAN         = 0x0000000000004000,
  46         BNXT_ULP_ACTION_BIT_PUSH_VLAN        = 0x0000000000008000,
  47         BNXT_ULP_ACTION_BIT_SET_VLAN_PCP     = 0x0000000000010000,
  48         BNXT_ULP_ACTION_BIT_SET_VLAN_VID     = 0x0000000000020000,
  49         BNXT_ULP_ACTION_BIT_SET_IPV4_SRC     = 0x0000000000040000,
  50         BNXT_ULP_ACTION_BIT_SET_IPV4_DST     = 0x0000000000080000,
  51         BNXT_ULP_ACTION_BIT_SET_IPV6_SRC     = 0x0000000000100000,
  52         BNXT_ULP_ACTION_BIT_SET_IPV6_DST     = 0x0000000000200000,
  53         BNXT_ULP_ACTION_BIT_DEC_TTL          = 0x0000000000400000,
  54         BNXT_ULP_ACTION_BIT_SET_TP_SRC       = 0x0000000000800000,
  55         BNXT_ULP_ACTION_BIT_SET_TP_DST       = 0x0000000001000000,
  56         BNXT_ULP_ACTION_BIT_VXLAN_ENCAP      = 0x0000000002000000,
  57         BNXT_ULP_ACTION_BIT_NVGRE_ENCAP      = 0x0000000004000000,
  58         BNXT_ULP_ACTION_BIT_LAST             = 0x0000000008000000
  59 };
  60
  61 enum bnxt_ulp_hdr_bit {
  62         BNXT_ULP_HDR_BIT_O_ETH               = 0x0000000000000001,
  63         BNXT_ULP_HDR_BIT_O_IPV4              = 0x0000000000000002,
  64         BNXT_ULP_HDR_BIT_O_IPV6              = 0x0000000000000004,
  65         BNXT_ULP_HDR_BIT_O_TCP               = 0x0000000000000008,
  66         BNXT_ULP_HDR_BIT_O_UDP               = 0x0000000000000010,
  67         BNXT_ULP_HDR_BIT_T_VXLAN             = 0x0000000000000020,
  68         BNXT_ULP_HDR_BIT_T_GRE               = 0x0000000000000040,
  69         BNXT_ULP_HDR_BIT_I_ETH               = 0x0000000000000080,
  70         BNXT_ULP_HDR_BIT_I_IPV4              = 0x0000000000000100,
  71         BNXT_ULP_HDR_BIT_I_IPV6              = 0x0000000000000200,
  72         BNXT_ULP_HDR_BIT_I_TCP               = 0x0000000000000400,
  73         BNXT_ULP_HDR_BIT_I_UDP               = 0x0000000000000800,
  74         BNXT_ULP_HDR_BIT_LAST                = 0x0000000000001000
  75 };
  76
  77 enum bnxt_ulp_act_type {
  78         BNXT_ULP_ACT_TYPE_NOT_SUPPORTED = 0,
  79         BNXT_ULP_ACT_TYPE_SUPPORTED = 1,
  80         BNXT_ULP_ACT_TYPE_END = 2,
  81         BNXT_ULP_ACT_TYPE_LAST = 3
  82 };
  83
  84 enum bnxt_ulp_byte_order {
  85         BNXT_ULP_BYTE_ORDER_BE = 0,
  86         BNXT_ULP_BYTE_ORDER_LE = 1,
  87         BNXT_ULP_BYTE_ORDER_LAST = 2
  88 };
  89
  90 enum bnxt_ulp_cf_idx {
  91         BNXT_ULP_CF_IDX_MPLS_TAG_NUM = 0,
  92         BNXT_ULP_CF_IDX_O_VTAG_NUM = 1,
  93         BNXT_ULP_CF_IDX_O_VTAG_PRESENT = 2,
  94         BNXT_ULP_CF_IDX_O_TWO_VTAGS = 3,
  95         BNXT_ULP_CF_IDX_I_VTAG_NUM = 4,
  96         BNXT_ULP_CF_IDX_I_VTAG_PRESENT = 5,
  97         BNXT_ULP_CF_IDX_I_TWO_VTAGS = 6,
  98         BNXT_ULP_CF_IDX_INCOMING_IF = 7,
  99         BNXT_ULP_CF_IDX_DIRECTION = 8,
 100         BNXT_ULP_CF_IDX_SVIF_FLAG = 9,
 101         BNXT_ULP_CF_IDX_O_L3 = 10,
 102         BNXT_ULP_CF_IDX_I_L3 = 11,
 103         BNXT_ULP_CF_IDX_O_L4 = 12,
 104         BNXT_ULP_CF_IDX_I_L4 = 13,
 105         BNXT_ULP_CF_IDX_DEV_PORT_ID = 14,
 106         BNXT_ULP_CF_IDX_DRV_FUNC_SVIF = 15,
 107         BNXT_ULP_CF_IDX_DRV_FUNC_SPIF = 16,
 108         BNXT_ULP_CF_IDX_DRV_FUNC_PARIF = 17,
 109         BNXT_ULP_CF_IDX_DRV_FUNC_VNIC = 18,
 110         BNXT_ULP_CF_IDX_DRV_FUNC_PHY_PORT = 19,
 111         BNXT_ULP_CF_IDX_VF_FUNC_SVIF = 20,
 112         BNXT_ULP_CF_IDX_VF_FUNC_SPIF = 21,
 113         BNXT_ULP_CF_IDX_VF_FUNC_PARIF = 22,
 114         BNXT_ULP_CF_IDX_VF_FUNC_VNIC = 23,
 115         BNXT_ULP_CF_IDX_PHY_PORT_SVIF = 24,
 116         BNXT_ULP_CF_IDX_PHY_PORT_SPIF = 25,
 117         BNXT_ULP_CF_IDX_PHY_PORT_PARIF = 26,
 118         BNXT_ULP_CF_IDX_PHY_PORT_VPORT = 27,
 119         BNXT_ULP_CF_IDX_LAST = 28
 120 };
 121
 122 enum bnxt_ulp_critical_resource {
 123         BNXT_ULP_CRITICAL_RESOURCE_NO = 0,
 124         BNXT_ULP_CRITICAL_RESOURCE_YES = 1,
 125         BNXT_ULP_CRITICAL_RESOURCE_LAST = 2
 126 };
 127
 128 enum bnxt_ulp_device_id {
 129         BNXT_ULP_DEVICE_ID_WH_PLUS = 0,
 130         BNXT_ULP_DEVICE_ID_THOR = 1,
 131         BNXT_ULP_DEVICE_ID_STINGRAY = 2,
 132         BNXT_ULP_DEVICE_ID_STINGRAY2 = 3,
 133         BNXT_ULP_DEVICE_ID_LAST = 4
 134 };
 135
 136 enum bnxt_ulp_direction {
 137         BNXT_ULP_DIRECTION_INGRESS = 0,
 138         BNXT_ULP_DIRECTION_EGRESS = 1,
 139         BNXT_ULP_DIRECTION_LAST = 2
 140 };
 141
 142 enum bnxt_ulp_flow_mem_type {
 143         BNXT_ULP_FLOW_MEM_TYPE_INT = 0,
 144         BNXT_ULP_FLOW_MEM_TYPE_EXT = 1,
 145         BNXT_ULP_FLOW_MEM_TYPE_BOTH = 2,
 146         BNXT_ULP_FLOW_MEM_TYPE_LAST = 3
 147 };
 148
 149 enum bnxt_ulp_glb_regfile_index {
 150         BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID = 0,
 151         BNXT_ULP_GLB_REGFILE_INDEX_LAST = 1
 152 };
 153
 154 enum bnxt_ulp_hdr_type {
 155         BNXT_ULP_HDR_TYPE_NOT_SUPPORTED = 0,
 156         BNXT_ULP_HDR_TYPE_SUPPORTED = 1,
 157         BNXT_ULP_HDR_TYPE_END = 2,
 158         BNXT_ULP_HDR_TYPE_LAST = 3
 159 };
 160
 161 enum bnxt_ulp_mark_db_opcode {
 162         BNXT_ULP_MARK_DB_OPCODE_NOP = 0,
 163         BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION = 1,
 164         BNXT_ULP_MARK_DB_OPCODE_SET_VFR_FLAG = 2,
 165         BNXT_ULP_MARK_DB_OPCODE_LAST = 3
 166 };
 167
 168 enum bnxt_ulp_mapper_opc {
 169         BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT = 0,
 170         BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD = 1,
 171         BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD = 2,
 172         BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE = 3,
 173         BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE = 4,
 174         BNXT_ULP_MAPPER_OPC_SET_TO_ZERO = 5,
 175         BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT = 6,
 176         BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP = 7,
 177         BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ = 8,
 178         BNXT_ULP_MAPPER_OPC_LAST = 9
 179 };
 180
 181 enum bnxt_ulp_match_type {
 182         BNXT_ULP_MATCH_TYPE_EM = 0,
 183         BNXT_ULP_MATCH_TYPE_WC = 1,
 184         BNXT_ULP_MATCH_TYPE_LAST = 2
 185 };
 186
 187 enum bnxt_ulp_priority {
 188         BNXT_ULP_PRIORITY_LEVEL_0 = 0,
 189         BNXT_ULP_PRIORITY_LEVEL_1 = 1,
 190         BNXT_ULP_PRIORITY_LEVEL_2 = 2,
 191         BNXT_ULP_PRIORITY_LEVEL_3 = 3,
 192         BNXT_ULP_PRIORITY_LEVEL_4 = 4,
 193         BNXT_ULP_PRIORITY_LEVEL_5 = 5,
 194         BNXT_ULP_PRIORITY_LEVEL_6 = 6,
 195         BNXT_ULP_PRIORITY_LEVEL_7 = 7,
 196         BNXT_ULP_PRIORITY_NOT_USED = 8,
 197         BNXT_ULP_PRIORITY_LAST = 9
 198 };
 199
 200 enum bnxt_ulp_regfile_index {
 201         BNXT_ULP_REGFILE_INDEX_CLASS_TID = 0,
 202         BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 = 1,
 203         BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_1 = 2,
 204         BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_0 = 3,
 205         BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_1 = 4,
 206         BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 = 5,
 207         BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_1 = 6,
 208         BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 = 7,
 209         BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_1 = 8,
 210         BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR = 9,
 211         BNXT_ULP_REGFILE_INDEX_ACTION_PTR_0 = 10,
 212         BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 = 11,
 213         BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_1 = 12,
 214         BNXT_ULP_REGFILE_INDEX_CRITICAL_RESOURCE = 13,
 215         BNXT_ULP_REGFILE_INDEX_NOT_USED = 14,
 216         BNXT_ULP_REGFILE_INDEX_LAST = 15
 217 };
 218
 219 enum bnxt_ulp_search_before_alloc {
 220         BNXT_ULP_SEARCH_BEFORE_ALLOC_NO = 0,
 221         BNXT_ULP_SEARCH_BEFORE_ALLOC_YES = 1,
 222         BNXT_ULP_SEARCH_BEFORE_ALLOC_LAST = 2
 223 };
 224
 225 enum bnxt_ulp_fdb_resource_flags {
 226         BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_EGR = 0x01,
 227         BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_INGR = 0x00
 228 };
 229
 230 enum bnxt_ulp_fdb_type {
 231         BNXT_ULP_FDB_TYPE_DEFAULT = 1,
 232         BNXT_ULP_FDB_TYPE_REGULAR = 0
 233 };
 234
 235 enum bnxt_ulp_flow_dir_bitmask {
 236         BNXT_ULP_FLOW_DIR_BITMASK_EGR = 0x8000000000000000,
 237         BNXT_ULP_FLOW_DIR_BITMASK_ING = 0x0000000000000000
 238 };
 239
 240 enum bnxt_ulp_match_type_bitmask {
 241         BNXT_ULP_MATCH_TYPE_BITMASK_EM = 0x0000000000000000,
 242         BNXT_ULP_MATCH_TYPE_BITMASK_WM = 0x0000000000000001
 243 };
 244
 245 enum bnxt_ulp_resource_func {
 246         BNXT_ULP_RESOURCE_FUNC_INVALID = 0x00,
 247         BNXT_ULP_RESOURCE_FUNC_EM_TABLE = 0x20,
 248         BNXT_ULP_RESOURCE_FUNC_RSVD1 = 0x40,
 249         BNXT_ULP_RESOURCE_FUNC_RSVD2 = 0x60,
 250         BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE = 0x80,
 251         BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE = 0x81,
 252         BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE = 0x82,
 253         BNXT_ULP_RESOURCE_FUNC_IDENTIFIER = 0x83,
 254         BNXT_ULP_RESOURCE_FUNC_IF_TABLE = 0x84,
 255         BNXT_ULP_RESOURCE_FUNC_HW_FID = 0x85
 256 };
 257
 258 enum bnxt_ulp_resource_sub_type {
 259         BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM = 0,
 260         BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM = 1,
 261         BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_EXT_CNT_IDX = 3,
 262         BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_CNT_IDX = 2,
 263         BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL = 0,
 264         BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_ACT_IDX = 1,
 265         BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED = 0
 266 };
 267
 268 enum bnxt_ulp_sym {
 269         BNXT_ULP_SYM_AGG_ERROR_IGNORE = 0,
 270         BNXT_ULP_SYM_AGG_ERROR_NO = 0,
 271         BNXT_ULP_SYM_AGG_ERROR_YES = 1,
 272         BNXT_ULP_SYM_BIG_ENDIAN = 0,
 273         BNXT_ULP_SYM_DECAP_FUNC_NONE = 0,
 274         BNXT_ULP_SYM_DECAP_FUNC_THRU_L2 = 11,
 275         BNXT_ULP_SYM_DECAP_FUNC_THRU_L3 = 12,
 276         BNXT_ULP_SYM_DECAP_FUNC_THRU_L4 = 13,
 277         BNXT_ULP_SYM_DECAP_FUNC_THRU_TL2 = 3,
 278         BNXT_ULP_SYM_DECAP_FUNC_THRU_TL3 = 8,
 279         BNXT_ULP_SYM_DECAP_FUNC_THRU_TL4 = 9,
 280         BNXT_ULP_SYM_DECAP_FUNC_THRU_TUN = 10,
 281         BNXT_ULP_SYM_ECV_CUSTOM_EN_NO = 0,
 282         BNXT_ULP_SYM_ECV_CUSTOM_EN_YES = 1,
 283         BNXT_ULP_SYM_ECV_L2_EN_NO = 0,
 284         BNXT_ULP_SYM_ECV_L2_EN_YES = 1,
 285         BNXT_ULP_SYM_ECV_L3_TYPE_IPV4 = 4,
 286         BNXT_ULP_SYM_ECV_L3_TYPE_IPV6 = 5,
 287         BNXT_ULP_SYM_ECV_L3_TYPE_MPLS_8847 = 6,
 288         BNXT_ULP_SYM_ECV_L3_TYPE_MPLS_8848 = 7,
 289         BNXT_ULP_SYM_ECV_L3_TYPE_NONE = 0,
 290         BNXT_ULP_SYM_ECV_L4_TYPE_NONE = 0,
 291         BNXT_ULP_SYM_ECV_L4_TYPE_UDP = 4,
 292         BNXT_ULP_SYM_ECV_L4_TYPE_UDP_CSUM = 5,
 293         BNXT_ULP_SYM_ECV_L4_TYPE_UDP_ENTROPY = 6,
 294         BNXT_ULP_SYM_ECV_L4_TYPE_UDP_ENTROPY_CSUM = 7,
 295         BNXT_ULP_SYM_ECV_TUN_TYPE_GENERIC = 1,
 296         BNXT_ULP_SYM_ECV_TUN_TYPE_GRE = 5,
 297         BNXT_ULP_SYM_ECV_TUN_TYPE_NGE = 3,
 298         BNXT_ULP_SYM_ECV_TUN_TYPE_NONE = 0,
 299         BNXT_ULP_SYM_ECV_TUN_TYPE_NVGRE = 4,
 300         BNXT_ULP_SYM_ECV_TUN_TYPE_VXLAN = 2,
 301         BNXT_ULP_SYM_ECV_VALID_NO = 0,
 302         BNXT_ULP_SYM_ECV_VALID_YES = 1,
 303         BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_ENCAP_PRI = 6,
 304         BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_0 = 8,
 305         BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_1 = 8,
 306         BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_2 = 8,
 307         BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_3 = 8,
 308         BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_4 = 8,
 309         BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_5 = 8,
 310         BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_6 = 8,
 311         BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_7 = 8,
 312         BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_REMAP_DIFFSERV = 7,
 313         BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI = 1,
 314         BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_IVLAN_PRI = 2,
 315         BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_REMAP_DIFFSERV = 3,
 316         BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI = 4,
 317         BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_REMAP_DIFFSERV = 5,
 318         BNXT_ULP_SYM_ECV_VTAG_TYPE_NOP = 0,
 319         BNXT_ULP_SYM_HREC_NEXT_IGNORE = 0,
 320         BNXT_ULP_SYM_HREC_NEXT_NO = 0,
 321         BNXT_ULP_SYM_HREC_NEXT_YES = 1,
 322         BNXT_ULP_SYM_IP_PROTO_ICMP = 1,
 323         BNXT_ULP_SYM_IP_PROTO_IGMP = 2,
 324         BNXT_ULP_SYM_IP_PROTO_IP_IN_IP = 4,
 325         BNXT_ULP_SYM_IP_PROTO_TCP = 6,
 326         BNXT_ULP_SYM_IP_PROTO_UDP = 17,
 327         BNXT_ULP_SYM_L2_HDR_ERROR_IGNORE = 0,
 328         BNXT_ULP_SYM_L2_HDR_ERROR_NO = 0,
 329         BNXT_ULP_SYM_L2_HDR_ERROR_YES = 1,
 330         BNXT_ULP_SYM_L2_HDR_TYPE_DIX = 0,
 331         BNXT_ULP_SYM_L2_HDR_TYPE_IGNORE = 0,
 332         BNXT_ULP_SYM_L2_HDR_TYPE_LLC = 2,
 333         BNXT_ULP_SYM_L2_HDR_TYPE_LLC_SNAP = 1,
 334         BNXT_ULP_SYM_L2_HDR_VALID_IGNORE = 0,
 335         BNXT_ULP_SYM_L2_HDR_VALID_NO = 0,
 336         BNXT_ULP_SYM_L2_HDR_VALID_YES = 1,
 337         BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE = 0,
 338         BNXT_ULP_SYM_L2_TWO_VTAGS_NO = 0,
 339         BNXT_ULP_SYM_L2_TWO_VTAGS_YES = 1,
 340         BNXT_ULP_SYM_L2_UC_MC_BC_BC = 3,
 341         BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE = 0,
 342         BNXT_ULP_SYM_L2_UC_MC_BC_MC = 2,
 343         BNXT_ULP_SYM_L2_UC_MC_BC_UC = 0,
 344         BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE = 0,
 345         BNXT_ULP_SYM_L2_VTAG_PRESENT_NO = 0,
 346         BNXT_ULP_SYM_L2_VTAG_PRESENT_YES = 1,
 347         BNXT_ULP_SYM_L3_HDR_ERROR_IGNORE = 0,
 348         BNXT_ULP_SYM_L3_HDR_ERROR_NO = 0,
 349         BNXT_ULP_SYM_L3_HDR_ERROR_YES = 1,
 350         BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE = 0,
 351         BNXT_ULP_SYM_L3_HDR_ISIP_NO = 0,
 352         BNXT_ULP_SYM_L3_HDR_ISIP_YES = 1,
 353         BNXT_ULP_SYM_L3_HDR_TYPE_ARP = 2,
 354         BNXT_ULP_SYM_L3_HDR_TYPE_EAPOL = 4,
 355         BNXT_ULP_SYM_L3_HDR_TYPE_FCOE = 6,
 356         BNXT_ULP_SYM_L3_HDR_TYPE_IGNORE = 0,
 357         BNXT_ULP_SYM_L3_HDR_TYPE_IPV4 = 0,
 358         BNXT_ULP_SYM_L3_HDR_TYPE_IPV6 = 1,
 359         BNXT_ULP_SYM_L3_HDR_TYPE_PTP = 3,
 360         BNXT_ULP_SYM_L3_HDR_TYPE_ROCE = 5,
 361         BNXT_ULP_SYM_L3_HDR_TYPE_UPAR1 = 7,
 362         BNXT_ULP_SYM_L3_HDR_TYPE_UPAR2 = 8,
 363         BNXT_ULP_SYM_L3_HDR_VALID_IGNORE = 0,
 364         BNXT_ULP_SYM_L3_HDR_VALID_NO = 0,
 365         BNXT_ULP_SYM_L3_HDR_VALID_YES = 1,
 366         BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE = 0,
 367         BNXT_ULP_SYM_L3_IPV6_CMP_DST_NO = 0,
 368         BNXT_ULP_SYM_L3_IPV6_CMP_DST_YES = 1,
 369         BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE = 0,
 370         BNXT_ULP_SYM_L3_IPV6_CMP_SRC_NO = 0,
 371         BNXT_ULP_SYM_L3_IPV6_CMP_SRC_YES = 1,
 372         BNXT_ULP_SYM_L4_HDR_ERROR_IGNORE = 0,
 373         BNXT_ULP_SYM_L4_HDR_ERROR_NO = 0,
 374         BNXT_ULP_SYM_L4_HDR_ERROR_YES = 1,
 375         BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0,
 376         BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_NO = 0,
 377         BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_YES = 1,
 378         BNXT_ULP_SYM_L4_HDR_TYPE_BTH_V1 = 5,
 379         BNXT_ULP_SYM_L4_HDR_TYPE_ICMP = 2,
 380         BNXT_ULP_SYM_L4_HDR_TYPE_IGNORE = 0,
 381         BNXT_ULP_SYM_L4_HDR_TYPE_TCP = 0,
 382         BNXT_ULP_SYM_L4_HDR_TYPE_UDP = 1,
 383         BNXT_ULP_SYM_L4_HDR_TYPE_UPAR1 = 3,
 384         BNXT_ULP_SYM_L4_HDR_TYPE_UPAR2 = 4,
 385         BNXT_ULP_SYM_L4_HDR_VALID_IGNORE = 0,
 386         BNXT_ULP_SYM_L4_HDR_VALID_NO = 0,
 387         BNXT_ULP_SYM_L4_HDR_VALID_YES = 1,
 388         BNXT_ULP_SYM_LITTLE_ENDIAN = 1,
 389         BNXT_ULP_SYM_MATCH_TYPE_EM = 0,
 390         BNXT_ULP_SYM_MATCH_TYPE_WM = 1,
 391         BNXT_ULP_SYM_NO = 0,
 392         BNXT_ULP_SYM_PKT_TYPE_IGNORE = 0,
 393         BNXT_ULP_SYM_PKT_TYPE_L2 = 0,
 394         BNXT_ULP_SYM_POP_VLAN_NO = 0,
 395         BNXT_ULP_SYM_POP_VLAN_YES = 1,
 396         BNXT_ULP_SYM_RECYCLE_CNT_IGNORE = 0,
 397         BNXT_ULP_SYM_RECYCLE_CNT_ONE = 1,
 398         BNXT_ULP_SYM_RECYCLE_CNT_THREE = 3,
 399         BNXT_ULP_SYM_RECYCLE_CNT_TWO = 2,
 400         BNXT_ULP_SYM_RECYCLE_CNT_ZERO = 0,
 401         BNXT_ULP_SYM_RESERVED_IGNORE = 0,
 402         BNXT_ULP_SYM_STINGRAY2_LOOPBACK_PORT = 3,
 403         BNXT_ULP_SYM_STINGRAY_LOOPBACK_PORT = 3,
 404         BNXT_ULP_SYM_THOR_LOOPBACK_PORT = 3,
 405         BNXT_ULP_SYM_TL2_HDR_TYPE_DIX = 0,
 406         BNXT_ULP_SYM_TL2_HDR_TYPE_IGNORE = 0,
 407         BNXT_ULP_SYM_TL2_HDR_VALID_IGNORE = 0,
 408         BNXT_ULP_SYM_TL2_HDR_VALID_NO = 0,
 409         BNXT_ULP_SYM_TL2_HDR_VALID_YES = 1,
 410         BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE = 0,
 411         BNXT_ULP_SYM_TL2_TWO_VTAGS_NO = 0,
 412         BNXT_ULP_SYM_TL2_TWO_VTAGS_YES = 1,
 413         BNXT_ULP_SYM_TL2_UC_MC_BC_BC = 3,
 414         BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE = 0,
 415         BNXT_ULP_SYM_TL2_UC_MC_BC_MC = 2,
 416         BNXT_ULP_SYM_TL2_UC_MC_BC_UC = 0,
 417         BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE = 0,
 418         BNXT_ULP_SYM_TL2_VTAG_PRESENT_NO = 0,
 419         BNXT_ULP_SYM_TL2_VTAG_PRESENT_YES = 1,
 420         BNXT_ULP_SYM_TL3_HDR_ERROR_IGNORE = 0,
 421         BNXT_ULP_SYM_TL3_HDR_ERROR_NO = 0,
 422         BNXT_ULP_SYM_TL3_HDR_ERROR_YES = 1,
 423         BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE = 0,
 424         BNXT_ULP_SYM_TL3_HDR_ISIP_NO = 0,
 425         BNXT_ULP_SYM_TL3_HDR_ISIP_YES = 1,
 426         BNXT_ULP_SYM_TL3_HDR_TYPE_IGNORE = 0,
 427         BNXT_ULP_SYM_TL3_HDR_TYPE_IPV4 = 0,
 428         BNXT_ULP_SYM_TL3_HDR_TYPE_IPV6 = 1,
 429         BNXT_ULP_SYM_TL3_HDR_VALID_IGNORE = 0,
 430         BNXT_ULP_SYM_TL3_HDR_VALID_NO = 0,
 431         BNXT_ULP_SYM_TL3_HDR_VALID_YES = 1,
 432         BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE = 0,
 433         BNXT_ULP_SYM_TL3_IPV6_CMP_DST_NO = 0,
 434         BNXT_ULP_SYM_TL3_IPV6_CMP_DST_YES = 1,
 435         BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE = 0,
 436         BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_NO = 0,
 437         BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_YES = 1,
 438         BNXT_ULP_SYM_TL4_HDR_ERROR_IGNORE = 0,
 439         BNXT_ULP_SYM_TL4_HDR_ERROR_NO = 0,
 440         BNXT_ULP_SYM_TL4_HDR_ERROR_YES = 1,
 441         BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE = 0,
 442         BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_NO = 0,
 443         BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_YES = 1,
 444         BNXT_ULP_SYM_TL4_HDR_TYPE_IGNORE = 0,
 445         BNXT_ULP_SYM_TL4_HDR_TYPE_TCP = 0,
 446         BNXT_ULP_SYM_TL4_HDR_TYPE_UDP = 1,
 447         BNXT_ULP_SYM_TL4_HDR_VALID_IGNORE = 0,
 448         BNXT_ULP_SYM_TL4_HDR_VALID_NO = 0,
 449         BNXT_ULP_SYM_TL4_HDR_VALID_YES = 1,
 450         BNXT_ULP_SYM_TUN_HDR_ERROR_IGNORE = 0,
 451         BNXT_ULP_SYM_TUN_HDR_ERROR_NO = 0,
 452         BNXT_ULP_SYM_TUN_HDR_ERROR_YES = 1,
 453         BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE = 0,
 454         BNXT_ULP_SYM_TUN_HDR_TYPE_GENEVE = 1,
 455         BNXT_ULP_SYM_TUN_HDR_TYPE_GRE = 3,
 456         BNXT_ULP_SYM_TUN_HDR_TYPE_IGNORE = 0,
 457         BNXT_ULP_SYM_TUN_HDR_TYPE_IPV4 = 4,
 458         BNXT_ULP_SYM_TUN_HDR_TYPE_IPV6 = 5,
 459         BNXT_ULP_SYM_TUN_HDR_TYPE_MPLS = 7,
 460         BNXT_ULP_SYM_TUN_HDR_TYPE_NONE = 15,
 461         BNXT_ULP_SYM_TUN_HDR_TYPE_NVGRE = 2,
 462         BNXT_ULP_SYM_TUN_HDR_TYPE_PPPOE = 6,
 463         BNXT_ULP_SYM_TUN_HDR_TYPE_UPAR1 = 8,
 464         BNXT_ULP_SYM_TUN_HDR_TYPE_UPAR2 = 9,
 465         BNXT_ULP_SYM_TUN_HDR_TYPE_VXLAN = 0,
 466         BNXT_ULP_SYM_TUN_HDR_VALID_IGNORE = 0,
 467         BNXT_ULP_SYM_TUN_HDR_VALID_NO = 0,
 468         BNXT_ULP_SYM_TUN_HDR_VALID_YES = 1,
 469         BNXT_ULP_SYM_WH_PLUS_LOOPBACK_PORT = 3,
 470         BNXT_ULP_SYM_YES = 1
 471 };
 472
 473 enum bnxt_ulp_act_prop_sz {
 474         BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN_SZ = 4,
 475         BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SZ = 4,
 476         BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_SZ = 4,
 477         BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_TYPE = 4,
 478         BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_NUM = 4,
 479         BNXT_ULP_ACT_PROP_SZ_ENCAP_L3_TYPE = 4,
 480         BNXT_ULP_ACT_PROP_SZ_MPLS_POP_NUM = 4,
 481         BNXT_ULP_ACT_PROP_SZ_MPLS_PUSH_NUM = 4,
 482         BNXT_ULP_ACT_PROP_SZ_PORT_ID = 4,
 483         BNXT_ULP_ACT_PROP_SZ_VNIC = 4,
 484         BNXT_ULP_ACT_PROP_SZ_VPORT = 4,
 485         BNXT_ULP_ACT_PROP_SZ_MARK = 4,
 486         BNXT_ULP_ACT_PROP_SZ_COUNT = 4,
 487         BNXT_ULP_ACT_PROP_SZ_METER = 4,
 488         BNXT_ULP_ACT_PROP_SZ_SET_MAC_SRC = 8,
 489         BNXT_ULP_ACT_PROP_SZ_SET_MAC_DST = 8,
 490         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_VLAN = 4,
 491         BNXT_ULP_ACT_PROP_SZ_OF_SET_VLAN_PCP = 4,
 492         BNXT_ULP_ACT_PROP_SZ_OF_SET_VLAN_VID = 4,
 493         BNXT_ULP_ACT_PROP_SZ_SET_IPV4_SRC = 4,
 494         BNXT_ULP_ACT_PROP_SZ_SET_IPV4_DST = 4,
 495         BNXT_ULP_ACT_PROP_SZ_SET_IPV6_SRC = 16,
 496         BNXT_ULP_ACT_PROP_SZ_SET_IPV6_DST = 16,
 497         BNXT_ULP_ACT_PROP_SZ_SET_TP_SRC = 4,
 498         BNXT_ULP_ACT_PROP_SZ_SET_TP_DST = 4,
 499         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_0 = 4,
 500         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_1 = 4,
 501         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_2 = 4,
 502         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_3 = 4,
 503         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_4 = 4,
 504         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_5 = 4,
 505         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_6 = 4,
 506         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_7 = 4,
 507         BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_DMAC = 6,
 508         BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_SMAC = 6,
 509         BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG = 8,
 510         BNXT_ULP_ACT_PROP_SZ_ENCAP_IP = 32,
 511         BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SRC = 16,
 512         BNXT_ULP_ACT_PROP_SZ_ENCAP_UDP = 4,
 513         BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN = 32,
 514         BNXT_ULP_ACT_PROP_SZ_LAST = 4
 515 };
 516
 517 enum bnxt_ulp_act_prop_idx {
 518         BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ = 0,
 519         BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ = 4,
 520         BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ = 8,
 521         BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE = 12,
 522         BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_NUM = 16,
 523         BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE = 20,
 524         BNXT_ULP_ACT_PROP_IDX_MPLS_POP_NUM = 24,
 525         BNXT_ULP_ACT_PROP_IDX_MPLS_PUSH_NUM = 28,
 526         BNXT_ULP_ACT_PROP_IDX_PORT_ID = 32,
 527         BNXT_ULP_ACT_PROP_IDX_VNIC = 36,
 528         BNXT_ULP_ACT_PROP_IDX_VPORT = 40,
 529         BNXT_ULP_ACT_PROP_IDX_MARK = 44,
 530         BNXT_ULP_ACT_PROP_IDX_COUNT = 48,
 531         BNXT_ULP_ACT_PROP_IDX_METER = 52,
 532         BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC = 56,
 533         BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST = 64,
 534         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_VLAN = 72,
 535         BNXT_ULP_ACT_PROP_IDX_OF_SET_VLAN_PCP = 76,
 536         BNXT_ULP_ACT_PROP_IDX_OF_SET_VLAN_VID = 80,
 537         BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC = 84,
 538         BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST = 88,
 539         BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC = 92,
 540         BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST = 108,
 541         BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC = 124,
 542         BNXT_ULP_ACT_PROP_IDX_SET_TP_DST = 128,
 543         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_0 = 132,
 544         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_1 = 136,
 545         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_2 = 140,
 546         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_3 = 144,
 547         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_4 = 148,
 548         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_5 = 152,
 549         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_6 = 156,
 550         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_7 = 160,
 551         BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC = 164,
 552         BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC = 170,
 553         BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG = 176,
 554         BNXT_ULP_ACT_PROP_IDX_ENCAP_IP = 184,
 555         BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC = 216,
 556         BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP = 232,
 557         BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN = 236,
 558         BNXT_ULP_ACT_PROP_IDX_LAST = 268
 559 };
 560
 561 enum bnxt_ulp_class_hid {
 562         BNXT_ULP_CLASS_HID_0080 = 0x0080,
 563         BNXT_ULP_CLASS_HID_0000 = 0x0000,
 564         BNXT_ULP_CLASS_HID_0087 = 0x0087
 565 };
 566
 567 enum bnxt_ulp_act_hid {
 568         BNXT_ULP_ACT_HID_00a1 = 0x00a1,
 569         BNXT_ULP_ACT_HID_0040 = 0x0040,
 570         BNXT_ULP_ACT_HID_0029 = 0x0029
 571 };
 572 #endif