drivers/net/cxgbe/base/t4_hw.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2014-2017 Chelsio Communications.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Chelsio Communications nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <netinet/in.h>
  35
  36 #include <rte_interrupts.h>
  37 #include <rte_log.h>
  38 #include <rte_debug.h>
  39 #include <rte_pci.h>
  40 #include <rte_atomic.h>
  41 #include <rte_branch_prediction.h>
  42 #include <rte_memory.h>
  43 #include <rte_memzone.h>
  44 #include <rte_tailq.h>
  45 #include <rte_eal.h>
  46 #include <rte_alarm.h>
  47 #include <rte_ether.h>
  48 #include <rte_ethdev.h>
  49 #include <rte_malloc.h>
  50 #include <rte_random.h>
  51 #include <rte_dev.h>
  52 #include <rte_byteorder.h>
  53
  54 #include "common.h"
  55 #include "t4_regs.h"
  56 #include "t4_regs_values.h"
  57 #include "t4fw_interface.h"
  58
  59 static void init_link_config(struct link_config *lc, unsigned int pcaps,
  60                              unsigned int acaps);
  61
  62 /**
  63  * t4_read_mtu_tbl - returns the values in the HW path MTU table
  64  * @adap: the adapter
  65  * @mtus: where to store the MTU values
  66  * @mtu_log: where to store the MTU base-2 log (may be %NULL)
  67  *
  68  * Reads the HW path MTU table.
  69  */
  70 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
  71 {
  72         u32 v;
  73         int i;
  74
  75         for (i = 0; i < NMTUS; ++i) {
  76                 t4_write_reg(adap, A_TP_MTU_TABLE,
  77                              V_MTUINDEX(0xff) | V_MTUVALUE(i));
  78                 v = t4_read_reg(adap, A_TP_MTU_TABLE);
  79                 mtus[i] = G_MTUVALUE(v);
  80                 if (mtu_log)
  81                         mtu_log[i] = G_MTUWIDTH(v);
  82         }
  83 }
  84
  85 /**
  86  * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
  87  * @adap: the adapter
  88  * @addr: the indirect TP register address
  89  * @mask: specifies the field within the register to modify
  90  * @val: new value for the field
  91  *
  92  * Sets a field of an indirect TP register to the given value.
  93  */
  94 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
  95                             unsigned int mask, unsigned int val)
  96 {
  97         t4_write_reg(adap, A_TP_PIO_ADDR, addr);
  98         val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask;
  99         t4_write_reg(adap, A_TP_PIO_DATA, val);
 100 }
 101
 102 /* The minimum additive increment value for the congestion control table */
 103 #define CC_MIN_INCR 2U
 104
 105 /**
 106  * t4_load_mtus - write the MTU and congestion control HW tables
 107  * @adap: the adapter
 108  * @mtus: the values for the MTU table
 109  * @alpha: the values for the congestion control alpha parameter
 110  * @beta: the values for the congestion control beta parameter
 111  *
 112  * Write the HW MTU table with the supplied MTUs and the high-speed
 113  * congestion control table with the supplied alpha, beta, and MTUs.
 114  * We write the two tables together because the additive increments
 115  * depend on the MTUs.
 116  */
 117 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
 118                   const unsigned short *alpha, const unsigned short *beta)
 119 {
 120         static const unsigned int avg_pkts[NCCTRL_WIN] = {
 121                 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
 122                 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
 123                 28672, 40960, 57344, 81920, 114688, 163840, 229376
 124         };
 125
 126         unsigned int i, w;
 127
 128         for (i = 0; i < NMTUS; ++i) {
 129                 unsigned int mtu = mtus[i];
 130                 unsigned int log2 = cxgbe_fls(mtu);
 131
 132                 if (!(mtu & ((1 << log2) >> 2)))     /* round */
 133                         log2--;
 134                 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) |
 135                              V_MTUWIDTH(log2) | V_MTUVALUE(mtu));
 136
 137                 for (w = 0; w < NCCTRL_WIN; ++w) {
 138                         unsigned int inc;
 139
 140                         inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
 141                                   CC_MIN_INCR);
 142
 143                         t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
 144                                      (w << 16) | (beta[w] << 13) | inc);
 145                 }
 146         }
 147 }
 148
 149 /**
 150  * t4_wait_op_done_val - wait until an operation is completed
 151  * @adapter: the adapter performing the operation
 152  * @reg: the register to check for completion
 153  * @mask: a single-bit field within @reg that indicates completion
 154  * @polarity: the value of the field when the operation is completed
 155  * @attempts: number of check iterations
 156  * @delay: delay in usecs between iterations
 157  * @valp: where to store the value of the register at completion time
 158  *
 159  * Wait until an operation is completed by checking a bit in a register
 160  * up to @attempts times.  If @valp is not NULL the value of the register
 161  * at the time it indicated completion is stored there.  Returns 0 if the
 162  * operation completes and -EAGAIN otherwise.
 163  */
 164 int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
 165                         int polarity, int attempts, int delay, u32 *valp)
 166 {
 167         while (1) {
 168                 u32 val = t4_read_reg(adapter, reg);
 169
 170                 if (!!(val & mask) == polarity) {
 171                         if (valp)
 172                                 *valp = val;
 173                         return 0;
 174                 }
 175                 if (--attempts == 0)
 176                         return -EAGAIN;
 177                 if (delay)
 178                         udelay(delay);
 179         }
 180 }
 181
 182 /**
 183  * t4_set_reg_field - set a register field to a value
 184  * @adapter: the adapter to program
 185  * @addr: the register address
 186  * @mask: specifies the portion of the register to modify
 187  * @val: the new value for the register field
 188  *
 189  * Sets a register field specified by the supplied mask to the
 190  * given value.
 191  */
 192 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
 193                       u32 val)
 194 {
 195         u32 v = t4_read_reg(adapter, addr) & ~mask;
 196
 197         t4_write_reg(adapter, addr, v | val);
 198         (void)t4_read_reg(adapter, addr);      /* flush */
 199 }
 200
 201 /**
 202  * t4_read_indirect - read indirectly addressed registers
 203  * @adap: the adapter
 204  * @addr_reg: register holding the indirect address
 205  * @data_reg: register holding the value of the indirect register
 206  * @vals: where the read register values are stored
 207  * @nregs: how many indirect registers to read
 208  * @start_idx: index of first indirect register to read
 209  *
 210  * Reads registers that are accessed indirectly through an address/data
 211  * register pair.
 212  */
 213 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
 214                       unsigned int data_reg, u32 *vals, unsigned int nregs,
 215                       unsigned int start_idx)
 216 {
 217         while (nregs--) {
 218                 t4_write_reg(adap, addr_reg, start_idx);
 219                 *vals++ = t4_read_reg(adap, data_reg);
 220                 start_idx++;
 221         }
 222 }
 223
 224 /**
 225  * t4_write_indirect - write indirectly addressed registers
 226  * @adap: the adapter
 227  * @addr_reg: register holding the indirect addresses
 228  * @data_reg: register holding the value for the indirect registers
 229  * @vals: values to write
 230  * @nregs: how many indirect registers to write
 231  * @start_idx: address of first indirect register to write
 232  *
 233  * Writes a sequential block of registers that are accessed indirectly
 234  * through an address/data register pair.
 235  */
 236 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
 237                        unsigned int data_reg, const u32 *vals,
 238                        unsigned int nregs, unsigned int start_idx)
 239 {
 240         while (nregs--) {
 241                 t4_write_reg(adap, addr_reg, start_idx++);
 242                 t4_write_reg(adap, data_reg, *vals++);
 243         }
 244 }
 245
 246 /**
 247  * t4_report_fw_error - report firmware error
 248  * @adap: the adapter
 249  *
 250  * The adapter firmware can indicate error conditions to the host.
 251  * If the firmware has indicated an error, print out the reason for
 252  * the firmware error.
 253  */
 254 static void t4_report_fw_error(struct adapter *adap)
 255 {
 256         static const char * const reason[] = {
 257                 "Crash",                        /* PCIE_FW_EVAL_CRASH */
 258                 "During Device Preparation",    /* PCIE_FW_EVAL_PREP */
 259                 "During Device Configuration",  /* PCIE_FW_EVAL_CONF */
 260                 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
 261                 "Unexpected Event",     /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
 262                 "Insufficient Airflow",         /* PCIE_FW_EVAL_OVERHEAT */
 263                 "Device Shutdown",      /* PCIE_FW_EVAL_DEVICESHUTDOWN */
 264                 "Reserved",                     /* reserved */
 265         };
 266         u32 pcie_fw;
 267
 268         pcie_fw = t4_read_reg(adap, A_PCIE_FW);
 269         if (pcie_fw & F_PCIE_FW_ERR)
 270                 pr_err("%s: Firmware reports adapter error: %s\n",
 271                        __func__, reason[G_PCIE_FW_EVAL(pcie_fw)]);
 272 }
 273
 274 /*
 275  * Get the reply to a mailbox command and store it in @rpl in big-endian order.
 276  */
 277 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
 278                          u32 mbox_addr)
 279 {
 280         for ( ; nflit; nflit--, mbox_addr += 8)
 281                 *rpl++ = htobe64(t4_read_reg64(adap, mbox_addr));
 282 }
 283
 284 /*
 285  * Handle a FW assertion reported in a mailbox.
 286  */
 287 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
 288 {
 289         struct fw_debug_cmd asrt;
 290
 291         get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
 292         pr_warn("FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
 293                 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
 294                 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
 295 }
 296
 297 #define X_CIM_PF_NOACCESS 0xeeeeeeee
 298
 299 /*
 300  * If the Host OS Driver needs locking arround accesses to the mailbox, this
 301  * can be turned on via the T4_OS_NEEDS_MBOX_LOCKING CPP define ...
 302  */
 303 /* makes single-statement usage a bit cleaner ... */
 304 #ifdef T4_OS_NEEDS_MBOX_LOCKING
 305 #define T4_OS_MBOX_LOCKING(x) x
 306 #else
 307 #define T4_OS_MBOX_LOCKING(x) do {} while (0)
 308 #endif
 309
 310 /**
 311  * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
 312  * @adap: the adapter
 313  * @mbox: index of the mailbox to use
 314  * @cmd: the command to write
 315  * @size: command length in bytes
 316  * @rpl: where to optionally store the reply
 317  * @sleep_ok: if true we may sleep while awaiting command completion
 318  * @timeout: time to wait for command to finish before timing out
 319  *           (negative implies @sleep_ok=false)
 320  *
 321  * Sends the given command to FW through the selected mailbox and waits
 322  * for the FW to execute the command.  If @rpl is not %NULL it is used to
 323  * store the FW's reply to the command.  The command and its optional
 324  * reply are of the same length.  Some FW commands like RESET and
 325  * INITIALIZE can take a considerable amount of time to execute.
 326  * @sleep_ok determines whether we may sleep while awaiting the response.
 327  * If sleeping is allowed we use progressive backoff otherwise we spin.
 328  * Note that passing in a negative @timeout is an alternate mechanism
 329  * for specifying @sleep_ok=false.  This is useful when a higher level
 330  * interface allows for specification of @timeout but not @sleep_ok ...
 331  *
 332  * Returns 0 on success or a negative errno on failure.  A
 333  * failure can happen either because we are not able to execute the
 334  * command or FW executes it but signals an error.  In the latter case
 335  * the return value is the error code indicated by FW (negated).
 336  */
 337 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox,
 338                             const void __attribute__((__may_alias__)) *cmd,
 339                             int size, void *rpl, bool sleep_ok, int timeout)
 340 {
 341         /*
 342          * We delay in small increments at first in an effort to maintain
 343          * responsiveness for simple, fast executing commands but then back
 344          * off to larger delays to a maximum retry delay.
 345          */
 346         static const int delay[] = {
 347                 1, 1, 3, 5, 10, 10, 20, 50, 100
 348         };
 349
 350         u32 v;
 351         u64 res;
 352         int i, ms;
 353         unsigned int delay_idx;
 354         __be64 *temp = (__be64 *)malloc(size * sizeof(char));
 355         __be64 *p = temp;
 356         u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA);
 357         u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL);
 358         u32 ctl;
 359         struct mbox_entry entry;
 360         u32 pcie_fw = 0;
 361
 362         if (!temp)
 363                 return -ENOMEM;
 364
 365         if ((size & 15) || size > MBOX_LEN) {
 366                 free(temp);
 367                 return -EINVAL;
 368         }
 369
 370         bzero(p, size);
 371         memcpy(p, (const __be64 *)cmd, size);
 372
 373         /*
 374          * If we have a negative timeout, that implies that we can't sleep.
 375          */
 376         if (timeout < 0) {
 377                 sleep_ok = false;
 378                 timeout = -timeout;
 379         }
 380
 381 #ifdef T4_OS_NEEDS_MBOX_LOCKING
 382         /*
 383          * Queue ourselves onto the mailbox access list.  When our entry is at
 384          * the front of the list, we have rights to access the mailbox.  So we
 385          * wait [for a while] till we're at the front [or bail out with an
 386          * EBUSY] ...
 387          */
 388         t4_os_atomic_add_tail(&entry, &adap->mbox_list, &adap->mbox_lock);
 389
 390         delay_idx = 0;
 391         ms = delay[0];
 392
 393         for (i = 0; ; i += ms) {
 394                 /*
 395                  * If we've waited too long, return a busy indication.  This
 396                  * really ought to be based on our initial position in the
 397                  * mailbox access list but this is a start.  We very rarely
 398                  * contend on access to the mailbox ...  Also check for a
 399                  * firmware error which we'll report as a device error.
 400                  */
 401                 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
 402                 if (i > 4 * timeout || (pcie_fw & F_PCIE_FW_ERR)) {
 403                         t4_os_atomic_list_del(&entry, &adap->mbox_list,
 404                                               &adap->mbox_lock);
 405                         t4_report_fw_error(adap);
 406                         free(temp);
 407                         return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -EBUSY;
 408                 }
 409
 410                 /*
 411                  * If we're at the head, break out and start the mailbox
 412                  * protocol.
 413                  */
 414                 if (t4_os_list_first_entry(&adap->mbox_list) == &entry)
 415                         break;
 416
 417                 /*
 418                  * Delay for a bit before checking again ...
 419                  */
 420                 if (sleep_ok) {
 421                         ms = delay[delay_idx];  /* last element may repeat */
 422                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 423                                 delay_idx++;
 424                         msleep(ms);
 425                 } else {
 426                         rte_delay_ms(ms);
 427                 }
 428         }
 429 #endif /* T4_OS_NEEDS_MBOX_LOCKING */
 430
 431         /*
 432          * Attempt to gain access to the mailbox.
 433          */
 434         for (i = 0; i < 4; i++) {
 435                 ctl = t4_read_reg(adap, ctl_reg);
 436                 v = G_MBOWNER(ctl);
 437                 if (v != X_MBOWNER_NONE)
 438                         break;
 439         }
 440
 441         /*
 442          * If we were unable to gain access, dequeue ourselves from the
 443          * mailbox atomic access list and report the error to our caller.
 444          */
 445         if (v != X_MBOWNER_PL) {
 446                 T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
 447                                                          &adap->mbox_list,
 448                                                          &adap->mbox_lock));
 449                 t4_report_fw_error(adap);
 450                 free(temp);
 451                 return (v == X_MBOWNER_FW ? -EBUSY : -ETIMEDOUT);
 452         }
 453
 454         /*
 455          * If we gain ownership of the mailbox and there's a "valid" message
 456          * in it, this is likely an asynchronous error message from the
 457          * firmware.  So we'll report that and then proceed on with attempting
 458          * to issue our own command ... which may well fail if the error
 459          * presaged the firmware crashing ...
 460          */
 461         if (ctl & F_MBMSGVALID) {
 462                 dev_err(adap, "found VALID command in mbox %u: "
 463                         "%llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
 464                         (unsigned long long)t4_read_reg64(adap, data_reg),
 465                         (unsigned long long)t4_read_reg64(adap, data_reg + 8),
 466                         (unsigned long long)t4_read_reg64(adap, data_reg + 16),
 467                         (unsigned long long)t4_read_reg64(adap, data_reg + 24),
 468                         (unsigned long long)t4_read_reg64(adap, data_reg + 32),
 469                         (unsigned long long)t4_read_reg64(adap, data_reg + 40),
 470                         (unsigned long long)t4_read_reg64(adap, data_reg + 48),
 471                         (unsigned long long)t4_read_reg64(adap, data_reg + 56));
 472         }
 473
 474         /*
 475          * Copy in the new mailbox command and send it on its way ...
 476          */
 477         for (i = 0; i < size; i += 8, p++)
 478                 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p));
 479
 480         CXGBE_DEBUG_MBOX(adap, "%s: mbox %u: %016llx %016llx %016llx %016llx "
 481                         "%016llx %016llx %016llx %016llx\n", __func__,  (mbox),
 482                         (unsigned long long)t4_read_reg64(adap, data_reg),
 483                         (unsigned long long)t4_read_reg64(adap, data_reg + 8),
 484                         (unsigned long long)t4_read_reg64(adap, data_reg + 16),
 485                         (unsigned long long)t4_read_reg64(adap, data_reg + 24),
 486                         (unsigned long long)t4_read_reg64(adap, data_reg + 32),
 487                         (unsigned long long)t4_read_reg64(adap, data_reg + 40),
 488                         (unsigned long long)t4_read_reg64(adap, data_reg + 48),
 489                         (unsigned long long)t4_read_reg64(adap, data_reg + 56));
 490
 491         t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW));
 492         t4_read_reg(adap, ctl_reg);          /* flush write */
 493
 494         delay_idx = 0;
 495         ms = delay[0];
 496
 497         /*
 498          * Loop waiting for the reply; bail out if we time out or the firmware
 499          * reports an error.
 500          */
 501         pcie_fw = t4_read_reg(adap, A_PCIE_FW);
 502         for (i = 0; i < timeout && !(pcie_fw & F_PCIE_FW_ERR); i += ms) {
 503                 if (sleep_ok) {
 504                         ms = delay[delay_idx];  /* last element may repeat */
 505                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 506                                 delay_idx++;
 507                         msleep(ms);
 508                 } else {
 509                         msleep(ms);
 510                 }
 511
 512                 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
 513                 v = t4_read_reg(adap, ctl_reg);
 514                 if (v == X_CIM_PF_NOACCESS)
 515                         continue;
 516                 if (G_MBOWNER(v) == X_MBOWNER_PL) {
 517                         if (!(v & F_MBMSGVALID)) {
 518                                 t4_write_reg(adap, ctl_reg,
 519                                              V_MBOWNER(X_MBOWNER_NONE));
 520                                 continue;
 521                         }
 522
 523                         CXGBE_DEBUG_MBOX(adap,
 524                         "%s: mbox %u: %016llx %016llx %016llx %016llx "
 525                         "%016llx %016llx %016llx %016llx\n", __func__,  (mbox),
 526                         (unsigned long long)t4_read_reg64(adap, data_reg),
 527                         (unsigned long long)t4_read_reg64(adap, data_reg + 8),
 528                         (unsigned long long)t4_read_reg64(adap, data_reg + 16),
 529                         (unsigned long long)t4_read_reg64(adap, data_reg + 24),
 530                         (unsigned long long)t4_read_reg64(adap, data_reg + 32),
 531                         (unsigned long long)t4_read_reg64(adap, data_reg + 40),
 532                         (unsigned long long)t4_read_reg64(adap, data_reg + 48),
 533                         (unsigned long long)t4_read_reg64(adap, data_reg + 56));
 534
 535                         CXGBE_DEBUG_MBOX(adap,
 536                                 "command %#x completed in %d ms (%ssleeping)\n",
 537                                 *(const u8 *)cmd,
 538                                 i + ms, sleep_ok ? "" : "non-");
 539
 540                         res = t4_read_reg64(adap, data_reg);
 541                         if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) {
 542                                 fw_asrt(adap, data_reg);
 543                                 res = V_FW_CMD_RETVAL(EIO);
 544                         } else if (rpl) {
 545                                 get_mbox_rpl(adap, rpl, size / 8, data_reg);
 546                         }
 547                         t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE));
 548                         T4_OS_MBOX_LOCKING(
 549                                 t4_os_atomic_list_del(&entry, &adap->mbox_list,
 550                                                       &adap->mbox_lock));
 551                         free(temp);
 552                         return -G_FW_CMD_RETVAL((int)res);
 553                 }
 554         }
 555
 556         /*
 557          * We timed out waiting for a reply to our mailbox command.  Report
 558          * the error and also check to see if the firmware reported any
 559          * errors ...
 560          */
 561         dev_err(adap, "command %#x in mailbox %d timed out\n",
 562                 *(const u8 *)cmd, mbox);
 563         T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
 564                                                  &adap->mbox_list,
 565                                                  &adap->mbox_lock));
 566         t4_report_fw_error(adap);
 567         free(temp);
 568         return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -ETIMEDOUT;
 569 }
 570
 571 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
 572                     void *rpl, bool sleep_ok)
 573 {
 574         return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
 575                                        FW_CMD_MAX_TIMEOUT);
 576 }
 577
 578 /**
 579  * t4_get_regs_len - return the size of the chips register set
 580  * @adapter: the adapter
 581  *
 582  * Returns the size of the chip's BAR0 register space.
 583  */
 584 unsigned int t4_get_regs_len(struct adapter *adapter)
 585 {
 586         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
 587
 588         switch (chip_version) {
 589         case CHELSIO_T5:
 590         case CHELSIO_T6:
 591                 return T5_REGMAP_SIZE;
 592         }
 593
 594         dev_err(adapter,
 595                 "Unsupported chip version %d\n", chip_version);
 596         return 0;
 597 }
 598
 599 /**
 600  * t4_get_regs - read chip registers into provided buffer
 601  * @adap: the adapter
 602  * @buf: register buffer
 603  * @buf_size: size (in bytes) of register buffer
 604  *
 605  * If the provided register buffer isn't large enough for the chip's
 606  * full register range, the register dump will be truncated to the
 607  * register buffer's size.
 608  */
 609 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
 610 {
 611         static const unsigned int t5_reg_ranges[] = {
 612                 0x1008, 0x10c0,
 613                 0x10cc, 0x10f8,
 614                 0x1100, 0x1100,
 615                 0x110c, 0x1148,
 616                 0x1180, 0x1184,
 617                 0x1190, 0x1194,
 618                 0x11a0, 0x11a4,
 619                 0x11b0, 0x11b4,
 620                 0x11fc, 0x123c,
 621                 0x1280, 0x173c,
 622                 0x1800, 0x18fc,
 623                 0x3000, 0x3028,
 624                 0x3060, 0x30b0,
 625                 0x30b8, 0x30d8,
 626                 0x30e0, 0x30fc,
 627                 0x3140, 0x357c,
 628                 0x35a8, 0x35cc,
 629                 0x35ec, 0x35ec,
 630                 0x3600, 0x5624,
 631                 0x56cc, 0x56ec,
 632                 0x56f4, 0x5720,
 633                 0x5728, 0x575c,
 634                 0x580c, 0x5814,
 635                 0x5890, 0x589c,
 636                 0x58a4, 0x58ac,
 637                 0x58b8, 0x58bc,
 638                 0x5940, 0x59c8,
 639                 0x59d0, 0x59dc,
 640                 0x59fc, 0x5a18,
 641                 0x5a60, 0x5a70,
 642                 0x5a80, 0x5a9c,
 643                 0x5b94, 0x5bfc,
 644                 0x6000, 0x6020,
 645                 0x6028, 0x6040,
 646                 0x6058, 0x609c,
 647                 0x60a8, 0x614c,
 648                 0x7700, 0x7798,
 649                 0x77c0, 0x78fc,
 650                 0x7b00, 0x7b58,
 651                 0x7b60, 0x7b84,
 652                 0x7b8c, 0x7c54,
 653                 0x7d00, 0x7d38,
 654                 0x7d40, 0x7d80,
 655                 0x7d8c, 0x7ddc,
 656                 0x7de4, 0x7e04,
 657                 0x7e10, 0x7e1c,
 658                 0x7e24, 0x7e38,
 659                 0x7e40, 0x7e44,
 660                 0x7e4c, 0x7e78,
 661                 0x7e80, 0x7edc,
 662                 0x7ee8, 0x7efc,
 663                 0x8dc0, 0x8de0,
 664                 0x8df8, 0x8e04,
 665                 0x8e10, 0x8e84,
 666                 0x8ea0, 0x8f84,
 667                 0x8fc0, 0x9058,
 668                 0x9060, 0x9060,
 669                 0x9068, 0x90f8,
 670                 0x9400, 0x9408,
 671                 0x9410, 0x9470,
 672                 0x9600, 0x9600,
 673                 0x9608, 0x9638,
 674                 0x9640, 0x96f4,
 675                 0x9800, 0x9808,
 676                 0x9820, 0x983c,
 677                 0x9850, 0x9864,
 678                 0x9c00, 0x9c6c,
 679                 0x9c80, 0x9cec,
 680                 0x9d00, 0x9d6c,
 681                 0x9d80, 0x9dec,
 682                 0x9e00, 0x9e6c,
 683                 0x9e80, 0x9eec,
 684                 0x9f00, 0x9f6c,
 685                 0x9f80, 0xa020,
 686                 0xd004, 0xd004,
 687                 0xd010, 0xd03c,
 688                 0xdfc0, 0xdfe0,
 689                 0xe000, 0x1106c,
 690                 0x11074, 0x11088,
 691                 0x1109c, 0x1117c,
 692                 0x11190, 0x11204,
 693                 0x19040, 0x1906c,
 694                 0x19078, 0x19080,
 695                 0x1908c, 0x190e8,
 696                 0x190f0, 0x190f8,
 697                 0x19100, 0x19110,
 698                 0x19120, 0x19124,
 699                 0x19150, 0x19194,
 700                 0x1919c, 0x191b0,
 701                 0x191d0, 0x191e8,
 702                 0x19238, 0x19290,
 703                 0x193f8, 0x19428,
 704                 0x19430, 0x19444,
 705                 0x1944c, 0x1946c,
 706                 0x19474, 0x19474,
 707                 0x19490, 0x194cc,
 708                 0x194f0, 0x194f8,
 709                 0x19c00, 0x19c08,
 710                 0x19c10, 0x19c60,
 711                 0x19c94, 0x19ce4,
 712                 0x19cf0, 0x19d40,
 713                 0x19d50, 0x19d94,
 714                 0x19da0, 0x19de8,
 715                 0x19df0, 0x19e10,
 716                 0x19e50, 0x19e90,
 717                 0x19ea0, 0x19f24,
 718                 0x19f34, 0x19f34,
 719                 0x19f40, 0x19f50,
 720                 0x19f90, 0x19fb4,
 721                 0x19fc4, 0x19fe4,
 722                 0x1a000, 0x1a004,
 723                 0x1a010, 0x1a06c,
 724                 0x1a0b0, 0x1a0e4,
 725                 0x1a0ec, 0x1a0f8,
 726                 0x1a100, 0x1a108,
 727                 0x1a114, 0x1a120,
 728                 0x1a128, 0x1a130,
 729                 0x1a138, 0x1a138,
 730                 0x1a190, 0x1a1c4,
 731                 0x1a1fc, 0x1a1fc,
 732                 0x1e008, 0x1e00c,
 733                 0x1e040, 0x1e044,
 734                 0x1e04c, 0x1e04c,
 735                 0x1e284, 0x1e290,
 736                 0x1e2c0, 0x1e2c0,
 737                 0x1e2e0, 0x1e2e0,
 738                 0x1e300, 0x1e384,
 739                 0x1e3c0, 0x1e3c8,
 740                 0x1e408, 0x1e40c,
 741                 0x1e440, 0x1e444,
 742                 0x1e44c, 0x1e44c,
 743                 0x1e684, 0x1e690,
 744                 0x1e6c0, 0x1e6c0,
 745                 0x1e6e0, 0x1e6e0,
 746                 0x1e700, 0x1e784,
 747                 0x1e7c0, 0x1e7c8,
 748                 0x1e808, 0x1e80c,
 749                 0x1e840, 0x1e844,
 750                 0x1e84c, 0x1e84c,
 751                 0x1ea84, 0x1ea90,
 752                 0x1eac0, 0x1eac0,
 753                 0x1eae0, 0x1eae0,
 754                 0x1eb00, 0x1eb84,
 755                 0x1ebc0, 0x1ebc8,
 756                 0x1ec08, 0x1ec0c,
 757                 0x1ec40, 0x1ec44,
 758                 0x1ec4c, 0x1ec4c,
 759                 0x1ee84, 0x1ee90,
 760                 0x1eec0, 0x1eec0,
 761                 0x1eee0, 0x1eee0,
 762                 0x1ef00, 0x1ef84,
 763                 0x1efc0, 0x1efc8,
 764                 0x1f008, 0x1f00c,
 765                 0x1f040, 0x1f044,
 766                 0x1f04c, 0x1f04c,
 767                 0x1f284, 0x1f290,
 768                 0x1f2c0, 0x1f2c0,
 769                 0x1f2e0, 0x1f2e0,
 770                 0x1f300, 0x1f384,
 771                 0x1f3c0, 0x1f3c8,
 772                 0x1f408, 0x1f40c,
 773                 0x1f440, 0x1f444,
 774                 0x1f44c, 0x1f44c,
 775                 0x1f684, 0x1f690,
 776                 0x1f6c0, 0x1f6c0,
 777                 0x1f6e0, 0x1f6e0,
 778                 0x1f700, 0x1f784,
 779                 0x1f7c0, 0x1f7c8,
 780                 0x1f808, 0x1f80c,
 781                 0x1f840, 0x1f844,
 782                 0x1f84c, 0x1f84c,
 783                 0x1fa84, 0x1fa90,
 784                 0x1fac0, 0x1fac0,
 785                 0x1fae0, 0x1fae0,
 786                 0x1fb00, 0x1fb84,
 787                 0x1fbc0, 0x1fbc8,
 788                 0x1fc08, 0x1fc0c,
 789                 0x1fc40, 0x1fc44,
 790                 0x1fc4c, 0x1fc4c,
 791                 0x1fe84, 0x1fe90,
 792                 0x1fec0, 0x1fec0,
 793                 0x1fee0, 0x1fee0,
 794                 0x1ff00, 0x1ff84,
 795                 0x1ffc0, 0x1ffc8,
 796                 0x30000, 0x30030,
 797                 0x30038, 0x30038,
 798                 0x30040, 0x30040,
 799                 0x30100, 0x30144,
 800                 0x30190, 0x301a0,
 801                 0x301a8, 0x301b8,
 802                 0x301c4, 0x301c8,
 803                 0x301d0, 0x301d0,
 804                 0x30200, 0x30318,
 805                 0x30400, 0x304b4,
 806                 0x304c0, 0x3052c,
 807                 0x30540, 0x3061c,
 808                 0x30800, 0x30828,
 809                 0x30834, 0x30834,
 810                 0x308c0, 0x30908,
 811                 0x30910, 0x309ac,
 812                 0x30a00, 0x30a14,
 813                 0x30a1c, 0x30a2c,
 814                 0x30a44, 0x30a50,
 815                 0x30a74, 0x30a74,
 816                 0x30a7c, 0x30afc,
 817                 0x30b08, 0x30c24,
 818                 0x30d00, 0x30d00,
 819                 0x30d08, 0x30d14,
 820                 0x30d1c, 0x30d20,
 821                 0x30d3c, 0x30d3c,
 822                 0x30d48, 0x30d50,
 823                 0x31200, 0x3120c,
 824                 0x31220, 0x31220,
 825                 0x31240, 0x31240,
 826                 0x31600, 0x3160c,
 827                 0x31a00, 0x31a1c,
 828                 0x31e00, 0x31e20,
 829                 0x31e38, 0x31e3c,
 830                 0x31e80, 0x31e80,
 831                 0x31e88, 0x31ea8,
 832                 0x31eb0, 0x31eb4,
 833                 0x31ec8, 0x31ed4,
 834                 0x31fb8, 0x32004,
 835                 0x32200, 0x32200,
 836                 0x32208, 0x32240,
 837                 0x32248, 0x32280,
 838                 0x32288, 0x322c0,
 839                 0x322c8, 0x322fc,
 840                 0x32600, 0x32630,
 841                 0x32a00, 0x32abc,
 842                 0x32b00, 0x32b10,
 843                 0x32b20, 0x32b30,
 844                 0x32b40, 0x32b50,
 845                 0x32b60, 0x32b70,
 846                 0x33000, 0x33028,
 847                 0x33030, 0x33048,
 848                 0x33060, 0x33068,
 849                 0x33070, 0x3309c,
 850                 0x330f0, 0x33128,
 851                 0x33130, 0x33148,
 852                 0x33160, 0x33168,
 853                 0x33170, 0x3319c,
 854                 0x331f0, 0x33238,
 855                 0x33240, 0x33240,
 856                 0x33248, 0x33250,
 857                 0x3325c, 0x33264,
 858                 0x33270, 0x332b8,
 859                 0x332c0, 0x332e4,
 860                 0x332f8, 0x33338,
 861                 0x33340, 0x33340,
 862                 0x33348, 0x33350,
 863                 0x3335c, 0x33364,
 864                 0x33370, 0x333b8,
 865                 0x333c0, 0x333e4,
 866                 0x333f8, 0x33428,
 867                 0x33430, 0x33448,
 868                 0x33460, 0x33468,
 869                 0x33470, 0x3349c,
 870                 0x334f0, 0x33528,
 871                 0x33530, 0x33548,
 872                 0x33560, 0x33568,
 873                 0x33570, 0x3359c,
 874                 0x335f0, 0x33638,
 875                 0x33640, 0x33640,
 876                 0x33648, 0x33650,
 877                 0x3365c, 0x33664,
 878                 0x33670, 0x336b8,
 879                 0x336c0, 0x336e4,
 880                 0x336f8, 0x33738,
 881                 0x33740, 0x33740,
 882                 0x33748, 0x33750,
 883                 0x3375c, 0x33764,
 884                 0x33770, 0x337b8,
 885                 0x337c0, 0x337e4,
 886                 0x337f8, 0x337fc,
 887                 0x33814, 0x33814,
 888                 0x3382c, 0x3382c,
 889                 0x33880, 0x3388c,
 890                 0x338e8, 0x338ec,
 891                 0x33900, 0x33928,
 892                 0x33930, 0x33948,
 893                 0x33960, 0x33968,
 894                 0x33970, 0x3399c,
 895                 0x339f0, 0x33a38,
 896                 0x33a40, 0x33a40,
 897                 0x33a48, 0x33a50,
 898                 0x33a5c, 0x33a64,
 899                 0x33a70, 0x33ab8,
 900                 0x33ac0, 0x33ae4,
 901                 0x33af8, 0x33b10,
 902                 0x33b28, 0x33b28,
 903                 0x33b3c, 0x33b50,
 904                 0x33bf0, 0x33c10,
 905                 0x33c28, 0x33c28,
 906                 0x33c3c, 0x33c50,
 907                 0x33cf0, 0x33cfc,
 908                 0x34000, 0x34030,
 909                 0x34038, 0x34038,
 910                 0x34040, 0x34040,
 911                 0x34100, 0x34144,
 912                 0x34190, 0x341a0,
 913                 0x341a8, 0x341b8,
 914                 0x341c4, 0x341c8,
 915                 0x341d0, 0x341d0,
 916                 0x34200, 0x34318,
 917                 0x34400, 0x344b4,
 918                 0x344c0, 0x3452c,
 919                 0x34540, 0x3461c,
 920                 0x34800, 0x34828,
 921                 0x34834, 0x34834,
 922                 0x348c0, 0x34908,
 923                 0x34910, 0x349ac,
 924                 0x34a00, 0x34a14,
 925                 0x34a1c, 0x34a2c,
 926                 0x34a44, 0x34a50,
 927                 0x34a74, 0x34a74,
 928                 0x34a7c, 0x34afc,
 929                 0x34b08, 0x34c24,
 930                 0x34d00, 0x34d00,
 931                 0x34d08, 0x34d14,
 932                 0x34d1c, 0x34d20,
 933                 0x34d3c, 0x34d3c,
 934                 0x34d48, 0x34d50,
 935                 0x35200, 0x3520c,
 936                 0x35220, 0x35220,
 937                 0x35240, 0x35240,
 938                 0x35600, 0x3560c,
 939                 0x35a00, 0x35a1c,
 940                 0x35e00, 0x35e20,
 941                 0x35e38, 0x35e3c,
 942                 0x35e80, 0x35e80,
 943                 0x35e88, 0x35ea8,
 944                 0x35eb0, 0x35eb4,
 945                 0x35ec8, 0x35ed4,
 946                 0x35fb8, 0x36004,
 947                 0x36200, 0x36200,
 948                 0x36208, 0x36240,
 949                 0x36248, 0x36280,
 950                 0x36288, 0x362c0,
 951                 0x362c8, 0x362fc,
 952                 0x36600, 0x36630,
 953                 0x36a00, 0x36abc,
 954                 0x36b00, 0x36b10,
 955                 0x36b20, 0x36b30,
 956                 0x36b40, 0x36b50,
 957                 0x36b60, 0x36b70,
 958                 0x37000, 0x37028,
 959                 0x37030, 0x37048,
 960                 0x37060, 0x37068,
 961                 0x37070, 0x3709c,
 962                 0x370f0, 0x37128,
 963                 0x37130, 0x37148,
 964                 0x37160, 0x37168,
 965                 0x37170, 0x3719c,
 966                 0x371f0, 0x37238,
 967                 0x37240, 0x37240,
 968                 0x37248, 0x37250,
 969                 0x3725c, 0x37264,
 970                 0x37270, 0x372b8,
 971                 0x372c0, 0x372e4,
 972                 0x372f8, 0x37338,
 973                 0x37340, 0x37340,
 974                 0x37348, 0x37350,
 975                 0x3735c, 0x37364,
 976                 0x37370, 0x373b8,
 977                 0x373c0, 0x373e4,
 978                 0x373f8, 0x37428,
 979                 0x37430, 0x37448,
 980                 0x37460, 0x37468,
 981                 0x37470, 0x3749c,
 982                 0x374f0, 0x37528,
 983                 0x37530, 0x37548,
 984                 0x37560, 0x37568,
 985                 0x37570, 0x3759c,
 986                 0x375f0, 0x37638,
 987                 0x37640, 0x37640,
 988                 0x37648, 0x37650,
 989                 0x3765c, 0x37664,
 990                 0x37670, 0x376b8,
 991                 0x376c0, 0x376e4,
 992                 0x376f8, 0x37738,
 993                 0x37740, 0x37740,
 994                 0x37748, 0x37750,
 995                 0x3775c, 0x37764,
 996                 0x37770, 0x377b8,
 997                 0x377c0, 0x377e4,
 998                 0x377f8, 0x377fc,
 999                 0x37814, 0x37814,
1000                 0x3782c, 0x3782c,
1001                 0x37880, 0x3788c,
1002                 0x378e8, 0x378ec,
1003                 0x37900, 0x37928,
1004                 0x37930, 0x37948,
1005                 0x37960, 0x37968,
1006                 0x37970, 0x3799c,
1007                 0x379f0, 0x37a38,
1008                 0x37a40, 0x37a40,
1009                 0x37a48, 0x37a50,
1010                 0x37a5c, 0x37a64,
1011                 0x37a70, 0x37ab8,
1012                 0x37ac0, 0x37ae4,
1013                 0x37af8, 0x37b10,
1014                 0x37b28, 0x37b28,
1015                 0x37b3c, 0x37b50,
1016                 0x37bf0, 0x37c10,
1017                 0x37c28, 0x37c28,
1018                 0x37c3c, 0x37c50,
1019                 0x37cf0, 0x37cfc,
1020                 0x38000, 0x38030,
1021                 0x38038, 0x38038,
1022                 0x38040, 0x38040,
1023                 0x38100, 0x38144,
1024                 0x38190, 0x381a0,
1025                 0x381a8, 0x381b8,
1026                 0x381c4, 0x381c8,
1027                 0x381d0, 0x381d0,
1028                 0x38200, 0x38318,
1029                 0x38400, 0x384b4,
1030                 0x384c0, 0x3852c,
1031                 0x38540, 0x3861c,
1032                 0x38800, 0x38828,
1033                 0x38834, 0x38834,
1034                 0x388c0, 0x38908,
1035                 0x38910, 0x389ac,
1036                 0x38a00, 0x38a14,
1037                 0x38a1c, 0x38a2c,
1038                 0x38a44, 0x38a50,
1039                 0x38a74, 0x38a74,
1040                 0x38a7c, 0x38afc,
1041                 0x38b08, 0x38c24,
1042                 0x38d00, 0x38d00,
1043                 0x38d08, 0x38d14,
1044                 0x38d1c, 0x38d20,
1045                 0x38d3c, 0x38d3c,
1046                 0x38d48, 0x38d50,
1047                 0x39200, 0x3920c,
1048                 0x39220, 0x39220,
1049                 0x39240, 0x39240,
1050                 0x39600, 0x3960c,
1051                 0x39a00, 0x39a1c,
1052                 0x39e00, 0x39e20,
1053                 0x39e38, 0x39e3c,
1054                 0x39e80, 0x39e80,
1055                 0x39e88, 0x39ea8,
1056                 0x39eb0, 0x39eb4,
1057                 0x39ec8, 0x39ed4,
1058                 0x39fb8, 0x3a004,
1059                 0x3a200, 0x3a200,
1060                 0x3a208, 0x3a240,
1061                 0x3a248, 0x3a280,
1062                 0x3a288, 0x3a2c0,
1063                 0x3a2c8, 0x3a2fc,
1064                 0x3a600, 0x3a630,
1065                 0x3aa00, 0x3aabc,
1066                 0x3ab00, 0x3ab10,
1067                 0x3ab20, 0x3ab30,
1068                 0x3ab40, 0x3ab50,
1069                 0x3ab60, 0x3ab70,
1070                 0x3b000, 0x3b028,
1071                 0x3b030, 0x3b048,
1072                 0x3b060, 0x3b068,
1073                 0x3b070, 0x3b09c,
1074                 0x3b0f0, 0x3b128,
1075                 0x3b130, 0x3b148,
1076                 0x3b160, 0x3b168,
1077                 0x3b170, 0x3b19c,
1078                 0x3b1f0, 0x3b238,
1079                 0x3b240, 0x3b240,
1080                 0x3b248, 0x3b250,
1081                 0x3b25c, 0x3b264,
1082                 0x3b270, 0x3b2b8,
1083                 0x3b2c0, 0x3b2e4,
1084                 0x3b2f8, 0x3b338,
1085                 0x3b340, 0x3b340,
1086                 0x3b348, 0x3b350,
1087                 0x3b35c, 0x3b364,
1088                 0x3b370, 0x3b3b8,
1089                 0x3b3c0, 0x3b3e4,
1090                 0x3b3f8, 0x3b428,
1091                 0x3b430, 0x3b448,
1092                 0x3b460, 0x3b468,
1093                 0x3b470, 0x3b49c,
1094                 0x3b4f0, 0x3b528,
1095                 0x3b530, 0x3b548,
1096                 0x3b560, 0x3b568,
1097                 0x3b570, 0x3b59c,
1098                 0x3b5f0, 0x3b638,
1099                 0x3b640, 0x3b640,
1100                 0x3b648, 0x3b650,
1101                 0x3b65c, 0x3b664,
1102                 0x3b670, 0x3b6b8,
1103                 0x3b6c0, 0x3b6e4,
1104                 0x3b6f8, 0x3b738,
1105                 0x3b740, 0x3b740,
1106                 0x3b748, 0x3b750,
1107                 0x3b75c, 0x3b764,
1108                 0x3b770, 0x3b7b8,
1109                 0x3b7c0, 0x3b7e4,
1110                 0x3b7f8, 0x3b7fc,
1111                 0x3b814, 0x3b814,
1112                 0x3b82c, 0x3b82c,
1113                 0x3b880, 0x3b88c,
1114                 0x3b8e8, 0x3b8ec,
1115                 0x3b900, 0x3b928,
1116                 0x3b930, 0x3b948,
1117                 0x3b960, 0x3b968,
1118                 0x3b970, 0x3b99c,
1119                 0x3b9f0, 0x3ba38,
1120                 0x3ba40, 0x3ba40,
1121                 0x3ba48, 0x3ba50,
1122                 0x3ba5c, 0x3ba64,
1123                 0x3ba70, 0x3bab8,
1124                 0x3bac0, 0x3bae4,
1125                 0x3baf8, 0x3bb10,
1126                 0x3bb28, 0x3bb28,
1127                 0x3bb3c, 0x3bb50,
1128                 0x3bbf0, 0x3bc10,
1129                 0x3bc28, 0x3bc28,
1130                 0x3bc3c, 0x3bc50,
1131                 0x3bcf0, 0x3bcfc,
1132                 0x3c000, 0x3c030,
1133                 0x3c038, 0x3c038,
1134                 0x3c040, 0x3c040,
1135                 0x3c100, 0x3c144,
1136                 0x3c190, 0x3c1a0,
1137                 0x3c1a8, 0x3c1b8,
1138                 0x3c1c4, 0x3c1c8,
1139                 0x3c1d0, 0x3c1d0,
1140                 0x3c200, 0x3c318,
1141                 0x3c400, 0x3c4b4,
1142                 0x3c4c0, 0x3c52c,
1143                 0x3c540, 0x3c61c,
1144                 0x3c800, 0x3c828,
1145                 0x3c834, 0x3c834,
1146                 0x3c8c0, 0x3c908,
1147                 0x3c910, 0x3c9ac,
1148                 0x3ca00, 0x3ca14,
1149                 0x3ca1c, 0x3ca2c,
1150                 0x3ca44, 0x3ca50,
1151                 0x3ca74, 0x3ca74,
1152                 0x3ca7c, 0x3cafc,
1153                 0x3cb08, 0x3cc24,
1154                 0x3cd00, 0x3cd00,
1155                 0x3cd08, 0x3cd14,
1156                 0x3cd1c, 0x3cd20,
1157                 0x3cd3c, 0x3cd3c,
1158                 0x3cd48, 0x3cd50,
1159                 0x3d200, 0x3d20c,
1160                 0x3d220, 0x3d220,
1161                 0x3d240, 0x3d240,
1162                 0x3d600, 0x3d60c,
1163                 0x3da00, 0x3da1c,
1164                 0x3de00, 0x3de20,
1165                 0x3de38, 0x3de3c,
1166                 0x3de80, 0x3de80,
1167                 0x3de88, 0x3dea8,
1168                 0x3deb0, 0x3deb4,
1169                 0x3dec8, 0x3ded4,
1170                 0x3dfb8, 0x3e004,
1171                 0x3e200, 0x3e200,
1172                 0x3e208, 0x3e240,
1173                 0x3e248, 0x3e280,
1174                 0x3e288, 0x3e2c0,
1175                 0x3e2c8, 0x3e2fc,
1176                 0x3e600, 0x3e630,
1177                 0x3ea00, 0x3eabc,
1178                 0x3eb00, 0x3eb10,
1179                 0x3eb20, 0x3eb30,
1180                 0x3eb40, 0x3eb50,
1181                 0x3eb60, 0x3eb70,
1182                 0x3f000, 0x3f028,
1183                 0x3f030, 0x3f048,
1184                 0x3f060, 0x3f068,
1185                 0x3f070, 0x3f09c,
1186                 0x3f0f0, 0x3f128,
1187                 0x3f130, 0x3f148,
1188                 0x3f160, 0x3f168,
1189                 0x3f170, 0x3f19c,
1190                 0x3f1f0, 0x3f238,
1191                 0x3f240, 0x3f240,
1192                 0x3f248, 0x3f250,
1193                 0x3f25c, 0x3f264,
1194                 0x3f270, 0x3f2b8,
1195                 0x3f2c0, 0x3f2e4,
1196                 0x3f2f8, 0x3f338,
1197                 0x3f340, 0x3f340,
1198                 0x3f348, 0x3f350,
1199                 0x3f35c, 0x3f364,
1200                 0x3f370, 0x3f3b8,
1201                 0x3f3c0, 0x3f3e4,
1202                 0x3f3f8, 0x3f428,
1203                 0x3f430, 0x3f448,
1204                 0x3f460, 0x3f468,
1205                 0x3f470, 0x3f49c,
1206                 0x3f4f0, 0x3f528,
1207                 0x3f530, 0x3f548,
1208                 0x3f560, 0x3f568,
1209                 0x3f570, 0x3f59c,
1210                 0x3f5f0, 0x3f638,
1211                 0x3f640, 0x3f640,
1212                 0x3f648, 0x3f650,
1213                 0x3f65c, 0x3f664,
1214                 0x3f670, 0x3f6b8,
1215                 0x3f6c0, 0x3f6e4,
1216                 0x3f6f8, 0x3f738,
1217                 0x3f740, 0x3f740,
1218                 0x3f748, 0x3f750,
1219                 0x3f75c, 0x3f764,
1220                 0x3f770, 0x3f7b8,
1221                 0x3f7c0, 0x3f7e4,
1222                 0x3f7f8, 0x3f7fc,
1223                 0x3f814, 0x3f814,
1224                 0x3f82c, 0x3f82c,
1225                 0x3f880, 0x3f88c,
1226                 0x3f8e8, 0x3f8ec,
1227                 0x3f900, 0x3f928,
1228                 0x3f930, 0x3f948,
1229                 0x3f960, 0x3f968,
1230                 0x3f970, 0x3f99c,
1231                 0x3f9f0, 0x3fa38,
1232                 0x3fa40, 0x3fa40,
1233                 0x3fa48, 0x3fa50,
1234                 0x3fa5c, 0x3fa64,
1235                 0x3fa70, 0x3fab8,
1236                 0x3fac0, 0x3fae4,
1237                 0x3faf8, 0x3fb10,
1238                 0x3fb28, 0x3fb28,
1239                 0x3fb3c, 0x3fb50,
1240                 0x3fbf0, 0x3fc10,
1241                 0x3fc28, 0x3fc28,
1242                 0x3fc3c, 0x3fc50,
1243                 0x3fcf0, 0x3fcfc,
1244                 0x40000, 0x4000c,
1245                 0x40040, 0x40050,
1246                 0x40060, 0x40068,
1247                 0x4007c, 0x4008c,
1248                 0x40094, 0x400b0,
1249                 0x400c0, 0x40144,
1250                 0x40180, 0x4018c,
1251                 0x40200, 0x40254,
1252                 0x40260, 0x40264,
1253                 0x40270, 0x40288,
1254                 0x40290, 0x40298,
1255                 0x402ac, 0x402c8,
1256                 0x402d0, 0x402e0,
1257                 0x402f0, 0x402f0,
1258                 0x40300, 0x4033c,
1259                 0x403f8, 0x403fc,
1260                 0x41304, 0x413c4,
1261                 0x41400, 0x4140c,
1262                 0x41414, 0x4141c,
1263                 0x41480, 0x414d0,
1264                 0x44000, 0x44054,
1265                 0x4405c, 0x44078,
1266                 0x440c0, 0x44174,
1267                 0x44180, 0x441ac,
1268                 0x441b4, 0x441b8,
1269                 0x441c0, 0x44254,
1270                 0x4425c, 0x44278,
1271                 0x442c0, 0x44374,
1272                 0x44380, 0x443ac,
1273                 0x443b4, 0x443b8,
1274                 0x443c0, 0x44454,
1275                 0x4445c, 0x44478,
1276                 0x444c0, 0x44574,
1277                 0x44580, 0x445ac,
1278                 0x445b4, 0x445b8,
1279                 0x445c0, 0x44654,
1280                 0x4465c, 0x44678,
1281                 0x446c0, 0x44774,
1282                 0x44780, 0x447ac,
1283                 0x447b4, 0x447b8,
1284                 0x447c0, 0x44854,
1285                 0x4485c, 0x44878,
1286                 0x448c0, 0x44974,
1287                 0x44980, 0x449ac,
1288                 0x449b4, 0x449b8,
1289                 0x449c0, 0x449fc,
1290                 0x45000, 0x45004,
1291                 0x45010, 0x45030,
1292                 0x45040, 0x45060,
1293                 0x45068, 0x45068,
1294                 0x45080, 0x45084,
1295                 0x450a0, 0x450b0,
1296                 0x45200, 0x45204,
1297                 0x45210, 0x45230,
1298                 0x45240, 0x45260,
1299                 0x45268, 0x45268,
1300                 0x45280, 0x45284,
1301                 0x452a0, 0x452b0,
1302                 0x460c0, 0x460e4,
1303                 0x47000, 0x4703c,
1304                 0x47044, 0x4708c,
1305                 0x47200, 0x47250,
1306                 0x47400, 0x47408,
1307                 0x47414, 0x47420,
1308                 0x47600, 0x47618,
1309                 0x47800, 0x47814,
1310                 0x48000, 0x4800c,
1311                 0x48040, 0x48050,
1312                 0x48060, 0x48068,
1313                 0x4807c, 0x4808c,
1314                 0x48094, 0x480b0,
1315                 0x480c0, 0x48144,
1316                 0x48180, 0x4818c,
1317                 0x48200, 0x48254,
1318                 0x48260, 0x48264,
1319                 0x48270, 0x48288,
1320                 0x48290, 0x48298,
1321                 0x482ac, 0x482c8,
1322                 0x482d0, 0x482e0,
1323                 0x482f0, 0x482f0,
1324                 0x48300, 0x4833c,
1325                 0x483f8, 0x483fc,
1326                 0x49304, 0x493c4,
1327                 0x49400, 0x4940c,
1328                 0x49414, 0x4941c,
1329                 0x49480, 0x494d0,
1330                 0x4c000, 0x4c054,
1331                 0x4c05c, 0x4c078,
1332                 0x4c0c0, 0x4c174,
1333                 0x4c180, 0x4c1ac,
1334                 0x4c1b4, 0x4c1b8,
1335                 0x4c1c0, 0x4c254,
1336                 0x4c25c, 0x4c278,
1337                 0x4c2c0, 0x4c374,
1338                 0x4c380, 0x4c3ac,
1339                 0x4c3b4, 0x4c3b8,
1340                 0x4c3c0, 0x4c454,
1341                 0x4c45c, 0x4c478,
1342                 0x4c4c0, 0x4c574,
1343                 0x4c580, 0x4c5ac,
1344                 0x4c5b4, 0x4c5b8,
1345                 0x4c5c0, 0x4c654,
1346                 0x4c65c, 0x4c678,
1347                 0x4c6c0, 0x4c774,
1348                 0x4c780, 0x4c7ac,
1349                 0x4c7b4, 0x4c7b8,
1350                 0x4c7c0, 0x4c854,
1351                 0x4c85c, 0x4c878,
1352                 0x4c8c0, 0x4c974,
1353                 0x4c980, 0x4c9ac,
1354                 0x4c9b4, 0x4c9b8,
1355                 0x4c9c0, 0x4c9fc,
1356                 0x4d000, 0x4d004,
1357                 0x4d010, 0x4d030,
1358                 0x4d040, 0x4d060,
1359                 0x4d068, 0x4d068,
1360                 0x4d080, 0x4d084,
1361                 0x4d0a0, 0x4d0b0,
1362                 0x4d200, 0x4d204,
1363                 0x4d210, 0x4d230,
1364                 0x4d240, 0x4d260,
1365                 0x4d268, 0x4d268,
1366                 0x4d280, 0x4d284,
1367                 0x4d2a0, 0x4d2b0,
1368                 0x4e0c0, 0x4e0e4,
1369                 0x4f000, 0x4f03c,
1370                 0x4f044, 0x4f08c,
1371                 0x4f200, 0x4f250,
1372                 0x4f400, 0x4f408,
1373                 0x4f414, 0x4f420,
1374                 0x4f600, 0x4f618,
1375                 0x4f800, 0x4f814,
1376                 0x50000, 0x50084,
1377                 0x50090, 0x500cc,
1378                 0x50400, 0x50400,
1379                 0x50800, 0x50884,
1380                 0x50890, 0x508cc,
1381                 0x50c00, 0x50c00,
1382                 0x51000, 0x5101c,
1383                 0x51300, 0x51308,
1384         };
1385
1386         static const unsigned int t6_reg_ranges[] = {
1387                 0x1008, 0x101c,
1388                 0x1024, 0x10a8,
1389                 0x10b4, 0x10f8,
1390                 0x1100, 0x1114,
1391                 0x111c, 0x112c,
1392                 0x1138, 0x113c,
1393                 0x1144, 0x114c,
1394                 0x1180, 0x1184,
1395                 0x1190, 0x1194,
1396                 0x11a0, 0x11a4,
1397                 0x11b0, 0x11b4,
1398                 0x11fc, 0x1274,
1399                 0x1280, 0x133c,
1400                 0x1800, 0x18fc,
1401                 0x3000, 0x302c,
1402                 0x3060, 0x30b0,
1403                 0x30b8, 0x30d8,
1404                 0x30e0, 0x30fc,
1405                 0x3140, 0x357c,
1406                 0x35a8, 0x35cc,
1407                 0x35ec, 0x35ec,
1408                 0x3600, 0x5624,
1409                 0x56cc, 0x56ec,
1410                 0x56f4, 0x5720,
1411                 0x5728, 0x575c,
1412                 0x580c, 0x5814,
1413                 0x5890, 0x589c,
1414                 0x58a4, 0x58ac,
1415                 0x58b8, 0x58bc,
1416                 0x5940, 0x595c,
1417                 0x5980, 0x598c,
1418                 0x59b0, 0x59c8,
1419                 0x59d0, 0x59dc,
1420                 0x59fc, 0x5a18,
1421                 0x5a60, 0x5a6c,
1422                 0x5a80, 0x5a8c,
1423                 0x5a94, 0x5a9c,
1424                 0x5b94, 0x5bfc,
1425                 0x5c10, 0x5e48,
1426                 0x5e50, 0x5e94,
1427                 0x5ea0, 0x5eb0,
1428                 0x5ec0, 0x5ec0,
1429                 0x5ec8, 0x5ed0,
1430                 0x5ee0, 0x5ee0,
1431                 0x5ef0, 0x5ef0,
1432                 0x5f00, 0x5f00,
1433                 0x6000, 0x6020,
1434                 0x6028, 0x6040,
1435                 0x6058, 0x609c,
1436                 0x60a8, 0x619c,
1437                 0x7700, 0x7798,
1438                 0x77c0, 0x7880,
1439                 0x78cc, 0x78fc,
1440                 0x7b00, 0x7b58,
1441                 0x7b60, 0x7b84,
1442                 0x7b8c, 0x7c54,
1443                 0x7d00, 0x7d38,
1444                 0x7d40, 0x7d84,
1445                 0x7d8c, 0x7ddc,
1446                 0x7de4, 0x7e04,
1447                 0x7e10, 0x7e1c,
1448                 0x7e24, 0x7e38,
1449                 0x7e40, 0x7e44,
1450                 0x7e4c, 0x7e78,
1451                 0x7e80, 0x7edc,
1452                 0x7ee8, 0x7efc,
1453                 0x8dc0, 0x8de4,
1454                 0x8df8, 0x8e04,
1455                 0x8e10, 0x8e84,
1456                 0x8ea0, 0x8f88,
1457                 0x8fb8, 0x9058,
1458                 0x9060, 0x9060,
1459                 0x9068, 0x90f8,
1460                 0x9100, 0x9124,
1461                 0x9400, 0x9470,
1462                 0x9600, 0x9600,
1463                 0x9608, 0x9638,
1464                 0x9640, 0x9704,
1465                 0x9710, 0x971c,
1466                 0x9800, 0x9808,
1467                 0x9820, 0x983c,
1468                 0x9850, 0x9864,
1469                 0x9c00, 0x9c6c,
1470                 0x9c80, 0x9cec,
1471                 0x9d00, 0x9d6c,
1472                 0x9d80, 0x9dec,
1473                 0x9e00, 0x9e6c,
1474                 0x9e80, 0x9eec,
1475                 0x9f00, 0x9f6c,
1476                 0x9f80, 0xa020,
1477                 0xd004, 0xd03c,
1478                 0xd100, 0xd118,
1479                 0xd200, 0xd214,
1480                 0xd220, 0xd234,
1481                 0xd240, 0xd254,
1482                 0xd260, 0xd274,
1483                 0xd280, 0xd294,
1484                 0xd2a0, 0xd2b4,
1485                 0xd2c0, 0xd2d4,
1486                 0xd2e0, 0xd2f4,
1487                 0xd300, 0xd31c,
1488                 0xdfc0, 0xdfe0,
1489                 0xe000, 0xf008,
1490                 0xf010, 0xf018,
1491                 0xf020, 0xf028,
1492                 0x11000, 0x11014,
1493                 0x11048, 0x1106c,
1494                 0x11074, 0x11088,
1495                 0x11098, 0x11120,
1496                 0x1112c, 0x1117c,
1497                 0x11190, 0x112e0,
1498                 0x11300, 0x1130c,
1499                 0x12000, 0x1206c,
1500                 0x19040, 0x1906c,
1501                 0x19078, 0x19080,
1502                 0x1908c, 0x190e8,
1503                 0x190f0, 0x190f8,
1504                 0x19100, 0x19110,
1505                 0x19120, 0x19124,
1506                 0x19150, 0x19194,
1507                 0x1919c, 0x191b0,
1508                 0x191d0, 0x191e8,
1509                 0x19238, 0x19290,
1510                 0x192a4, 0x192b0,
1511                 0x192bc, 0x192bc,
1512                 0x19348, 0x1934c,
1513                 0x193f8, 0x19418,
1514                 0x19420, 0x19428,
1515                 0x19430, 0x19444,
1516                 0x1944c, 0x1946c,
1517                 0x19474, 0x19474,
1518                 0x19490, 0x194cc,
1519                 0x194f0, 0x194f8,
1520                 0x19c00, 0x19c48,
1521                 0x19c50, 0x19c80,
1522                 0x19c94, 0x19c98,
1523                 0x19ca0, 0x19cbc,
1524                 0x19ce4, 0x19ce4,
1525                 0x19cf0, 0x19cf8,
1526                 0x19d00, 0x19d28,
1527                 0x19d50, 0x19d78,
1528                 0x19d94, 0x19d98,
1529                 0x19da0, 0x19dc8,
1530                 0x19df0, 0x19e10,
1531                 0x19e50, 0x19e6c,
1532                 0x19ea0, 0x19ebc,
1533                 0x19ec4, 0x19ef4,
1534                 0x19f04, 0x19f2c,
1535                 0x19f34, 0x19f34,
1536                 0x19f40, 0x19f50,
1537                 0x19f90, 0x19fac,
1538                 0x19fc4, 0x19fc8,
1539                 0x19fd0, 0x19fe4,
1540                 0x1a000, 0x1a004,
1541                 0x1a010, 0x1a06c,
1542                 0x1a0b0, 0x1a0e4,
1543                 0x1a0ec, 0x1a0f8,
1544                 0x1a100, 0x1a108,
1545                 0x1a114, 0x1a120,
1546                 0x1a128, 0x1a130,
1547                 0x1a138, 0x1a138,
1548                 0x1a190, 0x1a1c4,
1549                 0x1a1fc, 0x1a1fc,
1550                 0x1e008, 0x1e00c,
1551                 0x1e040, 0x1e044,
1552                 0x1e04c, 0x1e04c,
1553                 0x1e284, 0x1e290,
1554                 0x1e2c0, 0x1e2c0,
1555                 0x1e2e0, 0x1e2e0,
1556                 0x1e300, 0x1e384,
1557                 0x1e3c0, 0x1e3c8,
1558                 0x1e408, 0x1e40c,
1559                 0x1e440, 0x1e444,
1560                 0x1e44c, 0x1e44c,
1561                 0x1e684, 0x1e690,
1562                 0x1e6c0, 0x1e6c0,
1563                 0x1e6e0, 0x1e6e0,
1564                 0x1e700, 0x1e784,
1565                 0x1e7c0, 0x1e7c8,
1566                 0x1e808, 0x1e80c,
1567                 0x1e840, 0x1e844,
1568                 0x1e84c, 0x1e84c,
1569                 0x1ea84, 0x1ea90,
1570                 0x1eac0, 0x1eac0,
1571                 0x1eae0, 0x1eae0,
1572                 0x1eb00, 0x1eb84,
1573                 0x1ebc0, 0x1ebc8,
1574                 0x1ec08, 0x1ec0c,
1575                 0x1ec40, 0x1ec44,
1576                 0x1ec4c, 0x1ec4c,
1577                 0x1ee84, 0x1ee90,
1578                 0x1eec0, 0x1eec0,
1579                 0x1eee0, 0x1eee0,
1580                 0x1ef00, 0x1ef84,
1581                 0x1efc0, 0x1efc8,
1582                 0x1f008, 0x1f00c,
1583                 0x1f040, 0x1f044,
1584                 0x1f04c, 0x1f04c,
1585                 0x1f284, 0x1f290,
1586                 0x1f2c0, 0x1f2c0,
1587                 0x1f2e0, 0x1f2e0,
1588                 0x1f300, 0x1f384,
1589                 0x1f3c0, 0x1f3c8,
1590                 0x1f408, 0x1f40c,
1591                 0x1f440, 0x1f444,
1592                 0x1f44c, 0x1f44c,
1593                 0x1f684, 0x1f690,
1594                 0x1f6c0, 0x1f6c0,
1595                 0x1f6e0, 0x1f6e0,
1596                 0x1f700, 0x1f784,
1597                 0x1f7c0, 0x1f7c8,
1598                 0x1f808, 0x1f80c,
1599                 0x1f840, 0x1f844,
1600                 0x1f84c, 0x1f84c,
1601                 0x1fa84, 0x1fa90,
1602                 0x1fac0, 0x1fac0,
1603                 0x1fae0, 0x1fae0,
1604                 0x1fb00, 0x1fb84,
1605                 0x1fbc0, 0x1fbc8,
1606                 0x1fc08, 0x1fc0c,
1607                 0x1fc40, 0x1fc44,
1608                 0x1fc4c, 0x1fc4c,
1609                 0x1fe84, 0x1fe90,
1610                 0x1fec0, 0x1fec0,
1611                 0x1fee0, 0x1fee0,
1612                 0x1ff00, 0x1ff84,
1613                 0x1ffc0, 0x1ffc8,
1614                 0x30000, 0x30030,
1615                 0x30100, 0x30168,
1616                 0x30190, 0x301a0,
1617                 0x301a8, 0x301b8,
1618                 0x301c4, 0x301c8,
1619                 0x301d0, 0x301d0,
1620                 0x30200, 0x30320,
1621                 0x30400, 0x304b4,
1622                 0x304c0, 0x3052c,
1623                 0x30540, 0x3061c,
1624                 0x30800, 0x308a0,
1625                 0x308c0, 0x30908,
1626                 0x30910, 0x309b8,
1627                 0x30a00, 0x30a04,
1628                 0x30a0c, 0x30a14,
1629                 0x30a1c, 0x30a2c,
1630                 0x30a44, 0x30a50,
1631                 0x30a74, 0x30a74,
1632                 0x30a7c, 0x30afc,
1633                 0x30b08, 0x30c24,
1634                 0x30d00, 0x30d14,
1635                 0x30d1c, 0x30d3c,
1636                 0x30d44, 0x30d4c,
1637                 0x30d54, 0x30d74,
1638                 0x30d7c, 0x30d7c,
1639                 0x30de0, 0x30de0,
1640                 0x30e00, 0x30ed4,
1641                 0x30f00, 0x30fa4,
1642                 0x30fc0, 0x30fc4,
1643                 0x31000, 0x31004,
1644                 0x31080, 0x310fc,
1645                 0x31208, 0x31220,
1646                 0x3123c, 0x31254,
1647                 0x31300, 0x31300,
1648                 0x31308, 0x3131c,
1649                 0x31338, 0x3133c,
1650                 0x31380, 0x31380,
1651                 0x31388, 0x313a8,
1652                 0x313b4, 0x313b4,
1653                 0x31400, 0x31420,
1654                 0x31438, 0x3143c,
1655                 0x31480, 0x31480,
1656                 0x314a8, 0x314a8,
1657                 0x314b0, 0x314b4,
1658                 0x314c8, 0x314d4,
1659                 0x31a40, 0x31a4c,
1660                 0x31af0, 0x31b20,
1661                 0x31b38, 0x31b3c,
1662                 0x31b80, 0x31b80,
1663                 0x31ba8, 0x31ba8,
1664                 0x31bb0, 0x31bb4,
1665                 0x31bc8, 0x31bd4,
1666                 0x32140, 0x3218c,
1667                 0x321f0, 0x321f4,
1668                 0x32200, 0x32200,
1669                 0x32218, 0x32218,
1670                 0x32400, 0x32400,
1671                 0x32408, 0x3241c,
1672                 0x32618, 0x32620,
1673                 0x32664, 0x32664,
1674                 0x326a8, 0x326a8,
1675                 0x326ec, 0x326ec,
1676                 0x32a00, 0x32abc,
1677                 0x32b00, 0x32b38,
1678                 0x32b20, 0x32b38,
1679                 0x32b40, 0x32b58,
1680                 0x32b60, 0x32b78,
1681                 0x32c00, 0x32c00,
1682                 0x32c08, 0x32c3c,
1683                 0x33000, 0x3302c,
1684                 0x33034, 0x33050,
1685                 0x33058, 0x33058,
1686                 0x33060, 0x3308c,
1687                 0x3309c, 0x330ac,
1688                 0x330c0, 0x330c0,
1689                 0x330c8, 0x330d0,
1690                 0x330d8, 0x330e0,
1691                 0x330ec, 0x3312c,
1692                 0x33134, 0x33150,
1693                 0x33158, 0x33158,
1694                 0x33160, 0x3318c,
1695                 0x3319c, 0x331ac,
1696                 0x331c0, 0x331c0,
1697                 0x331c8, 0x331d0,
1698                 0x331d8, 0x331e0,
1699                 0x331ec, 0x33290,
1700                 0x33298, 0x332c4,
1701                 0x332e4, 0x33390,
1702                 0x33398, 0x333c4,
1703                 0x333e4, 0x3342c,
1704                 0x33434, 0x33450,
1705                 0x33458, 0x33458,
1706                 0x33460, 0x3348c,
1707                 0x3349c, 0x334ac,
1708                 0x334c0, 0x334c0,
1709                 0x334c8, 0x334d0,
1710                 0x334d8, 0x334e0,
1711                 0x334ec, 0x3352c,
1712                 0x33534, 0x33550,
1713                 0x33558, 0x33558,
1714                 0x33560, 0x3358c,
1715                 0x3359c, 0x335ac,
1716                 0x335c0, 0x335c0,
1717                 0x335c8, 0x335d0,
1718                 0x335d8, 0x335e0,
1719                 0x335ec, 0x33690,
1720                 0x33698, 0x336c4,
1721                 0x336e4, 0x33790,
1722                 0x33798, 0x337c4,
1723                 0x337e4, 0x337fc,
1724                 0x33814, 0x33814,
1725                 0x33854, 0x33868,
1726                 0x33880, 0x3388c,
1727                 0x338c0, 0x338d0,
1728                 0x338e8, 0x338ec,
1729                 0x33900, 0x3392c,
1730                 0x33934, 0x33950,
1731                 0x33958, 0x33958,
1732                 0x33960, 0x3398c,
1733                 0x3399c, 0x339ac,
1734                 0x339c0, 0x339c0,
1735                 0x339c8, 0x339d0,
1736                 0x339d8, 0x339e0,
1737                 0x339ec, 0x33a90,
1738                 0x33a98, 0x33ac4,
1739                 0x33ae4, 0x33b10,
1740                 0x33b24, 0x33b28,
1741                 0x33b38, 0x33b50,
1742                 0x33bf0, 0x33c10,
1743                 0x33c24, 0x33c28,
1744                 0x33c38, 0x33c50,
1745                 0x33cf0, 0x33cfc,
1746                 0x34000, 0x34030,
1747                 0x34100, 0x34168,
1748                 0x34190, 0x341a0,
1749                 0x341a8, 0x341b8,
1750                 0x341c4, 0x341c8,
1751                 0x341d0, 0x341d0,
1752                 0x34200, 0x34320,
1753                 0x34400, 0x344b4,
1754                 0x344c0, 0x3452c,
1755                 0x34540, 0x3461c,
1756                 0x34800, 0x348a0,
1757                 0x348c0, 0x34908,
1758                 0x34910, 0x349b8,
1759                 0x34a00, 0x34a04,
1760                 0x34a0c, 0x34a14,
1761                 0x34a1c, 0x34a2c,
1762                 0x34a44, 0x34a50,
1763                 0x34a74, 0x34a74,
1764                 0x34a7c, 0x34afc,
1765                 0x34b08, 0x34c24,
1766                 0x34d00, 0x34d14,
1767                 0x34d1c, 0x34d3c,
1768                 0x34d44, 0x34d4c,
1769                 0x34d54, 0x34d74,
1770                 0x34d7c, 0x34d7c,
1771                 0x34de0, 0x34de0,
1772                 0x34e00, 0x34ed4,
1773                 0x34f00, 0x34fa4,
1774                 0x34fc0, 0x34fc4,
1775                 0x35000, 0x35004,
1776                 0x35080, 0x350fc,
1777                 0x35208, 0x35220,
1778                 0x3523c, 0x35254,
1779                 0x35300, 0x35300,
1780                 0x35308, 0x3531c,
1781                 0x35338, 0x3533c,
1782                 0x35380, 0x35380,
1783                 0x35388, 0x353a8,
1784                 0x353b4, 0x353b4,
1785                 0x35400, 0x35420,
1786                 0x35438, 0x3543c,
1787                 0x35480, 0x35480,
1788                 0x354a8, 0x354a8,
1789                 0x354b0, 0x354b4,
1790                 0x354c8, 0x354d4,
1791                 0x35a40, 0x35a4c,
1792                 0x35af0, 0x35b20,
1793                 0x35b38, 0x35b3c,
1794                 0x35b80, 0x35b80,
1795                 0x35ba8, 0x35ba8,
1796                 0x35bb0, 0x35bb4,
1797                 0x35bc8, 0x35bd4,
1798                 0x36140, 0x3618c,
1799                 0x361f0, 0x361f4,
1800                 0x36200, 0x36200,
1801                 0x36218, 0x36218,
1802                 0x36400, 0x36400,
1803                 0x36408, 0x3641c,
1804                 0x36618, 0x36620,
1805                 0x36664, 0x36664,
1806                 0x366a8, 0x366a8,
1807                 0x366ec, 0x366ec,
1808                 0x36a00, 0x36abc,
1809                 0x36b00, 0x36b38,
1810                 0x36b20, 0x36b38,
1811                 0x36b40, 0x36b58,
1812                 0x36b60, 0x36b78,
1813                 0x36c00, 0x36c00,
1814                 0x36c08, 0x36c3c,
1815                 0x37000, 0x3702c,
1816                 0x37034, 0x37050,
1817                 0x37058, 0x37058,
1818                 0x37060, 0x3708c,
1819                 0x3709c, 0x370ac,
1820                 0x370c0, 0x370c0,
1821                 0x370c8, 0x370d0,
1822                 0x370d8, 0x370e0,
1823                 0x370ec, 0x3712c,
1824                 0x37134, 0x37150,
1825                 0x37158, 0x37158,
1826                 0x37160, 0x3718c,
1827                 0x3719c, 0x371ac,
1828                 0x371c0, 0x371c0,
1829                 0x371c8, 0x371d0,
1830                 0x371d8, 0x371e0,
1831                 0x371ec, 0x37290,
1832                 0x37298, 0x372c4,
1833                 0x372e4, 0x37390,
1834                 0x37398, 0x373c4,
1835                 0x373e4, 0x3742c,
1836                 0x37434, 0x37450,
1837                 0x37458, 0x37458,
1838                 0x37460, 0x3748c,
1839                 0x3749c, 0x374ac,
1840                 0x374c0, 0x374c0,
1841                 0x374c8, 0x374d0,
1842                 0x374d8, 0x374e0,
1843                 0x374ec, 0x3752c,
1844                 0x37534, 0x37550,
1845                 0x37558, 0x37558,
1846                 0x37560, 0x3758c,
1847                 0x3759c, 0x375ac,
1848                 0x375c0, 0x375c0,
1849                 0x375c8, 0x375d0,
1850                 0x375d8, 0x375e0,
1851                 0x375ec, 0x37690,
1852                 0x37698, 0x376c4,
1853                 0x376e4, 0x37790,
1854                 0x37798, 0x377c4,
1855                 0x377e4, 0x377fc,
1856                 0x37814, 0x37814,
1857                 0x37854, 0x37868,
1858                 0x37880, 0x3788c,
1859                 0x378c0, 0x378d0,
1860                 0x378e8, 0x378ec,
1861                 0x37900, 0x3792c,
1862                 0x37934, 0x37950,
1863                 0x37958, 0x37958,
1864                 0x37960, 0x3798c,
1865                 0x3799c, 0x379ac,
1866                 0x379c0, 0x379c0,
1867                 0x379c8, 0x379d0,
1868                 0x379d8, 0x379e0,
1869                 0x379ec, 0x37a90,
1870                 0x37a98, 0x37ac4,
1871                 0x37ae4, 0x37b10,
1872                 0x37b24, 0x37b28,
1873                 0x37b38, 0x37b50,
1874                 0x37bf0, 0x37c10,
1875                 0x37c24, 0x37c28,
1876                 0x37c38, 0x37c50,
1877                 0x37cf0, 0x37cfc,
1878                 0x40040, 0x40040,
1879                 0x40080, 0x40084,
1880                 0x40100, 0x40100,
1881                 0x40140, 0x401bc,
1882                 0x40200, 0x40214,
1883                 0x40228, 0x40228,
1884                 0x40240, 0x40258,
1885                 0x40280, 0x40280,
1886                 0x40304, 0x40304,
1887                 0x40330, 0x4033c,
1888                 0x41304, 0x413c8,
1889                 0x413d0, 0x413dc,
1890                 0x413f0, 0x413f0,
1891                 0x41400, 0x4140c,
1892                 0x41414, 0x4141c,
1893                 0x41480, 0x414d0,
1894                 0x44000, 0x4407c,
1895                 0x440c0, 0x441ac,
1896                 0x441b4, 0x4427c,
1897                 0x442c0, 0x443ac,
1898                 0x443b4, 0x4447c,
1899                 0x444c0, 0x445ac,
1900                 0x445b4, 0x4467c,
1901                 0x446c0, 0x447ac,
1902                 0x447b4, 0x4487c,
1903                 0x448c0, 0x449ac,
1904                 0x449b4, 0x44a7c,
1905                 0x44ac0, 0x44bac,
1906                 0x44bb4, 0x44c7c,
1907                 0x44cc0, 0x44dac,
1908                 0x44db4, 0x44e7c,
1909                 0x44ec0, 0x44fac,
1910                 0x44fb4, 0x4507c,
1911                 0x450c0, 0x451ac,
1912                 0x451b4, 0x451fc,
1913                 0x45800, 0x45804,
1914                 0x45810, 0x45830,
1915                 0x45840, 0x45860,
1916                 0x45868, 0x45868,
1917                 0x45880, 0x45884,
1918                 0x458a0, 0x458b0,
1919                 0x45a00, 0x45a04,
1920                 0x45a10, 0x45a30,
1921                 0x45a40, 0x45a60,
1922                 0x45a68, 0x45a68,
1923                 0x45a80, 0x45a84,
1924                 0x45aa0, 0x45ab0,
1925                 0x460c0, 0x460e4,
1926                 0x47000, 0x4703c,
1927                 0x47044, 0x4708c,
1928                 0x47200, 0x47250,
1929                 0x47400, 0x47408,
1930                 0x47414, 0x47420,
1931                 0x47600, 0x47618,
1932                 0x47800, 0x47814,
1933                 0x47820, 0x4782c,
1934                 0x50000, 0x50084,
1935                 0x50090, 0x500cc,
1936                 0x50300, 0x50384,
1937                 0x50400, 0x50400,
1938                 0x50800, 0x50884,
1939                 0x50890, 0x508cc,
1940                 0x50b00, 0x50b84,
1941                 0x50c00, 0x50c00,
1942                 0x51000, 0x51020,
1943                 0x51028, 0x510b0,
1944                 0x51300, 0x51324,
1945         };
1946
1947         u32 *buf_end = (u32 *)((char *)buf + buf_size);
1948         const unsigned int *reg_ranges;
1949         int reg_ranges_size, range;
1950         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
1951
1952         /* Select the right set of register ranges to dump depending on the
1953          * adapter chip type.
1954          */
1955         switch (chip_version) {
1956         case CHELSIO_T5:
1957                 reg_ranges = t5_reg_ranges;
1958                 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
1959                 break;
1960
1961         case CHELSIO_T6:
1962                 reg_ranges = t6_reg_ranges;
1963                 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
1964                 break;
1965
1966         default:
1967                 dev_err(adap,
1968                         "Unsupported chip version %d\n", chip_version);
1969                 return;
1970         }
1971
1972         /* Clear the register buffer and insert the appropriate register
1973          * values selected by the above register ranges.
1974          */
1975         memset(buf, 0, buf_size);
1976         for (range = 0; range < reg_ranges_size; range += 2) {
1977                 unsigned int reg = reg_ranges[range];
1978                 unsigned int last_reg = reg_ranges[range + 1];
1979                 u32 *bufp = (u32 *)((char *)buf + reg);
1980
1981                 /* Iterate across the register range filling in the register
1982                  * buffer but don't write past the end of the register buffer.
1983                  */
1984                 while (reg <= last_reg && bufp < buf_end) {
1985                         *bufp++ = t4_read_reg(adap, reg);
1986                         reg += sizeof(u32);
1987                 }
1988         }
1989 }
1990
1991 /* EEPROM reads take a few tens of us while writes can take a bit over 5 ms. */
1992 #define EEPROM_DELAY            10              /* 10us per poll spin */
1993 #define EEPROM_MAX_POLL         5000            /* x 5000 == 50ms */
1994
1995 #define EEPROM_STAT_ADDR        0x7bfc
1996
1997 /**
1998  * Small utility function to wait till any outstanding VPD Access is complete.
1999  * We have a per-adapter state variable "VPD Busy" to indicate when we have a
2000  * VPD Access in flight.  This allows us to handle the problem of having a
2001  * previous VPD Access time out and prevent an attempt to inject a new VPD
2002  * Request before any in-flight VPD request has completed.
2003  */
2004 static int t4_seeprom_wait(struct adapter *adapter)
2005 {
2006         unsigned int base = adapter->params.pci.vpd_cap_addr;
2007         int max_poll;
2008
2009         /* If no VPD Access is in flight, we can just return success right
2010          * away.
2011          */
2012         if (!adapter->vpd_busy)
2013                 return 0;
2014
2015         /* Poll the VPD Capability Address/Flag register waiting for it
2016          * to indicate that the operation is complete.
2017          */
2018         max_poll = EEPROM_MAX_POLL;
2019         do {
2020                 u16 val;
2021
2022                 udelay(EEPROM_DELAY);
2023                 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val);
2024
2025                 /* If the operation is complete, mark the VPD as no longer
2026                  * busy and return success.
2027                  */
2028                 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) {
2029                         adapter->vpd_busy = 0;
2030                         return 0;
2031                 }
2032         } while (--max_poll);
2033
2034         /* Failure!  Note that we leave the VPD Busy status set in order to
2035          * avoid pushing a new VPD Access request into the VPD Capability till
2036          * the current operation eventually succeeds.  It's a bug to issue a
2037          * new request when an existing request is in flight and will result
2038          * in corrupt hardware state.
2039          */
2040         return -ETIMEDOUT;
2041 }
2042
2043 /**
2044  * t4_seeprom_read - read a serial EEPROM location
2045  * @adapter: adapter to read
2046  * @addr: EEPROM virtual address
2047  * @data: where to store the read data
2048  *
2049  * Read a 32-bit word from a location in serial EEPROM using the card's PCI
2050  * VPD capability.  Note that this function must be called with a virtual
2051  * address.
2052  */
2053 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data)
2054 {
2055         unsigned int base = adapter->params.pci.vpd_cap_addr;
2056         int ret;
2057
2058         /* VPD Accesses must alway be 4-byte aligned!
2059          */
2060         if (addr >= EEPROMVSIZE || (addr & 3))
2061                 return -EINVAL;
2062
2063         /* Wait for any previous operation which may still be in flight to
2064          * complete.
2065          */
2066         ret = t4_seeprom_wait(adapter);
2067         if (ret) {
2068                 dev_err(adapter, "VPD still busy from previous operation\n");
2069                 return ret;
2070         }
2071
2072         /* Issue our new VPD Read request, mark the VPD as being busy and wait
2073          * for our request to complete.  If it doesn't complete, note the
2074          * error and return it to our caller.  Note that we do not reset the
2075          * VPD Busy status!
2076          */
2077         t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr);
2078         adapter->vpd_busy = 1;
2079         adapter->vpd_flag = PCI_VPD_ADDR_F;
2080         ret = t4_seeprom_wait(adapter);
2081         if (ret) {
2082                 dev_err(adapter, "VPD read of address %#x failed\n", addr);
2083                 return ret;
2084         }
2085
2086         /* Grab the returned data, swizzle it into our endianness and
2087          * return success.
2088          */
2089         t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data);
2090         *data = le32_to_cpu(*data);
2091         return 0;
2092 }
2093
2094 /**
2095  * t4_seeprom_write - write a serial EEPROM location
2096  * @adapter: adapter to write
2097  * @addr: virtual EEPROM address
2098  * @data: value to write
2099  *
2100  * Write a 32-bit word to a location in serial EEPROM using the card's PCI
2101  * VPD capability.  Note that this function must be called with a virtual
2102  * address.
2103  */
2104 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data)
2105 {
2106         unsigned int base = adapter->params.pci.vpd_cap_addr;
2107         int ret;
2108         u32 stats_reg = 0;
2109         int max_poll;
2110
2111         /* VPD Accesses must alway be 4-byte aligned!
2112          */
2113         if (addr >= EEPROMVSIZE || (addr & 3))
2114                 return -EINVAL;
2115
2116         /* Wait for any previous operation which may still be in flight to
2117          * complete.
2118          */
2119         ret = t4_seeprom_wait(adapter);
2120         if (ret) {
2121                 dev_err(adapter, "VPD still busy from previous operation\n");
2122                 return ret;
2123         }
2124
2125         /* Issue our new VPD Read request, mark the VPD as being busy and wait
2126          * for our request to complete.  If it doesn't complete, note the
2127          * error and return it to our caller.  Note that we do not reset the
2128          * VPD Busy status!
2129          */
2130         t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA,
2131                              cpu_to_le32(data));
2132         t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR,
2133                              (u16)addr | PCI_VPD_ADDR_F);
2134         adapter->vpd_busy = 1;
2135         adapter->vpd_flag = 0;
2136         ret = t4_seeprom_wait(adapter);
2137         if (ret) {
2138                 dev_err(adapter, "VPD write of address %#x failed\n", addr);
2139                 return ret;
2140         }
2141
2142         /* Reset PCI_VPD_DATA register after a transaction and wait for our
2143          * request to complete. If it doesn't complete, return error.
2144          */
2145         t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0);
2146         max_poll = EEPROM_MAX_POLL;
2147         do {
2148                 udelay(EEPROM_DELAY);
2149                 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg);
2150         } while ((stats_reg & 0x1) && --max_poll);
2151         if (!max_poll)
2152                 return -ETIMEDOUT;
2153
2154         /* Return success! */
2155         return 0;
2156 }
2157
2158 /**
2159  * t4_seeprom_wp - enable/disable EEPROM write protection
2160  * @adapter: the adapter
2161  * @enable: whether to enable or disable write protection
2162  *
2163  * Enables or disables write protection on the serial EEPROM.
2164  */
2165 int t4_seeprom_wp(struct adapter *adapter, int enable)
2166 {
2167         return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
2168 }
2169
2170 /**
2171  * t4_config_rss_range - configure a portion of the RSS mapping table
2172  * @adapter: the adapter
2173  * @mbox: mbox to use for the FW command
2174  * @viid: virtual interface whose RSS subtable is to be written
2175  * @start: start entry in the table to write
2176  * @n: how many table entries to write
2177  * @rspq: values for the "response queue" (Ingress Queue) lookup table
2178  * @nrspq: number of values in @rspq
2179  *
2180  * Programs the selected part of the VI's RSS mapping table with the
2181  * provided values.  If @nrspq < @n the supplied values are used repeatedly
2182  * until the full table range is populated.
2183  *
2184  * The caller must ensure the values in @rspq are in the range allowed for
2185  * @viid.
2186  */
2187 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
2188                         int start, int n, const u16 *rspq, unsigned int nrspq)
2189 {
2190         int ret;
2191         const u16 *rsp = rspq;
2192         const u16 *rsp_end = rspq + nrspq;
2193         struct fw_rss_ind_tbl_cmd cmd;
2194
2195         memset(&cmd, 0, sizeof(cmd));
2196         cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
2197                                      F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2198                                      V_FW_RSS_IND_TBL_CMD_VIID(viid));
2199         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
2200
2201         /*
2202          * Each firmware RSS command can accommodate up to 32 RSS Ingress
2203          * Queue Identifiers.  These Ingress Queue IDs are packed three to
2204          * a 32-bit word as 10-bit values with the upper remaining 2 bits
2205          * reserved.
2206          */
2207         while (n > 0) {
2208                 int nq = min(n, 32);
2209                 int nq_packed = 0;
2210                 __be32 *qp = &cmd.iq0_to_iq2;
2211
2212                 /*
2213                  * Set up the firmware RSS command header to send the next
2214                  * "nq" Ingress Queue IDs to the firmware.
2215                  */
2216                 cmd.niqid = cpu_to_be16(nq);
2217                 cmd.startidx = cpu_to_be16(start);
2218
2219                 /*
2220                  * "nq" more done for the start of the next loop.
2221                  */
2222                 start += nq;
2223                 n -= nq;
2224
2225                 /*
2226                  * While there are still Ingress Queue IDs to stuff into the
2227                  * current firmware RSS command, retrieve them from the
2228                  * Ingress Queue ID array and insert them into the command.
2229                  */
2230                 while (nq > 0) {
2231                         /*
2232                          * Grab up to the next 3 Ingress Queue IDs (wrapping
2233                          * around the Ingress Queue ID array if necessary) and
2234                          * insert them into the firmware RSS command at the
2235                          * current 3-tuple position within the commad.
2236                          */
2237                         u16 qbuf[3];
2238                         u16 *qbp = qbuf;
2239                         int nqbuf = min(3, nq);
2240
2241                         nq -= nqbuf;
2242                         qbuf[0] = 0;
2243                         qbuf[1] = 0;
2244                         qbuf[2] = 0;
2245                         while (nqbuf && nq_packed < 32) {
2246                                 nqbuf--;
2247                                 nq_packed++;
2248                                 *qbp++ = *rsp++;
2249                                 if (rsp >= rsp_end)
2250                                         rsp = rspq;
2251                         }
2252                         *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) |
2253                                             V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) |
2254                                             V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2]));
2255                 }
2256
2257                 /*
2258                  * Send this portion of the RRS table update to the firmware;
2259                  * bail out on any errors.
2260                  */
2261                 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
2262                 if (ret)
2263                         return ret;
2264         }
2265
2266         return 0;
2267 }
2268
2269 /**
2270  * t4_config_vi_rss - configure per VI RSS settings
2271  * @adapter: the adapter
2272  * @mbox: mbox to use for the FW command
2273  * @viid: the VI id
2274  * @flags: RSS flags
2275  * @defq: id of the default RSS queue for the VI.
2276  *
2277  * Configures VI-specific RSS properties.
2278  */
2279 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
2280                      unsigned int flags, unsigned int defq)
2281 {
2282         struct fw_rss_vi_config_cmd c;
2283
2284         memset(&c, 0, sizeof(c));
2285         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
2286                                    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2287                                    V_FW_RSS_VI_CONFIG_CMD_VIID(viid));
2288         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
2289         c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
2290                         V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq));
2291         return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
2292 }
2293
2294 /**
2295  * init_cong_ctrl - initialize congestion control parameters
2296  * @a: the alpha values for congestion control
2297  * @b: the beta values for congestion control
2298  *
2299  * Initialize the congestion control parameters.
2300  */
2301 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
2302 {
2303         int i;
2304
2305         for (i = 0; i < 9; i++) {
2306                 a[i] = 1;
2307                 b[i] = 0;
2308         }
2309
2310         a[9] = 2;
2311         a[10] = 3;
2312         a[11] = 4;
2313         a[12] = 5;
2314         a[13] = 6;
2315         a[14] = 7;
2316         a[15] = 8;
2317         a[16] = 9;
2318         a[17] = 10;
2319         a[18] = 14;
2320         a[19] = 17;
2321         a[20] = 21;
2322         a[21] = 25;
2323         a[22] = 30;
2324         a[23] = 35;
2325         a[24] = 45;
2326         a[25] = 60;
2327         a[26] = 80;
2328         a[27] = 100;
2329         a[28] = 200;
2330         a[29] = 300;
2331         a[30] = 400;
2332         a[31] = 500;
2333
2334         b[9] = 1;
2335         b[10] = 1;
2336         b[11] = 2;
2337         b[12] = 2;
2338         b[13] = 3;
2339         b[14] = 3;
2340         b[15] = 3;
2341         b[16] = 3;
2342         b[17] = 4;
2343         b[18] = 4;
2344         b[19] = 4;
2345         b[20] = 4;
2346         b[21] = 4;
2347         b[22] = 5;
2348         b[23] = 5;
2349         b[24] = 5;
2350         b[25] = 5;
2351         b[26] = 5;
2352         b[27] = 5;
2353         b[28] = 6;
2354         b[29] = 6;
2355         b[30] = 7;
2356         b[31] = 7;
2357 }
2358
2359 #define INIT_CMD(var, cmd, rd_wr) do { \
2360         (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \
2361                         F_FW_CMD_REQUEST | F_FW_CMD_##rd_wr); \
2362         (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
2363 } while (0)
2364
2365 int t4_get_core_clock(struct adapter *adapter, struct vpd_params *p)
2366 {
2367         u32 cclk_param, cclk_val;
2368         int ret;
2369
2370         /*
2371          * Ask firmware for the Core Clock since it knows how to translate the
2372          * Reference Clock ('V2') VPD field into a Core Clock value ...
2373          */
2374         cclk_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
2375                       V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CCLK));
2376         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2377                               1, &cclk_param, &cclk_val);
2378         if (ret) {
2379                 dev_err(adapter, "%s: error in fetching from coreclock - %d\n",
2380                         __func__, ret);
2381                 return ret;
2382         }
2383
2384         p->cclk = cclk_val;
2385         dev_debug(adapter, "%s: p->cclk = %u\n", __func__, p->cclk);
2386         return 0;
2387 }
2388
2389 /* serial flash and firmware constants and flash config file constants */
2390 enum {
2391         SF_ATTEMPTS = 10,             /* max retries for SF operations */
2392
2393         /* flash command opcodes */
2394         SF_PROG_PAGE    = 2,          /* program page */
2395         SF_WR_DISABLE   = 4,          /* disable writes */
2396         SF_RD_STATUS    = 5,          /* read status register */
2397         SF_WR_ENABLE    = 6,          /* enable writes */
2398         SF_RD_DATA_FAST = 0xb,        /* read flash */
2399         SF_RD_ID        = 0x9f,       /* read ID */
2400         SF_ERASE_SECTOR = 0xd8,       /* erase sector */
2401 };
2402
2403 /**
2404  * sf1_read - read data from the serial flash
2405  * @adapter: the adapter
2406  * @byte_cnt: number of bytes to read
2407  * @cont: whether another operation will be chained
2408  * @lock: whether to lock SF for PL access only
2409  * @valp: where to store the read data
2410  *
2411  * Reads up to 4 bytes of data from the serial flash.  The location of
2412  * the read needs to be specified prior to calling this by issuing the
2413  * appropriate commands to the serial flash.
2414  */
2415 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2416                     int lock, u32 *valp)
2417 {
2418         int ret;
2419
2420         if (!byte_cnt || byte_cnt > 4)
2421                 return -EINVAL;
2422         if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
2423                 return -EBUSY;
2424         t4_write_reg(adapter, A_SF_OP,
2425                      V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
2426         ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
2427         if (!ret)
2428                 *valp = t4_read_reg(adapter, A_SF_DATA);
2429         return ret;
2430 }
2431
2432 /**
2433  * sf1_write - write data to the serial flash
2434  * @adapter: the adapter
2435  * @byte_cnt: number of bytes to write
2436  * @cont: whether another operation will be chained
2437  * @lock: whether to lock SF for PL access only
2438  * @val: value to write
2439  *
2440  * Writes up to 4 bytes of data to the serial flash.  The location of
2441  * the write needs to be specified prior to calling this by issuing the
2442  * appropriate commands to the serial flash.
2443  */
2444 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2445                      int lock, u32 val)
2446 {
2447         if (!byte_cnt || byte_cnt > 4)
2448                 return -EINVAL;
2449         if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
2450                 return -EBUSY;
2451         t4_write_reg(adapter, A_SF_DATA, val);
2452         t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) |
2453                      V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1));
2454         return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
2455 }
2456
2457 /**
2458  * t4_read_flash - read words from serial flash
2459  * @adapter: the adapter
2460  * @addr: the start address for the read
2461  * @nwords: how many 32-bit words to read
2462  * @data: where to store the read data
2463  * @byte_oriented: whether to store data as bytes or as words
2464  *
2465  * Read the specified number of 32-bit words from the serial flash.
2466  * If @byte_oriented is set the read data is stored as a byte array
2467  * (i.e., big-endian), otherwise as 32-bit words in the platform's
2468  * natural endianness.
2469  */
2470 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2471                   unsigned int nwords, u32 *data, int byte_oriented)
2472 {
2473         int ret;
2474
2475         if (((addr + nwords * sizeof(u32)) > adapter->params.sf_size) ||
2476             (addr & 3))
2477                 return -EINVAL;
2478
2479         addr = rte_constant_bswap32(addr) | SF_RD_DATA_FAST;
2480
2481         ret = sf1_write(adapter, 4, 1, 0, addr);
2482         if (ret != 0)
2483                 return ret;
2484
2485         ret = sf1_read(adapter, 1, 1, 0, data);
2486         if (ret != 0)
2487                 return ret;
2488
2489         for ( ; nwords; nwords--, data++) {
2490                 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2491                 if (nwords == 1)
2492                         t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
2493                 if (ret)
2494                         return ret;
2495                 if (byte_oriented)
2496                         *data = cpu_to_be32(*data);
2497         }
2498         return 0;
2499 }
2500
2501 /**
2502  * t4_get_exprom_version - return the Expansion ROM version (if any)
2503  * @adapter: the adapter
2504  * @vers: where to place the version
2505  *
2506  * Reads the Expansion ROM header from FLASH and returns the version
2507  * number (if present) through the @vers return value pointer.  We return
2508  * this in the Firmware Version Format since it's convenient.  Return
2509  * 0 on success, -ENOENT if no Expansion ROM is present.
2510  */
2511 static int t4_get_exprom_version(struct adapter *adapter, u32 *vers)
2512 {
2513         struct exprom_header {
2514                 unsigned char hdr_arr[16];      /* must start with 0x55aa */
2515                 unsigned char hdr_ver[4];       /* Expansion ROM version */
2516         } *hdr;
2517         u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
2518                                            sizeof(u32))];
2519         int ret;
2520
2521         ret = t4_read_flash(adapter, FLASH_EXP_ROM_START,
2522                             ARRAY_SIZE(exprom_header_buf),
2523                             exprom_header_buf, 0);
2524         if (ret)
2525                 return ret;
2526
2527         hdr = (struct exprom_header *)exprom_header_buf;
2528         if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
2529                 return -ENOENT;
2530
2531         *vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) |
2532                  V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) |
2533                  V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) |
2534                  V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3]));
2535         return 0;
2536 }
2537
2538 /**
2539  * t4_get_fw_version - read the firmware version
2540  * @adapter: the adapter
2541  * @vers: where to place the version
2542  *
2543  * Reads the FW version from flash.
2544  */
2545 static int t4_get_fw_version(struct adapter *adapter, u32 *vers)
2546 {
2547         return t4_read_flash(adapter, FLASH_FW_START +
2548                              offsetof(struct fw_hdr, fw_ver), 1, vers, 0);
2549 }
2550
2551 /**
2552  *     t4_get_bs_version - read the firmware bootstrap version
2553  *     @adapter: the adapter
2554  *     @vers: where to place the version
2555  *
2556  *     Reads the FW Bootstrap version from flash.
2557  */
2558 static int t4_get_bs_version(struct adapter *adapter, u32 *vers)
2559 {
2560         return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
2561                              offsetof(struct fw_hdr, fw_ver), 1,
2562                              vers, 0);
2563 }
2564
2565 /**
2566  * t4_get_tp_version - read the TP microcode version
2567  * @adapter: the adapter
2568  * @vers: where to place the version
2569  *
2570  * Reads the TP microcode version from flash.
2571  */
2572 static int t4_get_tp_version(struct adapter *adapter, u32 *vers)
2573 {
2574         return t4_read_flash(adapter, FLASH_FW_START +
2575                              offsetof(struct fw_hdr, tp_microcode_ver),
2576                              1, vers, 0);
2577 }
2578
2579 /**
2580  * t4_get_version_info - extract various chip/firmware version information
2581  * @adapter: the adapter
2582  *
2583  * Reads various chip/firmware version numbers and stores them into the
2584  * adapter Adapter Parameters structure.  If any of the efforts fails
2585  * the first failure will be returned, but all of the version numbers
2586  * will be read.
2587  */
2588 int t4_get_version_info(struct adapter *adapter)
2589 {
2590         int ret = 0;
2591
2592 #define FIRST_RET(__getvinfo) \
2593         do { \
2594                 int __ret = __getvinfo; \
2595                 if (__ret && !ret) \
2596                         ret = __ret; \
2597         } while (0)
2598
2599         FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
2600         FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
2601         FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
2602         FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
2603
2604 #undef FIRST_RET
2605
2606         return ret;
2607 }
2608
2609 /**
2610  * t4_dump_version_info - dump all of the adapter configuration IDs
2611  * @adapter: the adapter
2612  *
2613  * Dumps all of the various bits of adapter configuration version/revision
2614  * IDs information.  This is typically called at some point after
2615  * t4_get_version_info() has been called.
2616  */
2617 void t4_dump_version_info(struct adapter *adapter)
2618 {
2619         /**
2620          * Device information.
2621          */
2622         dev_info(adapter, "Chelsio rev %d\n",
2623                  CHELSIO_CHIP_RELEASE(adapter->params.chip));
2624
2625         /**
2626          * Firmware Version.
2627          */
2628         if (!adapter->params.fw_vers)
2629                 dev_warn(adapter, "No firmware loaded\n");
2630         else
2631                 dev_info(adapter, "Firmware version: %u.%u.%u.%u\n",
2632                          G_FW_HDR_FW_VER_MAJOR(adapter->params.fw_vers),
2633                          G_FW_HDR_FW_VER_MINOR(adapter->params.fw_vers),
2634                          G_FW_HDR_FW_VER_MICRO(adapter->params.fw_vers),
2635                          G_FW_HDR_FW_VER_BUILD(adapter->params.fw_vers));
2636
2637         /**
2638          * Bootstrap Firmware Version.
2639          */
2640         if (!adapter->params.bs_vers)
2641                 dev_warn(adapter, "No bootstrap loaded\n");
2642         else
2643                 dev_info(adapter, "Bootstrap version: %u.%u.%u.%u\n",
2644                          G_FW_HDR_FW_VER_MAJOR(adapter->params.bs_vers),
2645                          G_FW_HDR_FW_VER_MINOR(adapter->params.bs_vers),
2646                          G_FW_HDR_FW_VER_MICRO(adapter->params.bs_vers),
2647                          G_FW_HDR_FW_VER_BUILD(adapter->params.bs_vers));
2648
2649         /**
2650          * TP Microcode Version.
2651          */
2652         if (!adapter->params.tp_vers)
2653                 dev_warn(adapter, "No TP Microcode loaded\n");
2654         else
2655                 dev_info(adapter, "TP Microcode version: %u.%u.%u.%u\n",
2656                          G_FW_HDR_FW_VER_MAJOR(adapter->params.tp_vers),
2657                          G_FW_HDR_FW_VER_MINOR(adapter->params.tp_vers),
2658                          G_FW_HDR_FW_VER_MICRO(adapter->params.tp_vers),
2659                          G_FW_HDR_FW_VER_BUILD(adapter->params.tp_vers));
2660
2661         /**
2662          * Expansion ROM version.
2663          */
2664         if (!adapter->params.er_vers)
2665                 dev_info(adapter, "No Expansion ROM loaded\n");
2666         else
2667                 dev_info(adapter, "Expansion ROM version: %u.%u.%u.%u\n",
2668                          G_FW_HDR_FW_VER_MAJOR(adapter->params.er_vers),
2669                          G_FW_HDR_FW_VER_MINOR(adapter->params.er_vers),
2670                          G_FW_HDR_FW_VER_MICRO(adapter->params.er_vers),
2671                          G_FW_HDR_FW_VER_BUILD(adapter->params.er_vers));
2672 }
2673
2674 #define ADVERT_MASK (V_FW_PORT_CAP_SPEED(M_FW_PORT_CAP_SPEED) | \
2675                      FW_PORT_CAP_ANEG)
2676
2677 /**
2678  * t4_link_l1cfg - apply link configuration to MAC/PHY
2679  * @phy: the PHY to setup
2680  * @mac: the MAC to setup
2681  * @lc: the requested link configuration
2682  *
2683  * Set up a port's MAC and PHY according to a desired link configuration.
2684  * - If the PHY can auto-negotiate first decide what to advertise, then
2685  *   enable/disable auto-negotiation as desired, and reset.
2686  * - If the PHY does not auto-negotiate just reset it.
2687  * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
2688  *   otherwise do it later based on the outcome of auto-negotiation.
2689  */
2690 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
2691                   struct link_config *lc)
2692 {
2693         struct fw_port_cmd c;
2694         unsigned int mdi = V_FW_PORT_CAP_MDI(FW_PORT_CAP_MDI_AUTO);
2695         unsigned int fc, fec;
2696
2697         lc->link_ok = 0;
2698         fc = 0;
2699         if (lc->requested_fc & PAUSE_RX)
2700                 fc |= FW_PORT_CAP_FC_RX;
2701         if (lc->requested_fc & PAUSE_TX)
2702                 fc |= FW_PORT_CAP_FC_TX;
2703
2704         fec = 0;
2705         if (lc->requested_fec & FEC_RS)
2706                 fec |= FW_PORT_CAP_FEC_RS;
2707         if (lc->requested_fec & FEC_BASER_RS)
2708                 fec |= FW_PORT_CAP_FEC_BASER_RS;
2709         if (lc->requested_fec & FEC_RESERVED)
2710                 fec |= FW_PORT_CAP_FEC_RESERVED;
2711
2712         memset(&c, 0, sizeof(c));
2713         c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
2714                                      F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
2715                                      V_FW_PORT_CMD_PORTID(port));
2716         c.action_to_len16 =
2717                 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
2718                             FW_LEN16(c));
2719
2720         if (!(lc->supported & FW_PORT_CAP_ANEG)) {
2721                 c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
2722                                              fc | fec);
2723                 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
2724                 lc->fec = lc->requested_fec;
2725         } else if (lc->autoneg == AUTONEG_DISABLE) {
2726                 c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc |
2727                                              fec | mdi);
2728                 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
2729                 lc->fec = lc->requested_fec;
2730         } else {
2731                 c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | fec | mdi);
2732         }
2733
2734         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2735 }
2736
2737 /**
2738  * t4_flash_cfg_addr - return the address of the flash configuration file
2739  * @adapter: the adapter
2740  *
2741  * Return the address within the flash where the Firmware Configuration
2742  * File is stored, or an error if the device FLASH is too small to contain
2743  * a Firmware Configuration File.
2744  */
2745 int t4_flash_cfg_addr(struct adapter *adapter)
2746 {
2747         /*
2748          * If the device FLASH isn't large enough to hold a Firmware
2749          * Configuration File, return an error.
2750          */
2751         if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE)
2752                 return -ENOSPC;
2753
2754         return FLASH_CFG_START;
2755 }
2756
2757 #define PF_INTR_MASK (F_PFSW | F_PFCIM)
2758
2759 /**
2760  * t4_intr_enable - enable interrupts
2761  * @adapter: the adapter whose interrupts should be enabled
2762  *
2763  * Enable PF-specific interrupts for the calling function and the top-level
2764  * interrupt concentrator for global interrupts.  Interrupts are already
2765  * enabled at each module, here we just enable the roots of the interrupt
2766  * hierarchies.
2767  *
2768  * Note: this function should be called only when the driver manages
2769  * non PF-specific interrupts from the various HW modules.  Only one PCI
2770  * function at a time should be doing this.
2771  */
2772 void t4_intr_enable(struct adapter *adapter)
2773 {
2774         u32 val = 0;
2775         u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
2776         u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
2777                  G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
2778
2779         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
2780                 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT;
2781         t4_write_reg(adapter, A_SGE_INT_ENABLE3, F_ERR_CPL_EXCEED_IQE_SIZE |
2782                      F_ERR_INVALID_CIDX_INC | F_ERR_CPL_OPCODE_0 |
2783                      F_ERR_DATA_CPL_ON_HIGH_QID1 | F_INGRESS_SIZE_ERR |
2784                      F_ERR_DATA_CPL_ON_HIGH_QID0 | F_ERR_BAD_DB_PIDX3 |
2785                      F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
2786                      F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO |
2787                      F_DBFIFO_LP_INT | F_EGRESS_SIZE_ERR | val);
2788         t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK);
2789         t4_set_reg_field(adapter, A_PL_INT_MAP0, 0, 1 << pf);
2790 }
2791
2792 /**
2793  * t4_intr_disable - disable interrupts
2794  * @adapter: the adapter whose interrupts should be disabled
2795  *
2796  * Disable interrupts.  We only disable the top-level interrupt
2797  * concentrators.  The caller must be a PCI function managing global
2798  * interrupts.
2799  */
2800 void t4_intr_disable(struct adapter *adapter)
2801 {
2802         u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
2803         u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
2804                  G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
2805
2806         t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), 0);
2807         t4_set_reg_field(adapter, A_PL_INT_MAP0, 1 << pf, 0);
2808 }
2809
2810 /**
2811  * t4_get_port_type_description - return Port Type string description
2812  * @port_type: firmware Port Type enumeration
2813  */
2814 const char *t4_get_port_type_description(enum fw_port_type port_type)
2815 {
2816         static const char * const port_type_description[] = {
2817                 "Fiber_XFI",
2818                 "Fiber_XAUI",
2819                 "BT_SGMII",
2820                 "BT_XFI",
2821                 "BT_XAUI",
2822                 "KX4",
2823                 "CX4",
2824                 "KX",
2825                 "KR",
2826                 "SFP",
2827                 "BP_AP",
2828                 "BP4_AP",
2829                 "QSFP_10G",
2830                 "QSA",
2831                 "QSFP",
2832                 "BP40_BA",
2833                 "KR4_100G",
2834                 "CR4_QSFP",
2835                 "CR_QSFP",
2836                 "CR2_QSFP",
2837                 "SFP28",
2838                 "KR_SFP28",
2839         };
2840
2841         if (port_type < ARRAY_SIZE(port_type_description))
2842                 return port_type_description[port_type];
2843         return "UNKNOWN";
2844 }
2845
2846 /**
2847  * t4_get_mps_bg_map - return the buffer groups associated with a port
2848  * @adap: the adapter
2849  * @pidx: the port index
2850  *
2851  * Returns a bitmap indicating which MPS buffer groups are associated
2852  * with the given port.  Bit i is set if buffer group i is used by the
2853  * port.
2854  */
2855 unsigned int t4_get_mps_bg_map(struct adapter *adap, unsigned int pidx)
2856 {
2857         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2858         unsigned int nports = 1 << G_NUMPORTS(t4_read_reg(adap,
2859                                                           A_MPS_CMN_CTL));
2860
2861         if (pidx >= nports) {
2862                 dev_warn(adap, "MPS Port Index %d >= Nports %d\n",
2863                          pidx, nports);
2864                 return 0;
2865         }
2866
2867         switch (chip_version) {
2868         case CHELSIO_T4:
2869         case CHELSIO_T5:
2870                 switch (nports) {
2871                 case 1: return 0xf;
2872                 case 2: return 3 << (2 * pidx);
2873                 case 4: return 1 << pidx;
2874                 }
2875                 break;
2876
2877         case CHELSIO_T6:
2878                 switch (nports) {
2879                 case 2: return 1 << (2 * pidx);
2880                 }
2881                 break;
2882         }
2883
2884         dev_err(adap, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
2885                 chip_version, nports);
2886         return 0;
2887 }
2888
2889 /**
2890  * t4_get_tp_ch_map - return TP ingress channels associated with a port
2891  * @adapter: the adapter
2892  * @pidx: the port index
2893  *
2894  * Returns a bitmap indicating which TP Ingress Channels are associated with
2895  * a given Port.  Bit i is set if TP Ingress Channel i is used by the Port.
2896  */
2897 unsigned int t4_get_tp_ch_map(struct adapter *adapter, unsigned int pidx)
2898 {
2899         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
2900         unsigned int nports = 1 << G_NUMPORTS(t4_read_reg(adapter,
2901                                                           A_MPS_CMN_CTL));
2902
2903         if (pidx >= nports) {
2904                 dev_warn(adap, "TP Port Index %d >= Nports %d\n",
2905                          pidx, nports);
2906                 return 0;
2907         }
2908
2909         switch (chip_version) {
2910         case CHELSIO_T4:
2911         case CHELSIO_T5:
2912                 /* Note that this happens to be the same values as the MPS
2913                  * Buffer Group Map for these Chips.  But we replicate the code
2914                  * here because they're really separate concepts.
2915                  */
2916                 switch (nports) {
2917                 case 1: return 0xf;
2918                 case 2: return 3 << (2 * pidx);
2919                 case 4: return 1 << pidx;
2920                 }
2921                 break;
2922
2923         case CHELSIO_T6:
2924                 switch (nports) {
2925                 case 2: return 1 << pidx;
2926                 }
2927                 break;
2928         }
2929
2930         dev_err(adapter, "Need TP Channel Map for Chip %0x, Nports %d\n",
2931                 chip_version, nports);
2932         return 0;
2933 }
2934
2935 /**
2936  * t4_get_port_stats - collect port statistics
2937  * @adap: the adapter
2938  * @idx: the port index
2939  * @p: the stats structure to fill
2940  *
2941  * Collect statistics related to the given port from HW.
2942  */
2943 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
2944 {
2945         u32 bgmap = t4_get_mps_bg_map(adap, idx);
2946         u32 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL);
2947
2948 #define GET_STAT(name) \
2949         t4_read_reg64(adap, \
2950                       (is_t4(adap->params.chip) ? \
2951                        PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) :\
2952                        T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L)))
2953 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
2954
2955         p->tx_octets           = GET_STAT(TX_PORT_BYTES);
2956         p->tx_frames           = GET_STAT(TX_PORT_FRAMES);
2957         p->tx_bcast_frames     = GET_STAT(TX_PORT_BCAST);
2958         p->tx_mcast_frames     = GET_STAT(TX_PORT_MCAST);
2959         p->tx_ucast_frames     = GET_STAT(TX_PORT_UCAST);
2960         p->tx_error_frames     = GET_STAT(TX_PORT_ERROR);
2961         p->tx_frames_64        = GET_STAT(TX_PORT_64B);
2962         p->tx_frames_65_127    = GET_STAT(TX_PORT_65B_127B);
2963         p->tx_frames_128_255   = GET_STAT(TX_PORT_128B_255B);
2964         p->tx_frames_256_511   = GET_STAT(TX_PORT_256B_511B);
2965         p->tx_frames_512_1023  = GET_STAT(TX_PORT_512B_1023B);
2966         p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
2967         p->tx_frames_1519_max  = GET_STAT(TX_PORT_1519B_MAX);
2968         p->tx_drop             = GET_STAT(TX_PORT_DROP);
2969         p->tx_pause            = GET_STAT(TX_PORT_PAUSE);
2970         p->tx_ppp0             = GET_STAT(TX_PORT_PPP0);
2971         p->tx_ppp1             = GET_STAT(TX_PORT_PPP1);
2972         p->tx_ppp2             = GET_STAT(TX_PORT_PPP2);
2973         p->tx_ppp3             = GET_STAT(TX_PORT_PPP3);
2974         p->tx_ppp4             = GET_STAT(TX_PORT_PPP4);
2975         p->tx_ppp5             = GET_STAT(TX_PORT_PPP5);
2976         p->tx_ppp6             = GET_STAT(TX_PORT_PPP6);
2977         p->tx_ppp7             = GET_STAT(TX_PORT_PPP7);
2978
2979         if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
2980                 if (stat_ctl & F_COUNTPAUSESTATTX) {
2981                         p->tx_frames -= p->tx_pause;
2982                         p->tx_octets -= p->tx_pause * 64;
2983                 }
2984                 if (stat_ctl & F_COUNTPAUSEMCTX)
2985                         p->tx_mcast_frames -= p->tx_pause;
2986         }
2987
2988         p->rx_octets           = GET_STAT(RX_PORT_BYTES);
2989         p->rx_frames           = GET_STAT(RX_PORT_FRAMES);
2990         p->rx_bcast_frames     = GET_STAT(RX_PORT_BCAST);
2991         p->rx_mcast_frames     = GET_STAT(RX_PORT_MCAST);
2992         p->rx_ucast_frames     = GET_STAT(RX_PORT_UCAST);
2993         p->rx_too_long         = GET_STAT(RX_PORT_MTU_ERROR);
2994         p->rx_jabber           = GET_STAT(RX_PORT_MTU_CRC_ERROR);
2995         p->rx_fcs_err          = GET_STAT(RX_PORT_CRC_ERROR);
2996         p->rx_len_err          = GET_STAT(RX_PORT_LEN_ERROR);
2997         p->rx_symbol_err       = GET_STAT(RX_PORT_SYM_ERROR);
2998         p->rx_runt             = GET_STAT(RX_PORT_LESS_64B);
2999         p->rx_frames_64        = GET_STAT(RX_PORT_64B);
3000         p->rx_frames_65_127    = GET_STAT(RX_PORT_65B_127B);
3001         p->rx_frames_128_255   = GET_STAT(RX_PORT_128B_255B);
3002         p->rx_frames_256_511   = GET_STAT(RX_PORT_256B_511B);
3003         p->rx_frames_512_1023  = GET_STAT(RX_PORT_512B_1023B);
3004         p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
3005         p->rx_frames_1519_max  = GET_STAT(RX_PORT_1519B_MAX);
3006         p->rx_pause            = GET_STAT(RX_PORT_PAUSE);
3007         p->rx_ppp0             = GET_STAT(RX_PORT_PPP0);
3008         p->rx_ppp1             = GET_STAT(RX_PORT_PPP1);
3009         p->rx_ppp2             = GET_STAT(RX_PORT_PPP2);
3010         p->rx_ppp3             = GET_STAT(RX_PORT_PPP3);
3011         p->rx_ppp4             = GET_STAT(RX_PORT_PPP4);
3012         p->rx_ppp5             = GET_STAT(RX_PORT_PPP5);
3013         p->rx_ppp6             = GET_STAT(RX_PORT_PPP6);
3014         p->rx_ppp7             = GET_STAT(RX_PORT_PPP7);
3015
3016         if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
3017                 if (stat_ctl & F_COUNTPAUSESTATRX) {
3018                         p->rx_frames -= p->rx_pause;
3019                         p->rx_octets -= p->rx_pause * 64;
3020                 }
3021                 if (stat_ctl & F_COUNTPAUSEMCRX)
3022                         p->rx_mcast_frames -= p->rx_pause;
3023         }
3024
3025         p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
3026         p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
3027         p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
3028         p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
3029         p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
3030         p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
3031         p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
3032         p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
3033
3034 #undef GET_STAT
3035 #undef GET_STAT_COM
3036 }
3037
3038 /**
3039  * t4_get_port_stats_offset - collect port stats relative to a previous snapshot
3040  * @adap: The adapter
3041  * @idx: The port
3042  * @stats: Current stats to fill
3043  * @offset: Previous stats snapshot
3044  */
3045 void t4_get_port_stats_offset(struct adapter *adap, int idx,
3046                               struct port_stats *stats,
3047                               struct port_stats *offset)
3048 {
3049         u64 *s, *o;
3050         unsigned int i;
3051
3052         t4_get_port_stats(adap, idx, stats);
3053         for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
3054              i < (sizeof(struct port_stats) / sizeof(u64));
3055              i++, s++, o++)
3056                 *s -= *o;
3057 }
3058
3059 /**
3060  * t4_clr_port_stats - clear port statistics
3061  * @adap: the adapter
3062  * @idx: the port index
3063  *
3064  * Clear HW statistics for the given port.
3065  */
3066 void t4_clr_port_stats(struct adapter *adap, int idx)
3067 {
3068         unsigned int i;
3069         u32 bgmap = t4_get_mps_bg_map(adap, idx);
3070         u32 port_base_addr;
3071
3072         if (is_t4(adap->params.chip))
3073                 port_base_addr = PORT_BASE(idx);
3074         else
3075                 port_base_addr = T5_PORT_BASE(idx);
3076
3077         for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L;
3078              i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8)
3079                 t4_write_reg(adap, port_base_addr + i, 0);
3080         for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L;
3081              i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8)
3082                 t4_write_reg(adap, port_base_addr + i, 0);
3083         for (i = 0; i < 4; i++)
3084                 if (bgmap & (1 << i)) {
3085                         t4_write_reg(adap,
3086                                      A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L +
3087                                      i * 8, 0);
3088                         t4_write_reg(adap,
3089                                      A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L +
3090                                      i * 8, 0);
3091                 }
3092 }
3093
3094 /**
3095  * t4_fw_hello - establish communication with FW
3096  * @adap: the adapter
3097  * @mbox: mailbox to use for the FW command
3098  * @evt_mbox: mailbox to receive async FW events
3099  * @master: specifies the caller's willingness to be the device master
3100  * @state: returns the current device state (if non-NULL)
3101  *
3102  * Issues a command to establish communication with FW.  Returns either
3103  * an error (negative integer) or the mailbox of the Master PF.
3104  */
3105 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
3106                 enum dev_master master, enum dev_state *state)
3107 {
3108         int ret;
3109         struct fw_hello_cmd c;
3110         u32 v;
3111         unsigned int master_mbox;
3112         int retries = FW_CMD_HELLO_RETRIES;
3113
3114 retry:
3115         memset(&c, 0, sizeof(c));
3116         INIT_CMD(c, HELLO, WRITE);
3117         c.err_to_clearinit = cpu_to_be32(
3118                         V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
3119                         V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
3120                         V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? mbox :
3121                                                 M_FW_HELLO_CMD_MBMASTER) |
3122                         V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
3123                         V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) |
3124                         F_FW_HELLO_CMD_CLEARINIT);
3125
3126         /*
3127          * Issue the HELLO command to the firmware.  If it's not successful
3128          * but indicates that we got a "busy" or "timeout" condition, retry
3129          * the HELLO until we exhaust our retry limit.  If we do exceed our
3130          * retry limit, check to see if the firmware left us any error
3131          * information and report that if so ...
3132          */
3133         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3134         if (ret != FW_SUCCESS) {
3135                 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
3136                         goto retry;
3137                 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR)
3138                         t4_report_fw_error(adap);
3139                 return ret;
3140         }
3141
3142         v = be32_to_cpu(c.err_to_clearinit);
3143         master_mbox = G_FW_HELLO_CMD_MBMASTER(v);
3144         if (state) {
3145                 if (v & F_FW_HELLO_CMD_ERR)
3146                         *state = DEV_STATE_ERR;
3147                 else if (v & F_FW_HELLO_CMD_INIT)
3148                         *state = DEV_STATE_INIT;
3149                 else
3150                         *state = DEV_STATE_UNINIT;
3151         }
3152
3153         /*
3154          * If we're not the Master PF then we need to wait around for the
3155          * Master PF Driver to finish setting up the adapter.
3156          *
3157          * Note that we also do this wait if we're a non-Master-capable PF and
3158          * there is no current Master PF; a Master PF may show up momentarily
3159          * and we wouldn't want to fail pointlessly.  (This can happen when an
3160          * OS loads lots of different drivers rapidly at the same time).  In
3161          * this case, the Master PF returned by the firmware will be
3162          * M_PCIE_FW_MASTER so the test below will work ...
3163          */
3164         if ((v & (F_FW_HELLO_CMD_ERR | F_FW_HELLO_CMD_INIT)) == 0 &&
3165             master_mbox != mbox) {
3166                 int waiting = FW_CMD_HELLO_TIMEOUT;
3167
3168                 /*
3169                  * Wait for the firmware to either indicate an error or
3170                  * initialized state.  If we see either of these we bail out
3171                  * and report the issue to the caller.  If we exhaust the
3172                  * "hello timeout" and we haven't exhausted our retries, try
3173                  * again.  Otherwise bail with a timeout error.
3174                  */
3175                 for (;;) {
3176                         u32 pcie_fw;
3177
3178                         msleep(50);
3179                         waiting -= 50;
3180
3181                         /*
3182                          * If neither Error nor Initialialized are indicated
3183                          * by the firmware keep waiting till we exaust our
3184                          * timeout ... and then retry if we haven't exhausted
3185                          * our retries ...
3186                          */
3187                         pcie_fw = t4_read_reg(adap, A_PCIE_FW);
3188                         if (!(pcie_fw & (F_PCIE_FW_ERR | F_PCIE_FW_INIT))) {
3189                                 if (waiting <= 0) {
3190                                         if (retries-- > 0)
3191                                                 goto retry;
3192
3193                                         return -ETIMEDOUT;
3194                                 }
3195                                 continue;
3196                         }
3197
3198                         /*
3199                          * We either have an Error or Initialized condition
3200                          * report errors preferentially.
3201                          */
3202                         if (state) {
3203                                 if (pcie_fw & F_PCIE_FW_ERR)
3204                                         *state = DEV_STATE_ERR;
3205                                 else if (pcie_fw & F_PCIE_FW_INIT)
3206                                         *state = DEV_STATE_INIT;
3207                         }
3208
3209                         /*
3210                          * If we arrived before a Master PF was selected and
3211                          * there's not a valid Master PF, grab its identity
3212                          * for our caller.
3213                          */
3214                         if (master_mbox == M_PCIE_FW_MASTER &&
3215                             (pcie_fw & F_PCIE_FW_MASTER_VLD))
3216                                 master_mbox = G_PCIE_FW_MASTER(pcie_fw);
3217                         break;
3218                 }
3219         }
3220
3221         return master_mbox;
3222 }
3223
3224 /**
3225  * t4_fw_bye - end communication with FW
3226  * @adap: the adapter
3227  * @mbox: mailbox to use for the FW command
3228  *
3229  * Issues a command to terminate communication with FW.
3230  */
3231 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
3232 {
3233         struct fw_bye_cmd c;
3234
3235         memset(&c, 0, sizeof(c));
3236         INIT_CMD(c, BYE, WRITE);
3237         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3238 }
3239
3240 /**
3241  * t4_fw_reset - issue a reset to FW
3242  * @adap: the adapter
3243  * @mbox: mailbox to use for the FW command
3244  * @reset: specifies the type of reset to perform
3245  *
3246  * Issues a reset command of the specified type to FW.
3247  */
3248 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
3249 {
3250         struct fw_reset_cmd c;
3251
3252         memset(&c, 0, sizeof(c));
3253         INIT_CMD(c, RESET, WRITE);
3254         c.val = cpu_to_be32(reset);
3255         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3256 }
3257
3258 /**
3259  * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
3260  * @adap: the adapter
3261  * @mbox: mailbox to use for the FW RESET command (if desired)
3262  * @force: force uP into RESET even if FW RESET command fails
3263  *
3264  * Issues a RESET command to firmware (if desired) with a HALT indication
3265  * and then puts the microprocessor into RESET state.  The RESET command
3266  * will only be issued if a legitimate mailbox is provided (mbox <=
3267  * M_PCIE_FW_MASTER).
3268  *
3269  * This is generally used in order for the host to safely manipulate the
3270  * adapter without fear of conflicting with whatever the firmware might
3271  * be doing.  The only way out of this state is to RESTART the firmware
3272  * ...
3273  */
3274 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
3275 {
3276         int ret = 0;
3277
3278         /*
3279          * If a legitimate mailbox is provided, issue a RESET command
3280          * with a HALT indication.
3281          */
3282         if (mbox <= M_PCIE_FW_MASTER) {
3283                 struct fw_reset_cmd c;
3284
3285                 memset(&c, 0, sizeof(c));
3286                 INIT_CMD(c, RESET, WRITE);
3287                 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE);
3288                 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT);
3289                 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3290         }
3291
3292         /*
3293          * Normally we won't complete the operation if the firmware RESET
3294          * command fails but if our caller insists we'll go ahead and put the
3295          * uP into RESET.  This can be useful if the firmware is hung or even
3296          * missing ...  We'll have to take the risk of putting the uP into
3297          * RESET without the cooperation of firmware in that case.
3298          *
3299          * We also force the firmware's HALT flag to be on in case we bypassed
3300          * the firmware RESET command above or we're dealing with old firmware
3301          * which doesn't have the HALT capability.  This will serve as a flag
3302          * for the incoming firmware to know that it's coming out of a HALT
3303          * rather than a RESET ... if it's new enough to understand that ...
3304          */
3305         if (ret == 0 || force) {
3306                 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST);
3307                 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT,
3308                                  F_PCIE_FW_HALT);
3309         }
3310
3311         /*
3312          * And we always return the result of the firmware RESET command
3313          * even when we force the uP into RESET ...
3314          */
3315         return ret;
3316 }
3317
3318 /**
3319  * t4_fw_restart - restart the firmware by taking the uP out of RESET
3320  * @adap: the adapter
3321  * @mbox: mailbox to use for the FW RESET command (if desired)
3322  * @reset: if we want to do a RESET to restart things
3323  *
3324  * Restart firmware previously halted by t4_fw_halt().  On successful
3325  * return the previous PF Master remains as the new PF Master and there
3326  * is no need to issue a new HELLO command, etc.
3327  *
3328  * We do this in two ways:
3329  *
3330  * 1. If we're dealing with newer firmware we'll simply want to take
3331  *    the chip's microprocessor out of RESET.  This will cause the
3332  *    firmware to start up from its start vector.  And then we'll loop
3333  *    until the firmware indicates it's started again (PCIE_FW.HALT
3334  *    reset to 0) or we timeout.
3335  *
3336  * 2. If we're dealing with older firmware then we'll need to RESET
3337  *    the chip since older firmware won't recognize the PCIE_FW.HALT
3338  *    flag and automatically RESET itself on startup.
3339  */
3340 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
3341 {
3342         if (reset) {
3343                 /*
3344                  * Since we're directing the RESET instead of the firmware
3345                  * doing it automatically, we need to clear the PCIE_FW.HALT
3346                  * bit.
3347                  */
3348                 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 0);
3349
3350                 /*
3351                  * If we've been given a valid mailbox, first try to get the
3352                  * firmware to do the RESET.  If that works, great and we can
3353                  * return success.  Otherwise, if we haven't been given a
3354                  * valid mailbox or the RESET command failed, fall back to
3355                  * hitting the chip with a hammer.
3356                  */
3357                 if (mbox <= M_PCIE_FW_MASTER) {
3358                         t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
3359                         msleep(100);
3360                         if (t4_fw_reset(adap, mbox,
3361                                         F_PIORST | F_PIORSTMODE) == 0)
3362                                 return 0;
3363                 }
3364
3365                 t4_write_reg(adap, A_PL_RST, F_PIORST | F_PIORSTMODE);
3366                 msleep(2000);
3367         } else {
3368                 int ms;
3369
3370                 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
3371                 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
3372                         if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT))
3373                                 return FW_SUCCESS;
3374                         msleep(100);
3375                         ms += 100;
3376                 }
3377                 return -ETIMEDOUT;
3378         }
3379         return 0;
3380 }
3381
3382 /**
3383  * t4_fl_pkt_align - return the fl packet alignment
3384  * @adap: the adapter
3385  *
3386  * T4 has a single field to specify the packing and padding boundary.
3387  * T5 onwards has separate fields for this and hence the alignment for
3388  * next packet offset is maximum of these two.
3389  */
3390 int t4_fl_pkt_align(struct adapter *adap)
3391 {
3392         u32 sge_control, sge_control2;
3393         unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
3394
3395         sge_control = t4_read_reg(adap, A_SGE_CONTROL);
3396
3397         /* T4 uses a single control field to specify both the PCIe Padding and
3398          * Packing Boundary.  T5 introduced the ability to specify these
3399          * separately.  The actual Ingress Packet Data alignment boundary
3400          * within Packed Buffer Mode is the maximum of these two
3401          * specifications.
3402          */
3403         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
3404                 ingpad_shift = X_INGPADBOUNDARY_SHIFT;
3405         else
3406                 ingpad_shift = X_T6_INGPADBOUNDARY_SHIFT;
3407
3408         ingpadboundary = 1 << (G_INGPADBOUNDARY(sge_control) + ingpad_shift);
3409
3410         fl_align = ingpadboundary;
3411         if (!is_t4(adap->params.chip)) {
3412                 sge_control2 = t4_read_reg(adap, A_SGE_CONTROL2);
3413                 ingpackboundary = G_INGPACKBOUNDARY(sge_control2);
3414                 if (ingpackboundary == X_INGPACKBOUNDARY_16B)
3415                         ingpackboundary = 16;
3416                 else
3417                         ingpackboundary = 1 << (ingpackboundary +
3418                                         X_INGPACKBOUNDARY_SHIFT);
3419
3420                 fl_align = max(ingpadboundary, ingpackboundary);
3421         }
3422         return fl_align;
3423 }
3424
3425 /**
3426  * t4_fixup_host_params_compat - fix up host-dependent parameters
3427  * @adap: the adapter
3428  * @page_size: the host's Base Page Size
3429  * @cache_line_size: the host's Cache Line Size
3430  * @chip_compat: maintain compatibility with designated chip
3431  *
3432  * Various registers in the chip contain values which are dependent on the
3433  * host's Base Page and Cache Line Sizes.  This function will fix all of
3434  * those registers with the appropriate values as passed in ...
3435  *
3436  * @chip_compat is used to limit the set of changes that are made
3437  * to be compatible with the indicated chip release.  This is used by
3438  * drivers to maintain compatibility with chip register settings when
3439  * the drivers haven't [yet] been updated with new chip support.
3440  */
3441 int t4_fixup_host_params_compat(struct adapter *adap,
3442                                 unsigned int page_size,
3443                                 unsigned int cache_line_size,
3444                                 enum chip_type chip_compat)
3445 {
3446         unsigned int page_shift = cxgbe_fls(page_size) - 1;
3447         unsigned int sge_hps = page_shift - 10;
3448         unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
3449         unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
3450         unsigned int fl_align_log = cxgbe_fls(fl_align) - 1;
3451
3452         t4_write_reg(adap, A_SGE_HOST_PAGE_SIZE,
3453                      V_HOSTPAGESIZEPF0(sge_hps) |
3454                      V_HOSTPAGESIZEPF1(sge_hps) |
3455                      V_HOSTPAGESIZEPF2(sge_hps) |
3456                      V_HOSTPAGESIZEPF3(sge_hps) |
3457                      V_HOSTPAGESIZEPF4(sge_hps) |
3458                      V_HOSTPAGESIZEPF5(sge_hps) |
3459                      V_HOSTPAGESIZEPF6(sge_hps) |
3460                      V_HOSTPAGESIZEPF7(sge_hps));
3461
3462         if (is_t4(adap->params.chip) || is_t4(chip_compat))
3463                 t4_set_reg_field(adap, A_SGE_CONTROL,
3464                                  V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
3465                                  F_EGRSTATUSPAGESIZE,
3466                                  V_INGPADBOUNDARY(fl_align_log -
3467                                                   X_INGPADBOUNDARY_SHIFT) |
3468                                 V_EGRSTATUSPAGESIZE(stat_len != 64));
3469         else {
3470                 unsigned int pack_align;
3471                 unsigned int ingpad, ingpack;
3472                 unsigned int pcie_cap;
3473
3474                 /*
3475                  * T5 introduced the separation of the Free List Padding and
3476                  * Packing Boundaries.  Thus, we can select a smaller Padding
3477                  * Boundary to avoid uselessly chewing up PCIe Link and Memory
3478                  * Bandwidth, and use a Packing Boundary which is large enough
3479                  * to avoid false sharing between CPUs, etc.
3480                  *
3481                  * For the PCI Link, the smaller the Padding Boundary the
3482                  * better.  For the Memory Controller, a smaller Padding
3483                  * Boundary is better until we cross under the Memory Line
3484                  * Size (the minimum unit of transfer to/from Memory).  If we
3485                  * have a Padding Boundary which is smaller than the Memory
3486                  * Line Size, that'll involve a Read-Modify-Write cycle on the
3487                  * Memory Controller which is never good.
3488                  */
3489
3490                 /* We want the Packing Boundary to be based on the Cache Line
3491                  * Size in order to help avoid False Sharing performance
3492                  * issues between CPUs, etc.  We also want the Packing
3493                  * Boundary to incorporate the PCI-E Maximum Payload Size.  We
3494                  * get best performance when the Packing Boundary is a
3495                  * multiple of the Maximum Payload Size.
3496                  */
3497                 pack_align = fl_align;
3498                 pcie_cap = t4_os_find_pci_capability(adap, PCI_CAP_ID_EXP);
3499                 if (pcie_cap) {
3500                         unsigned int mps, mps_log;
3501                         u16 devctl;
3502
3503                         /* The PCIe Device Control Maximum Payload Size field
3504                          * [bits 7:5] encodes sizes as powers of 2 starting at
3505                          * 128 bytes.
3506                          */
3507                         t4_os_pci_read_cfg2(adap, pcie_cap + PCI_EXP_DEVCTL,
3508                                             &devctl);
3509                         mps_log = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5) + 7;
3510                         mps = 1 << mps_log;
3511                         if (mps > pack_align)
3512                                 pack_align = mps;
3513                 }
3514
3515                 /*
3516                  * N.B. T5 has a different interpretation of the "0" value for
3517                  * the Packing Boundary.  This corresponds to 16 bytes instead
3518                  * of the expected 32 bytes.  We never have a Packing Boundary
3519                  * less than 32 bytes so we can't use that special value but
3520                  * on the other hand, if we wanted 32 bytes, the best we can
3521                  * really do is 64 bytes ...
3522                  */
3523                 if (pack_align <= 16) {
3524                         ingpack = X_INGPACKBOUNDARY_16B;
3525                         fl_align = 16;
3526                 } else if (pack_align == 32) {
3527                         ingpack = X_INGPACKBOUNDARY_64B;
3528                         fl_align = 64;
3529                 } else {
3530                         unsigned int pack_align_log = cxgbe_fls(pack_align) - 1;
3531
3532                         ingpack = pack_align_log - X_INGPACKBOUNDARY_SHIFT;
3533                         fl_align = pack_align;
3534                 }
3535
3536                 /* Use the smallest Ingress Padding which isn't smaller than
3537                  * the Memory Controller Read/Write Size.  We'll take that as
3538                  * being 8 bytes since we don't know of any system with a
3539                  * wider Memory Controller Bus Width.
3540                  */
3541                 if (is_t5(adap->params.chip))
3542                         ingpad = X_INGPADBOUNDARY_32B;
3543                 else
3544                         ingpad = X_T6_INGPADBOUNDARY_8B;
3545                 t4_set_reg_field(adap, A_SGE_CONTROL,
3546                                  V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
3547                                  F_EGRSTATUSPAGESIZE,
3548                                  V_INGPADBOUNDARY(ingpad) |
3549                                  V_EGRSTATUSPAGESIZE(stat_len != 64));
3550                 t4_set_reg_field(adap, A_SGE_CONTROL2,
3551                                  V_INGPACKBOUNDARY(M_INGPACKBOUNDARY),
3552                                  V_INGPACKBOUNDARY(ingpack));
3553         }
3554
3555         /*
3556          * Adjust various SGE Free List Host Buffer Sizes.
3557          *
3558          * The first four entries are:
3559          *
3560          *   0: Host Page Size
3561          *   1: 64KB
3562          *   2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
3563          *   3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
3564          *
3565          * For the single-MTU buffers in unpacked mode we need to include
3566          * space for the SGE Control Packet Shift, 14 byte Ethernet header,
3567          * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
3568          * Padding boundary.  All of these are accommodated in the Factory
3569          * Default Firmware Configuration File but we need to adjust it for
3570          * this host's cache line size.
3571          */
3572         t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE0, page_size);
3573         t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE2,
3574                      (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE2) + fl_align - 1)
3575                      & ~(fl_align - 1));
3576         t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE3,
3577                      (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE3) + fl_align - 1)
3578                      & ~(fl_align - 1));
3579
3580         t4_write_reg(adap, A_ULP_RX_TDDP_PSZ, V_HPZ0(page_shift - 12));
3581
3582         return 0;
3583 }
3584
3585 /**
3586  * t4_fixup_host_params - fix up host-dependent parameters (T4 compatible)
3587  * @adap: the adapter
3588  * @page_size: the host's Base Page Size
3589  * @cache_line_size: the host's Cache Line Size
3590  *
3591  * Various registers in T4 contain values which are dependent on the
3592  * host's Base Page and Cache Line Sizes.  This function will fix all of
3593  * those registers with the appropriate values as passed in ...
3594  *
3595  * This routine makes changes which are compatible with T4 chips.
3596  */
3597 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
3598                          unsigned int cache_line_size)
3599 {
3600         return t4_fixup_host_params_compat(adap, page_size, cache_line_size,
3601                                            T4_LAST_REV);
3602 }
3603
3604 /**
3605  * t4_fw_initialize - ask FW to initialize the device
3606  * @adap: the adapter
3607  * @mbox: mailbox to use for the FW command
3608  *
3609  * Issues a command to FW to partially initialize the device.  This
3610  * performs initialization that generally doesn't depend on user input.
3611  */
3612 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
3613 {
3614         struct fw_initialize_cmd c;
3615
3616         memset(&c, 0, sizeof(c));
3617         INIT_CMD(c, INITIALIZE, WRITE);
3618         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3619 }
3620
3621 /**
3622  * t4_query_params_rw - query FW or device parameters
3623  * @adap: the adapter
3624  * @mbox: mailbox to use for the FW command
3625  * @pf: the PF
3626  * @vf: the VF
3627  * @nparams: the number of parameters
3628  * @params: the parameter names
3629  * @val: the parameter values
3630  * @rw: Write and read flag
3631  *
3632  * Reads the value of FW or device parameters.  Up to 7 parameters can be
3633  * queried at once.
3634  */
3635 static int t4_query_params_rw(struct adapter *adap, unsigned int mbox,
3636                               unsigned int pf, unsigned int vf,
3637                               unsigned int nparams, const u32 *params,
3638                               u32 *val, int rw)
3639 {
3640         unsigned int i;
3641         int ret;
3642         struct fw_params_cmd c;
3643         __be32 *p = &c.param[0].mnem;
3644
3645         if (nparams > 7)
3646                 return -EINVAL;
3647
3648         memset(&c, 0, sizeof(c));
3649         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3650                                   F_FW_CMD_REQUEST | F_FW_CMD_READ |
3651                                   V_FW_PARAMS_CMD_PFN(pf) |
3652                                   V_FW_PARAMS_CMD_VFN(vf));
3653         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3654
3655         for (i = 0; i < nparams; i++) {
3656                 *p++ = cpu_to_be32(*params++);
3657                 if (rw)
3658                         *p = cpu_to_be32(*(val + i));
3659                 p++;
3660         }
3661
3662         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3663         if (ret == 0)
3664                 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
3665                         *val++ = be32_to_cpu(*p);
3666         return ret;
3667 }
3668
3669 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3670                     unsigned int vf, unsigned int nparams, const u32 *params,
3671                     u32 *val)
3672 {
3673         return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
3674 }
3675
3676 /**
3677  * t4_set_params_timeout - sets FW or device parameters
3678  * @adap: the adapter
3679  * @mbox: mailbox to use for the FW command
3680  * @pf: the PF
3681  * @vf: the VF
3682  * @nparams: the number of parameters
3683  * @params: the parameter names
3684  * @val: the parameter values
3685  * @timeout: the timeout time
3686  *
3687  * Sets the value of FW or device parameters.  Up to 7 parameters can be
3688  * specified at once.
3689  */
3690 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
3691                           unsigned int pf, unsigned int vf,
3692                           unsigned int nparams, const u32 *params,
3693                           const u32 *val, int timeout)
3694 {
3695         struct fw_params_cmd c;
3696         __be32 *p = &c.param[0].mnem;
3697
3698         if (nparams > 7)
3699                 return -EINVAL;
3700
3701         memset(&c, 0, sizeof(c));
3702         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3703                                   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3704                                   V_FW_PARAMS_CMD_PFN(pf) |
3705                                   V_FW_PARAMS_CMD_VFN(vf));
3706         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3707
3708         while (nparams--) {
3709                 *p++ = cpu_to_be32(*params++);
3710                 *p++ = cpu_to_be32(*val++);
3711         }
3712
3713         return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
3714 }
3715
3716 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3717                   unsigned int vf, unsigned int nparams, const u32 *params,
3718                   const u32 *val)
3719 {
3720         return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
3721                                      FW_CMD_MAX_TIMEOUT);
3722 }
3723
3724 /**
3725  * t4_alloc_vi_func - allocate a virtual interface
3726  * @adap: the adapter
3727  * @mbox: mailbox to use for the FW command
3728  * @port: physical port associated with the VI
3729  * @pf: the PF owning the VI
3730  * @vf: the VF owning the VI
3731  * @nmac: number of MAC addresses needed (1 to 5)
3732  * @mac: the MAC addresses of the VI
3733  * @rss_size: size of RSS table slice associated with this VI
3734  * @portfunc: which Port Application Function MAC Address is desired
3735  * @idstype: Intrusion Detection Type
3736  *
3737  * Allocates a virtual interface for the given physical port.  If @mac is
3738  * not %NULL it contains the MAC addresses of the VI as assigned by FW.
3739  * @mac should be large enough to hold @nmac Ethernet addresses, they are
3740  * stored consecutively so the space needed is @nmac * 6 bytes.
3741  * Returns a negative error number or the non-negative VI id.
3742  */
3743 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
3744                      unsigned int port, unsigned int pf, unsigned int vf,
3745                      unsigned int nmac, u8 *mac, unsigned int *rss_size,
3746                      unsigned int portfunc, unsigned int idstype)
3747 {
3748         int ret;
3749         struct fw_vi_cmd c;
3750
3751         memset(&c, 0, sizeof(c));
3752         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
3753                                   F_FW_CMD_WRITE | F_FW_CMD_EXEC |
3754                                   V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf));
3755         c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c));
3756         c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) |
3757                                      V_FW_VI_CMD_FUNC(portfunc));
3758         c.portid_pkd = V_FW_VI_CMD_PORTID(port);
3759         c.nmac = nmac - 1;
3760
3761         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3762         if (ret)
3763                 return ret;
3764
3765         if (mac) {
3766                 memcpy(mac, c.mac, sizeof(c.mac));
3767                 switch (nmac) {
3768                 case 5:
3769                         memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
3770                         /* FALLTHROUGH */
3771                 case 4:
3772                         memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
3773                         /* FALLTHROUGH */
3774                 case 3:
3775                         memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
3776                         /* FALLTHROUGH */
3777                 case 2:
3778                         memcpy(mac + 6,  c.nmac0, sizeof(c.nmac0));
3779                         /* FALLTHROUGH */
3780                 }
3781         }
3782         if (rss_size)
3783                 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize));
3784         return G_FW_VI_CMD_VIID(cpu_to_be16(c.type_to_viid));
3785 }
3786
3787 /**
3788  * t4_alloc_vi - allocate an [Ethernet Function] virtual interface
3789  * @adap: the adapter
3790  * @mbox: mailbox to use for the FW command
3791  * @port: physical port associated with the VI
3792  * @pf: the PF owning the VI
3793  * @vf: the VF owning the VI
3794  * @nmac: number of MAC addresses needed (1 to 5)
3795  * @mac: the MAC addresses of the VI
3796  * @rss_size: size of RSS table slice associated with this VI
3797  *
3798  * Backwards compatible and convieniance routine to allocate a Virtual
3799  * Interface with a Ethernet Port Application Function and Intrustion
3800  * Detection System disabled.
3801  */
3802 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
3803                 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
3804                 unsigned int *rss_size)
3805 {
3806         return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size,
3807                                 FW_VI_FUNC_ETH, 0);
3808 }
3809
3810 /**
3811  * t4_free_vi - free a virtual interface
3812  * @adap: the adapter
3813  * @mbox: mailbox to use for the FW command
3814  * @pf: the PF owning the VI
3815  * @vf: the VF owning the VI
3816  * @viid: virtual interface identifiler
3817  *
3818  * Free a previously allocated virtual interface.
3819  */
3820 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
3821                unsigned int vf, unsigned int viid)
3822 {
3823         struct fw_vi_cmd c;
3824
3825         memset(&c, 0, sizeof(c));
3826         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
3827                                   F_FW_CMD_EXEC | V_FW_VI_CMD_PFN(pf) |
3828                                   V_FW_VI_CMD_VFN(vf));
3829         c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c));
3830         c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid));
3831
3832         return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3833 }
3834
3835 /**
3836  * t4_set_rxmode - set Rx properties of a virtual interface
3837  * @adap: the adapter
3838  * @mbox: mailbox to use for the FW command
3839  * @viid: the VI id
3840  * @mtu: the new MTU or -1
3841  * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
3842  * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
3843  * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
3844  * @vlanex: 1 to enable hardware VLAN Tag extraction, 0 to disable it,
3845  *          -1 no change
3846  * @sleep_ok: if true we may sleep while awaiting command completion
3847  *
3848  * Sets Rx properties of a virtual interface.
3849  */
3850 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
3851                   int mtu, int promisc, int all_multi, int bcast, int vlanex,
3852                   bool sleep_ok)
3853 {
3854         struct fw_vi_rxmode_cmd c;
3855
3856         /* convert to FW values */
3857         if (mtu < 0)
3858                 mtu = M_FW_VI_RXMODE_CMD_MTU;
3859         if (promisc < 0)
3860                 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN;
3861         if (all_multi < 0)
3862                 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN;
3863         if (bcast < 0)
3864                 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN;
3865         if (vlanex < 0)
3866                 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN;
3867
3868         memset(&c, 0, sizeof(c));
3869         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) |
3870                                    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3871                                    V_FW_VI_RXMODE_CMD_VIID(viid));
3872         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3873         c.mtu_to_vlanexen = cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) |
3874                             V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
3875                             V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
3876                             V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
3877                             V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
3878         return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
3879 }
3880
3881 /**
3882  * t4_change_mac - modifies the exact-match filter for a MAC address
3883  * @adap: the adapter
3884  * @mbox: mailbox to use for the FW command
3885  * @viid: the VI id
3886  * @idx: index of existing filter for old value of MAC address, or -1
3887  * @addr: the new MAC address value
3888  * @persist: whether a new MAC allocation should be persistent
3889  * @add_smt: if true also add the address to the HW SMT
3890  *
3891  * Modifies an exact-match filter and sets it to the new MAC address if
3892  * @idx >= 0, or adds the MAC address to a new filter if @idx < 0.  In the
3893  * latter case the address is added persistently if @persist is %true.
3894  *
3895  * Note that in general it is not possible to modify the value of a given
3896  * filter so the generic way to modify an address filter is to free the one
3897  * being used by the old address value and allocate a new filter for the
3898  * new address value.
3899  *
3900  * Returns a negative error number or the index of the filter with the new
3901  * MAC value.  Note that this index may differ from @idx.
3902  */
3903 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
3904                   int idx, const u8 *addr, bool persist, bool add_smt)
3905 {
3906         int ret, mode;
3907         struct fw_vi_mac_cmd c;
3908         struct fw_vi_mac_exact *p = c.u.exact;
3909         int max_mac_addr = adap->params.arch.mps_tcam_size;
3910
3911         if (idx < 0)                             /* new allocation */
3912                 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
3913         mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
3914
3915         memset(&c, 0, sizeof(c));
3916         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
3917                                    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3918                                    V_FW_VI_MAC_CMD_VIID(viid));
3919         c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1));
3920         p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
3921                                       V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
3922                                       V_FW_VI_MAC_CMD_IDX(idx));
3923         memcpy(p->macaddr, addr, sizeof(p->macaddr));
3924
3925         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3926         if (ret == 0) {
3927                 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
3928                 if (ret >= max_mac_addr)
3929                         ret = -ENOMEM;
3930         }
3931         return ret;
3932 }
3933
3934 /**
3935  * t4_enable_vi_params - enable/disable a virtual interface
3936  * @adap: the adapter
3937  * @mbox: mailbox to use for the FW command
3938  * @viid: the VI id
3939  * @rx_en: 1=enable Rx, 0=disable Rx
3940  * @tx_en: 1=enable Tx, 0=disable Tx
3941  * @dcb_en: 1=enable delivery of Data Center Bridging messages.
3942  *
3943  * Enables/disables a virtual interface.  Note that setting DCB Enable
3944  * only makes sense when enabling a Virtual Interface ...
3945  */
3946 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
3947                         unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
3948 {
3949         struct fw_vi_enable_cmd c;
3950
3951         memset(&c, 0, sizeof(c));
3952         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
3953                                    F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3954                                    V_FW_VI_ENABLE_CMD_VIID(viid));
3955         c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) |
3956                                      V_FW_VI_ENABLE_CMD_EEN(tx_en) |
3957                                      V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) |
3958                                      FW_LEN16(c));
3959         return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
3960 }
3961
3962 /**
3963  * t4_enable_vi - enable/disable a virtual interface
3964  * @adap: the adapter
3965  * @mbox: mailbox to use for the FW command
3966  * @viid: the VI id
3967  * @rx_en: 1=enable Rx, 0=disable Rx
3968  * @tx_en: 1=enable Tx, 0=disable Tx
3969  *
3970  * Enables/disables a virtual interface.  Note that setting DCB Enable
3971  * only makes sense when enabling a Virtual Interface ...
3972  */
3973 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
3974                  bool rx_en, bool tx_en)
3975 {
3976         return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
3977 }
3978
3979 /**
3980  * t4_iq_start_stop - enable/disable an ingress queue and its FLs
3981  * @adap: the adapter
3982  * @mbox: mailbox to use for the FW command
3983  * @start: %true to enable the queues, %false to disable them
3984  * @pf: the PF owning the queues
3985  * @vf: the VF owning the queues
3986  * @iqid: ingress queue id
3987  * @fl0id: FL0 queue id or 0xffff if no attached FL0
3988  * @fl1id: FL1 queue id or 0xffff if no attached FL1
3989  *
3990  * Starts or stops an ingress queue and its associated FLs, if any.
3991  */
3992 int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start,
3993                      unsigned int pf, unsigned int vf, unsigned int iqid,
3994                      unsigned int fl0id, unsigned int fl1id)
3995 {
3996         struct fw_iq_cmd c;
3997
3998         memset(&c, 0, sizeof(c));
3999         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
4000                                   F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
4001                                   V_FW_IQ_CMD_VFN(vf));
4002         c.alloc_to_len16 = cpu_to_be32(V_FW_IQ_CMD_IQSTART(start) |
4003                                        V_FW_IQ_CMD_IQSTOP(!start) |
4004                                        FW_LEN16(c));
4005         c.iqid = cpu_to_be16(iqid);
4006         c.fl0id = cpu_to_be16(fl0id);
4007         c.fl1id = cpu_to_be16(fl1id);
4008         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4009 }
4010
4011 /**
4012  * t4_iq_free - free an ingress queue and its FLs
4013  * @adap: the adapter
4014  * @mbox: mailbox to use for the FW command
4015  * @pf: the PF owning the queues
4016  * @vf: the VF owning the queues
4017  * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
4018  * @iqid: ingress queue id
4019  * @fl0id: FL0 queue id or 0xffff if no attached FL0
4020  * @fl1id: FL1 queue id or 0xffff if no attached FL1
4021  *
4022  * Frees an ingress queue and its associated FLs, if any.
4023  */
4024 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
4025                unsigned int vf, unsigned int iqtype, unsigned int iqid,
4026                unsigned int fl0id, unsigned int fl1id)
4027 {
4028         struct fw_iq_cmd c;
4029
4030         memset(&c, 0, sizeof(c));
4031         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
4032                                   F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
4033                                   V_FW_IQ_CMD_VFN(vf));
4034         c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c));
4035         c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
4036         c.iqid = cpu_to_be16(iqid);
4037         c.fl0id = cpu_to_be16(fl0id);
4038         c.fl1id = cpu_to_be16(fl1id);
4039         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4040 }
4041
4042 /**
4043  * t4_eth_eq_free - free an Ethernet egress queue
4044  * @adap: the adapter
4045  * @mbox: mailbox to use for the FW command
4046  * @pf: the PF owning the queue
4047  * @vf: the VF owning the queue
4048  * @eqid: egress queue id
4049  *
4050  * Frees an Ethernet egress queue.
4051  */
4052 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
4053                    unsigned int vf, unsigned int eqid)
4054 {
4055         struct fw_eq_eth_cmd c;
4056
4057         memset(&c, 0, sizeof(c));
4058         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) |
4059                                   F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
4060                                   V_FW_EQ_ETH_CMD_PFN(pf) |
4061                                   V_FW_EQ_ETH_CMD_VFN(vf));
4062         c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
4063         c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid));
4064         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4065 }
4066
4067 /**
4068  * t4_handle_fw_rpl - process a FW reply message
4069  * @adap: the adapter
4070  * @rpl: start of the FW message
4071  *
4072  * Processes a FW message, such as link state change messages.
4073  */
4074 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
4075 {
4076         u8 opcode = *(const u8 *)rpl;
4077
4078         /*
4079          * This might be a port command ... this simplifies the following
4080          * conditionals ...  We can get away with pre-dereferencing
4081          * action_to_len16 because it's in the first 16 bytes and all messages
4082          * will be at least that long.
4083          */
4084         const struct fw_port_cmd *p = (const void *)rpl;
4085         unsigned int action =
4086                 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16));
4087
4088         if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) {
4089                 /* link/module state change message */
4090                 unsigned int speed = 0, fc = 0, i;
4091                 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));
4092                 struct port_info *pi = NULL;
4093                 struct link_config *lc;
4094                 u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
4095                 int link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0;
4096                 u32 mod = G_FW_PORT_CMD_MODTYPE(stat);
4097
4098                 if (stat & F_FW_PORT_CMD_RXPAUSE)
4099                         fc |= PAUSE_RX;
4100                 if (stat & F_FW_PORT_CMD_TXPAUSE)
4101                         fc |= PAUSE_TX;
4102                 if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
4103                         speed = ETH_SPEED_NUM_100M;
4104                 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
4105                         speed = ETH_SPEED_NUM_1G;
4106                 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
4107                         speed = ETH_SPEED_NUM_10G;
4108                 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G))
4109                         speed = ETH_SPEED_NUM_25G;
4110                 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
4111                         speed = ETH_SPEED_NUM_40G;
4112                 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G))
4113                         speed = ETH_SPEED_NUM_100G;
4114
4115                 for_each_port(adap, i) {
4116                         pi = adap2pinfo(adap, i);
4117                         if (pi->tx_chan == chan)
4118                                 break;
4119                 }
4120                 lc = &pi->link_cfg;
4121
4122                 if (mod != pi->mod_type) {
4123                         pi->mod_type = mod;
4124                         t4_os_portmod_changed(adap, i);
4125                 }
4126                 if (link_ok != lc->link_ok || speed != lc->speed ||
4127                     fc != lc->fc) {                    /* something changed */
4128                         if (!link_ok && lc->link_ok) {
4129                                 static const char * const reason[] = {
4130                                         "Link Down",
4131                                         "Remote Fault",
4132                                         "Auto-negotiation Failure",
4133                                         "Reserved",
4134                                         "Insufficient Airflow",
4135                                         "Unable To Determine Reason",
4136                                         "No RX Signal Detected",
4137                                         "Reserved",
4138                                 };
4139                                 unsigned int rc = G_FW_PORT_CMD_LINKDNRC(stat);
4140
4141                                 dev_warn(adap, "Port %d link down, reason: %s\n",
4142                                          chan, reason[rc]);
4143                         }
4144                         lc->link_ok = link_ok;
4145                         lc->speed = speed;
4146                         lc->fc = fc;
4147                         lc->supported = be16_to_cpu(p->u.info.pcap);
4148                 }
4149         } else {
4150                 dev_warn(adap, "Unknown firmware reply %d\n", opcode);
4151                 return -EINVAL;
4152         }
4153         return 0;
4154 }
4155
4156 void t4_reset_link_config(struct adapter *adap, int idx)
4157 {
4158         struct port_info *pi = adap2pinfo(adap, idx);
4159         struct link_config *lc = &pi->link_cfg;
4160
4161         lc->link_ok = 0;
4162         lc->requested_speed = 0;
4163         lc->requested_fc = 0;
4164         lc->speed = 0;
4165         lc->fc = 0;
4166 }
4167
4168 /**
4169  * init_link_config - initialize a link's SW state
4170  * @lc: structure holding the link state
4171  * @pcaps: link Port Capabilities
4172  * @acaps: link current Advertised Port Capabilities
4173  *
4174  * Initializes the SW state maintained for each link, including the link's
4175  * capabilities and default speed/flow-control/autonegotiation settings.
4176  */
4177 static void init_link_config(struct link_config *lc, unsigned int pcaps,
4178                              unsigned int acaps)
4179 {
4180         unsigned int fec;
4181
4182         lc->supported = pcaps;
4183         lc->requested_speed = 0;
4184         lc->speed = 0;
4185         lc->requested_fc = 0;
4186         lc->fc = 0;
4187
4188         /**
4189          * For Forward Error Control, we default to whatever the Firmware
4190          * tells us the Link is currently advertising.
4191          */
4192         fec = 0;
4193         if (acaps & FW_PORT_CAP_FEC_RS)
4194                 fec |= FEC_RS;
4195         if (acaps & FW_PORT_CAP_FEC_BASER_RS)
4196                 fec |= FEC_BASER_RS;
4197         if (acaps & FW_PORT_CAP_FEC_RESERVED)
4198                 fec |= FEC_RESERVED;
4199         lc->requested_fec = fec;
4200         lc->fec = fec;
4201
4202         if (lc->supported & FW_PORT_CAP_ANEG) {
4203                 lc->advertising = lc->supported & ADVERT_MASK;
4204                 lc->autoneg = AUTONEG_ENABLE;
4205         } else {
4206                 lc->advertising = 0;
4207                 lc->autoneg = AUTONEG_DISABLE;
4208         }
4209 }
4210
4211 /**
4212  * t4_wait_dev_ready - wait till to reads of registers work
4213  *
4214  * Right after the device is RESET is can take a small amount of time
4215  * for it to respond to register reads.  Until then, all reads will
4216  * return either 0xff...ff or 0xee...ee.  Return an error if reads
4217  * don't work within a reasonable time frame.
4218  */
4219 static int t4_wait_dev_ready(struct adapter *adapter)
4220 {
4221         u32 whoami;
4222
4223         whoami = t4_read_reg(adapter, A_PL_WHOAMI);
4224
4225         if (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS)
4226                 return 0;
4227
4228         msleep(500);
4229         whoami = t4_read_reg(adapter, A_PL_WHOAMI);
4230         if (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS)
4231                 return 0;
4232
4233         dev_err(adapter, "Device didn't become ready for access, whoami = %#x\n",
4234                 whoami);
4235         return -EIO;
4236 }
4237
4238 struct flash_desc {
4239         u32 vendor_and_model_id;
4240         u32 size_mb;
4241 };
4242
4243 int t4_get_flash_params(struct adapter *adapter)
4244 {
4245         /*
4246          * Table for non-Numonix supported flash parts.  Numonix parts are left
4247          * to the preexisting well-tested code.  All flash parts have 64KB
4248          * sectors.
4249          */
4250         static struct flash_desc supported_flash[] = {
4251                 { 0x00150201, 4 << 20 },       /* Spansion 4MB S25FL032P */
4252         };
4253
4254         int ret;
4255         u32 flashid = 0;
4256         unsigned int part, manufacturer;
4257         unsigned int density, size;
4258
4259         /**
4260          * Issue a Read ID Command to the Flash part.  We decode supported
4261          * Flash parts and their sizes from this.  There's a newer Query
4262          * Command which can retrieve detailed geometry information but
4263          * many Flash parts don't support it.
4264          */
4265         ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID);
4266         if (!ret)
4267                 ret = sf1_read(adapter, 3, 0, 1, &flashid);
4268         t4_write_reg(adapter, A_SF_OP, 0);               /* unlock SF */
4269         if (ret < 0)
4270                 return ret;
4271
4272         for (part = 0; part < ARRAY_SIZE(supported_flash); part++) {
4273                 if (supported_flash[part].vendor_and_model_id == flashid) {
4274                         adapter->params.sf_size =
4275                                 supported_flash[part].size_mb;
4276                         adapter->params.sf_nsec =
4277                                 adapter->params.sf_size / SF_SEC_SIZE;
4278                         goto found;
4279                 }
4280         }
4281
4282         manufacturer = flashid & 0xff;
4283         switch (manufacturer) {
4284         case 0x20: { /* Micron/Numonix */
4285                 /**
4286                  * This Density -> Size decoding table is taken from Micron
4287                  * Data Sheets.
4288                  */
4289                 density = (flashid >> 16) & 0xff;
4290                 switch (density) {
4291                 case 0x14:
4292                         size = 1 << 20; /* 1MB */
4293                         break;
4294                 case 0x15:
4295                         size = 1 << 21; /* 2MB */
4296                         break;
4297                 case 0x16:
4298                         size = 1 << 22; /* 4MB */
4299                         break;
4300                 case 0x17:
4301                         size = 1 << 23; /* 8MB */
4302                         break;
4303                 case 0x18:
4304                         size = 1 << 24; /* 16MB */
4305                         break;
4306                 case 0x19:
4307                         size = 1 << 25; /* 32MB */
4308                         break;
4309                 case 0x20:
4310                         size = 1 << 26; /* 64MB */
4311                         break;
4312                 case 0x21:
4313                         size = 1 << 27; /* 128MB */
4314                         break;
4315                 case 0x22:
4316                         size = 1 << 28; /* 256MB */
4317                         break;
4318                 default:
4319                         dev_err(adapter, "Micron Flash Part has bad size, ID = %#x, Density code = %#x\n",
4320                                 flashid, density);
4321                         return -EINVAL;
4322                 }
4323
4324                 adapter->params.sf_size = size;
4325                 adapter->params.sf_nsec = size / SF_SEC_SIZE;
4326                 break;
4327         }
4328         default:
4329                 dev_err(adapter, "Unsupported Flash Part, ID = %#x\n", flashid);
4330                 return -EINVAL;
4331         }
4332
4333 found:
4334         /*
4335          * We should reject adapters with FLASHes which are too small. So, emit
4336          * a warning.
4337          */
4338         if (adapter->params.sf_size < FLASH_MIN_SIZE)
4339                 dev_warn(adapter, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
4340                          flashid, adapter->params.sf_size, FLASH_MIN_SIZE);
4341
4342         return 0;
4343 }
4344
4345 static void set_pcie_completion_timeout(struct adapter *adapter,
4346                                         u8 range)
4347 {
4348         u32 pcie_cap;
4349         u16 val;
4350
4351         pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
4352         if (pcie_cap) {
4353                 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val);
4354                 val &= 0xfff0;
4355                 val |= range;
4356                 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val);
4357         }
4358 }
4359
4360 /**
4361  * t4_get_chip_type - Determine chip type from device ID
4362  * @adap: the adapter
4363  * @ver: adapter version
4364  */
4365 int t4_get_chip_type(struct adapter *adap, int ver)
4366 {
4367         enum chip_type chip = 0;
4368         u32 pl_rev = G_REV(t4_read_reg(adap, A_PL_REV));
4369
4370         /* Retrieve adapter's device ID */
4371         switch (ver) {
4372         case CHELSIO_T5:
4373                 chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4374                 break;
4375         case CHELSIO_T6:
4376                 chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
4377                 break;
4378         default:
4379                 dev_err(adap, "Device %d is not supported\n",
4380                         adap->params.pci.device_id);
4381                 return -EINVAL;
4382         }
4383
4384         return chip;
4385 }
4386
4387 /**
4388  * t4_prep_adapter - prepare SW and HW for operation
4389  * @adapter: the adapter
4390  *
4391  * Initialize adapter SW state for the various HW modules, set initial
4392  * values for some adapter tunables, take PHYs out of reset, and
4393  * initialize the MDIO interface.
4394  */
4395 int t4_prep_adapter(struct adapter *adapter)
4396 {
4397         int ret, ver;
4398         u32 pl_rev;
4399
4400         ret = t4_wait_dev_ready(adapter);
4401         if (ret < 0)
4402                 return ret;
4403
4404         pl_rev = G_REV(t4_read_reg(adapter, A_PL_REV));
4405         adapter->params.pci.device_id = adapter->pdev->id.device_id;
4406         adapter->params.pci.vendor_id = adapter->pdev->id.vendor_id;
4407
4408         /*
4409          * WE DON'T NEED adapter->params.chip CODE ONCE PL_REV CONTAINS
4410          * ADAPTER (VERSION << 4 | REVISION)
4411          */
4412         ver = CHELSIO_PCI_ID_VER(adapter->params.pci.device_id);
4413         adapter->params.chip = 0;
4414         switch (ver) {
4415         case CHELSIO_T5:
4416                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4417                 adapter->params.arch.sge_fl_db = F_DBPRIO | F_DBTYPE;
4418                 adapter->params.arch.mps_tcam_size =
4419                                                 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
4420                 adapter->params.arch.mps_rplc_size = 128;
4421                 adapter->params.arch.nchan = NCHAN;
4422                 adapter->params.arch.vfcount = 128;
4423                 break;
4424         case CHELSIO_T6:
4425                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
4426                 adapter->params.arch.sge_fl_db = 0;
4427                 adapter->params.arch.mps_tcam_size =
4428                                                 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
4429                 adapter->params.arch.mps_rplc_size = 256;
4430                 adapter->params.arch.nchan = 2;
4431                 adapter->params.arch.vfcount = 256;
4432                 break;
4433         default:
4434                 dev_err(adapter, "%s: Device %d is not supported\n",
4435                         __func__, adapter->params.pci.device_id);
4436                 return -EINVAL;
4437         }
4438
4439         adapter->params.pci.vpd_cap_addr =
4440                 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
4441
4442         ret = t4_get_flash_params(adapter);
4443         if (ret < 0) {
4444                 dev_err(adapter, "Unable to retrieve Flash Parameters, ret = %d\n",
4445                         -ret);
4446                 return ret;
4447         }
4448
4449         adapter->params.cim_la_size = CIMLA_SIZE;
4450
4451         init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
4452
4453         /*
4454          * Default port and clock for debugging in case we can't reach FW.
4455          */
4456         adapter->params.nports = 1;
4457         adapter->params.portvec = 1;
4458         adapter->params.vpd.cclk = 50000;
4459
4460         /* Set pci completion timeout value to 4 seconds. */
4461         set_pcie_completion_timeout(adapter, 0xd);
4462         return 0;
4463 }
4464
4465 /**
4466  * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
4467  * @adapter: the adapter
4468  * @qid: the Queue ID
4469  * @qtype: the Ingress or Egress type for @qid
4470  * @pbar2_qoffset: BAR2 Queue Offset
4471  * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
4472  *
4473  * Returns the BAR2 SGE Queue Registers information associated with the
4474  * indicated Absolute Queue ID.  These are passed back in return value
4475  * pointers.  @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
4476  * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
4477  *
4478  * This may return an error which indicates that BAR2 SGE Queue
4479  * registers aren't available.  If an error is not returned, then the
4480  * following values are returned:
4481  *
4482  *   *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
4483  *   *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
4484  *
4485  * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
4486  * require the "Inferred Queue ID" ability may be used.  E.g. the
4487  * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
4488  * then these "Inferred Queue ID" register may not be used.
4489  */
4490 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,
4491                       enum t4_bar2_qtype qtype, u64 *pbar2_qoffset,
4492                       unsigned int *pbar2_qid)
4493 {
4494         unsigned int page_shift, page_size, qpp_shift, qpp_mask;
4495         u64 bar2_page_offset, bar2_qoffset;
4496         unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
4497
4498         /*
4499          * T4 doesn't support BAR2 SGE Queue registers.
4500          */
4501         if (is_t4(adapter->params.chip))
4502                 return -EINVAL;
4503
4504         /*
4505          * Get our SGE Page Size parameters.
4506          */
4507         page_shift = adapter->params.sge.hps + 10;
4508         page_size = 1 << page_shift;
4509
4510         /*
4511          * Get the right Queues per Page parameters for our Queue.
4512          */
4513         qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS ?
4514                               adapter->params.sge.eq_qpp :
4515                               adapter->params.sge.iq_qpp);
4516         qpp_mask = (1 << qpp_shift) - 1;
4517
4518         /*
4519          * Calculate the basics of the BAR2 SGE Queue register area:
4520          *  o The BAR2 page the Queue registers will be in.
4521          *  o The BAR2 Queue ID.
4522          *  o The BAR2 Queue ID Offset into the BAR2 page.
4523          */
4524         bar2_page_offset = ((qid >> qpp_shift) << page_shift);
4525         bar2_qid = qid & qpp_mask;
4526         bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
4527
4528         /*
4529          * If the BAR2 Queue ID Offset is less than the Page Size, then the
4530          * hardware will infer the Absolute Queue ID simply from the writes to
4531          * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
4532          * BAR2 Queue ID of 0 for those writes).  Otherwise, we'll simply
4533          * write to the first BAR2 SGE Queue Area within the BAR2 Page with
4534          * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
4535          * from the BAR2 Page and BAR2 Queue ID.
4536          *
4537          * One important censequence of this is that some BAR2 SGE registers
4538          * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
4539          * there.  But other registers synthesize the SGE Queue ID purely
4540          * from the writes to the registers -- the Write Combined Doorbell
4541          * Buffer is a good example.  These BAR2 SGE Registers are only
4542          * available for those BAR2 SGE Register areas where the SGE Absolute
4543          * Queue ID can be inferred from simple writes.
4544          */
4545         bar2_qoffset = bar2_page_offset;
4546         bar2_qinferred = (bar2_qid_offset < page_size);
4547         if (bar2_qinferred) {
4548                 bar2_qoffset += bar2_qid_offset;
4549                 bar2_qid = 0;
4550         }
4551
4552         *pbar2_qoffset = bar2_qoffset;
4553         *pbar2_qid = bar2_qid;
4554         return 0;
4555 }
4556
4557 /**
4558  * t4_init_sge_params - initialize adap->params.sge
4559  * @adapter: the adapter
4560  *
4561  * Initialize various fields of the adapter's SGE Parameters structure.
4562  */
4563 int t4_init_sge_params(struct adapter *adapter)
4564 {
4565         struct sge_params *sge_params = &adapter->params.sge;
4566         u32 hps, qpp;
4567         unsigned int s_hps, s_qpp;
4568
4569         /*
4570          * Extract the SGE Page Size for our PF.
4571          */
4572         hps = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE);
4573         s_hps = (S_HOSTPAGESIZEPF0 + (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) *
4574                  adapter->pf);
4575         sge_params->hps = ((hps >> s_hps) & M_HOSTPAGESIZEPF0);
4576
4577         /*
4578          * Extract the SGE Egress and Ingess Queues Per Page for our PF.
4579          */
4580         s_qpp = (S_QUEUESPERPAGEPF0 +
4581                  (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf);
4582         qpp = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
4583         sge_params->eq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
4584         qpp = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
4585         sge_params->iq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
4586
4587         return 0;
4588 }
4589
4590 /**
4591  * t4_init_tp_params - initialize adap->params.tp
4592  * @adap: the adapter
4593  *
4594  * Initialize various fields of the adapter's TP Parameters structure.
4595  */
4596 int t4_init_tp_params(struct adapter *adap)
4597 {
4598         int chan;
4599         u32 v;
4600
4601         v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION);
4602         adap->params.tp.tre = G_TIMERRESOLUTION(v);
4603         adap->params.tp.dack_re = G_DELAYEDACKRESOLUTION(v);
4604
4605         /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
4606         for (chan = 0; chan < NCHAN; chan++)
4607                 adap->params.tp.tx_modq[chan] = chan;
4608
4609         /*
4610          * Cache the adapter's Compressed Filter Mode and global Incress
4611          * Configuration.
4612          */
4613         t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4614                          &adap->params.tp.vlan_pri_map, 1, A_TP_VLAN_PRI_MAP);
4615         t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4616                          &adap->params.tp.ingress_config, 1,
4617                          A_TP_INGRESS_CONFIG);
4618
4619         /* For T6, cache the adapter's compressed error vector
4620          * and passing outer header info for encapsulated packets.
4621          */
4622         if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
4623                 v = t4_read_reg(adap, A_TP_OUT_CONFIG);
4624                 adap->params.tp.rx_pkt_encap = (v & F_CRXPKTENC) ? 1 : 0;
4625         }
4626
4627         /*
4628          * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
4629          * shift positions of several elements of the Compressed Filter Tuple
4630          * for this adapter which we need frequently ...
4631          */
4632         adap->params.tp.vlan_shift = t4_filter_field_shift(adap, F_VLAN);
4633         adap->params.tp.vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
4634         adap->params.tp.port_shift = t4_filter_field_shift(adap, F_PORT);
4635         adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
4636                                                                F_PROTOCOL);
4637
4638         /*
4639          * If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
4640          * represents the presense of an Outer VLAN instead of a VNIC ID.
4641          */
4642         if ((adap->params.tp.ingress_config & F_VNIC) == 0)
4643                 adap->params.tp.vnic_shift = -1;
4644
4645         return 0;
4646 }
4647
4648 /**
4649  * t4_filter_field_shift - calculate filter field shift
4650  * @adap: the adapter
4651  * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
4652  *
4653  * Return the shift position of a filter field within the Compressed
4654  * Filter Tuple.  The filter field is specified via its selection bit
4655  * within TP_VLAN_PRI_MAL (filter mode).  E.g. F_VLAN.
4656  */
4657 int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel)
4658 {
4659         unsigned int filter_mode = adap->params.tp.vlan_pri_map;
4660         unsigned int sel;
4661         int field_shift;
4662
4663         if ((filter_mode & filter_sel) == 0)
4664                 return -1;
4665
4666         for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
4667                 switch (filter_mode & sel) {
4668                 case F_FCOE:
4669                         field_shift += W_FT_FCOE;
4670                         break;
4671                 case F_PORT:
4672                         field_shift += W_FT_PORT;
4673                         break;
4674                 case F_VNIC_ID:
4675                         field_shift += W_FT_VNIC_ID;
4676                         break;
4677                 case F_VLAN:
4678                         field_shift += W_FT_VLAN;
4679                         break;
4680                 case F_TOS:
4681                         field_shift += W_FT_TOS;
4682                         break;
4683                 case F_PROTOCOL:
4684                         field_shift += W_FT_PROTOCOL;
4685                         break;
4686                 case F_ETHERTYPE:
4687                         field_shift += W_FT_ETHERTYPE;
4688                         break;
4689                 case F_MACMATCH:
4690                         field_shift += W_FT_MACMATCH;
4691                         break;
4692                 case F_MPSHITTYPE:
4693                         field_shift += W_FT_MPSHITTYPE;
4694                         break;
4695                 case F_FRAGMENTATION:
4696                         field_shift += W_FT_FRAGMENTATION;
4697                         break;
4698                 }
4699         }
4700         return field_shift;
4701 }
4702
4703 int t4_init_rss_mode(struct adapter *adap, int mbox)
4704 {
4705         int i, ret;
4706         struct fw_rss_vi_config_cmd rvc;
4707
4708         memset(&rvc, 0, sizeof(rvc));
4709
4710         for_each_port(adap, i) {
4711                 struct port_info *p = adap2pinfo(adap, i);
4712
4713                 rvc.op_to_viid = htonl(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
4714                                        F_FW_CMD_REQUEST | F_FW_CMD_READ |
4715                                        V_FW_RSS_VI_CONFIG_CMD_VIID(p->viid));
4716                 rvc.retval_len16 = htonl(FW_LEN16(rvc));
4717                 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
4718                 if (ret)
4719                         return ret;
4720                 p->rss_mode = ntohl(rvc.u.basicvirtual.defaultq_to_udpen);
4721         }
4722         return 0;
4723 }
4724
4725 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
4726 {
4727         u8 addr[6];
4728         int ret, i, j = 0;
4729         struct fw_port_cmd c;
4730
4731         memset(&c, 0, sizeof(c));
4732
4733         for_each_port(adap, i) {
4734                 unsigned int rss_size = 0;
4735                 struct port_info *p = adap2pinfo(adap, i);
4736
4737                 while ((adap->params.portvec & (1 << j)) == 0)
4738                         j++;
4739
4740                 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
4741                                              F_FW_CMD_REQUEST | F_FW_CMD_READ |
4742                                              V_FW_PORT_CMD_PORTID(j));
4743                 c.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(
4744                                                 FW_PORT_ACTION_GET_PORT_INFO) |
4745                                                 FW_LEN16(c));
4746                 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
4747                 if (ret)
4748                         return ret;
4749
4750                 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
4751                 if (ret < 0)
4752                         return ret;
4753
4754                 p->viid = ret;
4755                 p->tx_chan = j;
4756                 p->rss_size = rss_size;
4757                 t4_os_set_hw_addr(adap, i, addr);
4758
4759                 ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
4760                 p->mdio_addr = (ret & F_FW_PORT_CMD_MDIOCAP) ?
4761                                 G_FW_PORT_CMD_MDIOADDR(ret) : -1;
4762                 p->port_type = G_FW_PORT_CMD_PTYPE(ret);
4763                 p->mod_type = FW_PORT_MOD_TYPE_NA;
4764
4765                 init_link_config(&p->link_cfg, be16_to_cpu(c.u.info.pcap),
4766                                  be16_to_cpu(c.u.info.acap));
4767                 j++;
4768         }
4769         return 0;
4770 }