drivers/net/cxgbe/base/t4_hw.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2014-2017 Chelsio Communications.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Chelsio Communications nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <netinet/in.h>
  35
  36 #include <rte_interrupts.h>
  37 #include <rte_log.h>
  38 #include <rte_debug.h>
  39 #include <rte_pci.h>
  40 #include <rte_atomic.h>
  41 #include <rte_branch_prediction.h>
  42 #include <rte_memory.h>
  43 #include <rte_memzone.h>
  44 #include <rte_tailq.h>
  45 #include <rte_eal.h>
  46 #include <rte_alarm.h>
  47 #include <rte_ether.h>
  48 #include <rte_ethdev.h>
  49 #include <rte_atomic.h>
  50 #include <rte_malloc.h>
  51 #include <rte_random.h>
  52 #include <rte_dev.h>
  53 #include <rte_byteorder.h>
  54
  55 #include "common.h"
  56 #include "t4_regs.h"
  57 #include "t4_regs_values.h"
  58 #include "t4fw_interface.h"
  59
  60 static void init_link_config(struct link_config *lc, unsigned int pcaps,
  61                              unsigned int acaps);
  62
  63 /**
  64  * t4_read_mtu_tbl - returns the values in the HW path MTU table
  65  * @adap: the adapter
  66  * @mtus: where to store the MTU values
  67  * @mtu_log: where to store the MTU base-2 log (may be %NULL)
  68  *
  69  * Reads the HW path MTU table.
  70  */
  71 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
  72 {
  73         u32 v;
  74         int i;
  75
  76         for (i = 0; i < NMTUS; ++i) {
  77                 t4_write_reg(adap, A_TP_MTU_TABLE,
  78                              V_MTUINDEX(0xff) | V_MTUVALUE(i));
  79                 v = t4_read_reg(adap, A_TP_MTU_TABLE);
  80                 mtus[i] = G_MTUVALUE(v);
  81                 if (mtu_log)
  82                         mtu_log[i] = G_MTUWIDTH(v);
  83         }
  84 }
  85
  86 /**
  87  * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
  88  * @adap: the adapter
  89  * @addr: the indirect TP register address
  90  * @mask: specifies the field within the register to modify
  91  * @val: new value for the field
  92  *
  93  * Sets a field of an indirect TP register to the given value.
  94  */
  95 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
  96                             unsigned int mask, unsigned int val)
  97 {
  98         t4_write_reg(adap, A_TP_PIO_ADDR, addr);
  99         val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask;
 100         t4_write_reg(adap, A_TP_PIO_DATA, val);
 101 }
 102
 103 /* The minimum additive increment value for the congestion control table */
 104 #define CC_MIN_INCR 2U
 105
 106 /**
 107  * t4_load_mtus - write the MTU and congestion control HW tables
 108  * @adap: the adapter
 109  * @mtus: the values for the MTU table
 110  * @alpha: the values for the congestion control alpha parameter
 111  * @beta: the values for the congestion control beta parameter
 112  *
 113  * Write the HW MTU table with the supplied MTUs and the high-speed
 114  * congestion control table with the supplied alpha, beta, and MTUs.
 115  * We write the two tables together because the additive increments
 116  * depend on the MTUs.
 117  */
 118 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
 119                   const unsigned short *alpha, const unsigned short *beta)
 120 {
 121         static const unsigned int avg_pkts[NCCTRL_WIN] = {
 122                 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
 123                 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
 124                 28672, 40960, 57344, 81920, 114688, 163840, 229376
 125         };
 126
 127         unsigned int i, w;
 128
 129         for (i = 0; i < NMTUS; ++i) {
 130                 unsigned int mtu = mtus[i];
 131                 unsigned int log2 = cxgbe_fls(mtu);
 132
 133                 if (!(mtu & ((1 << log2) >> 2)))     /* round */
 134                         log2--;
 135                 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) |
 136                              V_MTUWIDTH(log2) | V_MTUVALUE(mtu));
 137
 138                 for (w = 0; w < NCCTRL_WIN; ++w) {
 139                         unsigned int inc;
 140
 141                         inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
 142                                   CC_MIN_INCR);
 143
 144                         t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
 145                                      (w << 16) | (beta[w] << 13) | inc);
 146                 }
 147         }
 148 }
 149
 150 /**
 151  * t4_wait_op_done_val - wait until an operation is completed
 152  * @adapter: the adapter performing the operation
 153  * @reg: the register to check for completion
 154  * @mask: a single-bit field within @reg that indicates completion
 155  * @polarity: the value of the field when the operation is completed
 156  * @attempts: number of check iterations
 157  * @delay: delay in usecs between iterations
 158  * @valp: where to store the value of the register at completion time
 159  *
 160  * Wait until an operation is completed by checking a bit in a register
 161  * up to @attempts times.  If @valp is not NULL the value of the register
 162  * at the time it indicated completion is stored there.  Returns 0 if the
 163  * operation completes and -EAGAIN otherwise.
 164  */
 165 int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
 166                         int polarity, int attempts, int delay, u32 *valp)
 167 {
 168         while (1) {
 169                 u32 val = t4_read_reg(adapter, reg);
 170
 171                 if (!!(val & mask) == polarity) {
 172                         if (valp)
 173                                 *valp = val;
 174                         return 0;
 175                 }
 176                 if (--attempts == 0)
 177                         return -EAGAIN;
 178                 if (delay)
 179                         udelay(delay);
 180         }
 181 }
 182
 183 /**
 184  * t4_set_reg_field - set a register field to a value
 185  * @adapter: the adapter to program
 186  * @addr: the register address
 187  * @mask: specifies the portion of the register to modify
 188  * @val: the new value for the register field
 189  *
 190  * Sets a register field specified by the supplied mask to the
 191  * given value.
 192  */
 193 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
 194                       u32 val)
 195 {
 196         u32 v = t4_read_reg(adapter, addr) & ~mask;
 197
 198         t4_write_reg(adapter, addr, v | val);
 199         (void)t4_read_reg(adapter, addr);      /* flush */
 200 }
 201
 202 /**
 203  * t4_read_indirect - read indirectly addressed registers
 204  * @adap: the adapter
 205  * @addr_reg: register holding the indirect address
 206  * @data_reg: register holding the value of the indirect register
 207  * @vals: where the read register values are stored
 208  * @nregs: how many indirect registers to read
 209  * @start_idx: index of first indirect register to read
 210  *
 211  * Reads registers that are accessed indirectly through an address/data
 212  * register pair.
 213  */
 214 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
 215                       unsigned int data_reg, u32 *vals, unsigned int nregs,
 216                       unsigned int start_idx)
 217 {
 218         while (nregs--) {
 219                 t4_write_reg(adap, addr_reg, start_idx);
 220                 *vals++ = t4_read_reg(adap, data_reg);
 221                 start_idx++;
 222         }
 223 }
 224
 225 /**
 226  * t4_write_indirect - write indirectly addressed registers
 227  * @adap: the adapter
 228  * @addr_reg: register holding the indirect addresses
 229  * @data_reg: register holding the value for the indirect registers
 230  * @vals: values to write
 231  * @nregs: how many indirect registers to write
 232  * @start_idx: address of first indirect register to write
 233  *
 234  * Writes a sequential block of registers that are accessed indirectly
 235  * through an address/data register pair.
 236  */
 237 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
 238                        unsigned int data_reg, const u32 *vals,
 239                        unsigned int nregs, unsigned int start_idx)
 240 {
 241         while (nregs--) {
 242                 t4_write_reg(adap, addr_reg, start_idx++);
 243                 t4_write_reg(adap, data_reg, *vals++);
 244         }
 245 }
 246
 247 /**
 248  * t4_report_fw_error - report firmware error
 249  * @adap: the adapter
 250  *
 251  * The adapter firmware can indicate error conditions to the host.
 252  * If the firmware has indicated an error, print out the reason for
 253  * the firmware error.
 254  */
 255 static void t4_report_fw_error(struct adapter *adap)
 256 {
 257         static const char * const reason[] = {
 258                 "Crash",                        /* PCIE_FW_EVAL_CRASH */
 259                 "During Device Preparation",    /* PCIE_FW_EVAL_PREP */
 260                 "During Device Configuration",  /* PCIE_FW_EVAL_CONF */
 261                 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
 262                 "Unexpected Event",     /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
 263                 "Insufficient Airflow",         /* PCIE_FW_EVAL_OVERHEAT */
 264                 "Device Shutdown",      /* PCIE_FW_EVAL_DEVICESHUTDOWN */
 265                 "Reserved",                     /* reserved */
 266         };
 267         u32 pcie_fw;
 268
 269         pcie_fw = t4_read_reg(adap, A_PCIE_FW);
 270         if (pcie_fw & F_PCIE_FW_ERR)
 271                 pr_err("%s: Firmware reports adapter error: %s\n",
 272                        __func__, reason[G_PCIE_FW_EVAL(pcie_fw)]);
 273 }
 274
 275 /*
 276  * Get the reply to a mailbox command and store it in @rpl in big-endian order.
 277  */
 278 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
 279                          u32 mbox_addr)
 280 {
 281         for ( ; nflit; nflit--, mbox_addr += 8)
 282                 *rpl++ = htobe64(t4_read_reg64(adap, mbox_addr));
 283 }
 284
 285 /*
 286  * Handle a FW assertion reported in a mailbox.
 287  */
 288 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
 289 {
 290         struct fw_debug_cmd asrt;
 291
 292         get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
 293         pr_warn("FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
 294                 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
 295                 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
 296 }
 297
 298 #define X_CIM_PF_NOACCESS 0xeeeeeeee
 299
 300 /*
 301  * If the Host OS Driver needs locking arround accesses to the mailbox, this
 302  * can be turned on via the T4_OS_NEEDS_MBOX_LOCKING CPP define ...
 303  */
 304 /* makes single-statement usage a bit cleaner ... */
 305 #ifdef T4_OS_NEEDS_MBOX_LOCKING
 306 #define T4_OS_MBOX_LOCKING(x) x
 307 #else
 308 #define T4_OS_MBOX_LOCKING(x) do {} while (0)
 309 #endif
 310
 311 /**
 312  * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
 313  * @adap: the adapter
 314  * @mbox: index of the mailbox to use
 315  * @cmd: the command to write
 316  * @size: command length in bytes
 317  * @rpl: where to optionally store the reply
 318  * @sleep_ok: if true we may sleep while awaiting command completion
 319  * @timeout: time to wait for command to finish before timing out
 320  *           (negative implies @sleep_ok=false)
 321  *
 322  * Sends the given command to FW through the selected mailbox and waits
 323  * for the FW to execute the command.  If @rpl is not %NULL it is used to
 324  * store the FW's reply to the command.  The command and its optional
 325  * reply are of the same length.  Some FW commands like RESET and
 326  * INITIALIZE can take a considerable amount of time to execute.
 327  * @sleep_ok determines whether we may sleep while awaiting the response.
 328  * If sleeping is allowed we use progressive backoff otherwise we spin.
 329  * Note that passing in a negative @timeout is an alternate mechanism
 330  * for specifying @sleep_ok=false.  This is useful when a higher level
 331  * interface allows for specification of @timeout but not @sleep_ok ...
 332  *
 333  * Returns 0 on success or a negative errno on failure.  A
 334  * failure can happen either because we are not able to execute the
 335  * command or FW executes it but signals an error.  In the latter case
 336  * the return value is the error code indicated by FW (negated).
 337  */
 338 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox,
 339                             const void __attribute__((__may_alias__)) *cmd,
 340                             int size, void *rpl, bool sleep_ok, int timeout)
 341 {
 342         /*
 343          * We delay in small increments at first in an effort to maintain
 344          * responsiveness for simple, fast executing commands but then back
 345          * off to larger delays to a maximum retry delay.
 346          */
 347         static const int delay[] = {
 348                 1, 1, 3, 5, 10, 10, 20, 50, 100
 349         };
 350
 351         u32 v;
 352         u64 res;
 353         int i, ms;
 354         unsigned int delay_idx;
 355         __be64 *temp = (__be64 *)malloc(size * sizeof(char));
 356         __be64 *p = temp;
 357         u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA);
 358         u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL);
 359         u32 ctl;
 360         struct mbox_entry entry;
 361         u32 pcie_fw = 0;
 362
 363         if (!temp)
 364                 return -ENOMEM;
 365
 366         if ((size & 15) || size > MBOX_LEN) {
 367                 free(temp);
 368                 return -EINVAL;
 369         }
 370
 371         bzero(p, size);
 372         memcpy(p, (const __be64 *)cmd, size);
 373
 374         /*
 375          * If we have a negative timeout, that implies that we can't sleep.
 376          */
 377         if (timeout < 0) {
 378                 sleep_ok = false;
 379                 timeout = -timeout;
 380         }
 381
 382 #ifdef T4_OS_NEEDS_MBOX_LOCKING
 383         /*
 384          * Queue ourselves onto the mailbox access list.  When our entry is at
 385          * the front of the list, we have rights to access the mailbox.  So we
 386          * wait [for a while] till we're at the front [or bail out with an
 387          * EBUSY] ...
 388          */
 389         t4_os_atomic_add_tail(&entry, &adap->mbox_list, &adap->mbox_lock);
 390
 391         delay_idx = 0;
 392         ms = delay[0];
 393
 394         for (i = 0; ; i += ms) {
 395                 /*
 396                  * If we've waited too long, return a busy indication.  This
 397                  * really ought to be based on our initial position in the
 398                  * mailbox access list but this is a start.  We very rarely
 399                  * contend on access to the mailbox ...  Also check for a
 400                  * firmware error which we'll report as a device error.
 401                  */
 402                 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
 403                 if (i > 4 * timeout || (pcie_fw & F_PCIE_FW_ERR)) {
 404                         t4_os_atomic_list_del(&entry, &adap->mbox_list,
 405                                               &adap->mbox_lock);
 406                         t4_report_fw_error(adap);
 407                         return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -EBUSY;
 408                 }
 409
 410                 /*
 411                  * If we're at the head, break out and start the mailbox
 412                  * protocol.
 413                  */
 414                 if (t4_os_list_first_entry(&adap->mbox_list) == &entry)
 415                         break;
 416
 417                 /*
 418                  * Delay for a bit before checking again ...
 419                  */
 420                 if (sleep_ok) {
 421                         ms = delay[delay_idx];  /* last element may repeat */
 422                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 423                                 delay_idx++;
 424                         msleep(ms);
 425                 } else {
 426                         rte_delay_ms(ms);
 427                 }
 428         }
 429 #endif /* T4_OS_NEEDS_MBOX_LOCKING */
 430
 431         /*
 432          * Attempt to gain access to the mailbox.
 433          */
 434         for (i = 0; i < 4; i++) {
 435                 ctl = t4_read_reg(adap, ctl_reg);
 436                 v = G_MBOWNER(ctl);
 437                 if (v != X_MBOWNER_NONE)
 438                         break;
 439         }
 440
 441         /*
 442          * If we were unable to gain access, dequeue ourselves from the
 443          * mailbox atomic access list and report the error to our caller.
 444          */
 445         if (v != X_MBOWNER_PL) {
 446                 T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
 447                                                          &adap->mbox_list,
 448                                                          &adap->mbox_lock));
 449                 t4_report_fw_error(adap);
 450                 return (v == X_MBOWNER_FW ? -EBUSY : -ETIMEDOUT);
 451         }
 452
 453         /*
 454          * If we gain ownership of the mailbox and there's a "valid" message
 455          * in it, this is likely an asynchronous error message from the
 456          * firmware.  So we'll report that and then proceed on with attempting
 457          * to issue our own command ... which may well fail if the error
 458          * presaged the firmware crashing ...
 459          */
 460         if (ctl & F_MBMSGVALID) {
 461                 dev_err(adap, "found VALID command in mbox %u: "
 462                         "%llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
 463                         (unsigned long long)t4_read_reg64(adap, data_reg),
 464                         (unsigned long long)t4_read_reg64(adap, data_reg + 8),
 465                         (unsigned long long)t4_read_reg64(adap, data_reg + 16),
 466                         (unsigned long long)t4_read_reg64(adap, data_reg + 24),
 467                         (unsigned long long)t4_read_reg64(adap, data_reg + 32),
 468                         (unsigned long long)t4_read_reg64(adap, data_reg + 40),
 469                         (unsigned long long)t4_read_reg64(adap, data_reg + 48),
 470                         (unsigned long long)t4_read_reg64(adap, data_reg + 56));
 471         }
 472
 473         /*
 474          * Copy in the new mailbox command and send it on its way ...
 475          */
 476         for (i = 0; i < size; i += 8, p++)
 477                 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p));
 478
 479         CXGBE_DEBUG_MBOX(adap, "%s: mbox %u: %016llx %016llx %016llx %016llx "
 480                         "%016llx %016llx %016llx %016llx\n", __func__,  (mbox),
 481                         (unsigned long long)t4_read_reg64(adap, data_reg),
 482                         (unsigned long long)t4_read_reg64(adap, data_reg + 8),
 483                         (unsigned long long)t4_read_reg64(adap, data_reg + 16),
 484                         (unsigned long long)t4_read_reg64(adap, data_reg + 24),
 485                         (unsigned long long)t4_read_reg64(adap, data_reg + 32),
 486                         (unsigned long long)t4_read_reg64(adap, data_reg + 40),
 487                         (unsigned long long)t4_read_reg64(adap, data_reg + 48),
 488                         (unsigned long long)t4_read_reg64(adap, data_reg + 56));
 489
 490         t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW));
 491         t4_read_reg(adap, ctl_reg);          /* flush write */
 492
 493         delay_idx = 0;
 494         ms = delay[0];
 495
 496         /*
 497          * Loop waiting for the reply; bail out if we time out or the firmware
 498          * reports an error.
 499          */
 500         pcie_fw = t4_read_reg(adap, A_PCIE_FW);
 501         for (i = 0; i < timeout && !(pcie_fw & F_PCIE_FW_ERR); i += ms) {
 502                 if (sleep_ok) {
 503                         ms = delay[delay_idx];  /* last element may repeat */
 504                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 505                                 delay_idx++;
 506                         msleep(ms);
 507                 } else {
 508                         msleep(ms);
 509                 }
 510
 511                 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
 512                 v = t4_read_reg(adap, ctl_reg);
 513                 if (v == X_CIM_PF_NOACCESS)
 514                         continue;
 515                 if (G_MBOWNER(v) == X_MBOWNER_PL) {
 516                         if (!(v & F_MBMSGVALID)) {
 517                                 t4_write_reg(adap, ctl_reg,
 518                                              V_MBOWNER(X_MBOWNER_NONE));
 519                                 continue;
 520                         }
 521
 522                         CXGBE_DEBUG_MBOX(adap,
 523                         "%s: mbox %u: %016llx %016llx %016llx %016llx "
 524                         "%016llx %016llx %016llx %016llx\n", __func__,  (mbox),
 525                         (unsigned long long)t4_read_reg64(adap, data_reg),
 526                         (unsigned long long)t4_read_reg64(adap, data_reg + 8),
 527                         (unsigned long long)t4_read_reg64(adap, data_reg + 16),
 528                         (unsigned long long)t4_read_reg64(adap, data_reg + 24),
 529                         (unsigned long long)t4_read_reg64(adap, data_reg + 32),
 530                         (unsigned long long)t4_read_reg64(adap, data_reg + 40),
 531                         (unsigned long long)t4_read_reg64(adap, data_reg + 48),
 532                         (unsigned long long)t4_read_reg64(adap, data_reg + 56));
 533
 534                         CXGBE_DEBUG_MBOX(adap,
 535                                 "command %#x completed in %d ms (%ssleeping)\n",
 536                                 *(const u8 *)cmd,
 537                                 i + ms, sleep_ok ? "" : "non-");
 538
 539                         res = t4_read_reg64(adap, data_reg);
 540                         if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) {
 541                                 fw_asrt(adap, data_reg);
 542                                 res = V_FW_CMD_RETVAL(EIO);
 543                         } else if (rpl) {
 544                                 get_mbox_rpl(adap, rpl, size / 8, data_reg);
 545                         }
 546                         t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE));
 547                         T4_OS_MBOX_LOCKING(
 548                                 t4_os_atomic_list_del(&entry, &adap->mbox_list,
 549                                                       &adap->mbox_lock));
 550                         return -G_FW_CMD_RETVAL((int)res);
 551                 }
 552         }
 553
 554         /*
 555          * We timed out waiting for a reply to our mailbox command.  Report
 556          * the error and also check to see if the firmware reported any
 557          * errors ...
 558          */
 559         dev_err(adap, "command %#x in mailbox %d timed out\n",
 560                 *(const u8 *)cmd, mbox);
 561         T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
 562                                                  &adap->mbox_list,
 563                                                  &adap->mbox_lock));
 564         t4_report_fw_error(adap);
 565         free(temp);
 566         return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -ETIMEDOUT;
 567 }
 568
 569 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
 570                     void *rpl, bool sleep_ok)
 571 {
 572         return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
 573                                        FW_CMD_MAX_TIMEOUT);
 574 }
 575
 576 /**
 577  * t4_get_regs_len - return the size of the chips register set
 578  * @adapter: the adapter
 579  *
 580  * Returns the size of the chip's BAR0 register space.
 581  */
 582 unsigned int t4_get_regs_len(struct adapter *adapter)
 583 {
 584         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
 585
 586         switch (chip_version) {
 587         case CHELSIO_T5:
 588         case CHELSIO_T6:
 589                 return T5_REGMAP_SIZE;
 590         }
 591
 592         dev_err(adapter,
 593                 "Unsupported chip version %d\n", chip_version);
 594         return 0;
 595 }
 596
 597 /**
 598  * t4_get_regs - read chip registers into provided buffer
 599  * @adap: the adapter
 600  * @buf: register buffer
 601  * @buf_size: size (in bytes) of register buffer
 602  *
 603  * If the provided register buffer isn't large enough for the chip's
 604  * full register range, the register dump will be truncated to the
 605  * register buffer's size.
 606  */
 607 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
 608 {
 609         static const unsigned int t5_reg_ranges[] = {
 610                 0x1008, 0x10c0,
 611                 0x10cc, 0x10f8,
 612                 0x1100, 0x1100,
 613                 0x110c, 0x1148,
 614                 0x1180, 0x1184,
 615                 0x1190, 0x1194,
 616                 0x11a0, 0x11a4,
 617                 0x11b0, 0x11b4,
 618                 0x11fc, 0x123c,
 619                 0x1280, 0x173c,
 620                 0x1800, 0x18fc,
 621                 0x3000, 0x3028,
 622                 0x3060, 0x30b0,
 623                 0x30b8, 0x30d8,
 624                 0x30e0, 0x30fc,
 625                 0x3140, 0x357c,
 626                 0x35a8, 0x35cc,
 627                 0x35ec, 0x35ec,
 628                 0x3600, 0x5624,
 629                 0x56cc, 0x56ec,
 630                 0x56f4, 0x5720,
 631                 0x5728, 0x575c,
 632                 0x580c, 0x5814,
 633                 0x5890, 0x589c,
 634                 0x58a4, 0x58ac,
 635                 0x58b8, 0x58bc,
 636                 0x5940, 0x59c8,
 637                 0x59d0, 0x59dc,
 638                 0x59fc, 0x5a18,
 639                 0x5a60, 0x5a70,
 640                 0x5a80, 0x5a9c,
 641                 0x5b94, 0x5bfc,
 642                 0x6000, 0x6020,
 643                 0x6028, 0x6040,
 644                 0x6058, 0x609c,
 645                 0x60a8, 0x614c,
 646                 0x7700, 0x7798,
 647                 0x77c0, 0x78fc,
 648                 0x7b00, 0x7b58,
 649                 0x7b60, 0x7b84,
 650                 0x7b8c, 0x7c54,
 651                 0x7d00, 0x7d38,
 652                 0x7d40, 0x7d80,
 653                 0x7d8c, 0x7ddc,
 654                 0x7de4, 0x7e04,
 655                 0x7e10, 0x7e1c,
 656                 0x7e24, 0x7e38,
 657                 0x7e40, 0x7e44,
 658                 0x7e4c, 0x7e78,
 659                 0x7e80, 0x7edc,
 660                 0x7ee8, 0x7efc,
 661                 0x8dc0, 0x8de0,
 662                 0x8df8, 0x8e04,
 663                 0x8e10, 0x8e84,
 664                 0x8ea0, 0x8f84,
 665                 0x8fc0, 0x9058,
 666                 0x9060, 0x9060,
 667                 0x9068, 0x90f8,
 668                 0x9400, 0x9408,
 669                 0x9410, 0x9470,
 670                 0x9600, 0x9600,
 671                 0x9608, 0x9638,
 672                 0x9640, 0x96f4,
 673                 0x9800, 0x9808,
 674                 0x9820, 0x983c,
 675                 0x9850, 0x9864,
 676                 0x9c00, 0x9c6c,
 677                 0x9c80, 0x9cec,
 678                 0x9d00, 0x9d6c,
 679                 0x9d80, 0x9dec,
 680                 0x9e00, 0x9e6c,
 681                 0x9e80, 0x9eec,
 682                 0x9f00, 0x9f6c,
 683                 0x9f80, 0xa020,
 684                 0xd004, 0xd004,
 685                 0xd010, 0xd03c,
 686                 0xdfc0, 0xdfe0,
 687                 0xe000, 0x1106c,
 688                 0x11074, 0x11088,
 689                 0x1109c, 0x1117c,
 690                 0x11190, 0x11204,
 691                 0x19040, 0x1906c,
 692                 0x19078, 0x19080,
 693                 0x1908c, 0x190e8,
 694                 0x190f0, 0x190f8,
 695                 0x19100, 0x19110,
 696                 0x19120, 0x19124,
 697                 0x19150, 0x19194,
 698                 0x1919c, 0x191b0,
 699                 0x191d0, 0x191e8,
 700                 0x19238, 0x19290,
 701                 0x193f8, 0x19428,
 702                 0x19430, 0x19444,
 703                 0x1944c, 0x1946c,
 704                 0x19474, 0x19474,
 705                 0x19490, 0x194cc,
 706                 0x194f0, 0x194f8,
 707                 0x19c00, 0x19c08,
 708                 0x19c10, 0x19c60,
 709                 0x19c94, 0x19ce4,
 710                 0x19cf0, 0x19d40,
 711                 0x19d50, 0x19d94,
 712                 0x19da0, 0x19de8,
 713                 0x19df0, 0x19e10,
 714                 0x19e50, 0x19e90,
 715                 0x19ea0, 0x19f24,
 716                 0x19f34, 0x19f34,
 717                 0x19f40, 0x19f50,
 718                 0x19f90, 0x19fb4,
 719                 0x19fc4, 0x19fe4,
 720                 0x1a000, 0x1a004,
 721                 0x1a010, 0x1a06c,
 722                 0x1a0b0, 0x1a0e4,
 723                 0x1a0ec, 0x1a0f8,
 724                 0x1a100, 0x1a108,
 725                 0x1a114, 0x1a120,
 726                 0x1a128, 0x1a130,
 727                 0x1a138, 0x1a138,
 728                 0x1a190, 0x1a1c4,
 729                 0x1a1fc, 0x1a1fc,
 730                 0x1e008, 0x1e00c,
 731                 0x1e040, 0x1e044,
 732                 0x1e04c, 0x1e04c,
 733                 0x1e284, 0x1e290,
 734                 0x1e2c0, 0x1e2c0,
 735                 0x1e2e0, 0x1e2e0,
 736                 0x1e300, 0x1e384,
 737                 0x1e3c0, 0x1e3c8,
 738                 0x1e408, 0x1e40c,
 739                 0x1e440, 0x1e444,
 740                 0x1e44c, 0x1e44c,
 741                 0x1e684, 0x1e690,
 742                 0x1e6c0, 0x1e6c0,
 743                 0x1e6e0, 0x1e6e0,
 744                 0x1e700, 0x1e784,
 745                 0x1e7c0, 0x1e7c8,
 746                 0x1e808, 0x1e80c,
 747                 0x1e840, 0x1e844,
 748                 0x1e84c, 0x1e84c,
 749                 0x1ea84, 0x1ea90,
 750                 0x1eac0, 0x1eac0,
 751                 0x1eae0, 0x1eae0,
 752                 0x1eb00, 0x1eb84,
 753                 0x1ebc0, 0x1ebc8,
 754                 0x1ec08, 0x1ec0c,
 755                 0x1ec40, 0x1ec44,
 756                 0x1ec4c, 0x1ec4c,
 757                 0x1ee84, 0x1ee90,
 758                 0x1eec0, 0x1eec0,
 759                 0x1eee0, 0x1eee0,
 760                 0x1ef00, 0x1ef84,
 761                 0x1efc0, 0x1efc8,
 762                 0x1f008, 0x1f00c,
 763                 0x1f040, 0x1f044,
 764                 0x1f04c, 0x1f04c,
 765                 0x1f284, 0x1f290,
 766                 0x1f2c0, 0x1f2c0,
 767                 0x1f2e0, 0x1f2e0,
 768                 0x1f300, 0x1f384,
 769                 0x1f3c0, 0x1f3c8,
 770                 0x1f408, 0x1f40c,
 771                 0x1f440, 0x1f444,
 772                 0x1f44c, 0x1f44c,
 773                 0x1f684, 0x1f690,
 774                 0x1f6c0, 0x1f6c0,
 775                 0x1f6e0, 0x1f6e0,
 776                 0x1f700, 0x1f784,
 777                 0x1f7c0, 0x1f7c8,
 778                 0x1f808, 0x1f80c,
 779                 0x1f840, 0x1f844,
 780                 0x1f84c, 0x1f84c,
 781                 0x1fa84, 0x1fa90,
 782                 0x1fac0, 0x1fac0,
 783                 0x1fae0, 0x1fae0,
 784                 0x1fb00, 0x1fb84,
 785                 0x1fbc0, 0x1fbc8,
 786                 0x1fc08, 0x1fc0c,
 787                 0x1fc40, 0x1fc44,
 788                 0x1fc4c, 0x1fc4c,
 789                 0x1fe84, 0x1fe90,
 790                 0x1fec0, 0x1fec0,
 791                 0x1fee0, 0x1fee0,
 792                 0x1ff00, 0x1ff84,
 793                 0x1ffc0, 0x1ffc8,
 794                 0x30000, 0x30030,
 795                 0x30038, 0x30038,
 796                 0x30040, 0x30040,
 797                 0x30100, 0x30144,
 798                 0x30190, 0x301a0,
 799                 0x301a8, 0x301b8,
 800                 0x301c4, 0x301c8,
 801                 0x301d0, 0x301d0,
 802                 0x30200, 0x30318,
 803                 0x30400, 0x304b4,
 804                 0x304c0, 0x3052c,
 805                 0x30540, 0x3061c,
 806                 0x30800, 0x30828,
 807                 0x30834, 0x30834,
 808                 0x308c0, 0x30908,
 809                 0x30910, 0x309ac,
 810                 0x30a00, 0x30a14,
 811                 0x30a1c, 0x30a2c,
 812                 0x30a44, 0x30a50,
 813                 0x30a74, 0x30a74,
 814                 0x30a7c, 0x30afc,
 815                 0x30b08, 0x30c24,
 816                 0x30d00, 0x30d00,
 817                 0x30d08, 0x30d14,
 818                 0x30d1c, 0x30d20,
 819                 0x30d3c, 0x30d3c,
 820                 0x30d48, 0x30d50,
 821                 0x31200, 0x3120c,
 822                 0x31220, 0x31220,
 823                 0x31240, 0x31240,
 824                 0x31600, 0x3160c,
 825                 0x31a00, 0x31a1c,
 826                 0x31e00, 0x31e20,
 827                 0x31e38, 0x31e3c,
 828                 0x31e80, 0x31e80,
 829                 0x31e88, 0x31ea8,
 830                 0x31eb0, 0x31eb4,
 831                 0x31ec8, 0x31ed4,
 832                 0x31fb8, 0x32004,
 833                 0x32200, 0x32200,
 834                 0x32208, 0x32240,
 835                 0x32248, 0x32280,
 836                 0x32288, 0x322c0,
 837                 0x322c8, 0x322fc,
 838                 0x32600, 0x32630,
 839                 0x32a00, 0x32abc,
 840                 0x32b00, 0x32b10,
 841                 0x32b20, 0x32b30,
 842                 0x32b40, 0x32b50,
 843                 0x32b60, 0x32b70,
 844                 0x33000, 0x33028,
 845                 0x33030, 0x33048,
 846                 0x33060, 0x33068,
 847                 0x33070, 0x3309c,
 848                 0x330f0, 0x33128,
 849                 0x33130, 0x33148,
 850                 0x33160, 0x33168,
 851                 0x33170, 0x3319c,
 852                 0x331f0, 0x33238,
 853                 0x33240, 0x33240,
 854                 0x33248, 0x33250,
 855                 0x3325c, 0x33264,
 856                 0x33270, 0x332b8,
 857                 0x332c0, 0x332e4,
 858                 0x332f8, 0x33338,
 859                 0x33340, 0x33340,
 860                 0x33348, 0x33350,
 861                 0x3335c, 0x33364,
 862                 0x33370, 0x333b8,
 863                 0x333c0, 0x333e4,
 864                 0x333f8, 0x33428,
 865                 0x33430, 0x33448,
 866                 0x33460, 0x33468,
 867                 0x33470, 0x3349c,
 868                 0x334f0, 0x33528,
 869                 0x33530, 0x33548,
 870                 0x33560, 0x33568,
 871                 0x33570, 0x3359c,
 872                 0x335f0, 0x33638,
 873                 0x33640, 0x33640,
 874                 0x33648, 0x33650,
 875                 0x3365c, 0x33664,
 876                 0x33670, 0x336b8,
 877                 0x336c0, 0x336e4,
 878                 0x336f8, 0x33738,
 879                 0x33740, 0x33740,
 880                 0x33748, 0x33750,
 881                 0x3375c, 0x33764,
 882                 0x33770, 0x337b8,
 883                 0x337c0, 0x337e4,
 884                 0x337f8, 0x337fc,
 885                 0x33814, 0x33814,
 886                 0x3382c, 0x3382c,
 887                 0x33880, 0x3388c,
 888                 0x338e8, 0x338ec,
 889                 0x33900, 0x33928,
 890                 0x33930, 0x33948,
 891                 0x33960, 0x33968,
 892                 0x33970, 0x3399c,
 893                 0x339f0, 0x33a38,
 894                 0x33a40, 0x33a40,
 895                 0x33a48, 0x33a50,
 896                 0x33a5c, 0x33a64,
 897                 0x33a70, 0x33ab8,
 898                 0x33ac0, 0x33ae4,
 899                 0x33af8, 0x33b10,
 900                 0x33b28, 0x33b28,
 901                 0x33b3c, 0x33b50,
 902                 0x33bf0, 0x33c10,
 903                 0x33c28, 0x33c28,
 904                 0x33c3c, 0x33c50,
 905                 0x33cf0, 0x33cfc,
 906                 0x34000, 0x34030,
 907                 0x34038, 0x34038,
 908                 0x34040, 0x34040,
 909                 0x34100, 0x34144,
 910                 0x34190, 0x341a0,
 911                 0x341a8, 0x341b8,
 912                 0x341c4, 0x341c8,
 913                 0x341d0, 0x341d0,
 914                 0x34200, 0x34318,
 915                 0x34400, 0x344b4,
 916                 0x344c0, 0x3452c,
 917                 0x34540, 0x3461c,
 918                 0x34800, 0x34828,
 919                 0x34834, 0x34834,
 920                 0x348c0, 0x34908,
 921                 0x34910, 0x349ac,
 922                 0x34a00, 0x34a14,
 923                 0x34a1c, 0x34a2c,
 924                 0x34a44, 0x34a50,
 925                 0x34a74, 0x34a74,
 926                 0x34a7c, 0x34afc,
 927                 0x34b08, 0x34c24,
 928                 0x34d00, 0x34d00,
 929                 0x34d08, 0x34d14,
 930                 0x34d1c, 0x34d20,
 931                 0x34d3c, 0x34d3c,
 932                 0x34d48, 0x34d50,
 933                 0x35200, 0x3520c,
 934                 0x35220, 0x35220,
 935                 0x35240, 0x35240,
 936                 0x35600, 0x3560c,
 937                 0x35a00, 0x35a1c,
 938                 0x35e00, 0x35e20,
 939                 0x35e38, 0x35e3c,
 940                 0x35e80, 0x35e80,
 941                 0x35e88, 0x35ea8,
 942                 0x35eb0, 0x35eb4,
 943                 0x35ec8, 0x35ed4,
 944                 0x35fb8, 0x36004,
 945                 0x36200, 0x36200,
 946                 0x36208, 0x36240,
 947                 0x36248, 0x36280,
 948                 0x36288, 0x362c0,
 949                 0x362c8, 0x362fc,
 950                 0x36600, 0x36630,
 951                 0x36a00, 0x36abc,
 952                 0x36b00, 0x36b10,
 953                 0x36b20, 0x36b30,
 954                 0x36b40, 0x36b50,
 955                 0x36b60, 0x36b70,
 956                 0x37000, 0x37028,
 957                 0x37030, 0x37048,
 958                 0x37060, 0x37068,
 959                 0x37070, 0x3709c,
 960                 0x370f0, 0x37128,
 961                 0x37130, 0x37148,
 962                 0x37160, 0x37168,
 963                 0x37170, 0x3719c,
 964                 0x371f0, 0x37238,
 965                 0x37240, 0x37240,
 966                 0x37248, 0x37250,
 967                 0x3725c, 0x37264,
 968                 0x37270, 0x372b8,
 969                 0x372c0, 0x372e4,
 970                 0x372f8, 0x37338,
 971                 0x37340, 0x37340,
 972                 0x37348, 0x37350,
 973                 0x3735c, 0x37364,
 974                 0x37370, 0x373b8,
 975                 0x373c0, 0x373e4,
 976                 0x373f8, 0x37428,
 977                 0x37430, 0x37448,
 978                 0x37460, 0x37468,
 979                 0x37470, 0x3749c,
 980                 0x374f0, 0x37528,
 981                 0x37530, 0x37548,
 982                 0x37560, 0x37568,
 983                 0x37570, 0x3759c,
 984                 0x375f0, 0x37638,
 985                 0x37640, 0x37640,
 986                 0x37648, 0x37650,
 987                 0x3765c, 0x37664,
 988                 0x37670, 0x376b8,
 989                 0x376c0, 0x376e4,
 990                 0x376f8, 0x37738,
 991                 0x37740, 0x37740,
 992                 0x37748, 0x37750,
 993                 0x3775c, 0x37764,
 994                 0x37770, 0x377b8,
 995                 0x377c0, 0x377e4,
 996                 0x377f8, 0x377fc,
 997                 0x37814, 0x37814,
 998                 0x3782c, 0x3782c,
 999                 0x37880, 0x3788c,
1000                 0x378e8, 0x378ec,
1001                 0x37900, 0x37928,
1002                 0x37930, 0x37948,
1003                 0x37960, 0x37968,
1004                 0x37970, 0x3799c,
1005                 0x379f0, 0x37a38,
1006                 0x37a40, 0x37a40,
1007                 0x37a48, 0x37a50,
1008                 0x37a5c, 0x37a64,
1009                 0x37a70, 0x37ab8,
1010                 0x37ac0, 0x37ae4,
1011                 0x37af8, 0x37b10,
1012                 0x37b28, 0x37b28,
1013                 0x37b3c, 0x37b50,
1014                 0x37bf0, 0x37c10,
1015                 0x37c28, 0x37c28,
1016                 0x37c3c, 0x37c50,
1017                 0x37cf0, 0x37cfc,
1018                 0x38000, 0x38030,
1019                 0x38038, 0x38038,
1020                 0x38040, 0x38040,
1021                 0x38100, 0x38144,
1022                 0x38190, 0x381a0,
1023                 0x381a8, 0x381b8,
1024                 0x381c4, 0x381c8,
1025                 0x381d0, 0x381d0,
1026                 0x38200, 0x38318,
1027                 0x38400, 0x384b4,
1028                 0x384c0, 0x3852c,
1029                 0x38540, 0x3861c,
1030                 0x38800, 0x38828,
1031                 0x38834, 0x38834,
1032                 0x388c0, 0x38908,
1033                 0x38910, 0x389ac,
1034                 0x38a00, 0x38a14,
1035                 0x38a1c, 0x38a2c,
1036                 0x38a44, 0x38a50,
1037                 0x38a74, 0x38a74,
1038                 0x38a7c, 0x38afc,
1039                 0x38b08, 0x38c24,
1040                 0x38d00, 0x38d00,
1041                 0x38d08, 0x38d14,
1042                 0x38d1c, 0x38d20,
1043                 0x38d3c, 0x38d3c,
1044                 0x38d48, 0x38d50,
1045                 0x39200, 0x3920c,
1046                 0x39220, 0x39220,
1047                 0x39240, 0x39240,
1048                 0x39600, 0x3960c,
1049                 0x39a00, 0x39a1c,
1050                 0x39e00, 0x39e20,
1051                 0x39e38, 0x39e3c,
1052                 0x39e80, 0x39e80,
1053                 0x39e88, 0x39ea8,
1054                 0x39eb0, 0x39eb4,
1055                 0x39ec8, 0x39ed4,
1056                 0x39fb8, 0x3a004,
1057                 0x3a200, 0x3a200,
1058                 0x3a208, 0x3a240,
1059                 0x3a248, 0x3a280,
1060                 0x3a288, 0x3a2c0,
1061                 0x3a2c8, 0x3a2fc,
1062                 0x3a600, 0x3a630,
1063                 0x3aa00, 0x3aabc,
1064                 0x3ab00, 0x3ab10,
1065                 0x3ab20, 0x3ab30,
1066                 0x3ab40, 0x3ab50,
1067                 0x3ab60, 0x3ab70,
1068                 0x3b000, 0x3b028,
1069                 0x3b030, 0x3b048,
1070                 0x3b060, 0x3b068,
1071                 0x3b070, 0x3b09c,
1072                 0x3b0f0, 0x3b128,
1073                 0x3b130, 0x3b148,
1074                 0x3b160, 0x3b168,
1075                 0x3b170, 0x3b19c,
1076                 0x3b1f0, 0x3b238,
1077                 0x3b240, 0x3b240,
1078                 0x3b248, 0x3b250,
1079                 0x3b25c, 0x3b264,
1080                 0x3b270, 0x3b2b8,
1081                 0x3b2c0, 0x3b2e4,
1082                 0x3b2f8, 0x3b338,
1083                 0x3b340, 0x3b340,
1084                 0x3b348, 0x3b350,
1085                 0x3b35c, 0x3b364,
1086                 0x3b370, 0x3b3b8,
1087                 0x3b3c0, 0x3b3e4,
1088                 0x3b3f8, 0x3b428,
1089                 0x3b430, 0x3b448,
1090                 0x3b460, 0x3b468,
1091                 0x3b470, 0x3b49c,
1092                 0x3b4f0, 0x3b528,
1093                 0x3b530, 0x3b548,
1094                 0x3b560, 0x3b568,
1095                 0x3b570, 0x3b59c,
1096                 0x3b5f0, 0x3b638,
1097                 0x3b640, 0x3b640,
1098                 0x3b648, 0x3b650,
1099                 0x3b65c, 0x3b664,
1100                 0x3b670, 0x3b6b8,
1101                 0x3b6c0, 0x3b6e4,
1102                 0x3b6f8, 0x3b738,
1103                 0x3b740, 0x3b740,
1104                 0x3b748, 0x3b750,
1105                 0x3b75c, 0x3b764,
1106                 0x3b770, 0x3b7b8,
1107                 0x3b7c0, 0x3b7e4,
1108                 0x3b7f8, 0x3b7fc,
1109                 0x3b814, 0x3b814,
1110                 0x3b82c, 0x3b82c,
1111                 0x3b880, 0x3b88c,
1112                 0x3b8e8, 0x3b8ec,
1113                 0x3b900, 0x3b928,
1114                 0x3b930, 0x3b948,
1115                 0x3b960, 0x3b968,
1116                 0x3b970, 0x3b99c,
1117                 0x3b9f0, 0x3ba38,
1118                 0x3ba40, 0x3ba40,
1119                 0x3ba48, 0x3ba50,
1120                 0x3ba5c, 0x3ba64,
1121                 0x3ba70, 0x3bab8,
1122                 0x3bac0, 0x3bae4,
1123                 0x3baf8, 0x3bb10,
1124                 0x3bb28, 0x3bb28,
1125                 0x3bb3c, 0x3bb50,
1126                 0x3bbf0, 0x3bc10,
1127                 0x3bc28, 0x3bc28,
1128                 0x3bc3c, 0x3bc50,
1129                 0x3bcf0, 0x3bcfc,
1130                 0x3c000, 0x3c030,
1131                 0x3c038, 0x3c038,
1132                 0x3c040, 0x3c040,
1133                 0x3c100, 0x3c144,
1134                 0x3c190, 0x3c1a0,
1135                 0x3c1a8, 0x3c1b8,
1136                 0x3c1c4, 0x3c1c8,
1137                 0x3c1d0, 0x3c1d0,
1138                 0x3c200, 0x3c318,
1139                 0x3c400, 0x3c4b4,
1140                 0x3c4c0, 0x3c52c,
1141                 0x3c540, 0x3c61c,
1142                 0x3c800, 0x3c828,
1143                 0x3c834, 0x3c834,
1144                 0x3c8c0, 0x3c908,
1145                 0x3c910, 0x3c9ac,
1146                 0x3ca00, 0x3ca14,
1147                 0x3ca1c, 0x3ca2c,
1148                 0x3ca44, 0x3ca50,
1149                 0x3ca74, 0x3ca74,
1150                 0x3ca7c, 0x3cafc,
1151                 0x3cb08, 0x3cc24,
1152                 0x3cd00, 0x3cd00,
1153                 0x3cd08, 0x3cd14,
1154                 0x3cd1c, 0x3cd20,
1155                 0x3cd3c, 0x3cd3c,
1156                 0x3cd48, 0x3cd50,
1157                 0x3d200, 0x3d20c,
1158                 0x3d220, 0x3d220,
1159                 0x3d240, 0x3d240,
1160                 0x3d600, 0x3d60c,
1161                 0x3da00, 0x3da1c,
1162                 0x3de00, 0x3de20,
1163                 0x3de38, 0x3de3c,
1164                 0x3de80, 0x3de80,
1165                 0x3de88, 0x3dea8,
1166                 0x3deb0, 0x3deb4,
1167                 0x3dec8, 0x3ded4,
1168                 0x3dfb8, 0x3e004,
1169                 0x3e200, 0x3e200,
1170                 0x3e208, 0x3e240,
1171                 0x3e248, 0x3e280,
1172                 0x3e288, 0x3e2c0,
1173                 0x3e2c8, 0x3e2fc,
1174                 0x3e600, 0x3e630,
1175                 0x3ea00, 0x3eabc,
1176                 0x3eb00, 0x3eb10,
1177                 0x3eb20, 0x3eb30,
1178                 0x3eb40, 0x3eb50,
1179                 0x3eb60, 0x3eb70,
1180                 0x3f000, 0x3f028,
1181                 0x3f030, 0x3f048,
1182                 0x3f060, 0x3f068,
1183                 0x3f070, 0x3f09c,
1184                 0x3f0f0, 0x3f128,
1185                 0x3f130, 0x3f148,
1186                 0x3f160, 0x3f168,
1187                 0x3f170, 0x3f19c,
1188                 0x3f1f0, 0x3f238,
1189                 0x3f240, 0x3f240,
1190                 0x3f248, 0x3f250,
1191                 0x3f25c, 0x3f264,
1192                 0x3f270, 0x3f2b8,
1193                 0x3f2c0, 0x3f2e4,
1194                 0x3f2f8, 0x3f338,
1195                 0x3f340, 0x3f340,
1196                 0x3f348, 0x3f350,
1197                 0x3f35c, 0x3f364,
1198                 0x3f370, 0x3f3b8,
1199                 0x3f3c0, 0x3f3e4,
1200                 0x3f3f8, 0x3f428,
1201                 0x3f430, 0x3f448,
1202                 0x3f460, 0x3f468,
1203                 0x3f470, 0x3f49c,
1204                 0x3f4f0, 0x3f528,
1205                 0x3f530, 0x3f548,
1206                 0x3f560, 0x3f568,
1207                 0x3f570, 0x3f59c,
1208                 0x3f5f0, 0x3f638,
1209                 0x3f640, 0x3f640,
1210                 0x3f648, 0x3f650,
1211                 0x3f65c, 0x3f664,
1212                 0x3f670, 0x3f6b8,
1213                 0x3f6c0, 0x3f6e4,
1214                 0x3f6f8, 0x3f738,
1215                 0x3f740, 0x3f740,
1216                 0x3f748, 0x3f750,
1217                 0x3f75c, 0x3f764,
1218                 0x3f770, 0x3f7b8,
1219                 0x3f7c0, 0x3f7e4,
1220                 0x3f7f8, 0x3f7fc,
1221                 0x3f814, 0x3f814,
1222                 0x3f82c, 0x3f82c,
1223                 0x3f880, 0x3f88c,
1224                 0x3f8e8, 0x3f8ec,
1225                 0x3f900, 0x3f928,
1226                 0x3f930, 0x3f948,
1227                 0x3f960, 0x3f968,
1228                 0x3f970, 0x3f99c,
1229                 0x3f9f0, 0x3fa38,
1230                 0x3fa40, 0x3fa40,
1231                 0x3fa48, 0x3fa50,
1232                 0x3fa5c, 0x3fa64,
1233                 0x3fa70, 0x3fab8,
1234                 0x3fac0, 0x3fae4,
1235                 0x3faf8, 0x3fb10,
1236                 0x3fb28, 0x3fb28,
1237                 0x3fb3c, 0x3fb50,
1238                 0x3fbf0, 0x3fc10,
1239                 0x3fc28, 0x3fc28,
1240                 0x3fc3c, 0x3fc50,
1241                 0x3fcf0, 0x3fcfc,
1242                 0x40000, 0x4000c,
1243                 0x40040, 0x40050,
1244                 0x40060, 0x40068,
1245                 0x4007c, 0x4008c,
1246                 0x40094, 0x400b0,
1247                 0x400c0, 0x40144,
1248                 0x40180, 0x4018c,
1249                 0x40200, 0x40254,
1250                 0x40260, 0x40264,
1251                 0x40270, 0x40288,
1252                 0x40290, 0x40298,
1253                 0x402ac, 0x402c8,
1254                 0x402d0, 0x402e0,
1255                 0x402f0, 0x402f0,
1256                 0x40300, 0x4033c,
1257                 0x403f8, 0x403fc,
1258                 0x41304, 0x413c4,
1259                 0x41400, 0x4140c,
1260                 0x41414, 0x4141c,
1261                 0x41480, 0x414d0,
1262                 0x44000, 0x44054,
1263                 0x4405c, 0x44078,
1264                 0x440c0, 0x44174,
1265                 0x44180, 0x441ac,
1266                 0x441b4, 0x441b8,
1267                 0x441c0, 0x44254,
1268                 0x4425c, 0x44278,
1269                 0x442c0, 0x44374,
1270                 0x44380, 0x443ac,
1271                 0x443b4, 0x443b8,
1272                 0x443c0, 0x44454,
1273                 0x4445c, 0x44478,
1274                 0x444c0, 0x44574,
1275                 0x44580, 0x445ac,
1276                 0x445b4, 0x445b8,
1277                 0x445c0, 0x44654,
1278                 0x4465c, 0x44678,
1279                 0x446c0, 0x44774,
1280                 0x44780, 0x447ac,
1281                 0x447b4, 0x447b8,
1282                 0x447c0, 0x44854,
1283                 0x4485c, 0x44878,
1284                 0x448c0, 0x44974,
1285                 0x44980, 0x449ac,
1286                 0x449b4, 0x449b8,
1287                 0x449c0, 0x449fc,
1288                 0x45000, 0x45004,
1289                 0x45010, 0x45030,
1290                 0x45040, 0x45060,
1291                 0x45068, 0x45068,
1292                 0x45080, 0x45084,
1293                 0x450a0, 0x450b0,
1294                 0x45200, 0x45204,
1295                 0x45210, 0x45230,
1296                 0x45240, 0x45260,
1297                 0x45268, 0x45268,
1298                 0x45280, 0x45284,
1299                 0x452a0, 0x452b0,
1300                 0x460c0, 0x460e4,
1301                 0x47000, 0x4703c,
1302                 0x47044, 0x4708c,
1303                 0x47200, 0x47250,
1304                 0x47400, 0x47408,
1305                 0x47414, 0x47420,
1306                 0x47600, 0x47618,
1307                 0x47800, 0x47814,
1308                 0x48000, 0x4800c,
1309                 0x48040, 0x48050,
1310                 0x48060, 0x48068,
1311                 0x4807c, 0x4808c,
1312                 0x48094, 0x480b0,
1313                 0x480c0, 0x48144,
1314                 0x48180, 0x4818c,
1315                 0x48200, 0x48254,
1316                 0x48260, 0x48264,
1317                 0x48270, 0x48288,
1318                 0x48290, 0x48298,
1319                 0x482ac, 0x482c8,
1320                 0x482d0, 0x482e0,
1321                 0x482f0, 0x482f0,
1322                 0x48300, 0x4833c,
1323                 0x483f8, 0x483fc,
1324                 0x49304, 0x493c4,
1325                 0x49400, 0x4940c,
1326                 0x49414, 0x4941c,
1327                 0x49480, 0x494d0,
1328                 0x4c000, 0x4c054,
1329                 0x4c05c, 0x4c078,
1330                 0x4c0c0, 0x4c174,
1331                 0x4c180, 0x4c1ac,
1332                 0x4c1b4, 0x4c1b8,
1333                 0x4c1c0, 0x4c254,
1334                 0x4c25c, 0x4c278,
1335                 0x4c2c0, 0x4c374,
1336                 0x4c380, 0x4c3ac,
1337                 0x4c3b4, 0x4c3b8,
1338                 0x4c3c0, 0x4c454,
1339                 0x4c45c, 0x4c478,
1340                 0x4c4c0, 0x4c574,
1341                 0x4c580, 0x4c5ac,
1342                 0x4c5b4, 0x4c5b8,
1343                 0x4c5c0, 0x4c654,
1344                 0x4c65c, 0x4c678,
1345                 0x4c6c0, 0x4c774,
1346                 0x4c780, 0x4c7ac,
1347                 0x4c7b4, 0x4c7b8,
1348                 0x4c7c0, 0x4c854,
1349                 0x4c85c, 0x4c878,
1350                 0x4c8c0, 0x4c974,
1351                 0x4c980, 0x4c9ac,
1352                 0x4c9b4, 0x4c9b8,
1353                 0x4c9c0, 0x4c9fc,
1354                 0x4d000, 0x4d004,
1355                 0x4d010, 0x4d030,
1356                 0x4d040, 0x4d060,
1357                 0x4d068, 0x4d068,
1358                 0x4d080, 0x4d084,
1359                 0x4d0a0, 0x4d0b0,
1360                 0x4d200, 0x4d204,
1361                 0x4d210, 0x4d230,
1362                 0x4d240, 0x4d260,
1363                 0x4d268, 0x4d268,
1364                 0x4d280, 0x4d284,
1365                 0x4d2a0, 0x4d2b0,
1366                 0x4e0c0, 0x4e0e4,
1367                 0x4f000, 0x4f03c,
1368                 0x4f044, 0x4f08c,
1369                 0x4f200, 0x4f250,
1370                 0x4f400, 0x4f408,
1371                 0x4f414, 0x4f420,
1372                 0x4f600, 0x4f618,
1373                 0x4f800, 0x4f814,
1374                 0x50000, 0x50084,
1375                 0x50090, 0x500cc,
1376                 0x50400, 0x50400,
1377                 0x50800, 0x50884,
1378                 0x50890, 0x508cc,
1379                 0x50c00, 0x50c00,
1380                 0x51000, 0x5101c,
1381                 0x51300, 0x51308,
1382         };
1383
1384         static const unsigned int t6_reg_ranges[] = {
1385                 0x1008, 0x101c,
1386                 0x1024, 0x10a8,
1387                 0x10b4, 0x10f8,
1388                 0x1100, 0x1114,
1389                 0x111c, 0x112c,
1390                 0x1138, 0x113c,
1391                 0x1144, 0x114c,
1392                 0x1180, 0x1184,
1393                 0x1190, 0x1194,
1394                 0x11a0, 0x11a4,
1395                 0x11b0, 0x11b4,
1396                 0x11fc, 0x1274,
1397                 0x1280, 0x133c,
1398                 0x1800, 0x18fc,
1399                 0x3000, 0x302c,
1400                 0x3060, 0x30b0,
1401                 0x30b8, 0x30d8,
1402                 0x30e0, 0x30fc,
1403                 0x3140, 0x357c,
1404                 0x35a8, 0x35cc,
1405                 0x35ec, 0x35ec,
1406                 0x3600, 0x5624,
1407                 0x56cc, 0x56ec,
1408                 0x56f4, 0x5720,
1409                 0x5728, 0x575c,
1410                 0x580c, 0x5814,
1411                 0x5890, 0x589c,
1412                 0x58a4, 0x58ac,
1413                 0x58b8, 0x58bc,
1414                 0x5940, 0x595c,
1415                 0x5980, 0x598c,
1416                 0x59b0, 0x59c8,
1417                 0x59d0, 0x59dc,
1418                 0x59fc, 0x5a18,
1419                 0x5a60, 0x5a6c,
1420                 0x5a80, 0x5a8c,
1421                 0x5a94, 0x5a9c,
1422                 0x5b94, 0x5bfc,
1423                 0x5c10, 0x5e48,
1424                 0x5e50, 0x5e94,
1425                 0x5ea0, 0x5eb0,
1426                 0x5ec0, 0x5ec0,
1427                 0x5ec8, 0x5ed0,
1428                 0x5ee0, 0x5ee0,
1429                 0x5ef0, 0x5ef0,
1430                 0x5f00, 0x5f00,
1431                 0x6000, 0x6020,
1432                 0x6028, 0x6040,
1433                 0x6058, 0x609c,
1434                 0x60a8, 0x619c,
1435                 0x7700, 0x7798,
1436                 0x77c0, 0x7880,
1437                 0x78cc, 0x78fc,
1438                 0x7b00, 0x7b58,
1439                 0x7b60, 0x7b84,
1440                 0x7b8c, 0x7c54,
1441                 0x7d00, 0x7d38,
1442                 0x7d40, 0x7d84,
1443                 0x7d8c, 0x7ddc,
1444                 0x7de4, 0x7e04,
1445                 0x7e10, 0x7e1c,
1446                 0x7e24, 0x7e38,
1447                 0x7e40, 0x7e44,
1448                 0x7e4c, 0x7e78,
1449                 0x7e80, 0x7edc,
1450                 0x7ee8, 0x7efc,
1451                 0x8dc0, 0x8de4,
1452                 0x8df8, 0x8e04,
1453                 0x8e10, 0x8e84,
1454                 0x8ea0, 0x8f88,
1455                 0x8fb8, 0x9058,
1456                 0x9060, 0x9060,
1457                 0x9068, 0x90f8,
1458                 0x9100, 0x9124,
1459                 0x9400, 0x9470,
1460                 0x9600, 0x9600,
1461                 0x9608, 0x9638,
1462                 0x9640, 0x9704,
1463                 0x9710, 0x971c,
1464                 0x9800, 0x9808,
1465                 0x9820, 0x983c,
1466                 0x9850, 0x9864,
1467                 0x9c00, 0x9c6c,
1468                 0x9c80, 0x9cec,
1469                 0x9d00, 0x9d6c,
1470                 0x9d80, 0x9dec,
1471                 0x9e00, 0x9e6c,
1472                 0x9e80, 0x9eec,
1473                 0x9f00, 0x9f6c,
1474                 0x9f80, 0xa020,
1475                 0xd004, 0xd03c,
1476                 0xd100, 0xd118,
1477                 0xd200, 0xd214,
1478                 0xd220, 0xd234,
1479                 0xd240, 0xd254,
1480                 0xd260, 0xd274,
1481                 0xd280, 0xd294,
1482                 0xd2a0, 0xd2b4,
1483                 0xd2c0, 0xd2d4,
1484                 0xd2e0, 0xd2f4,
1485                 0xd300, 0xd31c,
1486                 0xdfc0, 0xdfe0,
1487                 0xe000, 0xf008,
1488                 0xf010, 0xf018,
1489                 0xf020, 0xf028,
1490                 0x11000, 0x11014,
1491                 0x11048, 0x1106c,
1492                 0x11074, 0x11088,
1493                 0x11098, 0x11120,
1494                 0x1112c, 0x1117c,
1495                 0x11190, 0x112e0,
1496                 0x11300, 0x1130c,
1497                 0x12000, 0x1206c,
1498                 0x19040, 0x1906c,
1499                 0x19078, 0x19080,
1500                 0x1908c, 0x190e8,
1501                 0x190f0, 0x190f8,
1502                 0x19100, 0x19110,
1503                 0x19120, 0x19124,
1504                 0x19150, 0x19194,
1505                 0x1919c, 0x191b0,
1506                 0x191d0, 0x191e8,
1507                 0x19238, 0x19290,
1508                 0x192a4, 0x192b0,
1509                 0x192bc, 0x192bc,
1510                 0x19348, 0x1934c,
1511                 0x193f8, 0x19418,
1512                 0x19420, 0x19428,
1513                 0x19430, 0x19444,
1514                 0x1944c, 0x1946c,
1515                 0x19474, 0x19474,
1516                 0x19490, 0x194cc,
1517                 0x194f0, 0x194f8,
1518                 0x19c00, 0x19c48,
1519                 0x19c50, 0x19c80,
1520                 0x19c94, 0x19c98,
1521                 0x19ca0, 0x19cbc,
1522                 0x19ce4, 0x19ce4,
1523                 0x19cf0, 0x19cf8,
1524                 0x19d00, 0x19d28,
1525                 0x19d50, 0x19d78,
1526                 0x19d94, 0x19d98,
1527                 0x19da0, 0x19dc8,
1528                 0x19df0, 0x19e10,
1529                 0x19e50, 0x19e6c,
1530                 0x19ea0, 0x19ebc,
1531                 0x19ec4, 0x19ef4,
1532                 0x19f04, 0x19f2c,
1533                 0x19f34, 0x19f34,
1534                 0x19f40, 0x19f50,
1535                 0x19f90, 0x19fac,
1536                 0x19fc4, 0x19fc8,
1537                 0x19fd0, 0x19fe4,
1538                 0x1a000, 0x1a004,
1539                 0x1a010, 0x1a06c,
1540                 0x1a0b0, 0x1a0e4,
1541                 0x1a0ec, 0x1a0f8,
1542                 0x1a100, 0x1a108,
1543                 0x1a114, 0x1a120,
1544                 0x1a128, 0x1a130,
1545                 0x1a138, 0x1a138,
1546                 0x1a190, 0x1a1c4,
1547                 0x1a1fc, 0x1a1fc,
1548                 0x1e008, 0x1e00c,
1549                 0x1e040, 0x1e044,
1550                 0x1e04c, 0x1e04c,
1551                 0x1e284, 0x1e290,
1552                 0x1e2c0, 0x1e2c0,
1553                 0x1e2e0, 0x1e2e0,
1554                 0x1e300, 0x1e384,
1555                 0x1e3c0, 0x1e3c8,
1556                 0x1e408, 0x1e40c,
1557                 0x1e440, 0x1e444,
1558                 0x1e44c, 0x1e44c,
1559                 0x1e684, 0x1e690,
1560                 0x1e6c0, 0x1e6c0,
1561                 0x1e6e0, 0x1e6e0,
1562                 0x1e700, 0x1e784,
1563                 0x1e7c0, 0x1e7c8,
1564                 0x1e808, 0x1e80c,
1565                 0x1e840, 0x1e844,
1566                 0x1e84c, 0x1e84c,
1567                 0x1ea84, 0x1ea90,
1568                 0x1eac0, 0x1eac0,
1569                 0x1eae0, 0x1eae0,
1570                 0x1eb00, 0x1eb84,
1571                 0x1ebc0, 0x1ebc8,
1572                 0x1ec08, 0x1ec0c,
1573                 0x1ec40, 0x1ec44,
1574                 0x1ec4c, 0x1ec4c,
1575                 0x1ee84, 0x1ee90,
1576                 0x1eec0, 0x1eec0,
1577                 0x1eee0, 0x1eee0,
1578                 0x1ef00, 0x1ef84,
1579                 0x1efc0, 0x1efc8,
1580                 0x1f008, 0x1f00c,
1581                 0x1f040, 0x1f044,
1582                 0x1f04c, 0x1f04c,
1583                 0x1f284, 0x1f290,
1584                 0x1f2c0, 0x1f2c0,
1585                 0x1f2e0, 0x1f2e0,
1586                 0x1f300, 0x1f384,
1587                 0x1f3c0, 0x1f3c8,
1588                 0x1f408, 0x1f40c,
1589                 0x1f440, 0x1f444,
1590                 0x1f44c, 0x1f44c,
1591                 0x1f684, 0x1f690,
1592                 0x1f6c0, 0x1f6c0,
1593                 0x1f6e0, 0x1f6e0,
1594                 0x1f700, 0x1f784,
1595                 0x1f7c0, 0x1f7c8,
1596                 0x1f808, 0x1f80c,
1597                 0x1f840, 0x1f844,
1598                 0x1f84c, 0x1f84c,
1599                 0x1fa84, 0x1fa90,
1600                 0x1fac0, 0x1fac0,
1601                 0x1fae0, 0x1fae0,
1602                 0x1fb00, 0x1fb84,
1603                 0x1fbc0, 0x1fbc8,
1604                 0x1fc08, 0x1fc0c,
1605                 0x1fc40, 0x1fc44,
1606                 0x1fc4c, 0x1fc4c,
1607                 0x1fe84, 0x1fe90,
1608                 0x1fec0, 0x1fec0,
1609                 0x1fee0, 0x1fee0,
1610                 0x1ff00, 0x1ff84,
1611                 0x1ffc0, 0x1ffc8,
1612                 0x30000, 0x30030,
1613                 0x30100, 0x30168,
1614                 0x30190, 0x301a0,
1615                 0x301a8, 0x301b8,
1616                 0x301c4, 0x301c8,
1617                 0x301d0, 0x301d0,
1618                 0x30200, 0x30320,
1619                 0x30400, 0x304b4,
1620                 0x304c0, 0x3052c,
1621                 0x30540, 0x3061c,
1622                 0x30800, 0x308a0,
1623                 0x308c0, 0x30908,
1624                 0x30910, 0x309b8,
1625                 0x30a00, 0x30a04,
1626                 0x30a0c, 0x30a14,
1627                 0x30a1c, 0x30a2c,
1628                 0x30a44, 0x30a50,
1629                 0x30a74, 0x30a74,
1630                 0x30a7c, 0x30afc,
1631                 0x30b08, 0x30c24,
1632                 0x30d00, 0x30d14,
1633                 0x30d1c, 0x30d3c,
1634                 0x30d44, 0x30d4c,
1635                 0x30d54, 0x30d74,
1636                 0x30d7c, 0x30d7c,
1637                 0x30de0, 0x30de0,
1638                 0x30e00, 0x30ed4,
1639                 0x30f00, 0x30fa4,
1640                 0x30fc0, 0x30fc4,
1641                 0x31000, 0x31004,
1642                 0x31080, 0x310fc,
1643                 0x31208, 0x31220,
1644                 0x3123c, 0x31254,
1645                 0x31300, 0x31300,
1646                 0x31308, 0x3131c,
1647                 0x31338, 0x3133c,
1648                 0x31380, 0x31380,
1649                 0x31388, 0x313a8,
1650                 0x313b4, 0x313b4,
1651                 0x31400, 0x31420,
1652                 0x31438, 0x3143c,
1653                 0x31480, 0x31480,
1654                 0x314a8, 0x314a8,
1655                 0x314b0, 0x314b4,
1656                 0x314c8, 0x314d4,
1657                 0x31a40, 0x31a4c,
1658                 0x31af0, 0x31b20,
1659                 0x31b38, 0x31b3c,
1660                 0x31b80, 0x31b80,
1661                 0x31ba8, 0x31ba8,
1662                 0x31bb0, 0x31bb4,
1663                 0x31bc8, 0x31bd4,
1664                 0x32140, 0x3218c,
1665                 0x321f0, 0x321f4,
1666                 0x32200, 0x32200,
1667                 0x32218, 0x32218,
1668                 0x32400, 0x32400,
1669                 0x32408, 0x3241c,
1670                 0x32618, 0x32620,
1671                 0x32664, 0x32664,
1672                 0x326a8, 0x326a8,
1673                 0x326ec, 0x326ec,
1674                 0x32a00, 0x32abc,
1675                 0x32b00, 0x32b38,
1676                 0x32b20, 0x32b38,
1677                 0x32b40, 0x32b58,
1678                 0x32b60, 0x32b78,
1679                 0x32c00, 0x32c00,
1680                 0x32c08, 0x32c3c,
1681                 0x33000, 0x3302c,
1682                 0x33034, 0x33050,
1683                 0x33058, 0x33058,
1684                 0x33060, 0x3308c,
1685                 0x3309c, 0x330ac,
1686                 0x330c0, 0x330c0,
1687                 0x330c8, 0x330d0,
1688                 0x330d8, 0x330e0,
1689                 0x330ec, 0x3312c,
1690                 0x33134, 0x33150,
1691                 0x33158, 0x33158,
1692                 0x33160, 0x3318c,
1693                 0x3319c, 0x331ac,
1694                 0x331c0, 0x331c0,
1695                 0x331c8, 0x331d0,
1696                 0x331d8, 0x331e0,
1697                 0x331ec, 0x33290,
1698                 0x33298, 0x332c4,
1699                 0x332e4, 0x33390,
1700                 0x33398, 0x333c4,
1701                 0x333e4, 0x3342c,
1702                 0x33434, 0x33450,
1703                 0x33458, 0x33458,
1704                 0x33460, 0x3348c,
1705                 0x3349c, 0x334ac,
1706                 0x334c0, 0x334c0,
1707                 0x334c8, 0x334d0,
1708                 0x334d8, 0x334e0,
1709                 0x334ec, 0x3352c,
1710                 0x33534, 0x33550,
1711                 0x33558, 0x33558,
1712                 0x33560, 0x3358c,
1713                 0x3359c, 0x335ac,
1714                 0x335c0, 0x335c0,
1715                 0x335c8, 0x335d0,
1716                 0x335d8, 0x335e0,
1717                 0x335ec, 0x33690,
1718                 0x33698, 0x336c4,
1719                 0x336e4, 0x33790,
1720                 0x33798, 0x337c4,
1721                 0x337e4, 0x337fc,
1722                 0x33814, 0x33814,
1723                 0x33854, 0x33868,
1724                 0x33880, 0x3388c,
1725                 0x338c0, 0x338d0,
1726                 0x338e8, 0x338ec,
1727                 0x33900, 0x3392c,
1728                 0x33934, 0x33950,
1729                 0x33958, 0x33958,
1730                 0x33960, 0x3398c,
1731                 0x3399c, 0x339ac,
1732                 0x339c0, 0x339c0,
1733                 0x339c8, 0x339d0,
1734                 0x339d8, 0x339e0,
1735                 0x339ec, 0x33a90,
1736                 0x33a98, 0x33ac4,
1737                 0x33ae4, 0x33b10,
1738                 0x33b24, 0x33b28,
1739                 0x33b38, 0x33b50,
1740                 0x33bf0, 0x33c10,
1741                 0x33c24, 0x33c28,
1742                 0x33c38, 0x33c50,
1743                 0x33cf0, 0x33cfc,
1744                 0x34000, 0x34030,
1745                 0x34100, 0x34168,
1746                 0x34190, 0x341a0,
1747                 0x341a8, 0x341b8,
1748                 0x341c4, 0x341c8,
1749                 0x341d0, 0x341d0,
1750                 0x34200, 0x34320,
1751                 0x34400, 0x344b4,
1752                 0x344c0, 0x3452c,
1753                 0x34540, 0x3461c,
1754                 0x34800, 0x348a0,
1755                 0x348c0, 0x34908,
1756                 0x34910, 0x349b8,
1757                 0x34a00, 0x34a04,
1758                 0x34a0c, 0x34a14,
1759                 0x34a1c, 0x34a2c,
1760                 0x34a44, 0x34a50,
1761                 0x34a74, 0x34a74,
1762                 0x34a7c, 0x34afc,
1763                 0x34b08, 0x34c24,
1764                 0x34d00, 0x34d14,
1765                 0x34d1c, 0x34d3c,
1766                 0x34d44, 0x34d4c,
1767                 0x34d54, 0x34d74,
1768                 0x34d7c, 0x34d7c,
1769                 0x34de0, 0x34de0,
1770                 0x34e00, 0x34ed4,
1771                 0x34f00, 0x34fa4,
1772                 0x34fc0, 0x34fc4,
1773                 0x35000, 0x35004,
1774                 0x35080, 0x350fc,
1775                 0x35208, 0x35220,
1776                 0x3523c, 0x35254,
1777                 0x35300, 0x35300,
1778                 0x35308, 0x3531c,
1779                 0x35338, 0x3533c,
1780                 0x35380, 0x35380,
1781                 0x35388, 0x353a8,
1782                 0x353b4, 0x353b4,
1783                 0x35400, 0x35420,
1784                 0x35438, 0x3543c,
1785                 0x35480, 0x35480,
1786                 0x354a8, 0x354a8,
1787                 0x354b0, 0x354b4,
1788                 0x354c8, 0x354d4,
1789                 0x35a40, 0x35a4c,
1790                 0x35af0, 0x35b20,
1791                 0x35b38, 0x35b3c,
1792                 0x35b80, 0x35b80,
1793                 0x35ba8, 0x35ba8,
1794                 0x35bb0, 0x35bb4,
1795                 0x35bc8, 0x35bd4,
1796                 0x36140, 0x3618c,
1797                 0x361f0, 0x361f4,
1798                 0x36200, 0x36200,
1799                 0x36218, 0x36218,
1800                 0x36400, 0x36400,
1801                 0x36408, 0x3641c,
1802                 0x36618, 0x36620,
1803                 0x36664, 0x36664,
1804                 0x366a8, 0x366a8,
1805                 0x366ec, 0x366ec,
1806                 0x36a00, 0x36abc,
1807                 0x36b00, 0x36b38,
1808                 0x36b20, 0x36b38,
1809                 0x36b40, 0x36b58,
1810                 0x36b60, 0x36b78,
1811                 0x36c00, 0x36c00,
1812                 0x36c08, 0x36c3c,
1813                 0x37000, 0x3702c,
1814                 0x37034, 0x37050,
1815                 0x37058, 0x37058,
1816                 0x37060, 0x3708c,
1817                 0x3709c, 0x370ac,
1818                 0x370c0, 0x370c0,
1819                 0x370c8, 0x370d0,
1820                 0x370d8, 0x370e0,
1821                 0x370ec, 0x3712c,
1822                 0x37134, 0x37150,
1823                 0x37158, 0x37158,
1824                 0x37160, 0x3718c,
1825                 0x3719c, 0x371ac,
1826                 0x371c0, 0x371c0,
1827                 0x371c8, 0x371d0,
1828                 0x371d8, 0x371e0,
1829                 0x371ec, 0x37290,
1830                 0x37298, 0x372c4,
1831                 0x372e4, 0x37390,
1832                 0x37398, 0x373c4,
1833                 0x373e4, 0x3742c,
1834                 0x37434, 0x37450,
1835                 0x37458, 0x37458,
1836                 0x37460, 0x3748c,
1837                 0x3749c, 0x374ac,
1838                 0x374c0, 0x374c0,
1839                 0x374c8, 0x374d0,
1840                 0x374d8, 0x374e0,
1841                 0x374ec, 0x3752c,
1842                 0x37534, 0x37550,
1843                 0x37558, 0x37558,
1844                 0x37560, 0x3758c,
1845                 0x3759c, 0x375ac,
1846                 0x375c0, 0x375c0,
1847                 0x375c8, 0x375d0,
1848                 0x375d8, 0x375e0,
1849                 0x375ec, 0x37690,
1850                 0x37698, 0x376c4,
1851                 0x376e4, 0x37790,
1852                 0x37798, 0x377c4,
1853                 0x377e4, 0x377fc,
1854                 0x37814, 0x37814,
1855                 0x37854, 0x37868,
1856                 0x37880, 0x3788c,
1857                 0x378c0, 0x378d0,
1858                 0x378e8, 0x378ec,
1859                 0x37900, 0x3792c,
1860                 0x37934, 0x37950,
1861                 0x37958, 0x37958,
1862                 0x37960, 0x3798c,
1863                 0x3799c, 0x379ac,
1864                 0x379c0, 0x379c0,
1865                 0x379c8, 0x379d0,
1866                 0x379d8, 0x379e0,
1867                 0x379ec, 0x37a90,
1868                 0x37a98, 0x37ac4,
1869                 0x37ae4, 0x37b10,
1870                 0x37b24, 0x37b28,
1871                 0x37b38, 0x37b50,
1872                 0x37bf0, 0x37c10,
1873                 0x37c24, 0x37c28,
1874                 0x37c38, 0x37c50,
1875                 0x37cf0, 0x37cfc,
1876                 0x40040, 0x40040,
1877                 0x40080, 0x40084,
1878                 0x40100, 0x40100,
1879                 0x40140, 0x401bc,
1880                 0x40200, 0x40214,
1881                 0x40228, 0x40228,
1882                 0x40240, 0x40258,
1883                 0x40280, 0x40280,
1884                 0x40304, 0x40304,
1885                 0x40330, 0x4033c,
1886                 0x41304, 0x413c8,
1887                 0x413d0, 0x413dc,
1888                 0x413f0, 0x413f0,
1889                 0x41400, 0x4140c,
1890                 0x41414, 0x4141c,
1891                 0x41480, 0x414d0,
1892                 0x44000, 0x4407c,
1893                 0x440c0, 0x441ac,
1894                 0x441b4, 0x4427c,
1895                 0x442c0, 0x443ac,
1896                 0x443b4, 0x4447c,
1897                 0x444c0, 0x445ac,
1898                 0x445b4, 0x4467c,
1899                 0x446c0, 0x447ac,
1900                 0x447b4, 0x4487c,
1901                 0x448c0, 0x449ac,
1902                 0x449b4, 0x44a7c,
1903                 0x44ac0, 0x44bac,
1904                 0x44bb4, 0x44c7c,
1905                 0x44cc0, 0x44dac,
1906                 0x44db4, 0x44e7c,
1907                 0x44ec0, 0x44fac,
1908                 0x44fb4, 0x4507c,
1909                 0x450c0, 0x451ac,
1910                 0x451b4, 0x451fc,
1911                 0x45800, 0x45804,
1912                 0x45810, 0x45830,
1913                 0x45840, 0x45860,
1914                 0x45868, 0x45868,
1915                 0x45880, 0x45884,
1916                 0x458a0, 0x458b0,
1917                 0x45a00, 0x45a04,
1918                 0x45a10, 0x45a30,
1919                 0x45a40, 0x45a60,
1920                 0x45a68, 0x45a68,
1921                 0x45a80, 0x45a84,
1922                 0x45aa0, 0x45ab0,
1923                 0x460c0, 0x460e4,
1924                 0x47000, 0x4703c,
1925                 0x47044, 0x4708c,
1926                 0x47200, 0x47250,
1927                 0x47400, 0x47408,
1928                 0x47414, 0x47420,
1929                 0x47600, 0x47618,
1930                 0x47800, 0x47814,
1931                 0x47820, 0x4782c,
1932                 0x50000, 0x50084,
1933                 0x50090, 0x500cc,
1934                 0x50300, 0x50384,
1935                 0x50400, 0x50400,
1936                 0x50800, 0x50884,
1937                 0x50890, 0x508cc,
1938                 0x50b00, 0x50b84,
1939                 0x50c00, 0x50c00,
1940                 0x51000, 0x51020,
1941                 0x51028, 0x510b0,
1942                 0x51300, 0x51324,
1943         };
1944
1945         u32 *buf_end = (u32 *)((char *)buf + buf_size);
1946         const unsigned int *reg_ranges;
1947         int reg_ranges_size, range;
1948         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
1949
1950         /* Select the right set of register ranges to dump depending on the
1951          * adapter chip type.
1952          */
1953         switch (chip_version) {
1954         case CHELSIO_T5:
1955                 reg_ranges = t5_reg_ranges;
1956                 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
1957                 break;
1958
1959         case CHELSIO_T6:
1960                 reg_ranges = t6_reg_ranges;
1961                 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
1962                 break;
1963
1964         default:
1965                 dev_err(adap,
1966                         "Unsupported chip version %d\n", chip_version);
1967                 return;
1968         }
1969
1970         /* Clear the register buffer and insert the appropriate register
1971          * values selected by the above register ranges.
1972          */
1973         memset(buf, 0, buf_size);
1974         for (range = 0; range < reg_ranges_size; range += 2) {
1975                 unsigned int reg = reg_ranges[range];
1976                 unsigned int last_reg = reg_ranges[range + 1];
1977                 u32 *bufp = (u32 *)((char *)buf + reg);
1978
1979                 /* Iterate across the register range filling in the register
1980                  * buffer but don't write past the end of the register buffer.
1981                  */
1982                 while (reg <= last_reg && bufp < buf_end) {
1983                         *bufp++ = t4_read_reg(adap, reg);
1984                         reg += sizeof(u32);
1985                 }
1986         }
1987 }
1988
1989 /* EEPROM reads take a few tens of us while writes can take a bit over 5 ms. */
1990 #define EEPROM_DELAY            10              /* 10us per poll spin */
1991 #define EEPROM_MAX_POLL         5000            /* x 5000 == 50ms */
1992
1993 #define EEPROM_STAT_ADDR        0x7bfc
1994
1995 /**
1996  * Small utility function to wait till any outstanding VPD Access is complete.
1997  * We have a per-adapter state variable "VPD Busy" to indicate when we have a
1998  * VPD Access in flight.  This allows us to handle the problem of having a
1999  * previous VPD Access time out and prevent an attempt to inject a new VPD
2000  * Request before any in-flight VPD request has completed.
2001  */
2002 static int t4_seeprom_wait(struct adapter *adapter)
2003 {
2004         unsigned int base = adapter->params.pci.vpd_cap_addr;
2005         int max_poll;
2006
2007         /* If no VPD Access is in flight, we can just return success right
2008          * away.
2009          */
2010         if (!adapter->vpd_busy)
2011                 return 0;
2012
2013         /* Poll the VPD Capability Address/Flag register waiting for it
2014          * to indicate that the operation is complete.
2015          */
2016         max_poll = EEPROM_MAX_POLL;
2017         do {
2018                 u16 val;
2019
2020                 udelay(EEPROM_DELAY);
2021                 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val);
2022
2023                 /* If the operation is complete, mark the VPD as no longer
2024                  * busy and return success.
2025                  */
2026                 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) {
2027                         adapter->vpd_busy = 0;
2028                         return 0;
2029                 }
2030         } while (--max_poll);
2031
2032         /* Failure!  Note that we leave the VPD Busy status set in order to
2033          * avoid pushing a new VPD Access request into the VPD Capability till
2034          * the current operation eventually succeeds.  It's a bug to issue a
2035          * new request when an existing request is in flight and will result
2036          * in corrupt hardware state.
2037          */
2038         return -ETIMEDOUT;
2039 }
2040
2041 /**
2042  * t4_seeprom_read - read a serial EEPROM location
2043  * @adapter: adapter to read
2044  * @addr: EEPROM virtual address
2045  * @data: where to store the read data
2046  *
2047  * Read a 32-bit word from a location in serial EEPROM using the card's PCI
2048  * VPD capability.  Note that this function must be called with a virtual
2049  * address.
2050  */
2051 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data)
2052 {
2053         unsigned int base = adapter->params.pci.vpd_cap_addr;
2054         int ret;
2055
2056         /* VPD Accesses must alway be 4-byte aligned!
2057          */
2058         if (addr >= EEPROMVSIZE || (addr & 3))
2059                 return -EINVAL;
2060
2061         /* Wait for any previous operation which may still be in flight to
2062          * complete.
2063          */
2064         ret = t4_seeprom_wait(adapter);
2065         if (ret) {
2066                 dev_err(adapter, "VPD still busy from previous operation\n");
2067                 return ret;
2068         }
2069
2070         /* Issue our new VPD Read request, mark the VPD as being busy and wait
2071          * for our request to complete.  If it doesn't complete, note the
2072          * error and return it to our caller.  Note that we do not reset the
2073          * VPD Busy status!
2074          */
2075         t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr);
2076         adapter->vpd_busy = 1;
2077         adapter->vpd_flag = PCI_VPD_ADDR_F;
2078         ret = t4_seeprom_wait(adapter);
2079         if (ret) {
2080                 dev_err(adapter, "VPD read of address %#x failed\n", addr);
2081                 return ret;
2082         }
2083
2084         /* Grab the returned data, swizzle it into our endianness and
2085          * return success.
2086          */
2087         t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data);
2088         *data = le32_to_cpu(*data);
2089         return 0;
2090 }
2091
2092 /**
2093  * t4_seeprom_write - write a serial EEPROM location
2094  * @adapter: adapter to write
2095  * @addr: virtual EEPROM address
2096  * @data: value to write
2097  *
2098  * Write a 32-bit word to a location in serial EEPROM using the card's PCI
2099  * VPD capability.  Note that this function must be called with a virtual
2100  * address.
2101  */
2102 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data)
2103 {
2104         unsigned int base = adapter->params.pci.vpd_cap_addr;
2105         int ret;
2106         u32 stats_reg = 0;
2107         int max_poll;
2108
2109         /* VPD Accesses must alway be 4-byte aligned!
2110          */
2111         if (addr >= EEPROMVSIZE || (addr & 3))
2112                 return -EINVAL;
2113
2114         /* Wait for any previous operation which may still be in flight to
2115          * complete.
2116          */
2117         ret = t4_seeprom_wait(adapter);
2118         if (ret) {
2119                 dev_err(adapter, "VPD still busy from previous operation\n");
2120                 return ret;
2121         }
2122
2123         /* Issue our new VPD Read request, mark the VPD as being busy and wait
2124          * for our request to complete.  If it doesn't complete, note the
2125          * error and return it to our caller.  Note that we do not reset the
2126          * VPD Busy status!
2127          */
2128         t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA,
2129                              cpu_to_le32(data));
2130         t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR,
2131                              (u16)addr | PCI_VPD_ADDR_F);
2132         adapter->vpd_busy = 1;
2133         adapter->vpd_flag = 0;
2134         ret = t4_seeprom_wait(adapter);
2135         if (ret) {
2136                 dev_err(adapter, "VPD write of address %#x failed\n", addr);
2137                 return ret;
2138         }
2139
2140         /* Reset PCI_VPD_DATA register after a transaction and wait for our
2141          * request to complete. If it doesn't complete, return error.
2142          */
2143         t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0);
2144         max_poll = EEPROM_MAX_POLL;
2145         do {
2146                 udelay(EEPROM_DELAY);
2147                 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg);
2148         } while ((stats_reg & 0x1) && --max_poll);
2149         if (!max_poll)
2150                 return -ETIMEDOUT;
2151
2152         /* Return success! */
2153         return 0;
2154 }
2155
2156 /**
2157  * t4_seeprom_wp - enable/disable EEPROM write protection
2158  * @adapter: the adapter
2159  * @enable: whether to enable or disable write protection
2160  *
2161  * Enables or disables write protection on the serial EEPROM.
2162  */
2163 int t4_seeprom_wp(struct adapter *adapter, int enable)
2164 {
2165         return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
2166 }
2167
2168 /**
2169  * t4_config_rss_range - configure a portion of the RSS mapping table
2170  * @adapter: the adapter
2171  * @mbox: mbox to use for the FW command
2172  * @viid: virtual interface whose RSS subtable is to be written
2173  * @start: start entry in the table to write
2174  * @n: how many table entries to write
2175  * @rspq: values for the "response queue" (Ingress Queue) lookup table
2176  * @nrspq: number of values in @rspq
2177  *
2178  * Programs the selected part of the VI's RSS mapping table with the
2179  * provided values.  If @nrspq < @n the supplied values are used repeatedly
2180  * until the full table range is populated.
2181  *
2182  * The caller must ensure the values in @rspq are in the range allowed for
2183  * @viid.
2184  */
2185 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
2186                         int start, int n, const u16 *rspq, unsigned int nrspq)
2187 {
2188         int ret;
2189         const u16 *rsp = rspq;
2190         const u16 *rsp_end = rspq + nrspq;
2191         struct fw_rss_ind_tbl_cmd cmd;
2192
2193         memset(&cmd, 0, sizeof(cmd));
2194         cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
2195                                      F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2196                                      V_FW_RSS_IND_TBL_CMD_VIID(viid));
2197         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
2198
2199         /*
2200          * Each firmware RSS command can accommodate up to 32 RSS Ingress
2201          * Queue Identifiers.  These Ingress Queue IDs are packed three to
2202          * a 32-bit word as 10-bit values with the upper remaining 2 bits
2203          * reserved.
2204          */
2205         while (n > 0) {
2206                 int nq = min(n, 32);
2207                 int nq_packed = 0;
2208                 __be32 *qp = &cmd.iq0_to_iq2;
2209
2210                 /*
2211                  * Set up the firmware RSS command header to send the next
2212                  * "nq" Ingress Queue IDs to the firmware.
2213                  */
2214                 cmd.niqid = cpu_to_be16(nq);
2215                 cmd.startidx = cpu_to_be16(start);
2216
2217                 /*
2218                  * "nq" more done for the start of the next loop.
2219                  */
2220                 start += nq;
2221                 n -= nq;
2222
2223                 /*
2224                  * While there are still Ingress Queue IDs to stuff into the
2225                  * current firmware RSS command, retrieve them from the
2226                  * Ingress Queue ID array and insert them into the command.
2227                  */
2228                 while (nq > 0) {
2229                         /*
2230                          * Grab up to the next 3 Ingress Queue IDs (wrapping
2231                          * around the Ingress Queue ID array if necessary) and
2232                          * insert them into the firmware RSS command at the
2233                          * current 3-tuple position within the commad.
2234                          */
2235                         u16 qbuf[3];
2236                         u16 *qbp = qbuf;
2237                         int nqbuf = min(3, nq);
2238
2239                         nq -= nqbuf;
2240                         qbuf[0] = 0;
2241                         qbuf[1] = 0;
2242                         qbuf[2] = 0;
2243                         while (nqbuf && nq_packed < 32) {
2244                                 nqbuf--;
2245                                 nq_packed++;
2246                                 *qbp++ = *rsp++;
2247                                 if (rsp >= rsp_end)
2248                                         rsp = rspq;
2249                         }
2250                         *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) |
2251                                             V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) |
2252                                             V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2]));
2253                 }
2254
2255                 /*
2256                  * Send this portion of the RRS table update to the firmware;
2257                  * bail out on any errors.
2258                  */
2259                 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
2260                 if (ret)
2261                         return ret;
2262         }
2263
2264         return 0;
2265 }
2266
2267 /**
2268  * t4_config_vi_rss - configure per VI RSS settings
2269  * @adapter: the adapter
2270  * @mbox: mbox to use for the FW command
2271  * @viid: the VI id
2272  * @flags: RSS flags
2273  * @defq: id of the default RSS queue for the VI.
2274  *
2275  * Configures VI-specific RSS properties.
2276  */
2277 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
2278                      unsigned int flags, unsigned int defq)
2279 {
2280         struct fw_rss_vi_config_cmd c;
2281
2282         memset(&c, 0, sizeof(c));
2283         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
2284                                    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2285                                    V_FW_RSS_VI_CONFIG_CMD_VIID(viid));
2286         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
2287         c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
2288                         V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq));
2289         return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
2290 }
2291
2292 /**
2293  * init_cong_ctrl - initialize congestion control parameters
2294  * @a: the alpha values for congestion control
2295  * @b: the beta values for congestion control
2296  *
2297  * Initialize the congestion control parameters.
2298  */
2299 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
2300 {
2301         int i;
2302
2303         for (i = 0; i < 9; i++) {
2304                 a[i] = 1;
2305                 b[i] = 0;
2306         }
2307
2308         a[9] = 2;
2309         a[10] = 3;
2310         a[11] = 4;
2311         a[12] = 5;
2312         a[13] = 6;
2313         a[14] = 7;
2314         a[15] = 8;
2315         a[16] = 9;
2316         a[17] = 10;
2317         a[18] = 14;
2318         a[19] = 17;
2319         a[20] = 21;
2320         a[21] = 25;
2321         a[22] = 30;
2322         a[23] = 35;
2323         a[24] = 45;
2324         a[25] = 60;
2325         a[26] = 80;
2326         a[27] = 100;
2327         a[28] = 200;
2328         a[29] = 300;
2329         a[30] = 400;
2330         a[31] = 500;
2331
2332         b[9] = 1;
2333         b[10] = 1;
2334         b[11] = 2;
2335         b[12] = 2;
2336         b[13] = 3;
2337         b[14] = 3;
2338         b[15] = 3;
2339         b[16] = 3;
2340         b[17] = 4;
2341         b[18] = 4;
2342         b[19] = 4;
2343         b[20] = 4;
2344         b[21] = 4;
2345         b[22] = 5;
2346         b[23] = 5;
2347         b[24] = 5;
2348         b[25] = 5;
2349         b[26] = 5;
2350         b[27] = 5;
2351         b[28] = 6;
2352         b[29] = 6;
2353         b[30] = 7;
2354         b[31] = 7;
2355 }
2356
2357 #define INIT_CMD(var, cmd, rd_wr) do { \
2358         (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \
2359                         F_FW_CMD_REQUEST | F_FW_CMD_##rd_wr); \
2360         (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
2361 } while (0)
2362
2363 int t4_get_core_clock(struct adapter *adapter, struct vpd_params *p)
2364 {
2365         u32 cclk_param, cclk_val;
2366         int ret;
2367
2368         /*
2369          * Ask firmware for the Core Clock since it knows how to translate the
2370          * Reference Clock ('V2') VPD field into a Core Clock value ...
2371          */
2372         cclk_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
2373                       V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CCLK));
2374         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2375                               1, &cclk_param, &cclk_val);
2376         if (ret) {
2377                 dev_err(adapter, "%s: error in fetching from coreclock - %d\n",
2378                         __func__, ret);
2379                 return ret;
2380         }
2381
2382         p->cclk = cclk_val;
2383         dev_debug(adapter, "%s: p->cclk = %u\n", __func__, p->cclk);
2384         return 0;
2385 }
2386
2387 /* serial flash and firmware constants and flash config file constants */
2388 enum {
2389         SF_ATTEMPTS = 10,             /* max retries for SF operations */
2390
2391         /* flash command opcodes */
2392         SF_PROG_PAGE    = 2,          /* program page */
2393         SF_WR_DISABLE   = 4,          /* disable writes */
2394         SF_RD_STATUS    = 5,          /* read status register */
2395         SF_WR_ENABLE    = 6,          /* enable writes */
2396         SF_RD_DATA_FAST = 0xb,        /* read flash */
2397         SF_RD_ID        = 0x9f,       /* read ID */
2398         SF_ERASE_SECTOR = 0xd8,       /* erase sector */
2399 };
2400
2401 /**
2402  * sf1_read - read data from the serial flash
2403  * @adapter: the adapter
2404  * @byte_cnt: number of bytes to read
2405  * @cont: whether another operation will be chained
2406  * @lock: whether to lock SF for PL access only
2407  * @valp: where to store the read data
2408  *
2409  * Reads up to 4 bytes of data from the serial flash.  The location of
2410  * the read needs to be specified prior to calling this by issuing the
2411  * appropriate commands to the serial flash.
2412  */
2413 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2414                     int lock, u32 *valp)
2415 {
2416         int ret;
2417
2418         if (!byte_cnt || byte_cnt > 4)
2419                 return -EINVAL;
2420         if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
2421                 return -EBUSY;
2422         t4_write_reg(adapter, A_SF_OP,
2423                      V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
2424         ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
2425         if (!ret)
2426                 *valp = t4_read_reg(adapter, A_SF_DATA);
2427         return ret;
2428 }
2429
2430 /**
2431  * sf1_write - write data to the serial flash
2432  * @adapter: the adapter
2433  * @byte_cnt: number of bytes to write
2434  * @cont: whether another operation will be chained
2435  * @lock: whether to lock SF for PL access only
2436  * @val: value to write
2437  *
2438  * Writes up to 4 bytes of data to the serial flash.  The location of
2439  * the write needs to be specified prior to calling this by issuing the
2440  * appropriate commands to the serial flash.
2441  */
2442 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2443                      int lock, u32 val)
2444 {
2445         if (!byte_cnt || byte_cnt > 4)
2446                 return -EINVAL;
2447         if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
2448                 return -EBUSY;
2449         t4_write_reg(adapter, A_SF_DATA, val);
2450         t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) |
2451                      V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1));
2452         return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
2453 }
2454
2455 /**
2456  * t4_read_flash - read words from serial flash
2457  * @adapter: the adapter
2458  * @addr: the start address for the read
2459  * @nwords: how many 32-bit words to read
2460  * @data: where to store the read data
2461  * @byte_oriented: whether to store data as bytes or as words
2462  *
2463  * Read the specified number of 32-bit words from the serial flash.
2464  * If @byte_oriented is set the read data is stored as a byte array
2465  * (i.e., big-endian), otherwise as 32-bit words in the platform's
2466  * natural endianness.
2467  */
2468 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2469                   unsigned int nwords, u32 *data, int byte_oriented)
2470 {
2471         int ret;
2472
2473         if (((addr + nwords * sizeof(u32)) > adapter->params.sf_size) ||
2474             (addr & 3))
2475                 return -EINVAL;
2476
2477         addr = rte_constant_bswap32(addr) | SF_RD_DATA_FAST;
2478
2479         ret = sf1_write(adapter, 4, 1, 0, addr);
2480         if (ret != 0)
2481                 return ret;
2482
2483         ret = sf1_read(adapter, 1, 1, 0, data);
2484         if (ret != 0)
2485                 return ret;
2486
2487         for ( ; nwords; nwords--, data++) {
2488                 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2489                 if (nwords == 1)
2490                         t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
2491                 if (ret)
2492                         return ret;
2493                 if (byte_oriented)
2494                         *data = cpu_to_be32(*data);
2495         }
2496         return 0;
2497 }
2498
2499 /**
2500  * t4_get_exprom_version - return the Expansion ROM version (if any)
2501  * @adapter: the adapter
2502  * @vers: where to place the version
2503  *
2504  * Reads the Expansion ROM header from FLASH and returns the version
2505  * number (if present) through the @vers return value pointer.  We return
2506  * this in the Firmware Version Format since it's convenient.  Return
2507  * 0 on success, -ENOENT if no Expansion ROM is present.
2508  */
2509 static int t4_get_exprom_version(struct adapter *adapter, u32 *vers)
2510 {
2511         struct exprom_header {
2512                 unsigned char hdr_arr[16];      /* must start with 0x55aa */
2513                 unsigned char hdr_ver[4];       /* Expansion ROM version */
2514         } *hdr;
2515         u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
2516                                            sizeof(u32))];
2517         int ret;
2518
2519         ret = t4_read_flash(adapter, FLASH_EXP_ROM_START,
2520                             ARRAY_SIZE(exprom_header_buf),
2521                             exprom_header_buf, 0);
2522         if (ret)
2523                 return ret;
2524
2525         hdr = (struct exprom_header *)exprom_header_buf;
2526         if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
2527                 return -ENOENT;
2528
2529         *vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) |
2530                  V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) |
2531                  V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) |
2532                  V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3]));
2533         return 0;
2534 }
2535
2536 /**
2537  * t4_get_fw_version - read the firmware version
2538  * @adapter: the adapter
2539  * @vers: where to place the version
2540  *
2541  * Reads the FW version from flash.
2542  */
2543 static int t4_get_fw_version(struct adapter *adapter, u32 *vers)
2544 {
2545         return t4_read_flash(adapter, FLASH_FW_START +
2546                              offsetof(struct fw_hdr, fw_ver), 1, vers, 0);
2547 }
2548
2549 /**
2550  *     t4_get_bs_version - read the firmware bootstrap version
2551  *     @adapter: the adapter
2552  *     @vers: where to place the version
2553  *
2554  *     Reads the FW Bootstrap version from flash.
2555  */
2556 static int t4_get_bs_version(struct adapter *adapter, u32 *vers)
2557 {
2558         return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
2559                              offsetof(struct fw_hdr, fw_ver), 1,
2560                              vers, 0);
2561 }
2562
2563 /**
2564  * t4_get_tp_version - read the TP microcode version
2565  * @adapter: the adapter
2566  * @vers: where to place the version
2567  *
2568  * Reads the TP microcode version from flash.
2569  */
2570 static int t4_get_tp_version(struct adapter *adapter, u32 *vers)
2571 {
2572         return t4_read_flash(adapter, FLASH_FW_START +
2573                              offsetof(struct fw_hdr, tp_microcode_ver),
2574                              1, vers, 0);
2575 }
2576
2577 /**
2578  * t4_get_version_info - extract various chip/firmware version information
2579  * @adapter: the adapter
2580  *
2581  * Reads various chip/firmware version numbers and stores them into the
2582  * adapter Adapter Parameters structure.  If any of the efforts fails
2583  * the first failure will be returned, but all of the version numbers
2584  * will be read.
2585  */
2586 int t4_get_version_info(struct adapter *adapter)
2587 {
2588         int ret = 0;
2589
2590 #define FIRST_RET(__getvinfo) \
2591         do { \
2592                 int __ret = __getvinfo; \
2593                 if (__ret && !ret) \
2594                         ret = __ret; \
2595         } while (0)
2596
2597         FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
2598         FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
2599         FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
2600         FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
2601
2602 #undef FIRST_RET
2603
2604         return ret;
2605 }
2606
2607 /**
2608  * t4_dump_version_info - dump all of the adapter configuration IDs
2609  * @adapter: the adapter
2610  *
2611  * Dumps all of the various bits of adapter configuration version/revision
2612  * IDs information.  This is typically called at some point after
2613  * t4_get_version_info() has been called.
2614  */
2615 void t4_dump_version_info(struct adapter *adapter)
2616 {
2617         /**
2618          * Device information.
2619          */
2620         dev_info(adapter, "Chelsio rev %d\n",
2621                  CHELSIO_CHIP_RELEASE(adapter->params.chip));
2622
2623         /**
2624          * Firmware Version.
2625          */
2626         if (!adapter->params.fw_vers)
2627                 dev_warn(adapter, "No firmware loaded\n");
2628         else
2629                 dev_info(adapter, "Firmware version: %u.%u.%u.%u\n",
2630                          G_FW_HDR_FW_VER_MAJOR(adapter->params.fw_vers),
2631                          G_FW_HDR_FW_VER_MINOR(adapter->params.fw_vers),
2632                          G_FW_HDR_FW_VER_MICRO(adapter->params.fw_vers),
2633                          G_FW_HDR_FW_VER_BUILD(adapter->params.fw_vers));
2634
2635         /**
2636          * Bootstrap Firmware Version.
2637          */
2638         if (!adapter->params.bs_vers)
2639                 dev_warn(adapter, "No bootstrap loaded\n");
2640         else
2641                 dev_info(adapter, "Bootstrap version: %u.%u.%u.%u\n",
2642                          G_FW_HDR_FW_VER_MAJOR(adapter->params.bs_vers),
2643                          G_FW_HDR_FW_VER_MINOR(adapter->params.bs_vers),
2644                          G_FW_HDR_FW_VER_MICRO(adapter->params.bs_vers),
2645                          G_FW_HDR_FW_VER_BUILD(adapter->params.bs_vers));
2646
2647         /**
2648          * TP Microcode Version.
2649          */
2650         if (!adapter->params.tp_vers)
2651                 dev_warn(adapter, "No TP Microcode loaded\n");
2652         else
2653                 dev_info(adapter, "TP Microcode version: %u.%u.%u.%u\n",
2654                          G_FW_HDR_FW_VER_MAJOR(adapter->params.tp_vers),
2655                          G_FW_HDR_FW_VER_MINOR(adapter->params.tp_vers),
2656                          G_FW_HDR_FW_VER_MICRO(adapter->params.tp_vers),
2657                          G_FW_HDR_FW_VER_BUILD(adapter->params.tp_vers));
2658
2659         /**
2660          * Expansion ROM version.
2661          */
2662         if (!adapter->params.er_vers)
2663                 dev_info(adapter, "No Expansion ROM loaded\n");
2664         else
2665                 dev_info(adapter, "Expansion ROM version: %u.%u.%u.%u\n",
2666                          G_FW_HDR_FW_VER_MAJOR(adapter->params.er_vers),
2667                          G_FW_HDR_FW_VER_MINOR(adapter->params.er_vers),
2668                          G_FW_HDR_FW_VER_MICRO(adapter->params.er_vers),
2669                          G_FW_HDR_FW_VER_BUILD(adapter->params.er_vers));
2670 }
2671
2672 #define ADVERT_MASK (V_FW_PORT_CAP_SPEED(M_FW_PORT_CAP_SPEED) | \
2673                      FW_PORT_CAP_ANEG)
2674
2675 /**
2676  * t4_link_l1cfg - apply link configuration to MAC/PHY
2677  * @phy: the PHY to setup
2678  * @mac: the MAC to setup
2679  * @lc: the requested link configuration
2680  *
2681  * Set up a port's MAC and PHY according to a desired link configuration.
2682  * - If the PHY can auto-negotiate first decide what to advertise, then
2683  *   enable/disable auto-negotiation as desired, and reset.
2684  * - If the PHY does not auto-negotiate just reset it.
2685  * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
2686  *   otherwise do it later based on the outcome of auto-negotiation.
2687  */
2688 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
2689                   struct link_config *lc)
2690 {
2691         struct fw_port_cmd c;
2692         unsigned int mdi = V_FW_PORT_CAP_MDI(FW_PORT_CAP_MDI_AUTO);
2693         unsigned int fc, fec;
2694
2695         lc->link_ok = 0;
2696         fc = 0;
2697         if (lc->requested_fc & PAUSE_RX)
2698                 fc |= FW_PORT_CAP_FC_RX;
2699         if (lc->requested_fc & PAUSE_TX)
2700                 fc |= FW_PORT_CAP_FC_TX;
2701
2702         fec = 0;
2703         if (lc->requested_fec & FEC_RS)
2704                 fec |= FW_PORT_CAP_FEC_RS;
2705         if (lc->requested_fec & FEC_BASER_RS)
2706                 fec |= FW_PORT_CAP_FEC_BASER_RS;
2707         if (lc->requested_fec & FEC_RESERVED)
2708                 fec |= FW_PORT_CAP_FEC_RESERVED;
2709
2710         memset(&c, 0, sizeof(c));
2711         c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
2712                                      F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
2713                                      V_FW_PORT_CMD_PORTID(port));
2714         c.action_to_len16 =
2715                 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
2716                             FW_LEN16(c));
2717
2718         if (!(lc->supported & FW_PORT_CAP_ANEG)) {
2719                 c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
2720                                              fc | fec);
2721                 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
2722                 lc->fec = lc->requested_fec;
2723         } else if (lc->autoneg == AUTONEG_DISABLE) {
2724                 c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc |
2725                                              fec | mdi);
2726                 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
2727                 lc->fec = lc->requested_fec;
2728         } else {
2729                 c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | fec | mdi);
2730         }
2731
2732         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2733 }
2734
2735 /**
2736  * t4_flash_cfg_addr - return the address of the flash configuration file
2737  * @adapter: the adapter
2738  *
2739  * Return the address within the flash where the Firmware Configuration
2740  * File is stored, or an error if the device FLASH is too small to contain
2741  * a Firmware Configuration File.
2742  */
2743 int t4_flash_cfg_addr(struct adapter *adapter)
2744 {
2745         /*
2746          * If the device FLASH isn't large enough to hold a Firmware
2747          * Configuration File, return an error.
2748          */
2749         if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE)
2750                 return -ENOSPC;
2751
2752         return FLASH_CFG_START;
2753 }
2754
2755 #define PF_INTR_MASK (F_PFSW | F_PFCIM)
2756
2757 /**
2758  * t4_intr_enable - enable interrupts
2759  * @adapter: the adapter whose interrupts should be enabled
2760  *
2761  * Enable PF-specific interrupts for the calling function and the top-level
2762  * interrupt concentrator for global interrupts.  Interrupts are already
2763  * enabled at each module, here we just enable the roots of the interrupt
2764  * hierarchies.
2765  *
2766  * Note: this function should be called only when the driver manages
2767  * non PF-specific interrupts from the various HW modules.  Only one PCI
2768  * function at a time should be doing this.
2769  */
2770 void t4_intr_enable(struct adapter *adapter)
2771 {
2772         u32 val = 0;
2773         u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
2774         u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
2775                  G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
2776
2777         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
2778                 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT;
2779         t4_write_reg(adapter, A_SGE_INT_ENABLE3, F_ERR_CPL_EXCEED_IQE_SIZE |
2780                      F_ERR_INVALID_CIDX_INC | F_ERR_CPL_OPCODE_0 |
2781                      F_ERR_DATA_CPL_ON_HIGH_QID1 | F_INGRESS_SIZE_ERR |
2782                      F_ERR_DATA_CPL_ON_HIGH_QID0 | F_ERR_BAD_DB_PIDX3 |
2783                      F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
2784                      F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO |
2785                      F_DBFIFO_LP_INT | F_EGRESS_SIZE_ERR | val);
2786         t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK);
2787         t4_set_reg_field(adapter, A_PL_INT_MAP0, 0, 1 << pf);
2788 }
2789
2790 /**
2791  * t4_intr_disable - disable interrupts
2792  * @adapter: the adapter whose interrupts should be disabled
2793  *
2794  * Disable interrupts.  We only disable the top-level interrupt
2795  * concentrators.  The caller must be a PCI function managing global
2796  * interrupts.
2797  */
2798 void t4_intr_disable(struct adapter *adapter)
2799 {
2800         u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
2801         u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
2802                  G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
2803
2804         t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), 0);
2805         t4_set_reg_field(adapter, A_PL_INT_MAP0, 1 << pf, 0);
2806 }
2807
2808 /**
2809  * t4_get_port_type_description - return Port Type string description
2810  * @port_type: firmware Port Type enumeration
2811  */
2812 const char *t4_get_port_type_description(enum fw_port_type port_type)
2813 {
2814         static const char * const port_type_description[] = {
2815                 "Fiber_XFI",
2816                 "Fiber_XAUI",
2817                 "BT_SGMII",
2818                 "BT_XFI",
2819                 "BT_XAUI",
2820                 "KX4",
2821                 "CX4",
2822                 "KX",
2823                 "KR",
2824                 "SFP",
2825                 "BP_AP",
2826                 "BP4_AP",
2827                 "QSFP_10G",
2828                 "QSA",
2829                 "QSFP",
2830                 "BP40_BA",
2831                 "KR4_100G",
2832                 "CR4_QSFP",
2833                 "CR_QSFP",
2834                 "CR2_QSFP",
2835                 "SFP28",
2836                 "KR_SFP28",
2837         };
2838
2839         if (port_type < ARRAY_SIZE(port_type_description))
2840                 return port_type_description[port_type];
2841         return "UNKNOWN";
2842 }
2843
2844 /**
2845  * t4_get_mps_bg_map - return the buffer groups associated with a port
2846  * @adap: the adapter
2847  * @pidx: the port index
2848  *
2849  * Returns a bitmap indicating which MPS buffer groups are associated
2850  * with the given port.  Bit i is set if buffer group i is used by the
2851  * port.
2852  */
2853 unsigned int t4_get_mps_bg_map(struct adapter *adap, unsigned int pidx)
2854 {
2855         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2856         unsigned int nports = 1 << G_NUMPORTS(t4_read_reg(adap,
2857                                                           A_MPS_CMN_CTL));
2858
2859         if (pidx >= nports) {
2860                 dev_warn(adap, "MPS Port Index %d >= Nports %d\n",
2861                          pidx, nports);
2862                 return 0;
2863         }
2864
2865         switch (chip_version) {
2866         case CHELSIO_T4:
2867         case CHELSIO_T5:
2868                 switch (nports) {
2869                 case 1: return 0xf;
2870                 case 2: return 3 << (2 * pidx);
2871                 case 4: return 1 << pidx;
2872                 }
2873                 break;
2874
2875         case CHELSIO_T6:
2876                 switch (nports) {
2877                 case 2: return 1 << (2 * pidx);
2878                 }
2879                 break;
2880         }
2881
2882         dev_err(adap, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
2883                 chip_version, nports);
2884         return 0;
2885 }
2886
2887 /**
2888  * t4_get_tp_ch_map - return TP ingress channels associated with a port
2889  * @adapter: the adapter
2890  * @pidx: the port index
2891  *
2892  * Returns a bitmap indicating which TP Ingress Channels are associated with
2893  * a given Port.  Bit i is set if TP Ingress Channel i is used by the Port.
2894  */
2895 unsigned int t4_get_tp_ch_map(struct adapter *adapter, unsigned int pidx)
2896 {
2897         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
2898         unsigned int nports = 1 << G_NUMPORTS(t4_read_reg(adapter,
2899                                                           A_MPS_CMN_CTL));
2900
2901         if (pidx >= nports) {
2902                 dev_warn(adap, "TP Port Index %d >= Nports %d\n",
2903                          pidx, nports);
2904                 return 0;
2905         }
2906
2907         switch (chip_version) {
2908         case CHELSIO_T4:
2909         case CHELSIO_T5:
2910                 /* Note that this happens to be the same values as the MPS
2911                  * Buffer Group Map for these Chips.  But we replicate the code
2912                  * here because they're really separate concepts.
2913                  */
2914                 switch (nports) {
2915                 case 1: return 0xf;
2916                 case 2: return 3 << (2 * pidx);
2917                 case 4: return 1 << pidx;
2918                 }
2919                 break;
2920
2921         case CHELSIO_T6:
2922                 switch (nports) {
2923                 case 2: return 1 << pidx;
2924                 }
2925                 break;
2926         }
2927
2928         dev_err(adapter, "Need TP Channel Map for Chip %0x, Nports %d\n",
2929                 chip_version, nports);
2930         return 0;
2931 }
2932
2933 /**
2934  * t4_get_port_stats - collect port statistics
2935  * @adap: the adapter
2936  * @idx: the port index
2937  * @p: the stats structure to fill
2938  *
2939  * Collect statistics related to the given port from HW.
2940  */
2941 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
2942 {
2943         u32 bgmap = t4_get_mps_bg_map(adap, idx);
2944         u32 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL);
2945
2946 #define GET_STAT(name) \
2947         t4_read_reg64(adap, \
2948                       (is_t4(adap->params.chip) ? \
2949                        PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) :\
2950                        T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L)))
2951 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
2952
2953         p->tx_octets           = GET_STAT(TX_PORT_BYTES);
2954         p->tx_frames           = GET_STAT(TX_PORT_FRAMES);
2955         p->tx_bcast_frames     = GET_STAT(TX_PORT_BCAST);
2956         p->tx_mcast_frames     = GET_STAT(TX_PORT_MCAST);
2957         p->tx_ucast_frames     = GET_STAT(TX_PORT_UCAST);
2958         p->tx_error_frames     = GET_STAT(TX_PORT_ERROR);
2959         p->tx_frames_64        = GET_STAT(TX_PORT_64B);
2960         p->tx_frames_65_127    = GET_STAT(TX_PORT_65B_127B);
2961         p->tx_frames_128_255   = GET_STAT(TX_PORT_128B_255B);
2962         p->tx_frames_256_511   = GET_STAT(TX_PORT_256B_511B);
2963         p->tx_frames_512_1023  = GET_STAT(TX_PORT_512B_1023B);
2964         p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
2965         p->tx_frames_1519_max  = GET_STAT(TX_PORT_1519B_MAX);
2966         p->tx_drop             = GET_STAT(TX_PORT_DROP);
2967         p->tx_pause            = GET_STAT(TX_PORT_PAUSE);
2968         p->tx_ppp0             = GET_STAT(TX_PORT_PPP0);
2969         p->tx_ppp1             = GET_STAT(TX_PORT_PPP1);
2970         p->tx_ppp2             = GET_STAT(TX_PORT_PPP2);
2971         p->tx_ppp3             = GET_STAT(TX_PORT_PPP3);
2972         p->tx_ppp4             = GET_STAT(TX_PORT_PPP4);
2973         p->tx_ppp5             = GET_STAT(TX_PORT_PPP5);
2974         p->tx_ppp6             = GET_STAT(TX_PORT_PPP6);
2975         p->tx_ppp7             = GET_STAT(TX_PORT_PPP7);
2976
2977         if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
2978                 if (stat_ctl & F_COUNTPAUSESTATTX) {
2979                         p->tx_frames -= p->tx_pause;
2980                         p->tx_octets -= p->tx_pause * 64;
2981                 }
2982                 if (stat_ctl & F_COUNTPAUSEMCTX)
2983                         p->tx_mcast_frames -= p->tx_pause;
2984         }
2985
2986         p->rx_octets           = GET_STAT(RX_PORT_BYTES);
2987         p->rx_frames           = GET_STAT(RX_PORT_FRAMES);
2988         p->rx_bcast_frames     = GET_STAT(RX_PORT_BCAST);
2989         p->rx_mcast_frames     = GET_STAT(RX_PORT_MCAST);
2990         p->rx_ucast_frames     = GET_STAT(RX_PORT_UCAST);
2991         p->rx_too_long         = GET_STAT(RX_PORT_MTU_ERROR);
2992         p->rx_jabber           = GET_STAT(RX_PORT_MTU_CRC_ERROR);
2993         p->rx_fcs_err          = GET_STAT(RX_PORT_CRC_ERROR);
2994         p->rx_len_err          = GET_STAT(RX_PORT_LEN_ERROR);
2995         p->rx_symbol_err       = GET_STAT(RX_PORT_SYM_ERROR);
2996         p->rx_runt             = GET_STAT(RX_PORT_LESS_64B);
2997         p->rx_frames_64        = GET_STAT(RX_PORT_64B);
2998         p->rx_frames_65_127    = GET_STAT(RX_PORT_65B_127B);
2999         p->rx_frames_128_255   = GET_STAT(RX_PORT_128B_255B);
3000         p->rx_frames_256_511   = GET_STAT(RX_PORT_256B_511B);
3001         p->rx_frames_512_1023  = GET_STAT(RX_PORT_512B_1023B);
3002         p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
3003         p->rx_frames_1519_max  = GET_STAT(RX_PORT_1519B_MAX);
3004         p->rx_pause            = GET_STAT(RX_PORT_PAUSE);
3005         p->rx_ppp0             = GET_STAT(RX_PORT_PPP0);
3006         p->rx_ppp1             = GET_STAT(RX_PORT_PPP1);
3007         p->rx_ppp2             = GET_STAT(RX_PORT_PPP2);
3008         p->rx_ppp3             = GET_STAT(RX_PORT_PPP3);
3009         p->rx_ppp4             = GET_STAT(RX_PORT_PPP4);
3010         p->rx_ppp5             = GET_STAT(RX_PORT_PPP5);
3011         p->rx_ppp6             = GET_STAT(RX_PORT_PPP6);
3012         p->rx_ppp7             = GET_STAT(RX_PORT_PPP7);
3013
3014         if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
3015                 if (stat_ctl & F_COUNTPAUSESTATRX) {
3016                         p->rx_frames -= p->rx_pause;
3017                         p->rx_octets -= p->rx_pause * 64;
3018                 }
3019                 if (stat_ctl & F_COUNTPAUSEMCRX)
3020                         p->rx_mcast_frames -= p->rx_pause;
3021         }
3022
3023         p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
3024         p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
3025         p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
3026         p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
3027         p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
3028         p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
3029         p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
3030         p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
3031
3032 #undef GET_STAT
3033 #undef GET_STAT_COM
3034 }
3035
3036 /**
3037  * t4_get_port_stats_offset - collect port stats relative to a previous snapshot
3038  * @adap: The adapter
3039  * @idx: The port
3040  * @stats: Current stats to fill
3041  * @offset: Previous stats snapshot
3042  */
3043 void t4_get_port_stats_offset(struct adapter *adap, int idx,
3044                               struct port_stats *stats,
3045                               struct port_stats *offset)
3046 {
3047         u64 *s, *o;
3048         unsigned int i;
3049
3050         t4_get_port_stats(adap, idx, stats);
3051         for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
3052              i < (sizeof(struct port_stats) / sizeof(u64));
3053              i++, s++, o++)
3054                 *s -= *o;
3055 }
3056
3057 /**
3058  * t4_clr_port_stats - clear port statistics
3059  * @adap: the adapter
3060  * @idx: the port index
3061  *
3062  * Clear HW statistics for the given port.
3063  */
3064 void t4_clr_port_stats(struct adapter *adap, int idx)
3065 {
3066         unsigned int i;
3067         u32 bgmap = t4_get_mps_bg_map(adap, idx);
3068         u32 port_base_addr;
3069
3070         if (is_t4(adap->params.chip))
3071                 port_base_addr = PORT_BASE(idx);
3072         else
3073                 port_base_addr = T5_PORT_BASE(idx);
3074
3075         for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L;
3076              i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8)
3077                 t4_write_reg(adap, port_base_addr + i, 0);
3078         for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L;
3079              i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8)
3080                 t4_write_reg(adap, port_base_addr + i, 0);
3081         for (i = 0; i < 4; i++)
3082                 if (bgmap & (1 << i)) {
3083                         t4_write_reg(adap,
3084                                      A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L +
3085                                      i * 8, 0);
3086                         t4_write_reg(adap,
3087                                      A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L +
3088                                      i * 8, 0);
3089                 }
3090 }
3091
3092 /**
3093  * t4_fw_hello - establish communication with FW
3094  * @adap: the adapter
3095  * @mbox: mailbox to use for the FW command
3096  * @evt_mbox: mailbox to receive async FW events
3097  * @master: specifies the caller's willingness to be the device master
3098  * @state: returns the current device state (if non-NULL)
3099  *
3100  * Issues a command to establish communication with FW.  Returns either
3101  * an error (negative integer) or the mailbox of the Master PF.
3102  */
3103 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
3104                 enum dev_master master, enum dev_state *state)
3105 {
3106         int ret;
3107         struct fw_hello_cmd c;
3108         u32 v;
3109         unsigned int master_mbox;
3110         int retries = FW_CMD_HELLO_RETRIES;
3111
3112 retry:
3113         memset(&c, 0, sizeof(c));
3114         INIT_CMD(c, HELLO, WRITE);
3115         c.err_to_clearinit = cpu_to_be32(
3116                         V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
3117                         V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
3118                         V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? mbox :
3119                                                 M_FW_HELLO_CMD_MBMASTER) |
3120                         V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
3121                         V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) |
3122                         F_FW_HELLO_CMD_CLEARINIT);
3123
3124         /*
3125          * Issue the HELLO command to the firmware.  If it's not successful
3126          * but indicates that we got a "busy" or "timeout" condition, retry
3127          * the HELLO until we exhaust our retry limit.  If we do exceed our
3128          * retry limit, check to see if the firmware left us any error
3129          * information and report that if so ...
3130          */
3131         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3132         if (ret != FW_SUCCESS) {
3133                 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
3134                         goto retry;
3135                 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR)
3136                         t4_report_fw_error(adap);
3137                 return ret;
3138         }
3139
3140         v = be32_to_cpu(c.err_to_clearinit);
3141         master_mbox = G_FW_HELLO_CMD_MBMASTER(v);
3142         if (state) {
3143                 if (v & F_FW_HELLO_CMD_ERR)
3144                         *state = DEV_STATE_ERR;
3145                 else if (v & F_FW_HELLO_CMD_INIT)
3146                         *state = DEV_STATE_INIT;
3147                 else
3148                         *state = DEV_STATE_UNINIT;
3149         }
3150
3151         /*
3152          * If we're not the Master PF then we need to wait around for the
3153          * Master PF Driver to finish setting up the adapter.
3154          *
3155          * Note that we also do this wait if we're a non-Master-capable PF and
3156          * there is no current Master PF; a Master PF may show up momentarily
3157          * and we wouldn't want to fail pointlessly.  (This can happen when an
3158          * OS loads lots of different drivers rapidly at the same time).  In
3159          * this case, the Master PF returned by the firmware will be
3160          * M_PCIE_FW_MASTER so the test below will work ...
3161          */
3162         if ((v & (F_FW_HELLO_CMD_ERR | F_FW_HELLO_CMD_INIT)) == 0 &&
3163             master_mbox != mbox) {
3164                 int waiting = FW_CMD_HELLO_TIMEOUT;
3165
3166                 /*
3167                  * Wait for the firmware to either indicate an error or
3168                  * initialized state.  If we see either of these we bail out
3169                  * and report the issue to the caller.  If we exhaust the
3170                  * "hello timeout" and we haven't exhausted our retries, try
3171                  * again.  Otherwise bail with a timeout error.
3172                  */
3173                 for (;;) {
3174                         u32 pcie_fw;
3175
3176                         msleep(50);
3177                         waiting -= 50;
3178
3179                         /*
3180                          * If neither Error nor Initialialized are indicated
3181                          * by the firmware keep waiting till we exaust our
3182                          * timeout ... and then retry if we haven't exhausted
3183                          * our retries ...
3184                          */
3185                         pcie_fw = t4_read_reg(adap, A_PCIE_FW);
3186                         if (!(pcie_fw & (F_PCIE_FW_ERR | F_PCIE_FW_INIT))) {
3187                                 if (waiting <= 0) {
3188                                         if (retries-- > 0)
3189                                                 goto retry;
3190
3191                                         return -ETIMEDOUT;
3192                                 }
3193                                 continue;
3194                         }
3195
3196                         /*
3197                          * We either have an Error or Initialized condition
3198                          * report errors preferentially.
3199                          */
3200                         if (state) {
3201                                 if (pcie_fw & F_PCIE_FW_ERR)
3202                                         *state = DEV_STATE_ERR;
3203                                 else if (pcie_fw & F_PCIE_FW_INIT)
3204                                         *state = DEV_STATE_INIT;
3205                         }
3206
3207                         /*
3208                          * If we arrived before a Master PF was selected and
3209                          * there's not a valid Master PF, grab its identity
3210                          * for our caller.
3211                          */
3212                         if (master_mbox == M_PCIE_FW_MASTER &&
3213                             (pcie_fw & F_PCIE_FW_MASTER_VLD))
3214                                 master_mbox = G_PCIE_FW_MASTER(pcie_fw);
3215                         break;
3216                 }
3217         }
3218
3219         return master_mbox;
3220 }
3221
3222 /**
3223  * t4_fw_bye - end communication with FW
3224  * @adap: the adapter
3225  * @mbox: mailbox to use for the FW command
3226  *
3227  * Issues a command to terminate communication with FW.
3228  */
3229 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
3230 {
3231         struct fw_bye_cmd c;
3232
3233         memset(&c, 0, sizeof(c));
3234         INIT_CMD(c, BYE, WRITE);
3235         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3236 }
3237
3238 /**
3239  * t4_fw_reset - issue a reset to FW
3240  * @adap: the adapter
3241  * @mbox: mailbox to use for the FW command
3242  * @reset: specifies the type of reset to perform
3243  *
3244  * Issues a reset command of the specified type to FW.
3245  */
3246 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
3247 {
3248         struct fw_reset_cmd c;
3249
3250         memset(&c, 0, sizeof(c));
3251         INIT_CMD(c, RESET, WRITE);
3252         c.val = cpu_to_be32(reset);
3253         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3254 }
3255
3256 /**
3257  * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
3258  * @adap: the adapter
3259  * @mbox: mailbox to use for the FW RESET command (if desired)
3260  * @force: force uP into RESET even if FW RESET command fails
3261  *
3262  * Issues a RESET command to firmware (if desired) with a HALT indication
3263  * and then puts the microprocessor into RESET state.  The RESET command
3264  * will only be issued if a legitimate mailbox is provided (mbox <=
3265  * M_PCIE_FW_MASTER).
3266  *
3267  * This is generally used in order for the host to safely manipulate the
3268  * adapter without fear of conflicting with whatever the firmware might
3269  * be doing.  The only way out of this state is to RESTART the firmware
3270  * ...
3271  */
3272 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
3273 {
3274         int ret = 0;
3275
3276         /*
3277          * If a legitimate mailbox is provided, issue a RESET command
3278          * with a HALT indication.
3279          */
3280         if (mbox <= M_PCIE_FW_MASTER) {
3281                 struct fw_reset_cmd c;
3282
3283                 memset(&c, 0, sizeof(c));
3284                 INIT_CMD(c, RESET, WRITE);
3285                 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE);
3286                 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT);
3287                 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3288         }
3289
3290         /*
3291          * Normally we won't complete the operation if the firmware RESET
3292          * command fails but if our caller insists we'll go ahead and put the
3293          * uP into RESET.  This can be useful if the firmware is hung or even
3294          * missing ...  We'll have to take the risk of putting the uP into
3295          * RESET without the cooperation of firmware in that case.
3296          *
3297          * We also force the firmware's HALT flag to be on in case we bypassed
3298          * the firmware RESET command above or we're dealing with old firmware
3299          * which doesn't have the HALT capability.  This will serve as a flag
3300          * for the incoming firmware to know that it's coming out of a HALT
3301          * rather than a RESET ... if it's new enough to understand that ...
3302          */
3303         if (ret == 0 || force) {
3304                 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST);
3305                 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT,
3306                                  F_PCIE_FW_HALT);
3307         }
3308
3309         /*
3310          * And we always return the result of the firmware RESET command
3311          * even when we force the uP into RESET ...
3312          */
3313         return ret;
3314 }
3315
3316 /**
3317  * t4_fw_restart - restart the firmware by taking the uP out of RESET
3318  * @adap: the adapter
3319  * @mbox: mailbox to use for the FW RESET command (if desired)
3320  * @reset: if we want to do a RESET to restart things
3321  *
3322  * Restart firmware previously halted by t4_fw_halt().  On successful
3323  * return the previous PF Master remains as the new PF Master and there
3324  * is no need to issue a new HELLO command, etc.
3325  *
3326  * We do this in two ways:
3327  *
3328  * 1. If we're dealing with newer firmware we'll simply want to take
3329  *    the chip's microprocessor out of RESET.  This will cause the
3330  *    firmware to start up from its start vector.  And then we'll loop
3331  *    until the firmware indicates it's started again (PCIE_FW.HALT
3332  *    reset to 0) or we timeout.
3333  *
3334  * 2. If we're dealing with older firmware then we'll need to RESET
3335  *    the chip since older firmware won't recognize the PCIE_FW.HALT
3336  *    flag and automatically RESET itself on startup.
3337  */
3338 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
3339 {
3340         if (reset) {
3341                 /*
3342                  * Since we're directing the RESET instead of the firmware
3343                  * doing it automatically, we need to clear the PCIE_FW.HALT
3344                  * bit.
3345                  */
3346                 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 0);
3347
3348                 /*
3349                  * If we've been given a valid mailbox, first try to get the
3350                  * firmware to do the RESET.  If that works, great and we can
3351                  * return success.  Otherwise, if we haven't been given a
3352                  * valid mailbox or the RESET command failed, fall back to
3353                  * hitting the chip with a hammer.
3354                  */
3355                 if (mbox <= M_PCIE_FW_MASTER) {
3356                         t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
3357                         msleep(100);
3358                         if (t4_fw_reset(adap, mbox,
3359                                         F_PIORST | F_PIORSTMODE) == 0)
3360                                 return 0;
3361                 }
3362
3363                 t4_write_reg(adap, A_PL_RST, F_PIORST | F_PIORSTMODE);
3364                 msleep(2000);
3365         } else {
3366                 int ms;
3367
3368                 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
3369                 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
3370                         if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT))
3371                                 return FW_SUCCESS;
3372                         msleep(100);
3373                         ms += 100;
3374                 }
3375                 return -ETIMEDOUT;
3376         }
3377         return 0;
3378 }
3379
3380 /**
3381  * t4_fl_pkt_align - return the fl packet alignment
3382  * @adap: the adapter
3383  *
3384  * T4 has a single field to specify the packing and padding boundary.
3385  * T5 onwards has separate fields for this and hence the alignment for
3386  * next packet offset is maximum of these two.
3387  */
3388 int t4_fl_pkt_align(struct adapter *adap)
3389 {
3390         u32 sge_control, sge_control2;
3391         unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
3392
3393         sge_control = t4_read_reg(adap, A_SGE_CONTROL);
3394
3395         /* T4 uses a single control field to specify both the PCIe Padding and
3396          * Packing Boundary.  T5 introduced the ability to specify these
3397          * separately.  The actual Ingress Packet Data alignment boundary
3398          * within Packed Buffer Mode is the maximum of these two
3399          * specifications.
3400          */
3401         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
3402                 ingpad_shift = X_INGPADBOUNDARY_SHIFT;
3403         else
3404                 ingpad_shift = X_T6_INGPADBOUNDARY_SHIFT;
3405
3406         ingpadboundary = 1 << (G_INGPADBOUNDARY(sge_control) + ingpad_shift);
3407
3408         fl_align = ingpadboundary;
3409         if (!is_t4(adap->params.chip)) {
3410                 sge_control2 = t4_read_reg(adap, A_SGE_CONTROL2);
3411                 ingpackboundary = G_INGPACKBOUNDARY(sge_control2);
3412                 if (ingpackboundary == X_INGPACKBOUNDARY_16B)
3413                         ingpackboundary = 16;
3414                 else
3415                         ingpackboundary = 1 << (ingpackboundary +
3416                                         X_INGPACKBOUNDARY_SHIFT);
3417
3418                 fl_align = max(ingpadboundary, ingpackboundary);
3419         }
3420         return fl_align;
3421 }
3422
3423 /**
3424  * t4_fixup_host_params_compat - fix up host-dependent parameters
3425  * @adap: the adapter
3426  * @page_size: the host's Base Page Size
3427  * @cache_line_size: the host's Cache Line Size
3428  * @chip_compat: maintain compatibility with designated chip
3429  *
3430  * Various registers in the chip contain values which are dependent on the
3431  * host's Base Page and Cache Line Sizes.  This function will fix all of
3432  * those registers with the appropriate values as passed in ...
3433  *
3434  * @chip_compat is used to limit the set of changes that are made
3435  * to be compatible with the indicated chip release.  This is used by
3436  * drivers to maintain compatibility with chip register settings when
3437  * the drivers haven't [yet] been updated with new chip support.
3438  */
3439 int t4_fixup_host_params_compat(struct adapter *adap,
3440                                 unsigned int page_size,
3441                                 unsigned int cache_line_size,
3442                                 enum chip_type chip_compat)
3443 {
3444         unsigned int page_shift = cxgbe_fls(page_size) - 1;
3445         unsigned int sge_hps = page_shift - 10;
3446         unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
3447         unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
3448         unsigned int fl_align_log = cxgbe_fls(fl_align) - 1;
3449
3450         t4_write_reg(adap, A_SGE_HOST_PAGE_SIZE,
3451                      V_HOSTPAGESIZEPF0(sge_hps) |
3452                      V_HOSTPAGESIZEPF1(sge_hps) |
3453                      V_HOSTPAGESIZEPF2(sge_hps) |
3454                      V_HOSTPAGESIZEPF3(sge_hps) |
3455                      V_HOSTPAGESIZEPF4(sge_hps) |
3456                      V_HOSTPAGESIZEPF5(sge_hps) |
3457                      V_HOSTPAGESIZEPF6(sge_hps) |
3458                      V_HOSTPAGESIZEPF7(sge_hps));
3459
3460         if (is_t4(adap->params.chip) || is_t4(chip_compat))
3461                 t4_set_reg_field(adap, A_SGE_CONTROL,
3462                                  V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
3463                                  F_EGRSTATUSPAGESIZE,
3464                                  V_INGPADBOUNDARY(fl_align_log -
3465                                                   X_INGPADBOUNDARY_SHIFT) |
3466                                 V_EGRSTATUSPAGESIZE(stat_len != 64));
3467         else {
3468                 unsigned int pack_align;
3469                 unsigned int ingpad, ingpack;
3470                 unsigned int pcie_cap;
3471
3472                 /*
3473                  * T5 introduced the separation of the Free List Padding and
3474                  * Packing Boundaries.  Thus, we can select a smaller Padding
3475                  * Boundary to avoid uselessly chewing up PCIe Link and Memory
3476                  * Bandwidth, and use a Packing Boundary which is large enough
3477                  * to avoid false sharing between CPUs, etc.
3478                  *
3479                  * For the PCI Link, the smaller the Padding Boundary the
3480                  * better.  For the Memory Controller, a smaller Padding
3481                  * Boundary is better until we cross under the Memory Line
3482                  * Size (the minimum unit of transfer to/from Memory).  If we
3483                  * have a Padding Boundary which is smaller than the Memory
3484                  * Line Size, that'll involve a Read-Modify-Write cycle on the
3485                  * Memory Controller which is never good.
3486                  */
3487
3488                 /* We want the Packing Boundary to be based on the Cache Line
3489                  * Size in order to help avoid False Sharing performance
3490                  * issues between CPUs, etc.  We also want the Packing
3491                  * Boundary to incorporate the PCI-E Maximum Payload Size.  We
3492                  * get best performance when the Packing Boundary is a
3493                  * multiple of the Maximum Payload Size.
3494                  */
3495                 pack_align = fl_align;
3496                 pcie_cap = t4_os_find_pci_capability(adap, PCI_CAP_ID_EXP);
3497                 if (pcie_cap) {
3498                         unsigned int mps, mps_log;
3499                         u16 devctl;
3500
3501                         /* The PCIe Device Control Maximum Payload Size field
3502                          * [bits 7:5] encodes sizes as powers of 2 starting at
3503                          * 128 bytes.
3504                          */
3505                         t4_os_pci_read_cfg2(adap, pcie_cap + PCI_EXP_DEVCTL,
3506                                             &devctl);
3507                         mps_log = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5) + 7;
3508                         mps = 1 << mps_log;
3509                         if (mps > pack_align)
3510                                 pack_align = mps;
3511                 }
3512
3513                 /*
3514                  * N.B. T5 has a different interpretation of the "0" value for
3515                  * the Packing Boundary.  This corresponds to 16 bytes instead
3516                  * of the expected 32 bytes.  We never have a Packing Boundary
3517                  * less than 32 bytes so we can't use that special value but
3518                  * on the other hand, if we wanted 32 bytes, the best we can
3519                  * really do is 64 bytes ...
3520                  */
3521                 if (pack_align <= 16) {
3522                         ingpack = X_INGPACKBOUNDARY_16B;
3523                         fl_align = 16;
3524                 } else if (pack_align == 32) {
3525                         ingpack = X_INGPACKBOUNDARY_64B;
3526                         fl_align = 64;
3527                 } else {
3528                         unsigned int pack_align_log = cxgbe_fls(pack_align) - 1;
3529
3530                         ingpack = pack_align_log - X_INGPACKBOUNDARY_SHIFT;
3531                         fl_align = pack_align;
3532                 }
3533
3534                 /* Use the smallest Ingress Padding which isn't smaller than
3535                  * the Memory Controller Read/Write Size.  We'll take that as
3536                  * being 8 bytes since we don't know of any system with a
3537                  * wider Memory Controller Bus Width.
3538                  */
3539                 if (is_t5(adap->params.chip))
3540                         ingpad = X_INGPADBOUNDARY_32B;
3541                 else
3542                         ingpad = X_T6_INGPADBOUNDARY_8B;
3543                 t4_set_reg_field(adap, A_SGE_CONTROL,
3544                                  V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
3545                                  F_EGRSTATUSPAGESIZE,
3546                                  V_INGPADBOUNDARY(ingpad) |
3547                                  V_EGRSTATUSPAGESIZE(stat_len != 64));
3548                 t4_set_reg_field(adap, A_SGE_CONTROL2,
3549                                  V_INGPACKBOUNDARY(M_INGPACKBOUNDARY),
3550                                  V_INGPACKBOUNDARY(ingpack));
3551         }
3552
3553         /*
3554          * Adjust various SGE Free List Host Buffer Sizes.
3555          *
3556          * The first four entries are:
3557          *
3558          *   0: Host Page Size
3559          *   1: 64KB
3560          *   2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
3561          *   3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
3562          *
3563          * For the single-MTU buffers in unpacked mode we need to include
3564          * space for the SGE Control Packet Shift, 14 byte Ethernet header,
3565          * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
3566          * Padding boundary.  All of these are accommodated in the Factory
3567          * Default Firmware Configuration File but we need to adjust it for
3568          * this host's cache line size.
3569          */
3570         t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE0, page_size);
3571         t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE2,
3572                      (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE2) + fl_align - 1)
3573                      & ~(fl_align - 1));
3574         t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE3,
3575                      (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE3) + fl_align - 1)
3576                      & ~(fl_align - 1));
3577
3578         t4_write_reg(adap, A_ULP_RX_TDDP_PSZ, V_HPZ0(page_shift - 12));
3579
3580         return 0;
3581 }
3582
3583 /**
3584  * t4_fixup_host_params - fix up host-dependent parameters (T4 compatible)
3585  * @adap: the adapter
3586  * @page_size: the host's Base Page Size
3587  * @cache_line_size: the host's Cache Line Size
3588  *
3589  * Various registers in T4 contain values which are dependent on the
3590  * host's Base Page and Cache Line Sizes.  This function will fix all of
3591  * those registers with the appropriate values as passed in ...
3592  *
3593  * This routine makes changes which are compatible with T4 chips.
3594  */
3595 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
3596                          unsigned int cache_line_size)
3597 {
3598         return t4_fixup_host_params_compat(adap, page_size, cache_line_size,
3599                                            T4_LAST_REV);
3600 }
3601
3602 /**
3603  * t4_fw_initialize - ask FW to initialize the device
3604  * @adap: the adapter
3605  * @mbox: mailbox to use for the FW command
3606  *
3607  * Issues a command to FW to partially initialize the device.  This
3608  * performs initialization that generally doesn't depend on user input.
3609  */
3610 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
3611 {
3612         struct fw_initialize_cmd c;
3613
3614         memset(&c, 0, sizeof(c));
3615         INIT_CMD(c, INITIALIZE, WRITE);
3616         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3617 }
3618
3619 /**
3620  * t4_query_params_rw - query FW or device parameters
3621  * @adap: the adapter
3622  * @mbox: mailbox to use for the FW command
3623  * @pf: the PF
3624  * @vf: the VF
3625  * @nparams: the number of parameters
3626  * @params: the parameter names
3627  * @val: the parameter values
3628  * @rw: Write and read flag
3629  *
3630  * Reads the value of FW or device parameters.  Up to 7 parameters can be
3631  * queried at once.
3632  */
3633 static int t4_query_params_rw(struct adapter *adap, unsigned int mbox,
3634                               unsigned int pf, unsigned int vf,
3635                               unsigned int nparams, const u32 *params,
3636                               u32 *val, int rw)
3637 {
3638         unsigned int i;
3639         int ret;
3640         struct fw_params_cmd c;
3641         __be32 *p = &c.param[0].mnem;
3642
3643         if (nparams > 7)
3644                 return -EINVAL;
3645
3646         memset(&c, 0, sizeof(c));
3647         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3648                                   F_FW_CMD_REQUEST | F_FW_CMD_READ |
3649                                   V_FW_PARAMS_CMD_PFN(pf) |
3650                                   V_FW_PARAMS_CMD_VFN(vf));
3651         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3652
3653         for (i = 0; i < nparams; i++) {
3654                 *p++ = cpu_to_be32(*params++);
3655                 if (rw)
3656                         *p = cpu_to_be32(*(val + i));
3657                 p++;
3658         }
3659
3660         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3661         if (ret == 0)
3662                 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
3663                         *val++ = be32_to_cpu(*p);
3664         return ret;
3665 }
3666
3667 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3668                     unsigned int vf, unsigned int nparams, const u32 *params,
3669                     u32 *val)
3670 {
3671         return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
3672 }
3673
3674 /**
3675  * t4_set_params_timeout - sets FW or device parameters
3676  * @adap: the adapter
3677  * @mbox: mailbox to use for the FW command
3678  * @pf: the PF
3679  * @vf: the VF
3680  * @nparams: the number of parameters
3681  * @params: the parameter names
3682  * @val: the parameter values
3683  * @timeout: the timeout time
3684  *
3685  * Sets the value of FW or device parameters.  Up to 7 parameters can be
3686  * specified at once.
3687  */
3688 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
3689                           unsigned int pf, unsigned int vf,
3690                           unsigned int nparams, const u32 *params,
3691                           const u32 *val, int timeout)
3692 {
3693         struct fw_params_cmd c;
3694         __be32 *p = &c.param[0].mnem;
3695
3696         if (nparams > 7)
3697                 return -EINVAL;
3698
3699         memset(&c, 0, sizeof(c));
3700         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3701                                   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3702                                   V_FW_PARAMS_CMD_PFN(pf) |
3703                                   V_FW_PARAMS_CMD_VFN(vf));
3704         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3705
3706         while (nparams--) {
3707                 *p++ = cpu_to_be32(*params++);
3708                 *p++ = cpu_to_be32(*val++);
3709         }
3710
3711         return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
3712 }
3713
3714 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3715                   unsigned int vf, unsigned int nparams, const u32 *params,
3716                   const u32 *val)
3717 {
3718         return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
3719                                      FW_CMD_MAX_TIMEOUT);
3720 }
3721
3722 /**
3723  * t4_alloc_vi_func - allocate a virtual interface
3724  * @adap: the adapter
3725  * @mbox: mailbox to use for the FW command
3726  * @port: physical port associated with the VI
3727  * @pf: the PF owning the VI
3728  * @vf: the VF owning the VI
3729  * @nmac: number of MAC addresses needed (1 to 5)
3730  * @mac: the MAC addresses of the VI
3731  * @rss_size: size of RSS table slice associated with this VI
3732  * @portfunc: which Port Application Function MAC Address is desired
3733  * @idstype: Intrusion Detection Type
3734  *
3735  * Allocates a virtual interface for the given physical port.  If @mac is
3736  * not %NULL it contains the MAC addresses of the VI as assigned by FW.
3737  * @mac should be large enough to hold @nmac Ethernet addresses, they are
3738  * stored consecutively so the space needed is @nmac * 6 bytes.
3739  * Returns a negative error number or the non-negative VI id.
3740  */
3741 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
3742                      unsigned int port, unsigned int pf, unsigned int vf,
3743                      unsigned int nmac, u8 *mac, unsigned int *rss_size,
3744                      unsigned int portfunc, unsigned int idstype)
3745 {
3746         int ret;
3747         struct fw_vi_cmd c;
3748
3749         memset(&c, 0, sizeof(c));
3750         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
3751                                   F_FW_CMD_WRITE | F_FW_CMD_EXEC |
3752                                   V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf));
3753         c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c));
3754         c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) |
3755                                      V_FW_VI_CMD_FUNC(portfunc));
3756         c.portid_pkd = V_FW_VI_CMD_PORTID(port);
3757         c.nmac = nmac - 1;
3758
3759         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3760         if (ret)
3761                 return ret;
3762
3763         if (mac) {
3764                 memcpy(mac, c.mac, sizeof(c.mac));
3765                 switch (nmac) {
3766                 case 5:
3767                         memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
3768                         /* FALLTHROUGH */
3769                 case 4:
3770                         memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
3771                         /* FALLTHROUGH */
3772                 case 3:
3773                         memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
3774                         /* FALLTHROUGH */
3775                 case 2:
3776                         memcpy(mac + 6,  c.nmac0, sizeof(c.nmac0));
3777                         /* FALLTHROUGH */
3778                 }
3779         }
3780         if (rss_size)
3781                 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize));
3782         return G_FW_VI_CMD_VIID(cpu_to_be16(c.type_to_viid));
3783 }
3784
3785 /**
3786  * t4_alloc_vi - allocate an [Ethernet Function] virtual interface
3787  * @adap: the adapter
3788  * @mbox: mailbox to use for the FW command
3789  * @port: physical port associated with the VI
3790  * @pf: the PF owning the VI
3791  * @vf: the VF owning the VI
3792  * @nmac: number of MAC addresses needed (1 to 5)
3793  * @mac: the MAC addresses of the VI
3794  * @rss_size: size of RSS table slice associated with this VI
3795  *
3796  * Backwards compatible and convieniance routine to allocate a Virtual
3797  * Interface with a Ethernet Port Application Function and Intrustion
3798  * Detection System disabled.
3799  */
3800 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
3801                 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
3802                 unsigned int *rss_size)
3803 {
3804         return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size,
3805                                 FW_VI_FUNC_ETH, 0);
3806 }
3807
3808 /**
3809  * t4_free_vi - free a virtual interface
3810  * @adap: the adapter
3811  * @mbox: mailbox to use for the FW command
3812  * @pf: the PF owning the VI
3813  * @vf: the VF owning the VI
3814  * @viid: virtual interface identifiler
3815  *
3816  * Free a previously allocated virtual interface.
3817  */
3818 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
3819                unsigned int vf, unsigned int viid)
3820 {
3821         struct fw_vi_cmd c;
3822
3823         memset(&c, 0, sizeof(c));
3824         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
3825                                   F_FW_CMD_EXEC | V_FW_VI_CMD_PFN(pf) |
3826                                   V_FW_VI_CMD_VFN(vf));
3827         c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c));
3828         c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid));
3829
3830         return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3831 }
3832
3833 /**
3834  * t4_set_rxmode - set Rx properties of a virtual interface
3835  * @adap: the adapter
3836  * @mbox: mailbox to use for the FW command
3837  * @viid: the VI id
3838  * @mtu: the new MTU or -1
3839  * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
3840  * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
3841  * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
3842  * @vlanex: 1 to enable hardware VLAN Tag extraction, 0 to disable it,
3843  *          -1 no change
3844  * @sleep_ok: if true we may sleep while awaiting command completion
3845  *
3846  * Sets Rx properties of a virtual interface.
3847  */
3848 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
3849                   int mtu, int promisc, int all_multi, int bcast, int vlanex,
3850                   bool sleep_ok)
3851 {
3852         struct fw_vi_rxmode_cmd c;
3853
3854         /* convert to FW values */
3855         if (mtu < 0)
3856                 mtu = M_FW_VI_RXMODE_CMD_MTU;
3857         if (promisc < 0)
3858                 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN;
3859         if (all_multi < 0)
3860                 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN;
3861         if (bcast < 0)
3862                 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN;
3863         if (vlanex < 0)
3864                 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN;
3865
3866         memset(&c, 0, sizeof(c));
3867         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) |
3868                                    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3869                                    V_FW_VI_RXMODE_CMD_VIID(viid));
3870         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3871         c.mtu_to_vlanexen = cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) |
3872                             V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
3873                             V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
3874                             V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
3875                             V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
3876         return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
3877 }
3878
3879 /**
3880  * t4_change_mac - modifies the exact-match filter for a MAC address
3881  * @adap: the adapter
3882  * @mbox: mailbox to use for the FW command
3883  * @viid: the VI id
3884  * @idx: index of existing filter for old value of MAC address, or -1
3885  * @addr: the new MAC address value
3886  * @persist: whether a new MAC allocation should be persistent
3887  * @add_smt: if true also add the address to the HW SMT
3888  *
3889  * Modifies an exact-match filter and sets it to the new MAC address if
3890  * @idx >= 0, or adds the MAC address to a new filter if @idx < 0.  In the
3891  * latter case the address is added persistently if @persist is %true.
3892  *
3893  * Note that in general it is not possible to modify the value of a given
3894  * filter so the generic way to modify an address filter is to free the one
3895  * being used by the old address value and allocate a new filter for the
3896  * new address value.
3897  *
3898  * Returns a negative error number or the index of the filter with the new
3899  * MAC value.  Note that this index may differ from @idx.
3900  */
3901 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
3902                   int idx, const u8 *addr, bool persist, bool add_smt)
3903 {
3904         int ret, mode;
3905         struct fw_vi_mac_cmd c;
3906         struct fw_vi_mac_exact *p = c.u.exact;
3907         int max_mac_addr = adap->params.arch.mps_tcam_size;
3908
3909         if (idx < 0)                             /* new allocation */
3910                 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
3911         mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
3912
3913         memset(&c, 0, sizeof(c));
3914         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
3915                                    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3916                                    V_FW_VI_MAC_CMD_VIID(viid));
3917         c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1));
3918         p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
3919                                       V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
3920                                       V_FW_VI_MAC_CMD_IDX(idx));
3921         memcpy(p->macaddr, addr, sizeof(p->macaddr));
3922
3923         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3924         if (ret == 0) {
3925                 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
3926                 if (ret >= max_mac_addr)
3927                         ret = -ENOMEM;
3928         }
3929         return ret;
3930 }
3931
3932 /**
3933  * t4_enable_vi_params - enable/disable a virtual interface
3934  * @adap: the adapter
3935  * @mbox: mailbox to use for the FW command
3936  * @viid: the VI id
3937  * @rx_en: 1=enable Rx, 0=disable Rx
3938  * @tx_en: 1=enable Tx, 0=disable Tx
3939  * @dcb_en: 1=enable delivery of Data Center Bridging messages.
3940  *
3941  * Enables/disables a virtual interface.  Note that setting DCB Enable
3942  * only makes sense when enabling a Virtual Interface ...
3943  */
3944 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
3945                         unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
3946 {
3947         struct fw_vi_enable_cmd c;
3948
3949         memset(&c, 0, sizeof(c));
3950         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
3951                                    F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3952                                    V_FW_VI_ENABLE_CMD_VIID(viid));
3953         c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) |
3954                                      V_FW_VI_ENABLE_CMD_EEN(tx_en) |
3955                                      V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) |
3956                                      FW_LEN16(c));
3957         return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
3958 }
3959
3960 /**
3961  * t4_enable_vi - enable/disable a virtual interface
3962  * @adap: the adapter
3963  * @mbox: mailbox to use for the FW command
3964  * @viid: the VI id
3965  * @rx_en: 1=enable Rx, 0=disable Rx
3966  * @tx_en: 1=enable Tx, 0=disable Tx
3967  *
3968  * Enables/disables a virtual interface.  Note that setting DCB Enable
3969  * only makes sense when enabling a Virtual Interface ...
3970  */
3971 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
3972                  bool rx_en, bool tx_en)
3973 {
3974         return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
3975 }
3976
3977 /**
3978  * t4_iq_start_stop - enable/disable an ingress queue and its FLs
3979  * @adap: the adapter
3980  * @mbox: mailbox to use for the FW command
3981  * @start: %true to enable the queues, %false to disable them
3982  * @pf: the PF owning the queues
3983  * @vf: the VF owning the queues
3984  * @iqid: ingress queue id
3985  * @fl0id: FL0 queue id or 0xffff if no attached FL0
3986  * @fl1id: FL1 queue id or 0xffff if no attached FL1
3987  *
3988  * Starts or stops an ingress queue and its associated FLs, if any.
3989  */
3990 int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start,
3991                      unsigned int pf, unsigned int vf, unsigned int iqid,
3992                      unsigned int fl0id, unsigned int fl1id)
3993 {
3994         struct fw_iq_cmd c;
3995
3996         memset(&c, 0, sizeof(c));
3997         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
3998                                   F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
3999                                   V_FW_IQ_CMD_VFN(vf));
4000         c.alloc_to_len16 = cpu_to_be32(V_FW_IQ_CMD_IQSTART(start) |
4001                                        V_FW_IQ_CMD_IQSTOP(!start) |
4002                                        FW_LEN16(c));
4003         c.iqid = cpu_to_be16(iqid);
4004         c.fl0id = cpu_to_be16(fl0id);
4005         c.fl1id = cpu_to_be16(fl1id);
4006         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4007 }
4008
4009 /**
4010  * t4_iq_free - free an ingress queue and its FLs
4011  * @adap: the adapter
4012  * @mbox: mailbox to use for the FW command
4013  * @pf: the PF owning the queues
4014  * @vf: the VF owning the queues
4015  * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
4016  * @iqid: ingress queue id
4017  * @fl0id: FL0 queue id or 0xffff if no attached FL0
4018  * @fl1id: FL1 queue id or 0xffff if no attached FL1
4019  *
4020  * Frees an ingress queue and its associated FLs, if any.
4021  */
4022 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
4023                unsigned int vf, unsigned int iqtype, unsigned int iqid,
4024                unsigned int fl0id, unsigned int fl1id)
4025 {
4026         struct fw_iq_cmd c;
4027
4028         memset(&c, 0, sizeof(c));
4029         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
4030                                   F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
4031                                   V_FW_IQ_CMD_VFN(vf));
4032         c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c));
4033         c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
4034         c.iqid = cpu_to_be16(iqid);
4035         c.fl0id = cpu_to_be16(fl0id);
4036         c.fl1id = cpu_to_be16(fl1id);
4037         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4038 }
4039
4040 /**
4041  * t4_eth_eq_free - free an Ethernet egress queue
4042  * @adap: the adapter
4043  * @mbox: mailbox to use for the FW command
4044  * @pf: the PF owning the queue
4045  * @vf: the VF owning the queue
4046  * @eqid: egress queue id
4047  *
4048  * Frees an Ethernet egress queue.
4049  */
4050 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
4051                    unsigned int vf, unsigned int eqid)
4052 {
4053         struct fw_eq_eth_cmd c;
4054
4055         memset(&c, 0, sizeof(c));
4056         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) |
4057                                   F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
4058                                   V_FW_EQ_ETH_CMD_PFN(pf) |
4059                                   V_FW_EQ_ETH_CMD_VFN(vf));
4060         c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
4061         c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid));
4062         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4063 }
4064
4065 /**
4066  * t4_handle_fw_rpl - process a FW reply message
4067  * @adap: the adapter
4068  * @rpl: start of the FW message
4069  *
4070  * Processes a FW message, such as link state change messages.
4071  */
4072 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
4073 {
4074         u8 opcode = *(const u8 *)rpl;
4075
4076         /*
4077          * This might be a port command ... this simplifies the following
4078          * conditionals ...  We can get away with pre-dereferencing
4079          * action_to_len16 because it's in the first 16 bytes and all messages
4080          * will be at least that long.
4081          */
4082         const struct fw_port_cmd *p = (const void *)rpl;
4083         unsigned int action =
4084                 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16));
4085
4086         if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) {
4087                 /* link/module state change message */
4088                 unsigned int speed = 0, fc = 0, i;
4089                 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));
4090                 struct port_info *pi = NULL;
4091                 struct link_config *lc;
4092                 u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
4093                 int link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0;
4094                 u32 mod = G_FW_PORT_CMD_MODTYPE(stat);
4095
4096                 if (stat & F_FW_PORT_CMD_RXPAUSE)
4097                         fc |= PAUSE_RX;
4098                 if (stat & F_FW_PORT_CMD_TXPAUSE)
4099                         fc |= PAUSE_TX;
4100                 if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
4101                         speed = ETH_SPEED_NUM_100M;
4102                 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
4103                         speed = ETH_SPEED_NUM_1G;
4104                 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
4105                         speed = ETH_SPEED_NUM_10G;
4106                 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G))
4107                         speed = ETH_SPEED_NUM_25G;
4108                 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
4109                         speed = ETH_SPEED_NUM_40G;
4110                 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G))
4111                         speed = ETH_SPEED_NUM_100G;
4112
4113                 for_each_port(adap, i) {
4114                         pi = adap2pinfo(adap, i);
4115                         if (pi->tx_chan == chan)
4116                                 break;
4117                 }
4118                 lc = &pi->link_cfg;
4119
4120                 if (mod != pi->mod_type) {
4121                         pi->mod_type = mod;
4122                         t4_os_portmod_changed(adap, i);
4123                 }
4124                 if (link_ok != lc->link_ok || speed != lc->speed ||
4125                     fc != lc->fc) {                    /* something changed */
4126                         if (!link_ok && lc->link_ok) {
4127                                 static const char * const reason[] = {
4128                                         "Link Down",
4129                                         "Remote Fault",
4130                                         "Auto-negotiation Failure",
4131                                         "Reserved",
4132                                         "Insufficient Airflow",
4133                                         "Unable To Determine Reason",
4134                                         "No RX Signal Detected",
4135                                         "Reserved",
4136                                 };
4137                                 unsigned int rc = G_FW_PORT_CMD_LINKDNRC(stat);
4138
4139                                 dev_warn(adap, "Port %d link down, reason: %s\n",
4140                                          chan, reason[rc]);
4141                         }
4142                         lc->link_ok = link_ok;
4143                         lc->speed = speed;
4144                         lc->fc = fc;
4145                         lc->supported = be16_to_cpu(p->u.info.pcap);
4146                 }
4147         } else {
4148                 dev_warn(adap, "Unknown firmware reply %d\n", opcode);
4149                 return -EINVAL;
4150         }
4151         return 0;
4152 }
4153
4154 void t4_reset_link_config(struct adapter *adap, int idx)
4155 {
4156         struct port_info *pi = adap2pinfo(adap, idx);
4157         struct link_config *lc = &pi->link_cfg;
4158
4159         lc->link_ok = 0;
4160         lc->requested_speed = 0;
4161         lc->requested_fc = 0;
4162         lc->speed = 0;
4163         lc->fc = 0;
4164 }
4165
4166 /**
4167  * init_link_config - initialize a link's SW state
4168  * @lc: structure holding the link state
4169  * @pcaps: link Port Capabilities
4170  * @acaps: link current Advertised Port Capabilities
4171  *
4172  * Initializes the SW state maintained for each link, including the link's
4173  * capabilities and default speed/flow-control/autonegotiation settings.
4174  */
4175 static void init_link_config(struct link_config *lc, unsigned int pcaps,
4176                              unsigned int acaps)
4177 {
4178         unsigned int fec;
4179
4180         lc->supported = pcaps;
4181         lc->requested_speed = 0;
4182         lc->speed = 0;
4183         lc->requested_fc = 0;
4184         lc->fc = 0;
4185
4186         /**
4187          * For Forward Error Control, we default to whatever the Firmware
4188          * tells us the Link is currently advertising.
4189          */
4190         fec = 0;
4191         if (acaps & FW_PORT_CAP_FEC_RS)
4192                 fec |= FEC_RS;
4193         if (acaps & FW_PORT_CAP_FEC_BASER_RS)
4194                 fec |= FEC_BASER_RS;
4195         if (acaps & FW_PORT_CAP_FEC_RESERVED)
4196                 fec |= FEC_RESERVED;
4197         lc->requested_fec = fec;
4198         lc->fec = fec;
4199
4200         if (lc->supported & FW_PORT_CAP_ANEG) {
4201                 lc->advertising = lc->supported & ADVERT_MASK;
4202                 lc->autoneg = AUTONEG_ENABLE;
4203         } else {
4204                 lc->advertising = 0;
4205                 lc->autoneg = AUTONEG_DISABLE;
4206         }
4207 }
4208
4209 /**
4210  * t4_wait_dev_ready - wait till to reads of registers work
4211  *
4212  * Right after the device is RESET is can take a small amount of time
4213  * for it to respond to register reads.  Until then, all reads will
4214  * return either 0xff...ff or 0xee...ee.  Return an error if reads
4215  * don't work within a reasonable time frame.
4216  */
4217 static int t4_wait_dev_ready(struct adapter *adapter)
4218 {
4219         u32 whoami;
4220
4221         whoami = t4_read_reg(adapter, A_PL_WHOAMI);
4222
4223         if (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS)
4224                 return 0;
4225
4226         msleep(500);
4227         whoami = t4_read_reg(adapter, A_PL_WHOAMI);
4228         if (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS)
4229                 return 0;
4230
4231         dev_err(adapter, "Device didn't become ready for access, whoami = %#x\n",
4232                 whoami);
4233         return -EIO;
4234 }
4235
4236 struct flash_desc {
4237         u32 vendor_and_model_id;
4238         u32 size_mb;
4239 };
4240
4241 int t4_get_flash_params(struct adapter *adapter)
4242 {
4243         /*
4244          * Table for non-Numonix supported flash parts.  Numonix parts are left
4245          * to the preexisting well-tested code.  All flash parts have 64KB
4246          * sectors.
4247          */
4248         static struct flash_desc supported_flash[] = {
4249                 { 0x00150201, 4 << 20 },       /* Spansion 4MB S25FL032P */
4250         };
4251
4252         int ret;
4253         u32 flashid = 0;
4254         unsigned int part, manufacturer;
4255         unsigned int density, size;
4256
4257         /**
4258          * Issue a Read ID Command to the Flash part.  We decode supported
4259          * Flash parts and their sizes from this.  There's a newer Query
4260          * Command which can retrieve detailed geometry information but
4261          * many Flash parts don't support it.
4262          */
4263         ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID);
4264         if (!ret)
4265                 ret = sf1_read(adapter, 3, 0, 1, &flashid);
4266         t4_write_reg(adapter, A_SF_OP, 0);               /* unlock SF */
4267         if (ret < 0)
4268                 return ret;
4269
4270         for (part = 0; part < ARRAY_SIZE(supported_flash); part++) {
4271                 if (supported_flash[part].vendor_and_model_id == flashid) {
4272                         adapter->params.sf_size =
4273                                 supported_flash[part].size_mb;
4274                         adapter->params.sf_nsec =
4275                                 adapter->params.sf_size / SF_SEC_SIZE;
4276                         goto found;
4277                 }
4278         }
4279
4280         manufacturer = flashid & 0xff;
4281         switch (manufacturer) {
4282         case 0x20: { /* Micron/Numonix */
4283                 /**
4284                  * This Density -> Size decoding table is taken from Micron
4285                  * Data Sheets.
4286                  */
4287                 density = (flashid >> 16) & 0xff;
4288                 switch (density) {
4289                 case 0x14:
4290                         size = 1 << 20; /* 1MB */
4291                         break;
4292                 case 0x15:
4293                         size = 1 << 21; /* 2MB */
4294                         break;
4295                 case 0x16:
4296                         size = 1 << 22; /* 4MB */
4297                         break;
4298                 case 0x17:
4299                         size = 1 << 23; /* 8MB */
4300                         break;
4301                 case 0x18:
4302                         size = 1 << 24; /* 16MB */
4303                         break;
4304                 case 0x19:
4305                         size = 1 << 25; /* 32MB */
4306                         break;
4307                 case 0x20:
4308                         size = 1 << 26; /* 64MB */
4309                         break;
4310                 case 0x21:
4311                         size = 1 << 27; /* 128MB */
4312                         break;
4313                 case 0x22:
4314                         size = 1 << 28; /* 256MB */
4315                         break;
4316                 default:
4317                         dev_err(adapter, "Micron Flash Part has bad size, ID = %#x, Density code = %#x\n",
4318                                 flashid, density);
4319                         return -EINVAL;
4320                 }
4321
4322                 adapter->params.sf_size = size;
4323                 adapter->params.sf_nsec = size / SF_SEC_SIZE;
4324                 break;
4325         }
4326         default:
4327                 dev_err(adapter, "Unsupported Flash Part, ID = %#x\n", flashid);
4328                 return -EINVAL;
4329         }
4330
4331 found:
4332         /*
4333          * We should reject adapters with FLASHes which are too small. So, emit
4334          * a warning.
4335          */
4336         if (adapter->params.sf_size < FLASH_MIN_SIZE)
4337                 dev_warn(adapter, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
4338                          flashid, adapter->params.sf_size, FLASH_MIN_SIZE);
4339
4340         return 0;
4341 }
4342
4343 static void set_pcie_completion_timeout(struct adapter *adapter,
4344                                         u8 range)
4345 {
4346         u32 pcie_cap;
4347         u16 val;
4348
4349         pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
4350         if (pcie_cap) {
4351                 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val);
4352                 val &= 0xfff0;
4353                 val |= range;
4354                 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val);
4355         }
4356 }
4357
4358 /**
4359  * t4_get_chip_type - Determine chip type from device ID
4360  * @adap: the adapter
4361  * @ver: adapter version
4362  */
4363 int t4_get_chip_type(struct adapter *adap, int ver)
4364 {
4365         enum chip_type chip = 0;
4366         u32 pl_rev = G_REV(t4_read_reg(adap, A_PL_REV));
4367
4368         /* Retrieve adapter's device ID */
4369         switch (ver) {
4370         case CHELSIO_T5:
4371                 chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4372                 break;
4373         case CHELSIO_T6:
4374                 chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
4375                 break;
4376         default:
4377                 dev_err(adap, "Device %d is not supported\n",
4378                         adap->params.pci.device_id);
4379                 return -EINVAL;
4380         }
4381
4382         return chip;
4383 }
4384
4385 /**
4386  * t4_prep_adapter - prepare SW and HW for operation
4387  * @adapter: the adapter
4388  *
4389  * Initialize adapter SW state for the various HW modules, set initial
4390  * values for some adapter tunables, take PHYs out of reset, and
4391  * initialize the MDIO interface.
4392  */
4393 int t4_prep_adapter(struct adapter *adapter)
4394 {
4395         int ret, ver;
4396         u32 pl_rev;
4397
4398         ret = t4_wait_dev_ready(adapter);
4399         if (ret < 0)
4400                 return ret;
4401
4402         pl_rev = G_REV(t4_read_reg(adapter, A_PL_REV));
4403         adapter->params.pci.device_id = adapter->pdev->id.device_id;
4404         adapter->params.pci.vendor_id = adapter->pdev->id.vendor_id;
4405
4406         /*
4407          * WE DON'T NEED adapter->params.chip CODE ONCE PL_REV CONTAINS
4408          * ADAPTER (VERSION << 4 | REVISION)
4409          */
4410         ver = CHELSIO_PCI_ID_VER(adapter->params.pci.device_id);
4411         adapter->params.chip = 0;
4412         switch (ver) {
4413         case CHELSIO_T5:
4414                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4415                 adapter->params.arch.sge_fl_db = F_DBPRIO | F_DBTYPE;
4416                 adapter->params.arch.mps_tcam_size =
4417                                                 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
4418                 adapter->params.arch.mps_rplc_size = 128;
4419                 adapter->params.arch.nchan = NCHAN;
4420                 adapter->params.arch.vfcount = 128;
4421                 break;
4422         case CHELSIO_T6:
4423                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
4424                 adapter->params.arch.sge_fl_db = 0;
4425                 adapter->params.arch.mps_tcam_size =
4426                                                 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
4427                 adapter->params.arch.mps_rplc_size = 256;
4428                 adapter->params.arch.nchan = 2;
4429                 adapter->params.arch.vfcount = 256;
4430                 break;
4431         default:
4432                 dev_err(adapter, "%s: Device %d is not supported\n",
4433                         __func__, adapter->params.pci.device_id);
4434                 return -EINVAL;
4435         }
4436
4437         adapter->params.pci.vpd_cap_addr =
4438                 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
4439
4440         ret = t4_get_flash_params(adapter);
4441         if (ret < 0) {
4442                 dev_err(adapter, "Unable to retrieve Flash Parameters, ret = %d\n",
4443                         -ret);
4444                 return ret;
4445         }
4446
4447         adapter->params.cim_la_size = CIMLA_SIZE;
4448
4449         init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
4450
4451         /*
4452          * Default port and clock for debugging in case we can't reach FW.
4453          */
4454         adapter->params.nports = 1;
4455         adapter->params.portvec = 1;
4456         adapter->params.vpd.cclk = 50000;
4457
4458         /* Set pci completion timeout value to 4 seconds. */
4459         set_pcie_completion_timeout(adapter, 0xd);
4460         return 0;
4461 }
4462
4463 /**
4464  * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
4465  * @adapter: the adapter
4466  * @qid: the Queue ID
4467  * @qtype: the Ingress or Egress type for @qid
4468  * @pbar2_qoffset: BAR2 Queue Offset
4469  * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
4470  *
4471  * Returns the BAR2 SGE Queue Registers information associated with the
4472  * indicated Absolute Queue ID.  These are passed back in return value
4473  * pointers.  @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
4474  * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
4475  *
4476  * This may return an error which indicates that BAR2 SGE Queue
4477  * registers aren't available.  If an error is not returned, then the
4478  * following values are returned:
4479  *
4480  *   *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
4481  *   *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
4482  *
4483  * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
4484  * require the "Inferred Queue ID" ability may be used.  E.g. the
4485  * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
4486  * then these "Inferred Queue ID" register may not be used.
4487  */
4488 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,
4489                       enum t4_bar2_qtype qtype, u64 *pbar2_qoffset,
4490                       unsigned int *pbar2_qid)
4491 {
4492         unsigned int page_shift, page_size, qpp_shift, qpp_mask;
4493         u64 bar2_page_offset, bar2_qoffset;
4494         unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
4495
4496         /*
4497          * T4 doesn't support BAR2 SGE Queue registers.
4498          */
4499         if (is_t4(adapter->params.chip))
4500                 return -EINVAL;
4501
4502         /*
4503          * Get our SGE Page Size parameters.
4504          */
4505         page_shift = adapter->params.sge.hps + 10;
4506         page_size = 1 << page_shift;
4507
4508         /*
4509          * Get the right Queues per Page parameters for our Queue.
4510          */
4511         qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS ?
4512                               adapter->params.sge.eq_qpp :
4513                               adapter->params.sge.iq_qpp);
4514         qpp_mask = (1 << qpp_shift) - 1;
4515
4516         /*
4517          * Calculate the basics of the BAR2 SGE Queue register area:
4518          *  o The BAR2 page the Queue registers will be in.
4519          *  o The BAR2 Queue ID.
4520          *  o The BAR2 Queue ID Offset into the BAR2 page.
4521          */
4522         bar2_page_offset = ((qid >> qpp_shift) << page_shift);
4523         bar2_qid = qid & qpp_mask;
4524         bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
4525
4526         /*
4527          * If the BAR2 Queue ID Offset is less than the Page Size, then the
4528          * hardware will infer the Absolute Queue ID simply from the writes to
4529          * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
4530          * BAR2 Queue ID of 0 for those writes).  Otherwise, we'll simply
4531          * write to the first BAR2 SGE Queue Area within the BAR2 Page with
4532          * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
4533          * from the BAR2 Page and BAR2 Queue ID.
4534          *
4535          * One important censequence of this is that some BAR2 SGE registers
4536          * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
4537          * there.  But other registers synthesize the SGE Queue ID purely
4538          * from the writes to the registers -- the Write Combined Doorbell
4539          * Buffer is a good example.  These BAR2 SGE Registers are only
4540          * available for those BAR2 SGE Register areas where the SGE Absolute
4541          * Queue ID can be inferred from simple writes.
4542          */
4543         bar2_qoffset = bar2_page_offset;
4544         bar2_qinferred = (bar2_qid_offset < page_size);
4545         if (bar2_qinferred) {
4546                 bar2_qoffset += bar2_qid_offset;
4547                 bar2_qid = 0;
4548         }
4549
4550         *pbar2_qoffset = bar2_qoffset;
4551         *pbar2_qid = bar2_qid;
4552         return 0;
4553 }
4554
4555 /**
4556  * t4_init_sge_params - initialize adap->params.sge
4557  * @adapter: the adapter
4558  *
4559  * Initialize various fields of the adapter's SGE Parameters structure.
4560  */
4561 int t4_init_sge_params(struct adapter *adapter)
4562 {
4563         struct sge_params *sge_params = &adapter->params.sge;
4564         u32 hps, qpp;
4565         unsigned int s_hps, s_qpp;
4566
4567         /*
4568          * Extract the SGE Page Size for our PF.
4569          */
4570         hps = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE);
4571         s_hps = (S_HOSTPAGESIZEPF0 + (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) *
4572                  adapter->pf);
4573         sge_params->hps = ((hps >> s_hps) & M_HOSTPAGESIZEPF0);
4574
4575         /*
4576          * Extract the SGE Egress and Ingess Queues Per Page for our PF.
4577          */
4578         s_qpp = (S_QUEUESPERPAGEPF0 +
4579                  (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf);
4580         qpp = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
4581         sge_params->eq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
4582         qpp = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
4583         sge_params->iq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
4584
4585         return 0;
4586 }
4587
4588 /**
4589  * t4_init_tp_params - initialize adap->params.tp
4590  * @adap: the adapter
4591  *
4592  * Initialize various fields of the adapter's TP Parameters structure.
4593  */
4594 int t4_init_tp_params(struct adapter *adap)
4595 {
4596         int chan;
4597         u32 v;
4598
4599         v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION);
4600         adap->params.tp.tre = G_TIMERRESOLUTION(v);
4601         adap->params.tp.dack_re = G_DELAYEDACKRESOLUTION(v);
4602
4603         /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
4604         for (chan = 0; chan < NCHAN; chan++)
4605                 adap->params.tp.tx_modq[chan] = chan;
4606
4607         /*
4608          * Cache the adapter's Compressed Filter Mode and global Incress
4609          * Configuration.
4610          */
4611         t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4612                          &adap->params.tp.vlan_pri_map, 1, A_TP_VLAN_PRI_MAP);
4613         t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4614                          &adap->params.tp.ingress_config, 1,
4615                          A_TP_INGRESS_CONFIG);
4616
4617         /* For T6, cache the adapter's compressed error vector
4618          * and passing outer header info for encapsulated packets.
4619          */
4620         if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
4621                 v = t4_read_reg(adap, A_TP_OUT_CONFIG);
4622                 adap->params.tp.rx_pkt_encap = (v & F_CRXPKTENC) ? 1 : 0;
4623         }
4624
4625         /*
4626          * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
4627          * shift positions of several elements of the Compressed Filter Tuple
4628          * for this adapter which we need frequently ...
4629          */
4630         adap->params.tp.vlan_shift = t4_filter_field_shift(adap, F_VLAN);
4631         adap->params.tp.vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
4632         adap->params.tp.port_shift = t4_filter_field_shift(adap, F_PORT);
4633         adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
4634                                                                F_PROTOCOL);
4635
4636         /*
4637          * If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
4638          * represents the presense of an Outer VLAN instead of a VNIC ID.
4639          */
4640         if ((adap->params.tp.ingress_config & F_VNIC) == 0)
4641                 adap->params.tp.vnic_shift = -1;
4642
4643         return 0;
4644 }
4645
4646 /**
4647  * t4_filter_field_shift - calculate filter field shift
4648  * @adap: the adapter
4649  * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
4650  *
4651  * Return the shift position of a filter field within the Compressed
4652  * Filter Tuple.  The filter field is specified via its selection bit
4653  * within TP_VLAN_PRI_MAL (filter mode).  E.g. F_VLAN.
4654  */
4655 int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel)
4656 {
4657         unsigned int filter_mode = adap->params.tp.vlan_pri_map;
4658         unsigned int sel;
4659         int field_shift;
4660
4661         if ((filter_mode & filter_sel) == 0)
4662                 return -1;
4663
4664         for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
4665                 switch (filter_mode & sel) {
4666                 case F_FCOE:
4667                         field_shift += W_FT_FCOE;
4668                         break;
4669                 case F_PORT:
4670                         field_shift += W_FT_PORT;
4671                         break;
4672                 case F_VNIC_ID:
4673                         field_shift += W_FT_VNIC_ID;
4674                         break;
4675                 case F_VLAN:
4676                         field_shift += W_FT_VLAN;
4677                         break;
4678                 case F_TOS:
4679                         field_shift += W_FT_TOS;
4680                         break;
4681                 case F_PROTOCOL:
4682                         field_shift += W_FT_PROTOCOL;
4683                         break;
4684                 case F_ETHERTYPE:
4685                         field_shift += W_FT_ETHERTYPE;
4686                         break;
4687                 case F_MACMATCH:
4688                         field_shift += W_FT_MACMATCH;
4689                         break;
4690                 case F_MPSHITTYPE:
4691                         field_shift += W_FT_MPSHITTYPE;
4692                         break;
4693                 case F_FRAGMENTATION:
4694                         field_shift += W_FT_FRAGMENTATION;
4695                         break;
4696                 }
4697         }
4698         return field_shift;
4699 }
4700
4701 int t4_init_rss_mode(struct adapter *adap, int mbox)
4702 {
4703         int i, ret;
4704         struct fw_rss_vi_config_cmd rvc;
4705
4706         memset(&rvc, 0, sizeof(rvc));
4707
4708         for_each_port(adap, i) {
4709                 struct port_info *p = adap2pinfo(adap, i);
4710
4711                 rvc.op_to_viid = htonl(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
4712                                        F_FW_CMD_REQUEST | F_FW_CMD_READ |
4713                                        V_FW_RSS_VI_CONFIG_CMD_VIID(p->viid));
4714                 rvc.retval_len16 = htonl(FW_LEN16(rvc));
4715                 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
4716                 if (ret)
4717                         return ret;
4718                 p->rss_mode = ntohl(rvc.u.basicvirtual.defaultq_to_udpen);
4719         }
4720         return 0;
4721 }
4722
4723 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
4724 {
4725         u8 addr[6];
4726         int ret, i, j = 0;
4727         struct fw_port_cmd c;
4728
4729         memset(&c, 0, sizeof(c));
4730
4731         for_each_port(adap, i) {
4732                 unsigned int rss_size = 0;
4733                 struct port_info *p = adap2pinfo(adap, i);
4734
4735                 while ((adap->params.portvec & (1 << j)) == 0)
4736                         j++;
4737
4738                 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
4739                                              F_FW_CMD_REQUEST | F_FW_CMD_READ |
4740                                              V_FW_PORT_CMD_PORTID(j));
4741                 c.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(
4742                                                 FW_PORT_ACTION_GET_PORT_INFO) |
4743                                                 FW_LEN16(c));
4744                 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
4745                 if (ret)
4746                         return ret;
4747
4748                 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
4749                 if (ret < 0)
4750                         return ret;
4751
4752                 p->viid = ret;
4753                 p->tx_chan = j;
4754                 p->rss_size = rss_size;
4755                 t4_os_set_hw_addr(adap, i, addr);
4756
4757                 ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
4758                 p->mdio_addr = (ret & F_FW_PORT_CMD_MDIOCAP) ?
4759                                 G_FW_PORT_CMD_MDIOADDR(ret) : -1;
4760                 p->port_type = G_FW_PORT_CMD_PTYPE(ret);
4761                 p->mod_type = FW_PORT_MOD_TYPE_NA;
4762
4763                 init_link_config(&p->link_cfg, be16_to_cpu(c.u.info.pcap),
4764                                  be16_to_cpu(c.u.info.acap));
4765                 j++;
4766         }
4767         return 0;
4768 }