drivers/net/cxgbe/cxgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Chelsio Communications.
   3  * All rights reserved.
   4  */
   5
   6 #include <sys/queue.h>
   7 #include <stdio.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <string.h>
  11 #include <unistd.h>
  12 #include <stdarg.h>
  13 #include <inttypes.h>
  14 #include <netinet/in.h>
  15
  16 #include <rte_byteorder.h>
  17 #include <rte_common.h>
  18 #include <rte_cycles.h>
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_atomic.h>
  25 #include <rte_branch_prediction.h>
  26 #include <rte_memory.h>
  27 #include <rte_tailq.h>
  28 #include <rte_eal.h>
  29 #include <rte_alarm.h>
  30 #include <rte_ether.h>
  31 #include <rte_ethdev_driver.h>
  32 #include <rte_ethdev_pci.h>
  33 #include <rte_malloc.h>
  34 #include <rte_random.h>
  35 #include <rte_dev.h>
  36
  37 #include "cxgbe.h"
  38 #include "cxgbe_pfvf.h"
  39 #include "cxgbe_flow.h"
  40
  41 /*
  42  * Macros needed to support the PCI Device ID Table ...
  43  */
  44 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
  45         static const struct rte_pci_id cxgb4_pci_tbl[] = {
  46 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
  47
  48 #define PCI_VENDOR_ID_CHELSIO 0x1425
  49
  50 #define CH_PCI_ID_TABLE_ENTRY(devid) \
  51                 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) }
  52
  53 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
  54                 { .vendor_id = 0, } \
  55         }
  56
  57 /*
  58  *... and the PCI ID Table itself ...
  59  */
  60 #include "t4_pci_id_tbl.h"
  61
  62 #define CXGBE_TX_OFFLOADS (DEV_TX_OFFLOAD_VLAN_INSERT |\
  63                            DEV_TX_OFFLOAD_IPV4_CKSUM |\
  64                            DEV_TX_OFFLOAD_UDP_CKSUM |\
  65                            DEV_TX_OFFLOAD_TCP_CKSUM |\
  66                            DEV_TX_OFFLOAD_TCP_TSO)
  67
  68 #define CXGBE_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_STRIP |\
  69                            DEV_RX_OFFLOAD_IPV4_CKSUM |\
  70                            DEV_RX_OFFLOAD_JUMBO_FRAME |\
  71                            DEV_RX_OFFLOAD_UDP_CKSUM |\
  72                            DEV_RX_OFFLOAD_TCP_CKSUM)
  73
  74 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
  75                          uint16_t nb_pkts)
  76 {
  77         struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue;
  78         uint16_t pkts_sent, pkts_remain;
  79         uint16_t total_sent = 0;
  80         int ret = 0;
  81
  82         CXGBE_DEBUG_TX(adapter, "%s: txq = %p; tx_pkts = %p; nb_pkts = %d\n",
  83                        __func__, txq, tx_pkts, nb_pkts);
  84
  85         t4_os_lock(&txq->txq_lock);
  86         /* free up desc from already completed tx */
  87         reclaim_completed_tx(&txq->q);
  88         while (total_sent < nb_pkts) {
  89                 pkts_remain = nb_pkts - total_sent;
  90
  91                 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) {
  92                         ret = t4_eth_xmit(txq, tx_pkts[total_sent + pkts_sent],
  93                                           nb_pkts);
  94                         if (ret < 0)
  95                                 break;
  96                 }
  97                 if (!pkts_sent)
  98                         break;
  99                 total_sent += pkts_sent;
 100                 /* reclaim as much as possible */
 101                 reclaim_completed_tx(&txq->q);
 102         }
 103
 104         t4_os_unlock(&txq->txq_lock);
 105         return total_sent;
 106 }
 107
 108 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 109                          uint16_t nb_pkts)
 110 {
 111         struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue;
 112         unsigned int work_done;
 113
 114         CXGBE_DEBUG_RX(adapter, "%s: rxq->rspq.cntxt_id = %u; nb_pkts = %d\n",
 115                        __func__, rxq->rspq.cntxt_id, nb_pkts);
 116
 117         if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done))
 118                 dev_err(adapter, "error in cxgbe poll\n");
 119
 120         CXGBE_DEBUG_RX(adapter, "%s: work_done = %u\n", __func__, work_done);
 121         return work_done;
 122 }
 123
 124 void cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
 125                         struct rte_eth_dev_info *device_info)
 126 {
 127         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 128         struct adapter *adapter = pi->adapter;
 129         int max_queues = adapter->sge.max_ethqsets / adapter->params.nports;
 130
 131         static const struct rte_eth_desc_lim cxgbe_desc_lim = {
 132                 .nb_max = CXGBE_MAX_RING_DESC_SIZE,
 133                 .nb_min = CXGBE_MIN_RING_DESC_SIZE,
 134                 .nb_align = 1,
 135         };
 136
 137         device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE;
 138         device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN;
 139         device_info->max_rx_queues = max_queues;
 140         device_info->max_tx_queues = max_queues;
 141         device_info->max_mac_addrs = 1;
 142         /* XXX: For now we support one MAC/port */
 143         device_info->max_vfs = adapter->params.arch.vfcount;
 144         device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */
 145
 146         device_info->rx_queue_offload_capa = 0UL;
 147         device_info->rx_offload_capa = CXGBE_RX_OFFLOADS;
 148
 149         device_info->tx_queue_offload_capa = 0UL;
 150         device_info->tx_offload_capa = CXGBE_TX_OFFLOADS;
 151
 152         device_info->reta_size = pi->rss_size;
 153         device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN;
 154         device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL;
 155
 156         device_info->rx_desc_lim = cxgbe_desc_lim;
 157         device_info->tx_desc_lim = cxgbe_desc_lim;
 158         cxgbe_get_speed_caps(pi, &device_info->speed_capa);
 159 }
 160
 161 void cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
 162 {
 163         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 164         struct adapter *adapter = pi->adapter;
 165
 166         t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 167                       1, -1, 1, -1, false);
 168 }
 169
 170 void cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
 171 {
 172         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 173         struct adapter *adapter = pi->adapter;
 174
 175         t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 176                       0, -1, 1, -1, false);
 177 }
 178
 179 void cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
 180 {
 181         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 182         struct adapter *adapter = pi->adapter;
 183
 184         /* TODO: address filters ?? */
 185
 186         t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 187                       -1, 1, 1, -1, false);
 188 }
 189
 190 void cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
 191 {
 192         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 193         struct adapter *adapter = pi->adapter;
 194
 195         /* TODO: address filters ?? */
 196
 197         t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 198                       -1, 0, 1, -1, false);
 199 }
 200
 201 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev,
 202                           int wait_to_complete)
 203 {
 204         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 205         struct adapter *adapter = pi->adapter;
 206         struct sge *s = &adapter->sge;
 207         struct rte_eth_link new_link = { 0 };
 208         unsigned int i, work_done, budget = 32;
 209         u8 old_link = pi->link_cfg.link_ok;
 210
 211         for (i = 0; i < CXGBE_LINK_STATUS_POLL_CNT; i++) {
 212                 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
 213
 214                 /* Exit if link status changed or always forced up */
 215                 if (pi->link_cfg.link_ok != old_link || force_linkup(adapter))
 216                         break;
 217
 218                 if (!wait_to_complete)
 219                         break;
 220
 221                 rte_delay_ms(CXGBE_LINK_STATUS_POLL_MS);
 222         }
 223
 224         new_link.link_status = force_linkup(adapter) ?
 225                                ETH_LINK_UP : pi->link_cfg.link_ok;
 226         new_link.link_autoneg = pi->link_cfg.autoneg;
 227         new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
 228         new_link.link_speed = pi->link_cfg.speed;
 229
 230         return rte_eth_linkstatus_set(eth_dev, &new_link);
 231 }
 232
 233 /**
 234  * Set device link up.
 235  */
 236 int cxgbe_dev_set_link_up(struct rte_eth_dev *dev)
 237 {
 238         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
 239         struct adapter *adapter = pi->adapter;
 240         unsigned int work_done, budget = 32;
 241         struct sge *s = &adapter->sge;
 242         int ret;
 243
 244         /* Flush all link events */
 245         cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
 246
 247         /* If link already up, nothing to do */
 248         if (pi->link_cfg.link_ok)
 249                 return 0;
 250
 251         ret = cxgbe_set_link_status(pi, true);
 252         if (ret)
 253                 return ret;
 254
 255         cxgbe_dev_link_update(dev, 1);
 256         return 0;
 257 }
 258
 259 /**
 260  * Set device link down.
 261  */
 262 int cxgbe_dev_set_link_down(struct rte_eth_dev *dev)
 263 {
 264         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
 265         struct adapter *adapter = pi->adapter;
 266         unsigned int work_done, budget = 32;
 267         struct sge *s = &adapter->sge;
 268         int ret;
 269
 270         /* Flush all link events */
 271         cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
 272
 273         /* If link already down, nothing to do */
 274         if (!pi->link_cfg.link_ok)
 275                 return 0;
 276
 277         ret = cxgbe_set_link_status(pi, false);
 278         if (ret)
 279                 return ret;
 280
 281         cxgbe_dev_link_update(dev, 0);
 282         return 0;
 283 }
 284
 285 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
 286 {
 287         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 288         struct adapter *adapter = pi->adapter;
 289         struct rte_eth_dev_info dev_info;
 290         int err;
 291         uint16_t new_mtu = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
 292
 293         cxgbe_dev_info_get(eth_dev, &dev_info);
 294
 295         /* Must accommodate at least ETHER_MIN_MTU */
 296         if ((new_mtu < ETHER_MIN_MTU) || (new_mtu > dev_info.max_rx_pktlen))
 297                 return -EINVAL;
 298
 299         /* set to jumbo mode if needed */
 300         if (new_mtu > ETHER_MAX_LEN)
 301                 eth_dev->data->dev_conf.rxmode.offloads |=
 302                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 303         else
 304                 eth_dev->data->dev_conf.rxmode.offloads &=
 305                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 306
 307         err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1,
 308                             -1, -1, true);
 309         if (!err)
 310                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu;
 311
 312         return err;
 313 }
 314
 315 /*
 316  * Stop device.
 317  */
 318 void cxgbe_dev_close(struct rte_eth_dev *eth_dev)
 319 {
 320         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 321         struct adapter *adapter = pi->adapter;
 322
 323         CXGBE_FUNC_TRACE();
 324
 325         if (!(adapter->flags & FULL_INIT_DONE))
 326                 return;
 327
 328         cxgbe_down(pi);
 329
 330         /*
 331          *  We clear queues only if both tx and rx path of the port
 332          *  have been disabled
 333          */
 334         t4_sge_eth_clear_queues(pi);
 335 }
 336
 337 /* Start the device.
 338  * It returns 0 on success.
 339  */
 340 int cxgbe_dev_start(struct rte_eth_dev *eth_dev)
 341 {
 342         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 343         struct adapter *adapter = pi->adapter;
 344         int err = 0, i;
 345
 346         CXGBE_FUNC_TRACE();
 347
 348         /*
 349          * If we don't have a connection to the firmware there's nothing we
 350          * can do.
 351          */
 352         if (!(adapter->flags & FW_OK)) {
 353                 err = -ENXIO;
 354                 goto out;
 355         }
 356
 357         if (!(adapter->flags & FULL_INIT_DONE)) {
 358                 err = cxgbe_up(adapter);
 359                 if (err < 0)
 360                         goto out;
 361         }
 362
 363         cxgbe_enable_rx_queues(pi);
 364
 365         err = setup_rss(pi);
 366         if (err)
 367                 goto out;
 368
 369         for (i = 0; i < pi->n_tx_qsets; i++) {
 370                 err = cxgbe_dev_tx_queue_start(eth_dev, i);
 371                 if (err)
 372                         goto out;
 373         }
 374
 375         for (i = 0; i < pi->n_rx_qsets; i++) {
 376                 err = cxgbe_dev_rx_queue_start(eth_dev, i);
 377                 if (err)
 378                         goto out;
 379         }
 380
 381         err = link_start(pi);
 382         if (err)
 383                 goto out;
 384
 385 out:
 386         return err;
 387 }
 388
 389 /*
 390  * Stop device: disable rx and tx functions to allow for reconfiguring.
 391  */
 392 void cxgbe_dev_stop(struct rte_eth_dev *eth_dev)
 393 {
 394         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 395         struct adapter *adapter = pi->adapter;
 396
 397         CXGBE_FUNC_TRACE();
 398
 399         if (!(adapter->flags & FULL_INIT_DONE))
 400                 return;
 401
 402         cxgbe_down(pi);
 403
 404         /*
 405          *  We clear queues only if both tx and rx path of the port
 406          *  have been disabled
 407          */
 408         t4_sge_eth_clear_queues(pi);
 409 }
 410
 411 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev)
 412 {
 413         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 414         struct adapter *adapter = pi->adapter;
 415         int err;
 416
 417         CXGBE_FUNC_TRACE();
 418
 419         if (!(adapter->flags & FW_QUEUE_BOUND)) {
 420                 err = setup_sge_fwevtq(adapter);
 421                 if (err)
 422                         return err;
 423                 adapter->flags |= FW_QUEUE_BOUND;
 424                 if (is_pf4(adapter)) {
 425                         err = setup_sge_ctrl_txq(adapter);
 426                         if (err)
 427                                 return err;
 428                 }
 429         }
 430
 431         err = cfg_queue_count(eth_dev);
 432         if (err)
 433                 return err;
 434
 435         return 0;
 436 }
 437
 438 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 439 {
 440         int ret;
 441         struct sge_eth_txq *txq = (struct sge_eth_txq *)
 442                                   (eth_dev->data->tx_queues[tx_queue_id]);
 443
 444         dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
 445
 446         ret = t4_sge_eth_txq_start(txq);
 447         if (ret == 0)
 448                 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 449
 450         return ret;
 451 }
 452
 453 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 454 {
 455         int ret;
 456         struct sge_eth_txq *txq = (struct sge_eth_txq *)
 457                                   (eth_dev->data->tx_queues[tx_queue_id]);
 458
 459         dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
 460
 461         ret = t4_sge_eth_txq_stop(txq);
 462         if (ret == 0)
 463                 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 464
 465         return ret;
 466 }
 467
 468 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
 469                              uint16_t queue_idx, uint16_t nb_desc,
 470                              unsigned int socket_id,
 471                              const struct rte_eth_txconf *tx_conf __rte_unused)
 472 {
 473         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 474         struct adapter *adapter = pi->adapter;
 475         struct sge *s = &adapter->sge;
 476         struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx];
 477         int err = 0;
 478         unsigned int temp_nb_desc;
 479
 480         dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n",
 481                   __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc,
 482                   socket_id, pi->first_qset);
 483
 484         /*  Free up the existing queue  */
 485         if (eth_dev->data->tx_queues[queue_idx]) {
 486                 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]);
 487                 eth_dev->data->tx_queues[queue_idx] = NULL;
 488         }
 489
 490         eth_dev->data->tx_queues[queue_idx] = (void *)txq;
 491
 492         /* Sanity Checking
 493          *
 494          * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE
 495          */
 496         temp_nb_desc = nb_desc;
 497         if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
 498                 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
 499                          __func__, CXGBE_MIN_RING_DESC_SIZE,
 500                          CXGBE_DEFAULT_TX_DESC_SIZE);
 501                 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE;
 502         } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
 503                 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
 504                         __func__, CXGBE_MIN_RING_DESC_SIZE,
 505                         CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE);
 506                 return -(EINVAL);
 507         }
 508
 509         txq->q.size = temp_nb_desc;
 510
 511         err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx,
 512                                    s->fw_evtq.cntxt_id, socket_id);
 513
 514         dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n",
 515                   __func__, txq->q.cntxt_id, txq->q.abs_id, err);
 516         return err;
 517 }
 518
 519 void cxgbe_dev_tx_queue_release(void *q)
 520 {
 521         struct sge_eth_txq *txq = (struct sge_eth_txq *)q;
 522
 523         if (txq) {
 524                 struct port_info *pi = (struct port_info *)
 525                                        (txq->eth_dev->data->dev_private);
 526                 struct adapter *adap = pi->adapter;
 527
 528                 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n",
 529                           __func__, pi->port_id, txq->q.cntxt_id);
 530
 531                 t4_sge_eth_txq_release(adap, txq);
 532         }
 533 }
 534
 535 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 536 {
 537         int ret;
 538         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 539         struct adapter *adap = pi->adapter;
 540         struct sge_rspq *q;
 541
 542         dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 543                   __func__, pi->port_id, rx_queue_id);
 544
 545         q = eth_dev->data->rx_queues[rx_queue_id];
 546
 547         ret = t4_sge_eth_rxq_start(adap, q);
 548         if (ret == 0)
 549                 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 550
 551         return ret;
 552 }
 553
 554 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 555 {
 556         int ret;
 557         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 558         struct adapter *adap = pi->adapter;
 559         struct sge_rspq *q;
 560
 561         dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 562                   __func__, pi->port_id, rx_queue_id);
 563
 564         q = eth_dev->data->rx_queues[rx_queue_id];
 565         ret = t4_sge_eth_rxq_stop(adap, q);
 566         if (ret == 0)
 567                 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 568
 569         return ret;
 570 }
 571
 572 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
 573                              uint16_t queue_idx, uint16_t nb_desc,
 574                              unsigned int socket_id,
 575                              const struct rte_eth_rxconf *rx_conf __rte_unused,
 576                              struct rte_mempool *mp)
 577 {
 578         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 579         struct adapter *adapter = pi->adapter;
 580         struct sge *s = &adapter->sge;
 581         struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset + queue_idx];
 582         int err = 0;
 583         int msi_idx = 0;
 584         unsigned int temp_nb_desc;
 585         struct rte_eth_dev_info dev_info;
 586         unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
 587
 588         dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n",
 589                   __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc,
 590                   socket_id, mp);
 591
 592         cxgbe_dev_info_get(eth_dev, &dev_info);
 593
 594         /* Must accommodate at least ETHER_MIN_MTU */
 595         if ((pkt_len < dev_info.min_rx_bufsize) ||
 596             (pkt_len > dev_info.max_rx_pktlen)) {
 597                 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n",
 598                         __func__, dev_info.min_rx_bufsize,
 599                         dev_info.max_rx_pktlen);
 600                 return -EINVAL;
 601         }
 602
 603         /*  Free up the existing queue  */
 604         if (eth_dev->data->rx_queues[queue_idx]) {
 605                 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]);
 606                 eth_dev->data->rx_queues[queue_idx] = NULL;
 607         }
 608
 609         eth_dev->data->rx_queues[queue_idx] = (void *)rxq;
 610
 611         /* Sanity Checking
 612          *
 613          * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE
 614          */
 615         temp_nb_desc = nb_desc;
 616         if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
 617                 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
 618                          __func__, CXGBE_MIN_RING_DESC_SIZE,
 619                          CXGBE_DEFAULT_RX_DESC_SIZE);
 620                 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE;
 621         } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
 622                 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
 623                         __func__, CXGBE_MIN_RING_DESC_SIZE,
 624                         CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE);
 625                 return -(EINVAL);
 626         }
 627
 628         rxq->rspq.size = temp_nb_desc;
 629         if ((&rxq->fl) != NULL)
 630                 rxq->fl.size = temp_nb_desc;
 631
 632         /* Set to jumbo mode if necessary */
 633         if (pkt_len > ETHER_MAX_LEN)
 634                 eth_dev->data->dev_conf.rxmode.offloads |=
 635                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 636         else
 637                 eth_dev->data->dev_conf.rxmode.offloads &=
 638                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 639
 640         err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx,
 641                                &rxq->fl, t4_ethrx_handler,
 642                                is_pf4(adapter) ?
 643                                t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp,
 644                                queue_idx, socket_id);
 645
 646         dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n",
 647                   __func__, err, pi->port_id, rxq->rspq.cntxt_id,
 648                   rxq->rspq.abs_id);
 649         return err;
 650 }
 651
 652 void cxgbe_dev_rx_queue_release(void *q)
 653 {
 654         struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q;
 655         struct sge_rspq *rq = &rxq->rspq;
 656
 657         if (rq) {
 658                 struct port_info *pi = (struct port_info *)
 659                                        (rq->eth_dev->data->dev_private);
 660                 struct adapter *adap = pi->adapter;
 661
 662                 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 663                           __func__, pi->port_id, rxq->rspq.cntxt_id);
 664
 665                 t4_sge_eth_rxq_release(adap, rxq);
 666         }
 667 }
 668
 669 /*
 670  * Get port statistics.
 671  */
 672 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev,
 673                                 struct rte_eth_stats *eth_stats)
 674 {
 675         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 676         struct adapter *adapter = pi->adapter;
 677         struct sge *s = &adapter->sge;
 678         struct port_stats ps;
 679         unsigned int i;
 680
 681         cxgbe_stats_get(pi, &ps);
 682
 683         /* RX Stats */
 684         eth_stats->imissed  = ps.rx_ovflow0 + ps.rx_ovflow1 +
 685                               ps.rx_ovflow2 + ps.rx_ovflow3 +
 686                               ps.rx_trunc0 + ps.rx_trunc1 +
 687                               ps.rx_trunc2 + ps.rx_trunc3;
 688         eth_stats->ierrors  = ps.rx_symbol_err + ps.rx_fcs_err +
 689                               ps.rx_jabber + ps.rx_too_long + ps.rx_runt +
 690                               ps.rx_len_err;
 691
 692         /* TX Stats */
 693         eth_stats->opackets = ps.tx_frames;
 694         eth_stats->obytes   = ps.tx_octets;
 695         eth_stats->oerrors  = ps.tx_error_frames;
 696
 697         for (i = 0; i < pi->n_rx_qsets; i++) {
 698                 struct sge_eth_rxq *rxq =
 699                         &s->ethrxq[pi->first_qset + i];
 700
 701                 eth_stats->q_ipackets[i] = rxq->stats.pkts;
 702                 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes;
 703                 eth_stats->ipackets += eth_stats->q_ipackets[i];
 704                 eth_stats->ibytes += eth_stats->q_ibytes[i];
 705         }
 706
 707         for (i = 0; i < pi->n_tx_qsets; i++) {
 708                 struct sge_eth_txq *txq =
 709                         &s->ethtxq[pi->first_qset + i];
 710
 711                 eth_stats->q_opackets[i] = txq->stats.pkts;
 712                 eth_stats->q_obytes[i] = txq->stats.tx_bytes;
 713                 eth_stats->q_errors[i] = txq->stats.mapping_err;
 714         }
 715         return 0;
 716 }
 717
 718 /*
 719  * Reset port statistics.
 720  */
 721 static void cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev)
 722 {
 723         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 724         struct adapter *adapter = pi->adapter;
 725         struct sge *s = &adapter->sge;
 726         unsigned int i;
 727
 728         cxgbe_stats_reset(pi);
 729         for (i = 0; i < pi->n_rx_qsets; i++) {
 730                 struct sge_eth_rxq *rxq =
 731                         &s->ethrxq[pi->first_qset + i];
 732
 733                 rxq->stats.pkts = 0;
 734                 rxq->stats.rx_bytes = 0;
 735         }
 736         for (i = 0; i < pi->n_tx_qsets; i++) {
 737                 struct sge_eth_txq *txq =
 738                         &s->ethtxq[pi->first_qset + i];
 739
 740                 txq->stats.pkts = 0;
 741                 txq->stats.tx_bytes = 0;
 742                 txq->stats.mapping_err = 0;
 743         }
 744 }
 745
 746 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev,
 747                                struct rte_eth_fc_conf *fc_conf)
 748 {
 749         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 750         struct link_config *lc = &pi->link_cfg;
 751         int rx_pause, tx_pause;
 752
 753         fc_conf->autoneg = lc->fc & PAUSE_AUTONEG;
 754         rx_pause = lc->fc & PAUSE_RX;
 755         tx_pause = lc->fc & PAUSE_TX;
 756
 757         if (rx_pause && tx_pause)
 758                 fc_conf->mode = RTE_FC_FULL;
 759         else if (rx_pause)
 760                 fc_conf->mode = RTE_FC_RX_PAUSE;
 761         else if (tx_pause)
 762                 fc_conf->mode = RTE_FC_TX_PAUSE;
 763         else
 764                 fc_conf->mode = RTE_FC_NONE;
 765         return 0;
 766 }
 767
 768 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev,
 769                                struct rte_eth_fc_conf *fc_conf)
 770 {
 771         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 772         struct adapter *adapter = pi->adapter;
 773         struct link_config *lc = &pi->link_cfg;
 774
 775         if (lc->pcaps & FW_PORT_CAP32_ANEG) {
 776                 if (fc_conf->autoneg)
 777                         lc->requested_fc |= PAUSE_AUTONEG;
 778                 else
 779                         lc->requested_fc &= ~PAUSE_AUTONEG;
 780         }
 781
 782         if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
 783             (fc_conf->mode & RTE_FC_RX_PAUSE))
 784                 lc->requested_fc |= PAUSE_RX;
 785         else
 786                 lc->requested_fc &= ~PAUSE_RX;
 787
 788         if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
 789             (fc_conf->mode & RTE_FC_TX_PAUSE))
 790                 lc->requested_fc |= PAUSE_TX;
 791         else
 792                 lc->requested_fc &= ~PAUSE_TX;
 793
 794         return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
 795                              &pi->link_cfg);
 796 }
 797
 798 const uint32_t *
 799 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
 800 {
 801         static const uint32_t ptypes[] = {
 802                 RTE_PTYPE_L3_IPV4,
 803                 RTE_PTYPE_L3_IPV6,
 804                 RTE_PTYPE_UNKNOWN
 805         };
 806
 807         if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts)
 808                 return ptypes;
 809         return NULL;
 810 }
 811
 812 /* Update RSS hash configuration
 813  */
 814 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
 815                                      struct rte_eth_rss_conf *rss_conf)
 816 {
 817         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
 818         struct adapter *adapter = pi->adapter;
 819         int err;
 820
 821         err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf);
 822         if (err)
 823                 return err;
 824
 825         pi->rss_hf = rss_conf->rss_hf;
 826
 827         if (rss_conf->rss_key) {
 828                 u32 key[10], mod_key[10];
 829                 int i, j;
 830
 831                 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN);
 832
 833                 for (i = 9, j = 0; i >= 0; i--, j++)
 834                         mod_key[j] = cpu_to_be32(key[i]);
 835
 836                 t4_write_rss_key(adapter, mod_key, -1);
 837         }
 838
 839         return 0;
 840 }
 841
 842 /* Get RSS hash configuration
 843  */
 844 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 845                                        struct rte_eth_rss_conf *rss_conf)
 846 {
 847         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
 848         struct adapter *adapter = pi->adapter;
 849         u64 rss_hf = 0;
 850         u64 flags = 0;
 851         int err;
 852
 853         err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid,
 854                                     &flags, NULL);
 855
 856         if (err)
 857                 return err;
 858
 859         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) {
 860                 rss_hf |= CXGBE_RSS_HF_TCP_IPV6_MASK;
 861                 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
 862                         rss_hf |= CXGBE_RSS_HF_UDP_IPV6_MASK;
 863         }
 864
 865         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
 866                 rss_hf |= CXGBE_RSS_HF_IPV6_MASK;
 867
 868         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) {
 869                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
 870                 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
 871                         rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
 872         }
 873
 874         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
 875                 rss_hf |= CXGBE_RSS_HF_IPV4_MASK;
 876
 877         rss_conf->rss_hf = rss_hf;
 878
 879         if (rss_conf->rss_key) {
 880                 u32 key[10], mod_key[10];
 881                 int i, j;
 882
 883                 t4_read_rss_key(adapter, key);
 884
 885                 for (i = 9, j = 0; i >= 0; i--, j++)
 886                         mod_key[j] = be32_to_cpu(key[i]);
 887
 888                 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN);
 889         }
 890
 891         return 0;
 892 }
 893
 894 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev)
 895 {
 896         RTE_SET_USED(dev);
 897         return EEPROMSIZE;
 898 }
 899
 900 /**
 901  * eeprom_ptov - translate a physical EEPROM address to virtual
 902  * @phys_addr: the physical EEPROM address
 903  * @fn: the PCI function number
 904  * @sz: size of function-specific area
 905  *
 906  * Translate a physical EEPROM address to virtual.  The first 1K is
 907  * accessed through virtual addresses starting at 31K, the rest is
 908  * accessed through virtual addresses starting at 0.
 909  *
 910  * The mapping is as follows:
 911  * [0..1K) -> [31K..32K)
 912  * [1K..1K+A) -> [31K-A..31K)
 913  * [1K+A..ES) -> [0..ES-A-1K)
 914  *
 915  * where A = @fn * @sz, and ES = EEPROM size.
 916  */
 917 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
 918 {
 919         fn *= sz;
 920         if (phys_addr < 1024)
 921                 return phys_addr + (31 << 10);
 922         if (phys_addr < 1024 + fn)
 923                 return fn + phys_addr - 1024;
 924         if (phys_addr < EEPROMSIZE)
 925                 return phys_addr - 1024 - fn;
 926         if (phys_addr < EEPROMVSIZE)
 927                 return phys_addr - 1024;
 928         return -EINVAL;
 929 }
 930
 931 /* The next two routines implement eeprom read/write from physical addresses.
 932  */
 933 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
 934 {
 935         int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
 936
 937         if (vaddr >= 0)
 938                 vaddr = t4_seeprom_read(adap, vaddr, v);
 939         return vaddr < 0 ? vaddr : 0;
 940 }
 941
 942 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
 943 {
 944         int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
 945
 946         if (vaddr >= 0)
 947                 vaddr = t4_seeprom_write(adap, vaddr, v);
 948         return vaddr < 0 ? vaddr : 0;
 949 }
 950
 951 #define EEPROM_MAGIC 0x38E2F10C
 952
 953 static int cxgbe_get_eeprom(struct rte_eth_dev *dev,
 954                             struct rte_dev_eeprom_info *e)
 955 {
 956         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
 957         struct adapter *adapter = pi->adapter;
 958         u32 i, err = 0;
 959         u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0);
 960
 961         if (!buf)
 962                 return -ENOMEM;
 963
 964         e->magic = EEPROM_MAGIC;
 965         for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4)
 966                 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
 967
 968         if (!err)
 969                 rte_memcpy(e->data, buf + e->offset, e->length);
 970         rte_free(buf);
 971         return err;
 972 }
 973
 974 static int cxgbe_set_eeprom(struct rte_eth_dev *dev,
 975                             struct rte_dev_eeprom_info *eeprom)
 976 {
 977         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
 978         struct adapter *adapter = pi->adapter;
 979         u8 *buf;
 980         int err = 0;
 981         u32 aligned_offset, aligned_len, *p;
 982
 983         if (eeprom->magic != EEPROM_MAGIC)
 984                 return -EINVAL;
 985
 986         aligned_offset = eeprom->offset & ~3;
 987         aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3;
 988
 989         if (adapter->pf > 0) {
 990                 u32 start = 1024 + adapter->pf * EEPROMPFSIZE;
 991
 992                 if (aligned_offset < start ||
 993                     aligned_offset + aligned_len > start + EEPROMPFSIZE)
 994                         return -EPERM;
 995         }
 996
 997         if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) {
 998                 /* RMW possibly needed for first or last words.
 999                  */
1000                 buf = rte_zmalloc(NULL, aligned_len, 0);
1001                 if (!buf)
1002                         return -ENOMEM;
1003                 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
1004                 if (!err && aligned_len > 4)
1005                         err = eeprom_rd_phys(adapter,
1006                                              aligned_offset + aligned_len - 4,
1007                                              (u32 *)&buf[aligned_len - 4]);
1008                 if (err)
1009                         goto out;
1010                 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data,
1011                            eeprom->length);
1012         } else {
1013                 buf = eeprom->data;
1014         }
1015
1016         err = t4_seeprom_wp(adapter, false);
1017         if (err)
1018                 goto out;
1019
1020         for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
1021                 err = eeprom_wr_phys(adapter, aligned_offset, *p);
1022                 aligned_offset += 4;
1023         }
1024
1025         if (!err)
1026                 err = t4_seeprom_wp(adapter, true);
1027 out:
1028         if (buf != eeprom->data)
1029                 rte_free(buf);
1030         return err;
1031 }
1032
1033 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev)
1034 {
1035         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1036         struct adapter *adapter = pi->adapter;
1037
1038         return t4_get_regs_len(adapter) / sizeof(uint32_t);
1039 }
1040
1041 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev,
1042                           struct rte_dev_reg_info *regs)
1043 {
1044         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1045         struct adapter *adapter = pi->adapter;
1046
1047         regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) |
1048                 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) |
1049                 (1 << 16);
1050
1051         if (regs->data == NULL) {
1052                 regs->length = cxgbe_get_regs_len(eth_dev);
1053                 regs->width = sizeof(uint32_t);
1054
1055                 return 0;
1056         }
1057
1058         t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t)));
1059
1060         return 0;
1061 }
1062
1063 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
1064 {
1065         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
1066         int ret;
1067
1068         ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt, (u8 *)addr);
1069         if (ret < 0) {
1070                 dev_err(adapter, "failed to set mac addr; err = %d\n",
1071                         ret);
1072                 return ret;
1073         }
1074         pi->xact_addr_filt = ret;
1075         return 0;
1076 }
1077
1078 static const struct eth_dev_ops cxgbe_eth_dev_ops = {
1079         .dev_start              = cxgbe_dev_start,
1080         .dev_stop               = cxgbe_dev_stop,
1081         .dev_close              = cxgbe_dev_close,
1082         .promiscuous_enable     = cxgbe_dev_promiscuous_enable,
1083         .promiscuous_disable    = cxgbe_dev_promiscuous_disable,
1084         .allmulticast_enable    = cxgbe_dev_allmulticast_enable,
1085         .allmulticast_disable   = cxgbe_dev_allmulticast_disable,
1086         .dev_configure          = cxgbe_dev_configure,
1087         .dev_infos_get          = cxgbe_dev_info_get,
1088         .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get,
1089         .link_update            = cxgbe_dev_link_update,
1090         .dev_set_link_up        = cxgbe_dev_set_link_up,
1091         .dev_set_link_down      = cxgbe_dev_set_link_down,
1092         .mtu_set                = cxgbe_dev_mtu_set,
1093         .tx_queue_setup         = cxgbe_dev_tx_queue_setup,
1094         .tx_queue_start         = cxgbe_dev_tx_queue_start,
1095         .tx_queue_stop          = cxgbe_dev_tx_queue_stop,
1096         .tx_queue_release       = cxgbe_dev_tx_queue_release,
1097         .rx_queue_setup         = cxgbe_dev_rx_queue_setup,
1098         .rx_queue_start         = cxgbe_dev_rx_queue_start,
1099         .rx_queue_stop          = cxgbe_dev_rx_queue_stop,
1100         .rx_queue_release       = cxgbe_dev_rx_queue_release,
1101         .filter_ctrl            = cxgbe_dev_filter_ctrl,
1102         .stats_get              = cxgbe_dev_stats_get,
1103         .stats_reset            = cxgbe_dev_stats_reset,
1104         .flow_ctrl_get          = cxgbe_flow_ctrl_get,
1105         .flow_ctrl_set          = cxgbe_flow_ctrl_set,
1106         .get_eeprom_length      = cxgbe_get_eeprom_length,
1107         .get_eeprom             = cxgbe_get_eeprom,
1108         .set_eeprom             = cxgbe_set_eeprom,
1109         .get_reg                = cxgbe_get_regs,
1110         .rss_hash_update        = cxgbe_dev_rss_hash_update,
1111         .rss_hash_conf_get      = cxgbe_dev_rss_hash_conf_get,
1112         .mac_addr_set           = cxgbe_mac_addr_set,
1113 };
1114
1115 /*
1116  * Initialize driver
1117  * It returns 0 on success.
1118  */
1119 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev)
1120 {
1121         struct rte_pci_device *pci_dev;
1122         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1123         struct adapter *adapter = NULL;
1124         char name[RTE_ETH_NAME_MAX_LEN];
1125         int err = 0;
1126
1127         CXGBE_FUNC_TRACE();
1128
1129         eth_dev->dev_ops = &cxgbe_eth_dev_ops;
1130         eth_dev->rx_pkt_burst = &cxgbe_recv_pkts;
1131         eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts;
1132         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1133
1134         /* for secondary processes, we attach to ethdevs allocated by primary
1135          * and do minimal initialization.
1136          */
1137         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1138                 int i;
1139
1140                 for (i = 1; i < MAX_NPORTS; i++) {
1141                         struct rte_eth_dev *rest_eth_dev;
1142                         char namei[RTE_ETH_NAME_MAX_LEN];
1143
1144                         snprintf(namei, sizeof(namei), "%s_%d",
1145                                  pci_dev->device.name, i);
1146                         rest_eth_dev = rte_eth_dev_attach_secondary(namei);
1147                         if (rest_eth_dev) {
1148                                 rest_eth_dev->device = &pci_dev->device;
1149                                 rest_eth_dev->dev_ops =
1150                                         eth_dev->dev_ops;
1151                                 rest_eth_dev->rx_pkt_burst =
1152                                         eth_dev->rx_pkt_burst;
1153                                 rest_eth_dev->tx_pkt_burst =
1154                                         eth_dev->tx_pkt_burst;
1155                                 rte_eth_dev_probing_finish(rest_eth_dev);
1156                         }
1157                 }
1158                 return 0;
1159         }
1160
1161         snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id);
1162         adapter = rte_zmalloc(name, sizeof(*adapter), 0);
1163         if (!adapter)
1164                 return -1;
1165
1166         adapter->use_unpacked_mode = 1;
1167         adapter->regs = (void *)pci_dev->mem_resource[0].addr;
1168         if (!adapter->regs) {
1169                 dev_err(adapter, "%s: cannot map device registers\n", __func__);
1170                 err = -ENOMEM;
1171                 goto out_free_adapter;
1172         }
1173         adapter->pdev = pci_dev;
1174         adapter->eth_dev = eth_dev;
1175         pi->adapter = adapter;
1176
1177         err = cxgbe_probe(adapter);
1178         if (err) {
1179                 dev_err(adapter, "%s: cxgbe probe failed with err %d\n",
1180                         __func__, err);
1181                 goto out_free_adapter;
1182         }
1183
1184         return 0;
1185
1186 out_free_adapter:
1187         rte_free(adapter);
1188         return err;
1189 }
1190
1191 static int eth_cxgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1192 {
1193         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1194         struct adapter *adap = pi->adapter;
1195
1196         /* Free up other ports and all resources */
1197         cxgbe_close(adap);
1198         return 0;
1199 }
1200
1201 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1202         struct rte_pci_device *pci_dev)
1203 {
1204         return rte_eth_dev_pci_generic_probe(pci_dev,
1205                 sizeof(struct port_info), eth_cxgbe_dev_init);
1206 }
1207
1208 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev)
1209 {
1210         return rte_eth_dev_pci_generic_remove(pci_dev, eth_cxgbe_dev_uninit);
1211 }
1212
1213 static struct rte_pci_driver rte_cxgbe_pmd = {
1214         .id_table = cxgb4_pci_tbl,
1215         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1216         .probe = eth_cxgbe_pci_probe,
1217         .remove = eth_cxgbe_pci_remove,
1218 };
1219
1220 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd);
1221 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl);
1222 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci");
1223 RTE_PMD_REGISTER_PARAM_STRING(net_cxgbe,
1224                               CXGBE_DEVARG_KEEP_OVLAN "=<0|1> "
1225                               CXGBE_DEVARG_FORCE_LINK_UP "=<0|1> ");