drivers/net/cxgbe/cxgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Chelsio Communications.
   3  * All rights reserved.
   4  */
   5
   6 #include <sys/queue.h>
   7 #include <stdio.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <string.h>
  11 #include <unistd.h>
  12 #include <stdarg.h>
  13 #include <inttypes.h>
  14 #include <netinet/in.h>
  15
  16 #include <rte_byteorder.h>
  17 #include <rte_common.h>
  18 #include <rte_cycles.h>
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_atomic.h>
  25 #include <rte_branch_prediction.h>
  26 #include <rte_memory.h>
  27 #include <rte_tailq.h>
  28 #include <rte_eal.h>
  29 #include <rte_alarm.h>
  30 #include <rte_ether.h>
  31 #include <rte_ethdev_driver.h>
  32 #include <rte_ethdev_pci.h>
  33 #include <rte_malloc.h>
  34 #include <rte_random.h>
  35 #include <rte_dev.h>
  36
  37 #include "cxgbe.h"
  38 #include "cxgbe_pfvf.h"
  39 #include "cxgbe_flow.h"
  40
  41 /*
  42  * Macros needed to support the PCI Device ID Table ...
  43  */
  44 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
  45         static const struct rte_pci_id cxgb4_pci_tbl[] = {
  46 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
  47
  48 #define PCI_VENDOR_ID_CHELSIO 0x1425
  49
  50 #define CH_PCI_ID_TABLE_ENTRY(devid) \
  51                 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) }
  52
  53 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
  54                 { .vendor_id = 0, } \
  55         }
  56
  57 /*
  58  *... and the PCI ID Table itself ...
  59  */
  60 #include "t4_pci_id_tbl.h"
  61
  62 #define CXGBE_TX_OFFLOADS (DEV_TX_OFFLOAD_VLAN_INSERT |\
  63                            DEV_TX_OFFLOAD_IPV4_CKSUM |\
  64                            DEV_TX_OFFLOAD_UDP_CKSUM |\
  65                            DEV_TX_OFFLOAD_TCP_CKSUM |\
  66                            DEV_TX_OFFLOAD_TCP_TSO)
  67
  68 #define CXGBE_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_STRIP |\
  69                            DEV_RX_OFFLOAD_CRC_STRIP |\
  70                            DEV_RX_OFFLOAD_IPV4_CKSUM |\
  71                            DEV_RX_OFFLOAD_JUMBO_FRAME |\
  72                            DEV_RX_OFFLOAD_UDP_CKSUM |\
  73                            DEV_RX_OFFLOAD_TCP_CKSUM)
  74
  75 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
  76                          uint16_t nb_pkts)
  77 {
  78         struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue;
  79         uint16_t pkts_sent, pkts_remain;
  80         uint16_t total_sent = 0;
  81         int ret = 0;
  82
  83         CXGBE_DEBUG_TX(adapter, "%s: txq = %p; tx_pkts = %p; nb_pkts = %d\n",
  84                        __func__, txq, tx_pkts, nb_pkts);
  85
  86         t4_os_lock(&txq->txq_lock);
  87         /* free up desc from already completed tx */
  88         reclaim_completed_tx(&txq->q);
  89         while (total_sent < nb_pkts) {
  90                 pkts_remain = nb_pkts - total_sent;
  91
  92                 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) {
  93                         ret = t4_eth_xmit(txq, tx_pkts[total_sent + pkts_sent],
  94                                           nb_pkts);
  95                         if (ret < 0)
  96                                 break;
  97                 }
  98                 if (!pkts_sent)
  99                         break;
 100                 total_sent += pkts_sent;
 101                 /* reclaim as much as possible */
 102                 reclaim_completed_tx(&txq->q);
 103         }
 104
 105         t4_os_unlock(&txq->txq_lock);
 106         return total_sent;
 107 }
 108
 109 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 110                          uint16_t nb_pkts)
 111 {
 112         struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue;
 113         unsigned int work_done;
 114
 115         CXGBE_DEBUG_RX(adapter, "%s: rxq->rspq.cntxt_id = %u; nb_pkts = %d\n",
 116                        __func__, rxq->rspq.cntxt_id, nb_pkts);
 117
 118         if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done))
 119                 dev_err(adapter, "error in cxgbe poll\n");
 120
 121         CXGBE_DEBUG_RX(adapter, "%s: work_done = %u\n", __func__, work_done);
 122         return work_done;
 123 }
 124
 125 void cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
 126                         struct rte_eth_dev_info *device_info)
 127 {
 128         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 129         struct adapter *adapter = pi->adapter;
 130         int max_queues = adapter->sge.max_ethqsets / adapter->params.nports;
 131
 132         static const struct rte_eth_desc_lim cxgbe_desc_lim = {
 133                 .nb_max = CXGBE_MAX_RING_DESC_SIZE,
 134                 .nb_min = CXGBE_MIN_RING_DESC_SIZE,
 135                 .nb_align = 1,
 136         };
 137
 138         device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE;
 139         device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN;
 140         device_info->max_rx_queues = max_queues;
 141         device_info->max_tx_queues = max_queues;
 142         device_info->max_mac_addrs = 1;
 143         /* XXX: For now we support one MAC/port */
 144         device_info->max_vfs = adapter->params.arch.vfcount;
 145         device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */
 146
 147         device_info->rx_queue_offload_capa = 0UL;
 148         device_info->rx_offload_capa = CXGBE_RX_OFFLOADS;
 149
 150         device_info->tx_queue_offload_capa = 0UL;
 151         device_info->tx_offload_capa = CXGBE_TX_OFFLOADS;
 152
 153         device_info->reta_size = pi->rss_size;
 154         device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN;
 155         device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL;
 156
 157         device_info->rx_desc_lim = cxgbe_desc_lim;
 158         device_info->tx_desc_lim = cxgbe_desc_lim;
 159         cxgbe_get_speed_caps(pi, &device_info->speed_capa);
 160 }
 161
 162 void cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
 163 {
 164         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 165         struct adapter *adapter = pi->adapter;
 166
 167         t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 168                       1, -1, 1, -1, false);
 169 }
 170
 171 void cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
 172 {
 173         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 174         struct adapter *adapter = pi->adapter;
 175
 176         t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 177                       0, -1, 1, -1, false);
 178 }
 179
 180 void cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
 181 {
 182         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 183         struct adapter *adapter = pi->adapter;
 184
 185         /* TODO: address filters ?? */
 186
 187         t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 188                       -1, 1, 1, -1, false);
 189 }
 190
 191 void cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
 192 {
 193         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 194         struct adapter *adapter = pi->adapter;
 195
 196         /* TODO: address filters ?? */
 197
 198         t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 199                       -1, 0, 1, -1, false);
 200 }
 201
 202 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev,
 203                           __rte_unused int wait_to_complete)
 204 {
 205         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 206         struct adapter *adapter = pi->adapter;
 207         struct sge *s = &adapter->sge;
 208         struct rte_eth_link new_link = { 0 };
 209         unsigned int work_done, budget = 4;
 210
 211         cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
 212
 213         new_link.link_status = force_linkup(adapter) ?
 214                                ETH_LINK_UP : pi->link_cfg.link_ok;
 215         new_link.link_autoneg = pi->link_cfg.autoneg;
 216         new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
 217         new_link.link_speed = pi->link_cfg.speed;
 218
 219         return rte_eth_linkstatus_set(eth_dev, &new_link);
 220 }
 221
 222 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
 223 {
 224         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 225         struct adapter *adapter = pi->adapter;
 226         struct rte_eth_dev_info dev_info;
 227         int err;
 228         uint16_t new_mtu = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
 229
 230         cxgbe_dev_info_get(eth_dev, &dev_info);
 231
 232         /* Must accommodate at least ETHER_MIN_MTU */
 233         if ((new_mtu < ETHER_MIN_MTU) || (new_mtu > dev_info.max_rx_pktlen))
 234                 return -EINVAL;
 235
 236         /* set to jumbo mode if needed */
 237         if (new_mtu > ETHER_MAX_LEN)
 238                 eth_dev->data->dev_conf.rxmode.offloads |=
 239                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 240         else
 241                 eth_dev->data->dev_conf.rxmode.offloads &=
 242                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 243
 244         err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1,
 245                             -1, -1, true);
 246         if (!err)
 247                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu;
 248
 249         return err;
 250 }
 251
 252 /*
 253  * Stop device.
 254  */
 255 void cxgbe_dev_close(struct rte_eth_dev *eth_dev)
 256 {
 257         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 258         struct adapter *adapter = pi->adapter;
 259
 260         CXGBE_FUNC_TRACE();
 261
 262         if (!(adapter->flags & FULL_INIT_DONE))
 263                 return;
 264
 265         cxgbe_down(pi);
 266
 267         /*
 268          *  We clear queues only if both tx and rx path of the port
 269          *  have been disabled
 270          */
 271         t4_sge_eth_clear_queues(pi);
 272 }
 273
 274 /* Start the device.
 275  * It returns 0 on success.
 276  */
 277 int cxgbe_dev_start(struct rte_eth_dev *eth_dev)
 278 {
 279         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 280         struct adapter *adapter = pi->adapter;
 281         int err = 0, i;
 282
 283         CXGBE_FUNC_TRACE();
 284
 285         /*
 286          * If we don't have a connection to the firmware there's nothing we
 287          * can do.
 288          */
 289         if (!(adapter->flags & FW_OK)) {
 290                 err = -ENXIO;
 291                 goto out;
 292         }
 293
 294         if (!(adapter->flags & FULL_INIT_DONE)) {
 295                 err = cxgbe_up(adapter);
 296                 if (err < 0)
 297                         goto out;
 298         }
 299
 300         cxgbe_enable_rx_queues(pi);
 301
 302         err = setup_rss(pi);
 303         if (err)
 304                 goto out;
 305
 306         for (i = 0; i < pi->n_tx_qsets; i++) {
 307                 err = cxgbe_dev_tx_queue_start(eth_dev, i);
 308                 if (err)
 309                         goto out;
 310         }
 311
 312         for (i = 0; i < pi->n_rx_qsets; i++) {
 313                 err = cxgbe_dev_rx_queue_start(eth_dev, i);
 314                 if (err)
 315                         goto out;
 316         }
 317
 318         err = link_start(pi);
 319         if (err)
 320                 goto out;
 321
 322 out:
 323         return err;
 324 }
 325
 326 /*
 327  * Stop device: disable rx and tx functions to allow for reconfiguring.
 328  */
 329 void cxgbe_dev_stop(struct rte_eth_dev *eth_dev)
 330 {
 331         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 332         struct adapter *adapter = pi->adapter;
 333
 334         CXGBE_FUNC_TRACE();
 335
 336         if (!(adapter->flags & FULL_INIT_DONE))
 337                 return;
 338
 339         cxgbe_down(pi);
 340
 341         /*
 342          *  We clear queues only if both tx and rx path of the port
 343          *  have been disabled
 344          */
 345         t4_sge_eth_clear_queues(pi);
 346 }
 347
 348 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev)
 349 {
 350         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 351         struct adapter *adapter = pi->adapter;
 352         uint64_t configured_offloads;
 353         int err;
 354
 355         CXGBE_FUNC_TRACE();
 356         configured_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 357         if (!(configured_offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
 358                 dev_info(adapter, "can't disable hw crc strip\n");
 359                 eth_dev->data->dev_conf.rxmode.offloads |=
 360                         DEV_RX_OFFLOAD_CRC_STRIP;
 361         }
 362
 363         if (!(adapter->flags & FW_QUEUE_BOUND)) {
 364                 err = setup_sge_fwevtq(adapter);
 365                 if (err)
 366                         return err;
 367                 adapter->flags |= FW_QUEUE_BOUND;
 368                 err = setup_sge_ctrl_txq(adapter);
 369                 if (err)
 370                         return err;
 371         }
 372
 373         err = cfg_queue_count(eth_dev);
 374         if (err)
 375                 return err;
 376
 377         return 0;
 378 }
 379
 380 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 381 {
 382         int ret;
 383         struct sge_eth_txq *txq = (struct sge_eth_txq *)
 384                                   (eth_dev->data->tx_queues[tx_queue_id]);
 385
 386         dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
 387
 388         ret = t4_sge_eth_txq_start(txq);
 389         if (ret == 0)
 390                 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 391
 392         return ret;
 393 }
 394
 395 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 396 {
 397         int ret;
 398         struct sge_eth_txq *txq = (struct sge_eth_txq *)
 399                                   (eth_dev->data->tx_queues[tx_queue_id]);
 400
 401         dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
 402
 403         ret = t4_sge_eth_txq_stop(txq);
 404         if (ret == 0)
 405                 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 406
 407         return ret;
 408 }
 409
 410 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
 411                              uint16_t queue_idx, uint16_t nb_desc,
 412                              unsigned int socket_id,
 413                              const struct rte_eth_txconf *tx_conf __rte_unused)
 414 {
 415         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 416         struct adapter *adapter = pi->adapter;
 417         struct sge *s = &adapter->sge;
 418         struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx];
 419         int err = 0;
 420         unsigned int temp_nb_desc;
 421
 422         dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n",
 423                   __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc,
 424                   socket_id, pi->first_qset);
 425
 426         /*  Free up the existing queue  */
 427         if (eth_dev->data->tx_queues[queue_idx]) {
 428                 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]);
 429                 eth_dev->data->tx_queues[queue_idx] = NULL;
 430         }
 431
 432         eth_dev->data->tx_queues[queue_idx] = (void *)txq;
 433
 434         /* Sanity Checking
 435          *
 436          * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE
 437          */
 438         temp_nb_desc = nb_desc;
 439         if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
 440                 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
 441                          __func__, CXGBE_MIN_RING_DESC_SIZE,
 442                          CXGBE_DEFAULT_TX_DESC_SIZE);
 443                 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE;
 444         } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
 445                 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
 446                         __func__, CXGBE_MIN_RING_DESC_SIZE,
 447                         CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE);
 448                 return -(EINVAL);
 449         }
 450
 451         txq->q.size = temp_nb_desc;
 452
 453         err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx,
 454                                    s->fw_evtq.cntxt_id, socket_id);
 455
 456         dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n",
 457                   __func__, txq->q.cntxt_id, txq->q.abs_id, err);
 458         return err;
 459 }
 460
 461 void cxgbe_dev_tx_queue_release(void *q)
 462 {
 463         struct sge_eth_txq *txq = (struct sge_eth_txq *)q;
 464
 465         if (txq) {
 466                 struct port_info *pi = (struct port_info *)
 467                                        (txq->eth_dev->data->dev_private);
 468                 struct adapter *adap = pi->adapter;
 469
 470                 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n",
 471                           __func__, pi->port_id, txq->q.cntxt_id);
 472
 473                 t4_sge_eth_txq_release(adap, txq);
 474         }
 475 }
 476
 477 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 478 {
 479         int ret;
 480         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 481         struct adapter *adap = pi->adapter;
 482         struct sge_rspq *q;
 483
 484         dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 485                   __func__, pi->port_id, rx_queue_id);
 486
 487         q = eth_dev->data->rx_queues[rx_queue_id];
 488
 489         ret = t4_sge_eth_rxq_start(adap, q);
 490         if (ret == 0)
 491                 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 492
 493         return ret;
 494 }
 495
 496 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 497 {
 498         int ret;
 499         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 500         struct adapter *adap = pi->adapter;
 501         struct sge_rspq *q;
 502
 503         dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 504                   __func__, pi->port_id, rx_queue_id);
 505
 506         q = eth_dev->data->rx_queues[rx_queue_id];
 507         ret = t4_sge_eth_rxq_stop(adap, q);
 508         if (ret == 0)
 509                 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 510
 511         return ret;
 512 }
 513
 514 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
 515                              uint16_t queue_idx, uint16_t nb_desc,
 516                              unsigned int socket_id,
 517                              const struct rte_eth_rxconf *rx_conf __rte_unused,
 518                              struct rte_mempool *mp)
 519 {
 520         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 521         struct adapter *adapter = pi->adapter;
 522         struct sge *s = &adapter->sge;
 523         struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset + queue_idx];
 524         int err = 0;
 525         int msi_idx = 0;
 526         unsigned int temp_nb_desc;
 527         struct rte_eth_dev_info dev_info;
 528         unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
 529
 530         dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n",
 531                   __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc,
 532                   socket_id, mp);
 533
 534         cxgbe_dev_info_get(eth_dev, &dev_info);
 535
 536         /* Must accommodate at least ETHER_MIN_MTU */
 537         if ((pkt_len < dev_info.min_rx_bufsize) ||
 538             (pkt_len > dev_info.max_rx_pktlen)) {
 539                 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n",
 540                         __func__, dev_info.min_rx_bufsize,
 541                         dev_info.max_rx_pktlen);
 542                 return -EINVAL;
 543         }
 544
 545         /*  Free up the existing queue  */
 546         if (eth_dev->data->rx_queues[queue_idx]) {
 547                 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]);
 548                 eth_dev->data->rx_queues[queue_idx] = NULL;
 549         }
 550
 551         eth_dev->data->rx_queues[queue_idx] = (void *)rxq;
 552
 553         /* Sanity Checking
 554          *
 555          * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE
 556          */
 557         temp_nb_desc = nb_desc;
 558         if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
 559                 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
 560                          __func__, CXGBE_MIN_RING_DESC_SIZE,
 561                          CXGBE_DEFAULT_RX_DESC_SIZE);
 562                 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE;
 563         } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
 564                 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
 565                         __func__, CXGBE_MIN_RING_DESC_SIZE,
 566                         CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE);
 567                 return -(EINVAL);
 568         }
 569
 570         rxq->rspq.size = temp_nb_desc;
 571         if ((&rxq->fl) != NULL)
 572                 rxq->fl.size = temp_nb_desc;
 573
 574         /* Set to jumbo mode if necessary */
 575         if (pkt_len > ETHER_MAX_LEN)
 576                 eth_dev->data->dev_conf.rxmode.offloads |=
 577                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 578         else
 579                 eth_dev->data->dev_conf.rxmode.offloads &=
 580                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 581
 582         err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx,
 583                                &rxq->fl, t4_ethrx_handler,
 584                                is_pf4(adapter) ?
 585                                t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp,
 586                                queue_idx, socket_id);
 587
 588         dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n",
 589                   __func__, err, pi->port_id, rxq->rspq.cntxt_id,
 590                   rxq->rspq.abs_id);
 591         return err;
 592 }
 593
 594 void cxgbe_dev_rx_queue_release(void *q)
 595 {
 596         struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q;
 597         struct sge_rspq *rq = &rxq->rspq;
 598
 599         if (rq) {
 600                 struct port_info *pi = (struct port_info *)
 601                                        (rq->eth_dev->data->dev_private);
 602                 struct adapter *adap = pi->adapter;
 603
 604                 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 605                           __func__, pi->port_id, rxq->rspq.cntxt_id);
 606
 607                 t4_sge_eth_rxq_release(adap, rxq);
 608         }
 609 }
 610
 611 /*
 612  * Get port statistics.
 613  */
 614 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev,
 615                                 struct rte_eth_stats *eth_stats)
 616 {
 617         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 618         struct adapter *adapter = pi->adapter;
 619         struct sge *s = &adapter->sge;
 620         struct port_stats ps;
 621         unsigned int i;
 622
 623         cxgbe_stats_get(pi, &ps);
 624
 625         /* RX Stats */
 626         eth_stats->imissed  = ps.rx_ovflow0 + ps.rx_ovflow1 +
 627                               ps.rx_ovflow2 + ps.rx_ovflow3 +
 628                               ps.rx_trunc0 + ps.rx_trunc1 +
 629                               ps.rx_trunc2 + ps.rx_trunc3;
 630         eth_stats->ierrors  = ps.rx_symbol_err + ps.rx_fcs_err +
 631                               ps.rx_jabber + ps.rx_too_long + ps.rx_runt +
 632                               ps.rx_len_err;
 633
 634         /* TX Stats */
 635         eth_stats->opackets = ps.tx_frames;
 636         eth_stats->obytes   = ps.tx_octets;
 637         eth_stats->oerrors  = ps.tx_error_frames;
 638
 639         for (i = 0; i < pi->n_rx_qsets; i++) {
 640                 struct sge_eth_rxq *rxq =
 641                         &s->ethrxq[pi->first_qset + i];
 642
 643                 eth_stats->q_ipackets[i] = rxq->stats.pkts;
 644                 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes;
 645                 eth_stats->ipackets += eth_stats->q_ipackets[i];
 646                 eth_stats->ibytes += eth_stats->q_ibytes[i];
 647         }
 648
 649         for (i = 0; i < pi->n_tx_qsets; i++) {
 650                 struct sge_eth_txq *txq =
 651                         &s->ethtxq[pi->first_qset + i];
 652
 653                 eth_stats->q_opackets[i] = txq->stats.pkts;
 654                 eth_stats->q_obytes[i] = txq->stats.tx_bytes;
 655                 eth_stats->q_errors[i] = txq->stats.mapping_err;
 656         }
 657         return 0;
 658 }
 659
 660 /*
 661  * Reset port statistics.
 662  */
 663 static void cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev)
 664 {
 665         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 666         struct adapter *adapter = pi->adapter;
 667         struct sge *s = &adapter->sge;
 668         unsigned int i;
 669
 670         cxgbe_stats_reset(pi);
 671         for (i = 0; i < pi->n_rx_qsets; i++) {
 672                 struct sge_eth_rxq *rxq =
 673                         &s->ethrxq[pi->first_qset + i];
 674
 675                 rxq->stats.pkts = 0;
 676                 rxq->stats.rx_bytes = 0;
 677         }
 678         for (i = 0; i < pi->n_tx_qsets; i++) {
 679                 struct sge_eth_txq *txq =
 680                         &s->ethtxq[pi->first_qset + i];
 681
 682                 txq->stats.pkts = 0;
 683                 txq->stats.tx_bytes = 0;
 684                 txq->stats.mapping_err = 0;
 685         }
 686 }
 687
 688 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev,
 689                                struct rte_eth_fc_conf *fc_conf)
 690 {
 691         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 692         struct link_config *lc = &pi->link_cfg;
 693         int rx_pause, tx_pause;
 694
 695         fc_conf->autoneg = lc->fc & PAUSE_AUTONEG;
 696         rx_pause = lc->fc & PAUSE_RX;
 697         tx_pause = lc->fc & PAUSE_TX;
 698
 699         if (rx_pause && tx_pause)
 700                 fc_conf->mode = RTE_FC_FULL;
 701         else if (rx_pause)
 702                 fc_conf->mode = RTE_FC_RX_PAUSE;
 703         else if (tx_pause)
 704                 fc_conf->mode = RTE_FC_TX_PAUSE;
 705         else
 706                 fc_conf->mode = RTE_FC_NONE;
 707         return 0;
 708 }
 709
 710 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev,
 711                                struct rte_eth_fc_conf *fc_conf)
 712 {
 713         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 714         struct adapter *adapter = pi->adapter;
 715         struct link_config *lc = &pi->link_cfg;
 716
 717         if (lc->pcaps & FW_PORT_CAP32_ANEG) {
 718                 if (fc_conf->autoneg)
 719                         lc->requested_fc |= PAUSE_AUTONEG;
 720                 else
 721                         lc->requested_fc &= ~PAUSE_AUTONEG;
 722         }
 723
 724         if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
 725             (fc_conf->mode & RTE_FC_RX_PAUSE))
 726                 lc->requested_fc |= PAUSE_RX;
 727         else
 728                 lc->requested_fc &= ~PAUSE_RX;
 729
 730         if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
 731             (fc_conf->mode & RTE_FC_TX_PAUSE))
 732                 lc->requested_fc |= PAUSE_TX;
 733         else
 734                 lc->requested_fc &= ~PAUSE_TX;
 735
 736         return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
 737                              &pi->link_cfg);
 738 }
 739
 740 const uint32_t *
 741 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
 742 {
 743         static const uint32_t ptypes[] = {
 744                 RTE_PTYPE_L3_IPV4,
 745                 RTE_PTYPE_L3_IPV6,
 746                 RTE_PTYPE_UNKNOWN
 747         };
 748
 749         if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts)
 750                 return ptypes;
 751         return NULL;
 752 }
 753
 754 /* Update RSS hash configuration
 755  */
 756 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
 757                                      struct rte_eth_rss_conf *rss_conf)
 758 {
 759         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
 760         struct adapter *adapter = pi->adapter;
 761         int err;
 762
 763         err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf);
 764         if (err)
 765                 return err;
 766
 767         pi->rss_hf = rss_conf->rss_hf;
 768
 769         if (rss_conf->rss_key) {
 770                 u32 key[10], mod_key[10];
 771                 int i, j;
 772
 773                 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN);
 774
 775                 for (i = 9, j = 0; i >= 0; i--, j++)
 776                         mod_key[j] = cpu_to_be32(key[i]);
 777
 778                 t4_write_rss_key(adapter, mod_key, -1);
 779         }
 780
 781         return 0;
 782 }
 783
 784 /* Get RSS hash configuration
 785  */
 786 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 787                                        struct rte_eth_rss_conf *rss_conf)
 788 {
 789         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
 790         struct adapter *adapter = pi->adapter;
 791         u64 rss_hf = 0;
 792         u64 flags = 0;
 793         int err;
 794
 795         err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid,
 796                                     &flags, NULL);
 797
 798         if (err)
 799                 return err;
 800
 801         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) {
 802                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
 803                 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
 804                         rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
 805         }
 806
 807         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
 808                 rss_hf |= ETH_RSS_IPV6;
 809
 810         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) {
 811                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
 812                 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
 813                         rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
 814         }
 815
 816         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
 817                 rss_hf |= ETH_RSS_IPV4;
 818
 819         rss_conf->rss_hf = rss_hf;
 820
 821         if (rss_conf->rss_key) {
 822                 u32 key[10], mod_key[10];
 823                 int i, j;
 824
 825                 t4_read_rss_key(adapter, key);
 826
 827                 for (i = 9, j = 0; i >= 0; i--, j++)
 828                         mod_key[j] = be32_to_cpu(key[i]);
 829
 830                 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN);
 831         }
 832
 833         return 0;
 834 }
 835
 836 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev)
 837 {
 838         RTE_SET_USED(dev);
 839         return EEPROMSIZE;
 840 }
 841
 842 /**
 843  * eeprom_ptov - translate a physical EEPROM address to virtual
 844  * @phys_addr: the physical EEPROM address
 845  * @fn: the PCI function number
 846  * @sz: size of function-specific area
 847  *
 848  * Translate a physical EEPROM address to virtual.  The first 1K is
 849  * accessed through virtual addresses starting at 31K, the rest is
 850  * accessed through virtual addresses starting at 0.
 851  *
 852  * The mapping is as follows:
 853  * [0..1K) -> [31K..32K)
 854  * [1K..1K+A) -> [31K-A..31K)
 855  * [1K+A..ES) -> [0..ES-A-1K)
 856  *
 857  * where A = @fn * @sz, and ES = EEPROM size.
 858  */
 859 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
 860 {
 861         fn *= sz;
 862         if (phys_addr < 1024)
 863                 return phys_addr + (31 << 10);
 864         if (phys_addr < 1024 + fn)
 865                 return fn + phys_addr - 1024;
 866         if (phys_addr < EEPROMSIZE)
 867                 return phys_addr - 1024 - fn;
 868         if (phys_addr < EEPROMVSIZE)
 869                 return phys_addr - 1024;
 870         return -EINVAL;
 871 }
 872
 873 /* The next two routines implement eeprom read/write from physical addresses.
 874  */
 875 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
 876 {
 877         int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
 878
 879         if (vaddr >= 0)
 880                 vaddr = t4_seeprom_read(adap, vaddr, v);
 881         return vaddr < 0 ? vaddr : 0;
 882 }
 883
 884 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
 885 {
 886         int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
 887
 888         if (vaddr >= 0)
 889                 vaddr = t4_seeprom_write(adap, vaddr, v);
 890         return vaddr < 0 ? vaddr : 0;
 891 }
 892
 893 #define EEPROM_MAGIC 0x38E2F10C
 894
 895 static int cxgbe_get_eeprom(struct rte_eth_dev *dev,
 896                             struct rte_dev_eeprom_info *e)
 897 {
 898         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
 899         struct adapter *adapter = pi->adapter;
 900         u32 i, err = 0;
 901         u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0);
 902
 903         if (!buf)
 904                 return -ENOMEM;
 905
 906         e->magic = EEPROM_MAGIC;
 907         for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4)
 908                 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
 909
 910         if (!err)
 911                 rte_memcpy(e->data, buf + e->offset, e->length);
 912         rte_free(buf);
 913         return err;
 914 }
 915
 916 static int cxgbe_set_eeprom(struct rte_eth_dev *dev,
 917                             struct rte_dev_eeprom_info *eeprom)
 918 {
 919         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
 920         struct adapter *adapter = pi->adapter;
 921         u8 *buf;
 922         int err = 0;
 923         u32 aligned_offset, aligned_len, *p;
 924
 925         if (eeprom->magic != EEPROM_MAGIC)
 926                 return -EINVAL;
 927
 928         aligned_offset = eeprom->offset & ~3;
 929         aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3;
 930
 931         if (adapter->pf > 0) {
 932                 u32 start = 1024 + adapter->pf * EEPROMPFSIZE;
 933
 934                 if (aligned_offset < start ||
 935                     aligned_offset + aligned_len > start + EEPROMPFSIZE)
 936                         return -EPERM;
 937         }
 938
 939         if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) {
 940                 /* RMW possibly needed for first or last words.
 941                  */
 942                 buf = rte_zmalloc(NULL, aligned_len, 0);
 943                 if (!buf)
 944                         return -ENOMEM;
 945                 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
 946                 if (!err && aligned_len > 4)
 947                         err = eeprom_rd_phys(adapter,
 948                                              aligned_offset + aligned_len - 4,
 949                                              (u32 *)&buf[aligned_len - 4]);
 950                 if (err)
 951                         goto out;
 952                 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data,
 953                            eeprom->length);
 954         } else {
 955                 buf = eeprom->data;
 956         }
 957
 958         err = t4_seeprom_wp(adapter, false);
 959         if (err)
 960                 goto out;
 961
 962         for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
 963                 err = eeprom_wr_phys(adapter, aligned_offset, *p);
 964                 aligned_offset += 4;
 965         }
 966
 967         if (!err)
 968                 err = t4_seeprom_wp(adapter, true);
 969 out:
 970         if (buf != eeprom->data)
 971                 rte_free(buf);
 972         return err;
 973 }
 974
 975 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev)
 976 {
 977         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 978         struct adapter *adapter = pi->adapter;
 979
 980         return t4_get_regs_len(adapter) / sizeof(uint32_t);
 981 }
 982
 983 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev,
 984                           struct rte_dev_reg_info *regs)
 985 {
 986         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 987         struct adapter *adapter = pi->adapter;
 988
 989         regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) |
 990                 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) |
 991                 (1 << 16);
 992
 993         if (regs->data == NULL) {
 994                 regs->length = cxgbe_get_regs_len(eth_dev);
 995                 regs->width = sizeof(uint32_t);
 996
 997                 return 0;
 998         }
 999
1000         t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t)));
1001
1002         return 0;
1003 }
1004
1005 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
1006 {
1007         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
1008         struct adapter *adapter = pi->adapter;
1009         int ret;
1010
1011         ret = t4_change_mac(adapter, adapter->mbox, pi->viid,
1012                             pi->xact_addr_filt, (u8 *)addr, true, true);
1013         if (ret < 0) {
1014                 dev_err(adapter, "failed to set mac addr; err = %d\n",
1015                         ret);
1016                 return ret;
1017         }
1018         pi->xact_addr_filt = ret;
1019         return 0;
1020 }
1021
1022 static const struct eth_dev_ops cxgbe_eth_dev_ops = {
1023         .dev_start              = cxgbe_dev_start,
1024         .dev_stop               = cxgbe_dev_stop,
1025         .dev_close              = cxgbe_dev_close,
1026         .promiscuous_enable     = cxgbe_dev_promiscuous_enable,
1027         .promiscuous_disable    = cxgbe_dev_promiscuous_disable,
1028         .allmulticast_enable    = cxgbe_dev_allmulticast_enable,
1029         .allmulticast_disable   = cxgbe_dev_allmulticast_disable,
1030         .dev_configure          = cxgbe_dev_configure,
1031         .dev_infos_get          = cxgbe_dev_info_get,
1032         .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get,
1033         .link_update            = cxgbe_dev_link_update,
1034         .mtu_set                = cxgbe_dev_mtu_set,
1035         .tx_queue_setup         = cxgbe_dev_tx_queue_setup,
1036         .tx_queue_start         = cxgbe_dev_tx_queue_start,
1037         .tx_queue_stop          = cxgbe_dev_tx_queue_stop,
1038         .tx_queue_release       = cxgbe_dev_tx_queue_release,
1039         .rx_queue_setup         = cxgbe_dev_rx_queue_setup,
1040         .rx_queue_start         = cxgbe_dev_rx_queue_start,
1041         .rx_queue_stop          = cxgbe_dev_rx_queue_stop,
1042         .rx_queue_release       = cxgbe_dev_rx_queue_release,
1043         .filter_ctrl            = cxgbe_dev_filter_ctrl,
1044         .stats_get              = cxgbe_dev_stats_get,
1045         .stats_reset            = cxgbe_dev_stats_reset,
1046         .flow_ctrl_get          = cxgbe_flow_ctrl_get,
1047         .flow_ctrl_set          = cxgbe_flow_ctrl_set,
1048         .get_eeprom_length      = cxgbe_get_eeprom_length,
1049         .get_eeprom             = cxgbe_get_eeprom,
1050         .set_eeprom             = cxgbe_set_eeprom,
1051         .get_reg                = cxgbe_get_regs,
1052         .rss_hash_update        = cxgbe_dev_rss_hash_update,
1053         .rss_hash_conf_get      = cxgbe_dev_rss_hash_conf_get,
1054         .mac_addr_set           = cxgbe_mac_addr_set,
1055 };
1056
1057 /*
1058  * Initialize driver
1059  * It returns 0 on success.
1060  */
1061 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev)
1062 {
1063         struct rte_pci_device *pci_dev;
1064         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1065         struct adapter *adapter = NULL;
1066         char name[RTE_ETH_NAME_MAX_LEN];
1067         int err = 0;
1068
1069         CXGBE_FUNC_TRACE();
1070
1071         eth_dev->dev_ops = &cxgbe_eth_dev_ops;
1072         eth_dev->rx_pkt_burst = &cxgbe_recv_pkts;
1073         eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts;
1074         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1075
1076         /* for secondary processes, we attach to ethdevs allocated by primary
1077          * and do minimal initialization.
1078          */
1079         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1080                 int i;
1081
1082                 for (i = 1; i < MAX_NPORTS; i++) {
1083                         struct rte_eth_dev *rest_eth_dev;
1084                         char namei[RTE_ETH_NAME_MAX_LEN];
1085
1086                         snprintf(namei, sizeof(namei), "%s_%d",
1087                                  pci_dev->device.name, i);
1088                         rest_eth_dev = rte_eth_dev_attach_secondary(namei);
1089                         if (rest_eth_dev) {
1090                                 rest_eth_dev->device = &pci_dev->device;
1091                                 rest_eth_dev->dev_ops =
1092                                         eth_dev->dev_ops;
1093                                 rest_eth_dev->rx_pkt_burst =
1094                                         eth_dev->rx_pkt_burst;
1095                                 rest_eth_dev->tx_pkt_burst =
1096                                         eth_dev->tx_pkt_burst;
1097                                 rte_eth_dev_probing_finish(rest_eth_dev);
1098                         }
1099                 }
1100                 return 0;
1101         }
1102
1103         snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id);
1104         adapter = rte_zmalloc(name, sizeof(*adapter), 0);
1105         if (!adapter)
1106                 return -1;
1107
1108         adapter->use_unpacked_mode = 1;
1109         adapter->regs = (void *)pci_dev->mem_resource[0].addr;
1110         if (!adapter->regs) {
1111                 dev_err(adapter, "%s: cannot map device registers\n", __func__);
1112                 err = -ENOMEM;
1113                 goto out_free_adapter;
1114         }
1115         adapter->pdev = pci_dev;
1116         adapter->eth_dev = eth_dev;
1117         pi->adapter = adapter;
1118
1119         err = cxgbe_probe(adapter);
1120         if (err) {
1121                 dev_err(adapter, "%s: cxgbe probe failed with err %d\n",
1122                         __func__, err);
1123                 goto out_free_adapter;
1124         }
1125
1126         return 0;
1127
1128 out_free_adapter:
1129         rte_free(adapter);
1130         return err;
1131 }
1132
1133 static int eth_cxgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1134 {
1135         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1136         struct adapter *adap = pi->adapter;
1137
1138         /* Free up other ports and all resources */
1139         cxgbe_close(adap);
1140         return 0;
1141 }
1142
1143 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1144         struct rte_pci_device *pci_dev)
1145 {
1146         return rte_eth_dev_pci_generic_probe(pci_dev,
1147                 sizeof(struct port_info), eth_cxgbe_dev_init);
1148 }
1149
1150 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev)
1151 {
1152         return rte_eth_dev_pci_generic_remove(pci_dev, eth_cxgbe_dev_uninit);
1153 }
1154
1155 static struct rte_pci_driver rte_cxgbe_pmd = {
1156         .id_table = cxgb4_pci_tbl,
1157         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1158         .probe = eth_cxgbe_pci_probe,
1159         .remove = eth_cxgbe_pci_remove,
1160 };
1161
1162 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd);
1163 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl);
1164 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci");
1165 RTE_PMD_REGISTER_PARAM_STRING(net_cxgbe,
1166                               CXGBE_DEVARG_KEEP_OVLAN "=<0|1> "
1167                               CXGBE_DEVARG_FORCE_LINK_UP "=<0|1> ");