drivers/net/cxgbe/cxgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Chelsio Communications.
   3  * All rights reserved.
   4  */
   5
   6 #include <sys/queue.h>
   7 #include <stdio.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <string.h>
  11 #include <unistd.h>
  12 #include <stdarg.h>
  13 #include <inttypes.h>
  14 #include <netinet/in.h>
  15
  16 #include <rte_byteorder.h>
  17 #include <rte_common.h>
  18 #include <rte_cycles.h>
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_atomic.h>
  25 #include <rte_branch_prediction.h>
  26 #include <rte_memory.h>
  27 #include <rte_tailq.h>
  28 #include <rte_eal.h>
  29 #include <rte_alarm.h>
  30 #include <rte_ether.h>
  31 #include <rte_ethdev_driver.h>
  32 #include <rte_ethdev_pci.h>
  33 #include <rte_malloc.h>
  34 #include <rte_random.h>
  35 #include <rte_dev.h>
  36
  37 #include "cxgbe.h"
  38 #include "cxgbe_pfvf.h"
  39
  40 /*
  41  * Macros needed to support the PCI Device ID Table ...
  42  */
  43 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
  44         static const struct rte_pci_id cxgb4_pci_tbl[] = {
  45 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
  46
  47 #define PCI_VENDOR_ID_CHELSIO 0x1425
  48
  49 #define CH_PCI_ID_TABLE_ENTRY(devid) \
  50                 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) }
  51
  52 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
  53                 { .vendor_id = 0, } \
  54         }
  55
  56 /*
  57  *... and the PCI ID Table itself ...
  58  */
  59 #include "t4_pci_id_tbl.h"
  60
  61 #define CXGBE_TX_OFFLOADS (DEV_TX_OFFLOAD_VLAN_INSERT |\
  62                            DEV_TX_OFFLOAD_IPV4_CKSUM |\
  63                            DEV_TX_OFFLOAD_UDP_CKSUM |\
  64                            DEV_TX_OFFLOAD_TCP_CKSUM |\
  65                            DEV_TX_OFFLOAD_TCP_TSO)
  66
  67 #define CXGBE_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_STRIP |\
  68                            DEV_RX_OFFLOAD_CRC_STRIP |\
  69                            DEV_RX_OFFLOAD_IPV4_CKSUM |\
  70                            DEV_RX_OFFLOAD_JUMBO_FRAME |\
  71                            DEV_RX_OFFLOAD_UDP_CKSUM |\
  72                            DEV_RX_OFFLOAD_TCP_CKSUM)
  73
  74 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
  75                          uint16_t nb_pkts)
  76 {
  77         struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue;
  78         uint16_t pkts_sent, pkts_remain;
  79         uint16_t total_sent = 0;
  80         int ret = 0;
  81
  82         CXGBE_DEBUG_TX(adapter, "%s: txq = %p; tx_pkts = %p; nb_pkts = %d\n",
  83                        __func__, txq, tx_pkts, nb_pkts);
  84
  85         t4_os_lock(&txq->txq_lock);
  86         /* free up desc from already completed tx */
  87         reclaim_completed_tx(&txq->q);
  88         while (total_sent < nb_pkts) {
  89                 pkts_remain = nb_pkts - total_sent;
  90
  91                 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) {
  92                         ret = t4_eth_xmit(txq, tx_pkts[total_sent + pkts_sent],
  93                                           nb_pkts);
  94                         if (ret < 0)
  95                                 break;
  96                 }
  97                 if (!pkts_sent)
  98                         break;
  99                 total_sent += pkts_sent;
 100                 /* reclaim as much as possible */
 101                 reclaim_completed_tx(&txq->q);
 102         }
 103
 104         t4_os_unlock(&txq->txq_lock);
 105         return total_sent;
 106 }
 107
 108 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 109                          uint16_t nb_pkts)
 110 {
 111         struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue;
 112         unsigned int work_done;
 113
 114         CXGBE_DEBUG_RX(adapter, "%s: rxq->rspq.cntxt_id = %u; nb_pkts = %d\n",
 115                        __func__, rxq->rspq.cntxt_id, nb_pkts);
 116
 117         if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done))
 118                 dev_err(adapter, "error in cxgbe poll\n");
 119
 120         CXGBE_DEBUG_RX(adapter, "%s: work_done = %u\n", __func__, work_done);
 121         return work_done;
 122 }
 123
 124 void cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
 125                         struct rte_eth_dev_info *device_info)
 126 {
 127         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 128         struct adapter *adapter = pi->adapter;
 129         int max_queues = adapter->sge.max_ethqsets / adapter->params.nports;
 130
 131         static const struct rte_eth_desc_lim cxgbe_desc_lim = {
 132                 .nb_max = CXGBE_MAX_RING_DESC_SIZE,
 133                 .nb_min = CXGBE_MIN_RING_DESC_SIZE,
 134                 .nb_align = 1,
 135         };
 136
 137         device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE;
 138         device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN;
 139         device_info->max_rx_queues = max_queues;
 140         device_info->max_tx_queues = max_queues;
 141         device_info->max_mac_addrs = 1;
 142         /* XXX: For now we support one MAC/port */
 143         device_info->max_vfs = adapter->params.arch.vfcount;
 144         device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */
 145
 146         device_info->rx_queue_offload_capa = 0UL;
 147         device_info->rx_offload_capa = CXGBE_RX_OFFLOADS;
 148
 149         device_info->tx_queue_offload_capa = 0UL;
 150         device_info->tx_offload_capa = CXGBE_TX_OFFLOADS;
 151
 152         device_info->reta_size = pi->rss_size;
 153         device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN;
 154         device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL;
 155
 156         device_info->rx_desc_lim = cxgbe_desc_lim;
 157         device_info->tx_desc_lim = cxgbe_desc_lim;
 158         cxgbe_get_speed_caps(pi, &device_info->speed_capa);
 159 }
 160
 161 void cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
 162 {
 163         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 164         struct adapter *adapter = pi->adapter;
 165
 166         t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 167                       1, -1, 1, -1, false);
 168 }
 169
 170 void cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
 171 {
 172         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 173         struct adapter *adapter = pi->adapter;
 174
 175         t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 176                       0, -1, 1, -1, false);
 177 }
 178
 179 void cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
 180 {
 181         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 182         struct adapter *adapter = pi->adapter;
 183
 184         /* TODO: address filters ?? */
 185
 186         t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 187                       -1, 1, 1, -1, false);
 188 }
 189
 190 void cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
 191 {
 192         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 193         struct adapter *adapter = pi->adapter;
 194
 195         /* TODO: address filters ?? */
 196
 197         t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 198                       -1, 0, 1, -1, false);
 199 }
 200
 201 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev,
 202                           __rte_unused int wait_to_complete)
 203 {
 204         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 205         struct adapter *adapter = pi->adapter;
 206         struct sge *s = &adapter->sge;
 207         struct rte_eth_link *old_link = &eth_dev->data->dev_link;
 208         unsigned int work_done, budget = 4;
 209
 210         cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
 211         if (old_link->link_status == pi->link_cfg.link_ok)
 212                 return -1;  /* link not changed */
 213
 214         eth_dev->data->dev_link.link_status = pi->link_cfg.link_ok;
 215         eth_dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;
 216         eth_dev->data->dev_link.link_speed = pi->link_cfg.speed;
 217
 218         /* link has changed */
 219         return 0;
 220 }
 221
 222 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
 223 {
 224         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 225         struct adapter *adapter = pi->adapter;
 226         struct rte_eth_dev_info dev_info;
 227         int err;
 228         uint16_t new_mtu = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
 229
 230         cxgbe_dev_info_get(eth_dev, &dev_info);
 231
 232         /* Must accommodate at least ETHER_MIN_MTU */
 233         if ((new_mtu < ETHER_MIN_MTU) || (new_mtu > dev_info.max_rx_pktlen))
 234                 return -EINVAL;
 235
 236         /* set to jumbo mode if needed */
 237         if (new_mtu > ETHER_MAX_LEN)
 238                 eth_dev->data->dev_conf.rxmode.offloads |=
 239                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 240         else
 241                 eth_dev->data->dev_conf.rxmode.offloads &=
 242                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 243
 244         err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1,
 245                             -1, -1, true);
 246         if (!err)
 247                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu;
 248
 249         return err;
 250 }
 251
 252 /*
 253  * Stop device.
 254  */
 255 void cxgbe_dev_close(struct rte_eth_dev *eth_dev)
 256 {
 257         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 258         struct adapter *adapter = pi->adapter;
 259         int i, dev_down = 0;
 260
 261         CXGBE_FUNC_TRACE();
 262
 263         if (!(adapter->flags & FULL_INIT_DONE))
 264                 return;
 265
 266         cxgbe_down(pi);
 267
 268         /*
 269          *  We clear queues only if both tx and rx path of the port
 270          *  have been disabled
 271          */
 272         t4_sge_eth_clear_queues(pi);
 273
 274         /*  See if all ports are down */
 275         for_each_port(adapter, i) {
 276                 pi = adap2pinfo(adapter, i);
 277                 /*
 278                  * Skip first port of the adapter since it will be closed
 279                  * by DPDK
 280                  */
 281                 if (i == 0)
 282                         continue;
 283                 dev_down += (pi->eth_dev->data->dev_started == 0) ? 1 : 0;
 284         }
 285
 286         /* If rest of the ports are stopped, then free up resources */
 287         if (dev_down == (adapter->params.nports - 1))
 288                 cxgbe_close(adapter);
 289 }
 290
 291 /* Start the device.
 292  * It returns 0 on success.
 293  */
 294 int cxgbe_dev_start(struct rte_eth_dev *eth_dev)
 295 {
 296         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 297         struct adapter *adapter = pi->adapter;
 298         int err = 0, i;
 299
 300         CXGBE_FUNC_TRACE();
 301
 302         /*
 303          * If we don't have a connection to the firmware there's nothing we
 304          * can do.
 305          */
 306         if (!(adapter->flags & FW_OK)) {
 307                 err = -ENXIO;
 308                 goto out;
 309         }
 310
 311         if (!(adapter->flags & FULL_INIT_DONE)) {
 312                 err = cxgbe_up(adapter);
 313                 if (err < 0)
 314                         goto out;
 315         }
 316
 317         cxgbe_enable_rx_queues(pi);
 318
 319         err = setup_rss(pi);
 320         if (err)
 321                 goto out;
 322
 323         for (i = 0; i < pi->n_tx_qsets; i++) {
 324                 err = cxgbe_dev_tx_queue_start(eth_dev, i);
 325                 if (err)
 326                         goto out;
 327         }
 328
 329         for (i = 0; i < pi->n_rx_qsets; i++) {
 330                 err = cxgbe_dev_rx_queue_start(eth_dev, i);
 331                 if (err)
 332                         goto out;
 333         }
 334
 335         err = link_start(pi);
 336         if (err)
 337                 goto out;
 338
 339 out:
 340         return err;
 341 }
 342
 343 /*
 344  * Stop device: disable rx and tx functions to allow for reconfiguring.
 345  */
 346 void cxgbe_dev_stop(struct rte_eth_dev *eth_dev)
 347 {
 348         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 349         struct adapter *adapter = pi->adapter;
 350
 351         CXGBE_FUNC_TRACE();
 352
 353         if (!(adapter->flags & FULL_INIT_DONE))
 354                 return;
 355
 356         cxgbe_down(pi);
 357
 358         /*
 359          *  We clear queues only if both tx and rx path of the port
 360          *  have been disabled
 361          */
 362         t4_sge_eth_clear_queues(pi);
 363 }
 364
 365 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev)
 366 {
 367         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 368         struct adapter *adapter = pi->adapter;
 369         uint64_t configured_offloads;
 370         int err;
 371
 372         CXGBE_FUNC_TRACE();
 373         configured_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 374         if (!(configured_offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
 375                 dev_info(adapter, "can't disable hw crc strip\n");
 376                 eth_dev->data->dev_conf.rxmode.offloads |=
 377                         DEV_RX_OFFLOAD_CRC_STRIP;
 378         }
 379
 380         if (!(adapter->flags & FW_QUEUE_BOUND)) {
 381                 err = setup_sge_fwevtq(adapter);
 382                 if (err)
 383                         return err;
 384                 adapter->flags |= FW_QUEUE_BOUND;
 385         }
 386
 387         err = cfg_queue_count(eth_dev);
 388         if (err)
 389                 return err;
 390
 391         return 0;
 392 }
 393
 394 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 395 {
 396         int ret;
 397         struct sge_eth_txq *txq = (struct sge_eth_txq *)
 398                                   (eth_dev->data->tx_queues[tx_queue_id]);
 399
 400         dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
 401
 402         ret = t4_sge_eth_txq_start(txq);
 403         if (ret == 0)
 404                 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 405
 406         return ret;
 407 }
 408
 409 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 410 {
 411         int ret;
 412         struct sge_eth_txq *txq = (struct sge_eth_txq *)
 413                                   (eth_dev->data->tx_queues[tx_queue_id]);
 414
 415         dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
 416
 417         ret = t4_sge_eth_txq_stop(txq);
 418         if (ret == 0)
 419                 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 420
 421         return ret;
 422 }
 423
 424 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
 425                              uint16_t queue_idx, uint16_t nb_desc,
 426                              unsigned int socket_id,
 427                              const struct rte_eth_txconf *tx_conf __rte_unused)
 428 {
 429         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 430         struct adapter *adapter = pi->adapter;
 431         struct sge *s = &adapter->sge;
 432         struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx];
 433         int err = 0;
 434         unsigned int temp_nb_desc;
 435
 436         dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n",
 437                   __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc,
 438                   socket_id, pi->first_qset);
 439
 440         /*  Free up the existing queue  */
 441         if (eth_dev->data->tx_queues[queue_idx]) {
 442                 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]);
 443                 eth_dev->data->tx_queues[queue_idx] = NULL;
 444         }
 445
 446         eth_dev->data->tx_queues[queue_idx] = (void *)txq;
 447
 448         /* Sanity Checking
 449          *
 450          * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE
 451          */
 452         temp_nb_desc = nb_desc;
 453         if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
 454                 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
 455                          __func__, CXGBE_MIN_RING_DESC_SIZE,
 456                          CXGBE_DEFAULT_TX_DESC_SIZE);
 457                 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE;
 458         } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
 459                 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
 460                         __func__, CXGBE_MIN_RING_DESC_SIZE,
 461                         CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE);
 462                 return -(EINVAL);
 463         }
 464
 465         txq->q.size = temp_nb_desc;
 466
 467         err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx,
 468                                    s->fw_evtq.cntxt_id, socket_id);
 469
 470         dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n",
 471                   __func__, txq->q.cntxt_id, txq->q.abs_id, err);
 472         return err;
 473 }
 474
 475 void cxgbe_dev_tx_queue_release(void *q)
 476 {
 477         struct sge_eth_txq *txq = (struct sge_eth_txq *)q;
 478
 479         if (txq) {
 480                 struct port_info *pi = (struct port_info *)
 481                                        (txq->eth_dev->data->dev_private);
 482                 struct adapter *adap = pi->adapter;
 483
 484                 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n",
 485                           __func__, pi->port_id, txq->q.cntxt_id);
 486
 487                 t4_sge_eth_txq_release(adap, txq);
 488         }
 489 }
 490
 491 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 492 {
 493         int ret;
 494         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 495         struct adapter *adap = pi->adapter;
 496         struct sge_rspq *q;
 497
 498         dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 499                   __func__, pi->port_id, rx_queue_id);
 500
 501         q = eth_dev->data->rx_queues[rx_queue_id];
 502
 503         ret = t4_sge_eth_rxq_start(adap, q);
 504         if (ret == 0)
 505                 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 506
 507         return ret;
 508 }
 509
 510 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 511 {
 512         int ret;
 513         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 514         struct adapter *adap = pi->adapter;
 515         struct sge_rspq *q;
 516
 517         dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 518                   __func__, pi->port_id, rx_queue_id);
 519
 520         q = eth_dev->data->rx_queues[rx_queue_id];
 521         ret = t4_sge_eth_rxq_stop(adap, q);
 522         if (ret == 0)
 523                 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 524
 525         return ret;
 526 }
 527
 528 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
 529                              uint16_t queue_idx, uint16_t nb_desc,
 530                              unsigned int socket_id,
 531                              const struct rte_eth_rxconf *rx_conf __rte_unused,
 532                              struct rte_mempool *mp)
 533 {
 534         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 535         struct adapter *adapter = pi->adapter;
 536         struct sge *s = &adapter->sge;
 537         struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset + queue_idx];
 538         int err = 0;
 539         int msi_idx = 0;
 540         unsigned int temp_nb_desc;
 541         struct rte_eth_dev_info dev_info;
 542         unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
 543
 544         dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n",
 545                   __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc,
 546                   socket_id, mp);
 547
 548         cxgbe_dev_info_get(eth_dev, &dev_info);
 549
 550         /* Must accommodate at least ETHER_MIN_MTU */
 551         if ((pkt_len < dev_info.min_rx_bufsize) ||
 552             (pkt_len > dev_info.max_rx_pktlen)) {
 553                 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n",
 554                         __func__, dev_info.min_rx_bufsize,
 555                         dev_info.max_rx_pktlen);
 556                 return -EINVAL;
 557         }
 558
 559         /*  Free up the existing queue  */
 560         if (eth_dev->data->rx_queues[queue_idx]) {
 561                 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]);
 562                 eth_dev->data->rx_queues[queue_idx] = NULL;
 563         }
 564
 565         eth_dev->data->rx_queues[queue_idx] = (void *)rxq;
 566
 567         /* Sanity Checking
 568          *
 569          * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE
 570          */
 571         temp_nb_desc = nb_desc;
 572         if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
 573                 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
 574                          __func__, CXGBE_MIN_RING_DESC_SIZE,
 575                          CXGBE_DEFAULT_RX_DESC_SIZE);
 576                 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE;
 577         } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
 578                 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
 579                         __func__, CXGBE_MIN_RING_DESC_SIZE,
 580                         CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE);
 581                 return -(EINVAL);
 582         }
 583
 584         rxq->rspq.size = temp_nb_desc;
 585         if ((&rxq->fl) != NULL)
 586                 rxq->fl.size = temp_nb_desc;
 587
 588         /* Set to jumbo mode if necessary */
 589         if (pkt_len > ETHER_MAX_LEN)
 590                 eth_dev->data->dev_conf.rxmode.offloads |=
 591                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 592         else
 593                 eth_dev->data->dev_conf.rxmode.offloads &=
 594                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 595
 596         err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx,
 597                                &rxq->fl, t4_ethrx_handler,
 598                                is_pf4(adapter) ?
 599                                t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp,
 600                                queue_idx, socket_id);
 601
 602         dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n",
 603                   __func__, err, pi->port_id, rxq->rspq.cntxt_id,
 604                   rxq->rspq.abs_id);
 605         return err;
 606 }
 607
 608 void cxgbe_dev_rx_queue_release(void *q)
 609 {
 610         struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q;
 611         struct sge_rspq *rq = &rxq->rspq;
 612
 613         if (rq) {
 614                 struct port_info *pi = (struct port_info *)
 615                                        (rq->eth_dev->data->dev_private);
 616                 struct adapter *adap = pi->adapter;
 617
 618                 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 619                           __func__, pi->port_id, rxq->rspq.cntxt_id);
 620
 621                 t4_sge_eth_rxq_release(adap, rxq);
 622         }
 623 }
 624
 625 /*
 626  * Get port statistics.
 627  */
 628 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev,
 629                                 struct rte_eth_stats *eth_stats)
 630 {
 631         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 632         struct adapter *adapter = pi->adapter;
 633         struct sge *s = &adapter->sge;
 634         struct port_stats ps;
 635         unsigned int i;
 636
 637         cxgbe_stats_get(pi, &ps);
 638
 639         /* RX Stats */
 640         eth_stats->imissed  = ps.rx_ovflow0 + ps.rx_ovflow1 +
 641                               ps.rx_ovflow2 + ps.rx_ovflow3 +
 642                               ps.rx_trunc0 + ps.rx_trunc1 +
 643                               ps.rx_trunc2 + ps.rx_trunc3;
 644         eth_stats->ierrors  = ps.rx_symbol_err + ps.rx_fcs_err +
 645                               ps.rx_jabber + ps.rx_too_long + ps.rx_runt +
 646                               ps.rx_len_err;
 647
 648         /* TX Stats */
 649         eth_stats->opackets = ps.tx_frames;
 650         eth_stats->obytes   = ps.tx_octets;
 651         eth_stats->oerrors  = ps.tx_error_frames;
 652
 653         for (i = 0; i < pi->n_rx_qsets; i++) {
 654                 struct sge_eth_rxq *rxq =
 655                         &s->ethrxq[pi->first_qset + i];
 656
 657                 eth_stats->q_ipackets[i] = rxq->stats.pkts;
 658                 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes;
 659                 eth_stats->ipackets += eth_stats->q_ipackets[i];
 660                 eth_stats->ibytes += eth_stats->q_ibytes[i];
 661         }
 662
 663         for (i = 0; i < pi->n_tx_qsets; i++) {
 664                 struct sge_eth_txq *txq =
 665                         &s->ethtxq[pi->first_qset + i];
 666
 667                 eth_stats->q_opackets[i] = txq->stats.pkts;
 668                 eth_stats->q_obytes[i] = txq->stats.tx_bytes;
 669                 eth_stats->q_errors[i] = txq->stats.mapping_err;
 670         }
 671         return 0;
 672 }
 673
 674 /*
 675  * Reset port statistics.
 676  */
 677 static void cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev)
 678 {
 679         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 680         struct adapter *adapter = pi->adapter;
 681         struct sge *s = &adapter->sge;
 682         unsigned int i;
 683
 684         cxgbe_stats_reset(pi);
 685         for (i = 0; i < pi->n_rx_qsets; i++) {
 686                 struct sge_eth_rxq *rxq =
 687                         &s->ethrxq[pi->first_qset + i];
 688
 689                 rxq->stats.pkts = 0;
 690                 rxq->stats.rx_bytes = 0;
 691         }
 692         for (i = 0; i < pi->n_tx_qsets; i++) {
 693                 struct sge_eth_txq *txq =
 694                         &s->ethtxq[pi->first_qset + i];
 695
 696                 txq->stats.pkts = 0;
 697                 txq->stats.tx_bytes = 0;
 698                 txq->stats.mapping_err = 0;
 699         }
 700 }
 701
 702 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev,
 703                                struct rte_eth_fc_conf *fc_conf)
 704 {
 705         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 706         struct link_config *lc = &pi->link_cfg;
 707         int rx_pause, tx_pause;
 708
 709         fc_conf->autoneg = lc->fc & PAUSE_AUTONEG;
 710         rx_pause = lc->fc & PAUSE_RX;
 711         tx_pause = lc->fc & PAUSE_TX;
 712
 713         if (rx_pause && tx_pause)
 714                 fc_conf->mode = RTE_FC_FULL;
 715         else if (rx_pause)
 716                 fc_conf->mode = RTE_FC_RX_PAUSE;
 717         else if (tx_pause)
 718                 fc_conf->mode = RTE_FC_TX_PAUSE;
 719         else
 720                 fc_conf->mode = RTE_FC_NONE;
 721         return 0;
 722 }
 723
 724 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev,
 725                                struct rte_eth_fc_conf *fc_conf)
 726 {
 727         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 728         struct adapter *adapter = pi->adapter;
 729         struct link_config *lc = &pi->link_cfg;
 730
 731         if (lc->pcaps & FW_PORT_CAP32_ANEG) {
 732                 if (fc_conf->autoneg)
 733                         lc->requested_fc |= PAUSE_AUTONEG;
 734                 else
 735                         lc->requested_fc &= ~PAUSE_AUTONEG;
 736         }
 737
 738         if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
 739             (fc_conf->mode & RTE_FC_RX_PAUSE))
 740                 lc->requested_fc |= PAUSE_RX;
 741         else
 742                 lc->requested_fc &= ~PAUSE_RX;
 743
 744         if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
 745             (fc_conf->mode & RTE_FC_TX_PAUSE))
 746                 lc->requested_fc |= PAUSE_TX;
 747         else
 748                 lc->requested_fc &= ~PAUSE_TX;
 749
 750         return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
 751                              &pi->link_cfg);
 752 }
 753
 754 const uint32_t *
 755 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
 756 {
 757         static const uint32_t ptypes[] = {
 758                 RTE_PTYPE_L3_IPV4,
 759                 RTE_PTYPE_L3_IPV6,
 760                 RTE_PTYPE_UNKNOWN
 761         };
 762
 763         if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts)
 764                 return ptypes;
 765         return NULL;
 766 }
 767
 768 /* Update RSS hash configuration
 769  */
 770 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
 771                                      struct rte_eth_rss_conf *rss_conf)
 772 {
 773         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
 774         struct adapter *adapter = pi->adapter;
 775         int err;
 776
 777         err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf);
 778         if (err)
 779                 return err;
 780
 781         pi->rss_hf = rss_conf->rss_hf;
 782
 783         if (rss_conf->rss_key) {
 784                 u32 key[10], mod_key[10];
 785                 int i, j;
 786
 787                 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN);
 788
 789                 for (i = 9, j = 0; i >= 0; i--, j++)
 790                         mod_key[j] = cpu_to_be32(key[i]);
 791
 792                 t4_write_rss_key(adapter, mod_key, -1);
 793         }
 794
 795         return 0;
 796 }
 797
 798 /* Get RSS hash configuration
 799  */
 800 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 801                                        struct rte_eth_rss_conf *rss_conf)
 802 {
 803         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
 804         struct adapter *adapter = pi->adapter;
 805         u64 rss_hf = 0;
 806         u64 flags = 0;
 807         int err;
 808
 809         err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid,
 810                                     &flags, NULL);
 811
 812         if (err)
 813                 return err;
 814
 815         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) {
 816                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
 817                 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
 818                         rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
 819         }
 820
 821         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
 822                 rss_hf |= ETH_RSS_IPV6;
 823
 824         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) {
 825                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
 826                 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
 827                         rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
 828         }
 829
 830         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
 831                 rss_hf |= ETH_RSS_IPV4;
 832
 833         rss_conf->rss_hf = rss_hf;
 834
 835         if (rss_conf->rss_key) {
 836                 u32 key[10], mod_key[10];
 837                 int i, j;
 838
 839                 t4_read_rss_key(adapter, key);
 840
 841                 for (i = 9, j = 0; i >= 0; i--, j++)
 842                         mod_key[j] = be32_to_cpu(key[i]);
 843
 844                 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN);
 845         }
 846
 847         return 0;
 848 }
 849
 850 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev)
 851 {
 852         RTE_SET_USED(dev);
 853         return EEPROMSIZE;
 854 }
 855
 856 /**
 857  * eeprom_ptov - translate a physical EEPROM address to virtual
 858  * @phys_addr: the physical EEPROM address
 859  * @fn: the PCI function number
 860  * @sz: size of function-specific area
 861  *
 862  * Translate a physical EEPROM address to virtual.  The first 1K is
 863  * accessed through virtual addresses starting at 31K, the rest is
 864  * accessed through virtual addresses starting at 0.
 865  *
 866  * The mapping is as follows:
 867  * [0..1K) -> [31K..32K)
 868  * [1K..1K+A) -> [31K-A..31K)
 869  * [1K+A..ES) -> [0..ES-A-1K)
 870  *
 871  * where A = @fn * @sz, and ES = EEPROM size.
 872  */
 873 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
 874 {
 875         fn *= sz;
 876         if (phys_addr < 1024)
 877                 return phys_addr + (31 << 10);
 878         if (phys_addr < 1024 + fn)
 879                 return fn + phys_addr - 1024;
 880         if (phys_addr < EEPROMSIZE)
 881                 return phys_addr - 1024 - fn;
 882         if (phys_addr < EEPROMVSIZE)
 883                 return phys_addr - 1024;
 884         return -EINVAL;
 885 }
 886
 887 /* The next two routines implement eeprom read/write from physical addresses.
 888  */
 889 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
 890 {
 891         int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
 892
 893         if (vaddr >= 0)
 894                 vaddr = t4_seeprom_read(adap, vaddr, v);
 895         return vaddr < 0 ? vaddr : 0;
 896 }
 897
 898 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
 899 {
 900         int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
 901
 902         if (vaddr >= 0)
 903                 vaddr = t4_seeprom_write(adap, vaddr, v);
 904         return vaddr < 0 ? vaddr : 0;
 905 }
 906
 907 #define EEPROM_MAGIC 0x38E2F10C
 908
 909 static int cxgbe_get_eeprom(struct rte_eth_dev *dev,
 910                             struct rte_dev_eeprom_info *e)
 911 {
 912         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
 913         struct adapter *adapter = pi->adapter;
 914         u32 i, err = 0;
 915         u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0);
 916
 917         if (!buf)
 918                 return -ENOMEM;
 919
 920         e->magic = EEPROM_MAGIC;
 921         for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4)
 922                 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
 923
 924         if (!err)
 925                 rte_memcpy(e->data, buf + e->offset, e->length);
 926         rte_free(buf);
 927         return err;
 928 }
 929
 930 static int cxgbe_set_eeprom(struct rte_eth_dev *dev,
 931                             struct rte_dev_eeprom_info *eeprom)
 932 {
 933         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
 934         struct adapter *adapter = pi->adapter;
 935         u8 *buf;
 936         int err = 0;
 937         u32 aligned_offset, aligned_len, *p;
 938
 939         if (eeprom->magic != EEPROM_MAGIC)
 940                 return -EINVAL;
 941
 942         aligned_offset = eeprom->offset & ~3;
 943         aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3;
 944
 945         if (adapter->pf > 0) {
 946                 u32 start = 1024 + adapter->pf * EEPROMPFSIZE;
 947
 948                 if (aligned_offset < start ||
 949                     aligned_offset + aligned_len > start + EEPROMPFSIZE)
 950                         return -EPERM;
 951         }
 952
 953         if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) {
 954                 /* RMW possibly needed for first or last words.
 955                  */
 956                 buf = rte_zmalloc(NULL, aligned_len, 0);
 957                 if (!buf)
 958                         return -ENOMEM;
 959                 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
 960                 if (!err && aligned_len > 4)
 961                         err = eeprom_rd_phys(adapter,
 962                                              aligned_offset + aligned_len - 4,
 963                                              (u32 *)&buf[aligned_len - 4]);
 964                 if (err)
 965                         goto out;
 966                 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data,
 967                            eeprom->length);
 968         } else {
 969                 buf = eeprom->data;
 970         }
 971
 972         err = t4_seeprom_wp(adapter, false);
 973         if (err)
 974                 goto out;
 975
 976         for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
 977                 err = eeprom_wr_phys(adapter, aligned_offset, *p);
 978                 aligned_offset += 4;
 979         }
 980
 981         if (!err)
 982                 err = t4_seeprom_wp(adapter, true);
 983 out:
 984         if (buf != eeprom->data)
 985                 rte_free(buf);
 986         return err;
 987 }
 988
 989 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev)
 990 {
 991         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 992         struct adapter *adapter = pi->adapter;
 993
 994         return t4_get_regs_len(adapter) / sizeof(uint32_t);
 995 }
 996
 997 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev,
 998                           struct rte_dev_reg_info *regs)
 999 {
1000         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1001         struct adapter *adapter = pi->adapter;
1002
1003         regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) |
1004                 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) |
1005                 (1 << 16);
1006
1007         if (regs->data == NULL) {
1008                 regs->length = cxgbe_get_regs_len(eth_dev);
1009                 regs->width = sizeof(uint32_t);
1010
1011                 return 0;
1012         }
1013
1014         t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t)));
1015
1016         return 0;
1017 }
1018
1019 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
1020 {
1021         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
1022         struct adapter *adapter = pi->adapter;
1023         int ret;
1024
1025         ret = t4_change_mac(adapter, adapter->mbox, pi->viid,
1026                             pi->xact_addr_filt, (u8 *)addr, true, true);
1027         if (ret < 0) {
1028                 dev_err(adapter, "failed to set mac addr; err = %d\n",
1029                         ret);
1030                 return ret;
1031         }
1032         pi->xact_addr_filt = ret;
1033         return 0;
1034 }
1035
1036 static const struct eth_dev_ops cxgbe_eth_dev_ops = {
1037         .dev_start              = cxgbe_dev_start,
1038         .dev_stop               = cxgbe_dev_stop,
1039         .dev_close              = cxgbe_dev_close,
1040         .promiscuous_enable     = cxgbe_dev_promiscuous_enable,
1041         .promiscuous_disable    = cxgbe_dev_promiscuous_disable,
1042         .allmulticast_enable    = cxgbe_dev_allmulticast_enable,
1043         .allmulticast_disable   = cxgbe_dev_allmulticast_disable,
1044         .dev_configure          = cxgbe_dev_configure,
1045         .dev_infos_get          = cxgbe_dev_info_get,
1046         .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get,
1047         .link_update            = cxgbe_dev_link_update,
1048         .mtu_set                = cxgbe_dev_mtu_set,
1049         .tx_queue_setup         = cxgbe_dev_tx_queue_setup,
1050         .tx_queue_start         = cxgbe_dev_tx_queue_start,
1051         .tx_queue_stop          = cxgbe_dev_tx_queue_stop,
1052         .tx_queue_release       = cxgbe_dev_tx_queue_release,
1053         .rx_queue_setup         = cxgbe_dev_rx_queue_setup,
1054         .rx_queue_start         = cxgbe_dev_rx_queue_start,
1055         .rx_queue_stop          = cxgbe_dev_rx_queue_stop,
1056         .rx_queue_release       = cxgbe_dev_rx_queue_release,
1057         .stats_get              = cxgbe_dev_stats_get,
1058         .stats_reset            = cxgbe_dev_stats_reset,
1059         .flow_ctrl_get          = cxgbe_flow_ctrl_get,
1060         .flow_ctrl_set          = cxgbe_flow_ctrl_set,
1061         .get_eeprom_length      = cxgbe_get_eeprom_length,
1062         .get_eeprom             = cxgbe_get_eeprom,
1063         .set_eeprom             = cxgbe_set_eeprom,
1064         .get_reg                = cxgbe_get_regs,
1065         .rss_hash_update        = cxgbe_dev_rss_hash_update,
1066         .rss_hash_conf_get      = cxgbe_dev_rss_hash_conf_get,
1067         .mac_addr_set           = cxgbe_mac_addr_set,
1068 };
1069
1070 /*
1071  * Initialize driver
1072  * It returns 0 on success.
1073  */
1074 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev)
1075 {
1076         struct rte_pci_device *pci_dev;
1077         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1078         struct adapter *adapter = NULL;
1079         char name[RTE_ETH_NAME_MAX_LEN];
1080         int err = 0;
1081
1082         CXGBE_FUNC_TRACE();
1083
1084         eth_dev->dev_ops = &cxgbe_eth_dev_ops;
1085         eth_dev->rx_pkt_burst = &cxgbe_recv_pkts;
1086         eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts;
1087         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1088
1089         /* for secondary processes, we attach to ethdevs allocated by primary
1090          * and do minimal initialization.
1091          */
1092         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1093                 int i;
1094
1095                 for (i = 1; i < MAX_NPORTS; i++) {
1096                         struct rte_eth_dev *rest_eth_dev;
1097                         char namei[RTE_ETH_NAME_MAX_LEN];
1098
1099                         snprintf(namei, sizeof(namei), "%s_%d",
1100                                  pci_dev->device.name, i);
1101                         rest_eth_dev = rte_eth_dev_attach_secondary(namei);
1102                         if (rest_eth_dev) {
1103                                 rest_eth_dev->device = &pci_dev->device;
1104                                 rest_eth_dev->dev_ops =
1105                                         eth_dev->dev_ops;
1106                                 rest_eth_dev->rx_pkt_burst =
1107                                         eth_dev->rx_pkt_burst;
1108                                 rest_eth_dev->tx_pkt_burst =
1109                                         eth_dev->tx_pkt_burst;
1110                         }
1111                 }
1112                 return 0;
1113         }
1114
1115         snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id);
1116         adapter = rte_zmalloc(name, sizeof(*adapter), 0);
1117         if (!adapter)
1118                 return -1;
1119
1120         adapter->use_unpacked_mode = 1;
1121         adapter->regs = (void *)pci_dev->mem_resource[0].addr;
1122         if (!adapter->regs) {
1123                 dev_err(adapter, "%s: cannot map device registers\n", __func__);
1124                 err = -ENOMEM;
1125                 goto out_free_adapter;
1126         }
1127         adapter->pdev = pci_dev;
1128         adapter->eth_dev = eth_dev;
1129         pi->adapter = adapter;
1130
1131         err = cxgbe_probe(adapter);
1132         if (err) {
1133                 dev_err(adapter, "%s: cxgbe probe failed with err %d\n",
1134                         __func__, err);
1135                 goto out_free_adapter;
1136         }
1137
1138         return 0;
1139
1140 out_free_adapter:
1141         rte_free(adapter);
1142         return err;
1143 }
1144
1145 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1146         struct rte_pci_device *pci_dev)
1147 {
1148         return rte_eth_dev_pci_generic_probe(pci_dev,
1149                 sizeof(struct port_info), eth_cxgbe_dev_init);
1150 }
1151
1152 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev)
1153 {
1154         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
1155 }
1156
1157 static struct rte_pci_driver rte_cxgbe_pmd = {
1158         .id_table = cxgb4_pci_tbl,
1159         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1160         .probe = eth_cxgbe_pci_probe,
1161         .remove = eth_cxgbe_pci_remove,
1162 };
1163
1164 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd);
1165 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl);
1166 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci");