drivers/net/cxgbe/cxgbe_filter.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Chelsio Communications.
   3  * All rights reserved.
   4  */
   5 #include <rte_net.h>
   6
   7 #include "base/common.h"
   8 #include "base/t4_tcb.h"
   9 #include "base/t4_regs.h"
  10 #include "cxgbe_filter.h"
  11 #include "clip_tbl.h"
  12 #include "l2t.h"
  13
  14 /**
  15  * Initialize Hash Filters
  16  */
  17 int cxgbe_init_hash_filter(struct adapter *adap)
  18 {
  19         unsigned int n_user_filters;
  20         unsigned int user_filter_perc;
  21         int ret;
  22         u32 params[7], val[7];
  23
  24 #define FW_PARAM_DEV(param) \
  25         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
  26         V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
  27
  28 #define FW_PARAM_PFVF(param) \
  29         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
  30         V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) |  \
  31         V_FW_PARAMS_PARAM_Y(0) | \
  32         V_FW_PARAMS_PARAM_Z(0))
  33
  34         params[0] = FW_PARAM_DEV(NTID);
  35         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
  36                               params, val);
  37         if (ret < 0)
  38                 return ret;
  39         adap->tids.ntids = val[0];
  40         adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
  41
  42         user_filter_perc = 100;
  43         n_user_filters = mult_frac(adap->tids.nftids,
  44                                    user_filter_perc,
  45                                    100);
  46
  47         adap->tids.nftids = n_user_filters;
  48         adap->params.hash_filter = 1;
  49         return 0;
  50 }
  51
  52 /**
  53  * Validate if the requested filter specification can be set by checking
  54  * if the requested features have been enabled
  55  */
  56 int cxgbe_validate_filter(struct adapter *adapter,
  57                           struct ch_filter_specification *fs)
  58 {
  59         u32 fconf, iconf;
  60
  61         /*
  62          * Check for unconfigured fields being used.
  63          */
  64         fconf = adapter->params.tp.vlan_pri_map;
  65
  66         iconf = adapter->params.tp.ingress_config;
  67
  68 #define S(_field) \
  69         (fs->val._field || fs->mask._field)
  70 #define U(_mask, _field) \
  71         (!(fconf & (_mask)) && S(_field))
  72
  73         if (U(F_PORT, iport) || U(F_ETHERTYPE, ethtype) ||
  74             U(F_PROTOCOL, proto) || U(F_MACMATCH, macidx) ||
  75             U(F_VLAN, ivlan_vld) || U(F_VNIC_ID, ovlan_vld) ||
  76             U(F_TOS, tos))
  77                 return -EOPNOTSUPP;
  78
  79         /* Ensure OVLAN match is enabled in hardware */
  80         if (S(ovlan_vld) && (iconf & F_VNIC))
  81                 return -EOPNOTSUPP;
  82
  83         /* To use OVLAN, L4 encapsulation match must not be enabled */
  84         if (S(ovlan_vld) && (iconf & F_USE_ENC_IDX))
  85                 return -EOPNOTSUPP;
  86
  87 #undef S
  88 #undef U
  89
  90         /*
  91          * If the user is requesting that the filter action loop
  92          * matching packets back out one of our ports, make sure that
  93          * the egress port is in range.
  94          */
  95         if (fs->action == FILTER_SWITCH &&
  96             fs->eport >= adapter->params.nports)
  97                 return -ERANGE;
  98
  99         /*
 100          * Don't allow various trivially obvious bogus out-of-range
 101          * values ...
 102          */
 103         if (fs->val.iport >= adapter->params.nports)
 104                 return -ERANGE;
 105
 106         if (!fs->cap && fs->nat_mode && !adapter->params.filter2_wr_support)
 107                 return -EOPNOTSUPP;
 108
 109         if (!fs->cap && fs->swapmac && !adapter->params.filter2_wr_support)
 110                 return -EOPNOTSUPP;
 111
 112         return 0;
 113 }
 114
 115 /**
 116  * Get the queue to which the traffic must be steered to.
 117  */
 118 static unsigned int get_filter_steerq(struct rte_eth_dev *dev,
 119                                       struct ch_filter_specification *fs)
 120 {
 121         struct port_info *pi = ethdev2pinfo(dev);
 122         struct adapter *adapter = pi->adapter;
 123         unsigned int iq;
 124
 125         /*
 126          * If the user has requested steering matching Ingress Packets
 127          * to a specific Queue Set, we need to make sure it's in range
 128          * for the port and map that into the Absolute Queue ID of the
 129          * Queue Set's Response Queue.
 130          */
 131         if (!fs->dirsteer) {
 132                 iq = 0;
 133         } else {
 134                 /*
 135                  * If the iq id is greater than the number of qsets,
 136                  * then assume it is an absolute qid.
 137                  */
 138                 if (fs->iq < pi->n_rx_qsets)
 139                         iq = adapter->sge.ethrxq[pi->first_qset +
 140                                                  fs->iq].rspq.abs_id;
 141                 else
 142                         iq = fs->iq;
 143         }
 144
 145         return iq;
 146 }
 147
 148 /* Return an error number if the indicated filter isn't writable ... */
 149 static int writable_filter(struct filter_entry *f)
 150 {
 151         if (f->locked)
 152                 return -EPERM;
 153         if (f->pending)
 154                 return -EBUSY;
 155
 156         return 0;
 157 }
 158
 159 /**
 160  * Send CPL_SET_TCB_FIELD message
 161  */
 162 static void set_tcb_field(struct adapter *adapter, unsigned int ftid,
 163                           u16 word, u64 mask, u64 val, int no_reply)
 164 {
 165         struct rte_mbuf *mbuf;
 166         struct cpl_set_tcb_field *req;
 167         struct sge_ctrl_txq *ctrlq;
 168
 169         ctrlq = &adapter->sge.ctrlq[0];
 170         mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
 171         WARN_ON(!mbuf);
 172
 173         mbuf->data_len = sizeof(*req);
 174         mbuf->pkt_len = mbuf->data_len;
 175
 176         req = rte_pktmbuf_mtod(mbuf, struct cpl_set_tcb_field *);
 177         memset(req, 0, sizeof(*req));
 178         INIT_TP_WR_MIT_CPL(req, CPL_SET_TCB_FIELD, ftid);
 179         req->reply_ctrl = cpu_to_be16(V_REPLY_CHAN(0) |
 180                                       V_QUEUENO(adapter->sge.fw_evtq.abs_id) |
 181                                       V_NO_REPLY(no_reply));
 182         req->word_cookie = cpu_to_be16(V_WORD(word) | V_COOKIE(ftid));
 183         req->mask = cpu_to_be64(mask);
 184         req->val = cpu_to_be64(val);
 185
 186         t4_mgmt_tx(ctrlq, mbuf);
 187 }
 188
 189 /**
 190  * Set one of the t_flags bits in the TCB.
 191  */
 192 static void set_tcb_tflag(struct adapter *adap, unsigned int ftid,
 193                           unsigned int bit_pos, unsigned int val, int no_reply)
 194 {
 195         set_tcb_field(adap, ftid,  W_TCB_T_FLAGS, 1ULL << bit_pos,
 196                       (unsigned long long)val << bit_pos, no_reply);
 197 }
 198
 199 /**
 200  * Build a CPL_SET_TCB_FIELD message as payload of a ULP_TX_PKT command.
 201  */
 202 static inline void mk_set_tcb_field_ulp(struct filter_entry *f,
 203                                         struct cpl_set_tcb_field *req,
 204                                         unsigned int word,
 205                                         u64 mask, u64 val, u8 cookie,
 206                                         int no_reply)
 207 {
 208         struct ulp_txpkt *txpkt = (struct ulp_txpkt *)req;
 209         struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1);
 210
 211         txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
 212                                       V_ULP_TXPKT_DEST(0));
 213         txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*req), 16));
 214         sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
 215         sc->len = cpu_to_be32(sizeof(*req) - sizeof(struct work_request_hdr));
 216         OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_SET_TCB_FIELD, f->tid));
 217         req->reply_ctrl = cpu_to_be16(V_NO_REPLY(no_reply) | V_REPLY_CHAN(0) |
 218                                       V_QUEUENO(0));
 219         req->word_cookie = cpu_to_be16(V_WORD(word) | V_COOKIE(cookie));
 220         req->mask = cpu_to_be64(mask);
 221         req->val = cpu_to_be64(val);
 222         sc = (struct ulptx_idata *)(req + 1);
 223         sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
 224         sc->len = cpu_to_be32(0);
 225 }
 226
 227 /**
 228  * IPv6 requires 2 slots on T6 and 4 slots for cards below T6.
 229  * IPv4 requires only 1 slot on all cards.
 230  */
 231 u8 cxgbe_filter_slots(struct adapter *adap, u8 family)
 232 {
 233         if (family == FILTER_TYPE_IPV6) {
 234                 if (CHELSIO_CHIP_VERSION(adap->params.chip) < CHELSIO_T6)
 235                         return 4;
 236
 237                 return 2;
 238         }
 239
 240         return 1;
 241 }
 242
 243 /**
 244  * Check if entries are already filled.
 245  */
 246 bool cxgbe_is_filter_set(struct tid_info *t, u32 fidx, u8 nentries)
 247 {
 248         bool result = FALSE;
 249         u32 i;
 250
 251         /* Ensure there's enough slots available. */
 252         t4_os_lock(&t->ftid_lock);
 253         for (i = fidx; i < fidx + nentries; i++) {
 254                 if (rte_bitmap_get(t->ftid_bmap, i)) {
 255                         result = TRUE;
 256                         break;
 257                 }
 258         }
 259         t4_os_unlock(&t->ftid_lock);
 260         return result;
 261 }
 262
 263 /**
 264  * Allocate available free entries.
 265  */
 266 int cxgbe_alloc_ftid(struct adapter *adap, u8 nentries)
 267 {
 268         struct tid_info *t = &adap->tids;
 269         int pos;
 270         int size = t->nftids;
 271
 272         t4_os_lock(&t->ftid_lock);
 273         if (nentries > 1)
 274                 pos = cxgbe_bitmap_find_free_region(t->ftid_bmap, size,
 275                                                     nentries);
 276         else
 277                 pos = cxgbe_find_first_zero_bit(t->ftid_bmap, size);
 278         t4_os_unlock(&t->ftid_lock);
 279
 280         return pos < size ? pos : -1;
 281 }
 282
 283 /**
 284  * Construct hash filter ntuple.
 285  */
 286 static u64 hash_filter_ntuple(const struct filter_entry *f)
 287 {
 288         struct adapter *adap = ethdev2adap(f->dev);
 289         struct tp_params *tp = &adap->params.tp;
 290         u64 ntuple = 0;
 291         u16 tcp_proto = IPPROTO_TCP; /* TCP Protocol Number */
 292
 293         if (tp->port_shift >= 0 && f->fs.mask.iport)
 294                 ntuple |= (u64)f->fs.val.iport << tp->port_shift;
 295
 296         if (tp->protocol_shift >= 0) {
 297                 if (!f->fs.val.proto)
 298                         ntuple |= (u64)tcp_proto << tp->protocol_shift;
 299                 else
 300                         ntuple |= (u64)f->fs.val.proto << tp->protocol_shift;
 301         }
 302
 303         if (tp->ethertype_shift >= 0 && f->fs.mask.ethtype)
 304                 ntuple |= (u64)(f->fs.val.ethtype) << tp->ethertype_shift;
 305         if (tp->macmatch_shift >= 0 && f->fs.mask.macidx)
 306                 ntuple |= (u64)(f->fs.val.macidx) << tp->macmatch_shift;
 307         if (tp->vlan_shift >= 0 && f->fs.mask.ivlan)
 308                 ntuple |= (u64)(F_FT_VLAN_VLD | f->fs.val.ivlan) <<
 309                           tp->vlan_shift;
 310         if (tp->vnic_shift >= 0) {
 311                 if (!(adap->params.tp.ingress_config & F_VNIC) &&
 312                     f->fs.mask.ovlan_vld)
 313                         ntuple |= (u64)(f->fs.val.ovlan_vld << 16 |
 314                                         f->fs.val.ovlan) << tp->vnic_shift;
 315         }
 316         if (tp->tos_shift >= 0 && f->fs.mask.tos)
 317                 ntuple |= (u64)f->fs.val.tos << tp->tos_shift;
 318
 319         return ntuple;
 320 }
 321
 322 /**
 323  * Build a CPL_ABORT_REQ message as payload of a ULP_TX_PKT command.
 324  */
 325 static void mk_abort_req_ulp(struct cpl_abort_req *abort_req,
 326                              unsigned int tid)
 327 {
 328         struct ulp_txpkt *txpkt = (struct ulp_txpkt *)abort_req;
 329         struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1);
 330
 331         txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
 332                                       V_ULP_TXPKT_DEST(0));
 333         txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*abort_req), 16));
 334         sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
 335         sc->len = cpu_to_be32(sizeof(*abort_req) -
 336                               sizeof(struct work_request_hdr));
 337         OPCODE_TID(abort_req) = cpu_to_be32(MK_OPCODE_TID(CPL_ABORT_REQ, tid));
 338         abort_req->rsvd0 = cpu_to_be32(0);
 339         abort_req->rsvd1 = 0;
 340         abort_req->cmd = CPL_ABORT_NO_RST;
 341         sc = (struct ulptx_idata *)(abort_req + 1);
 342         sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
 343         sc->len = cpu_to_be32(0);
 344 }
 345
 346 /**
 347  * Build a CPL_ABORT_RPL message as payload of a ULP_TX_PKT command.
 348  */
 349 static void mk_abort_rpl_ulp(struct cpl_abort_rpl *abort_rpl,
 350                              unsigned int tid)
 351 {
 352         struct ulp_txpkt *txpkt = (struct ulp_txpkt *)abort_rpl;
 353         struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1);
 354
 355         txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
 356                                       V_ULP_TXPKT_DEST(0));
 357         txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*abort_rpl), 16));
 358         sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
 359         sc->len = cpu_to_be32(sizeof(*abort_rpl) -
 360                               sizeof(struct work_request_hdr));
 361         OPCODE_TID(abort_rpl) = cpu_to_be32(MK_OPCODE_TID(CPL_ABORT_RPL, tid));
 362         abort_rpl->rsvd0 = cpu_to_be32(0);
 363         abort_rpl->rsvd1 = 0;
 364         abort_rpl->cmd = CPL_ABORT_NO_RST;
 365         sc = (struct ulptx_idata *)(abort_rpl + 1);
 366         sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
 367         sc->len = cpu_to_be32(0);
 368 }
 369
 370 /**
 371  * Delete the specified hash filter.
 372  */
 373 static int cxgbe_del_hash_filter(struct rte_eth_dev *dev,
 374                                  unsigned int filter_id,
 375                                  struct filter_ctx *ctx)
 376 {
 377         struct adapter *adapter = ethdev2adap(dev);
 378         struct tid_info *t = &adapter->tids;
 379         struct filter_entry *f;
 380         struct sge_ctrl_txq *ctrlq;
 381         unsigned int port_id = ethdev2pinfo(dev)->port_id;
 382         int ret;
 383
 384         if (filter_id > adapter->tids.ntids)
 385                 return -E2BIG;
 386
 387         f = lookup_tid(t, filter_id);
 388         if (!f) {
 389                 dev_err(adapter, "%s: no filter entry for filter_id = %d\n",
 390                         __func__, filter_id);
 391                 return -EINVAL;
 392         }
 393
 394         ret = writable_filter(f);
 395         if (ret)
 396                 return ret;
 397
 398         if (f->valid) {
 399                 unsigned int wrlen;
 400                 struct rte_mbuf *mbuf;
 401                 struct work_request_hdr *wr;
 402                 struct ulptx_idata *aligner;
 403                 struct cpl_set_tcb_field *req;
 404                 struct cpl_abort_req *abort_req;
 405                 struct cpl_abort_rpl *abort_rpl;
 406
 407                 f->ctx = ctx;
 408                 f->pending = 1;
 409
 410                 wrlen = cxgbe_roundup(sizeof(*wr) +
 411                                       (sizeof(*req) + sizeof(*aligner)) +
 412                                       sizeof(*abort_req) + sizeof(*abort_rpl),
 413                                       16);
 414
 415                 ctrlq = &adapter->sge.ctrlq[port_id];
 416                 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
 417                 if (!mbuf) {
 418                         dev_err(adapter, "%s: could not allocate skb ..\n",
 419                                 __func__);
 420                         goto out_err;
 421                 }
 422
 423                 mbuf->data_len = wrlen;
 424                 mbuf->pkt_len = mbuf->data_len;
 425
 426                 req = rte_pktmbuf_mtod(mbuf, struct cpl_set_tcb_field *);
 427                 INIT_ULPTX_WR(req, wrlen, 0, 0);
 428                 wr = (struct work_request_hdr *)req;
 429                 wr++;
 430                 req = (struct cpl_set_tcb_field *)wr;
 431                 mk_set_tcb_field_ulp(f, req, W_TCB_RSS_INFO,
 432                                 V_TCB_RSS_INFO(M_TCB_RSS_INFO),
 433                                 V_TCB_RSS_INFO(adapter->sge.fw_evtq.abs_id),
 434                                 0, 1);
 435                 aligner = (struct ulptx_idata *)(req + 1);
 436                 abort_req = (struct cpl_abort_req *)(aligner + 1);
 437                 mk_abort_req_ulp(abort_req, f->tid);
 438                 abort_rpl = (struct cpl_abort_rpl *)(abort_req + 1);
 439                 mk_abort_rpl_ulp(abort_rpl, f->tid);
 440                 t4_mgmt_tx(ctrlq, mbuf);
 441         }
 442         return 0;
 443
 444 out_err:
 445         return -ENOMEM;
 446 }
 447
 448 /**
 449  * Build a ACT_OPEN_REQ6 message for setting IPv6 hash filter.
 450  */
 451 static void mk_act_open_req6(struct filter_entry *f, struct rte_mbuf *mbuf,
 452                              unsigned int qid_filterid, struct adapter *adap)
 453 {
 454         struct cpl_t6_act_open_req6 *req = NULL;
 455         u64 local_lo, local_hi, peer_lo, peer_hi;
 456         u32 *lip = (u32 *)f->fs.val.lip;
 457         u32 *fip = (u32 *)f->fs.val.fip;
 458
 459         switch (CHELSIO_CHIP_VERSION(adap->params.chip)) {
 460         case CHELSIO_T6:
 461                 req = rte_pktmbuf_mtod(mbuf, struct cpl_t6_act_open_req6 *);
 462
 463                 INIT_TP_WR(req, 0);
 464                 break;
 465         default:
 466                 dev_err(adap, "%s: unsupported chip type!\n", __func__);
 467                 return;
 468         }
 469
 470         local_hi = ((u64)lip[1]) << 32 | lip[0];
 471         local_lo = ((u64)lip[3]) << 32 | lip[2];
 472         peer_hi = ((u64)fip[1]) << 32 | fip[0];
 473         peer_lo = ((u64)fip[3]) << 32 | fip[2];
 474
 475         OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_ACT_OPEN_REQ6,
 476                                                     qid_filterid));
 477         req->local_port = cpu_to_be16(f->fs.val.lport);
 478         req->peer_port = cpu_to_be16(f->fs.val.fport);
 479         req->local_ip_hi = local_hi;
 480         req->local_ip_lo = local_lo;
 481         req->peer_ip_hi = peer_hi;
 482         req->peer_ip_lo = peer_lo;
 483         req->opt0 = cpu_to_be64(V_NAGLE(f->fs.newvlan == VLAN_REMOVE ||
 484                                         f->fs.newvlan == VLAN_REWRITE) |
 485                                 V_DELACK(f->fs.hitcnts) |
 486                                 V_L2T_IDX(f->l2t ? f->l2t->idx : 0) |
 487                                 V_SMAC_SEL((cxgbe_port_viid(f->dev) & 0x7F)
 488                                            << 1) |
 489                                 V_TX_CHAN(f->fs.eport) |
 490                                 V_ULP_MODE(ULP_MODE_NONE) |
 491                                 F_TCAM_BYPASS | F_NON_OFFLOAD);
 492         req->params = cpu_to_be64(V_FILTER_TUPLE(hash_filter_ntuple(f)));
 493         req->opt2 = cpu_to_be32(F_RSS_QUEUE_VALID |
 494                             V_RSS_QUEUE(f->fs.iq) |
 495                             F_T5_OPT_2_VALID |
 496                             F_RX_CHANNEL |
 497                             V_SACK_EN(f->fs.swapmac) |
 498                             V_CONG_CNTRL((f->fs.action == FILTER_DROP) |
 499                                          (f->fs.dirsteer << 1)) |
 500                             V_CCTRL_ECN(f->fs.action == FILTER_SWITCH));
 501 }
 502
 503 /**
 504  * Build a ACT_OPEN_REQ message for setting IPv4 hash filter.
 505  */
 506 static void mk_act_open_req(struct filter_entry *f, struct rte_mbuf *mbuf,
 507                             unsigned int qid_filterid, struct adapter *adap)
 508 {
 509         struct cpl_t6_act_open_req *req = NULL;
 510
 511         switch (CHELSIO_CHIP_VERSION(adap->params.chip)) {
 512         case CHELSIO_T6:
 513                 req = rte_pktmbuf_mtod(mbuf, struct cpl_t6_act_open_req *);
 514
 515                 INIT_TP_WR(req, 0);
 516                 break;
 517         default:
 518                 dev_err(adap, "%s: unsupported chip type!\n", __func__);
 519                 return;
 520         }
 521
 522         OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_ACT_OPEN_REQ,
 523                                                     qid_filterid));
 524         req->local_port = cpu_to_be16(f->fs.val.lport);
 525         req->peer_port = cpu_to_be16(f->fs.val.fport);
 526         req->local_ip = f->fs.val.lip[0] | f->fs.val.lip[1] << 8 |
 527                         f->fs.val.lip[2] << 16 | f->fs.val.lip[3] << 24;
 528         req->peer_ip = f->fs.val.fip[0] | f->fs.val.fip[1] << 8 |
 529                         f->fs.val.fip[2] << 16 | f->fs.val.fip[3] << 24;
 530         req->opt0 = cpu_to_be64(V_NAGLE(f->fs.newvlan == VLAN_REMOVE ||
 531                                         f->fs.newvlan == VLAN_REWRITE) |
 532                                 V_DELACK(f->fs.hitcnts) |
 533                                 V_L2T_IDX(f->l2t ? f->l2t->idx : 0) |
 534                                 V_SMAC_SEL((cxgbe_port_viid(f->dev) & 0x7F)
 535                                            << 1) |
 536                                 V_TX_CHAN(f->fs.eport) |
 537                                 V_ULP_MODE(ULP_MODE_NONE) |
 538                                 F_TCAM_BYPASS | F_NON_OFFLOAD);
 539         req->params = cpu_to_be64(V_FILTER_TUPLE(hash_filter_ntuple(f)));
 540         req->opt2 = cpu_to_be32(F_RSS_QUEUE_VALID |
 541                             V_RSS_QUEUE(f->fs.iq) |
 542                             F_T5_OPT_2_VALID |
 543                             F_RX_CHANNEL |
 544                             V_SACK_EN(f->fs.swapmac) |
 545                             V_CONG_CNTRL((f->fs.action == FILTER_DROP) |
 546                                          (f->fs.dirsteer << 1)) |
 547                             V_CCTRL_ECN(f->fs.action == FILTER_SWITCH));
 548 }
 549
 550 /**
 551  * Set the specified hash filter.
 552  */
 553 static int cxgbe_set_hash_filter(struct rte_eth_dev *dev,
 554                                  struct ch_filter_specification *fs,
 555                                  struct filter_ctx *ctx)
 556 {
 557         struct port_info *pi = ethdev2pinfo(dev);
 558         struct adapter *adapter = pi->adapter;
 559         struct tid_info *t = &adapter->tids;
 560         struct filter_entry *f;
 561         struct rte_mbuf *mbuf;
 562         struct sge_ctrl_txq *ctrlq;
 563         unsigned int iq;
 564         int atid, size;
 565         int ret = 0;
 566
 567         ret = cxgbe_validate_filter(adapter, fs);
 568         if (ret)
 569                 return ret;
 570
 571         iq = get_filter_steerq(dev, fs);
 572
 573         ctrlq = &adapter->sge.ctrlq[pi->port_id];
 574
 575         f = t4_os_alloc(sizeof(*f));
 576         if (!f)
 577                 goto out_err;
 578
 579         f->fs = *fs;
 580         f->ctx = ctx;
 581         f->dev = dev;
 582         f->fs.iq = iq;
 583
 584         /*
 585          * If the new filter requires loopback Destination MAC and/or VLAN
 586          * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
 587          * the filter.
 588          */
 589         if (f->fs.newvlan == VLAN_INSERT ||
 590             f->fs.newvlan == VLAN_REWRITE) {
 591                 /* allocate L2T entry for new filter */
 592                 f->l2t = cxgbe_l2t_alloc_switching(dev, f->fs.vlan,
 593                                                    f->fs.eport, f->fs.dmac);
 594                 if (!f->l2t) {
 595                         ret = -ENOMEM;
 596                         goto out_err;
 597                 }
 598         }
 599
 600         atid = cxgbe_alloc_atid(t, f);
 601         if (atid < 0)
 602                 goto out_err;
 603
 604         if (f->fs.type == FILTER_TYPE_IPV6) {
 605                 /* IPv6 hash filter */
 606                 f->clipt = cxgbe_clip_alloc(f->dev, (u32 *)&f->fs.val.lip);
 607                 if (!f->clipt)
 608                         goto free_atid;
 609
 610                 size = sizeof(struct cpl_t6_act_open_req6);
 611                 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
 612                 if (!mbuf) {
 613                         ret = -ENOMEM;
 614                         goto free_clip;
 615                 }
 616
 617                 mbuf->data_len = size;
 618                 mbuf->pkt_len = mbuf->data_len;
 619
 620                 mk_act_open_req6(f, mbuf,
 621                                  ((adapter->sge.fw_evtq.abs_id << 14) | atid),
 622                                  adapter);
 623         } else {
 624                 /* IPv4 hash filter */
 625                 size = sizeof(struct cpl_t6_act_open_req);
 626                 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
 627                 if (!mbuf) {
 628                         ret = -ENOMEM;
 629                         goto free_atid;
 630                 }
 631
 632                 mbuf->data_len = size;
 633                 mbuf->pkt_len = mbuf->data_len;
 634
 635                 mk_act_open_req(f, mbuf,
 636                                 ((adapter->sge.fw_evtq.abs_id << 14) | atid),
 637                                 adapter);
 638         }
 639
 640         f->pending = 1;
 641         t4_mgmt_tx(ctrlq, mbuf);
 642         return 0;
 643
 644 free_clip:
 645         cxgbe_clip_release(f->dev, f->clipt);
 646 free_atid:
 647         cxgbe_free_atid(t, atid);
 648
 649 out_err:
 650         t4_os_free(f);
 651         return ret;
 652 }
 653
 654 /**
 655  * Clear a filter and release any of its resources that we own.  This also
 656  * clears the filter's "pending" status.
 657  */
 658 static void clear_filter(struct filter_entry *f)
 659 {
 660         if (f->clipt)
 661                 cxgbe_clip_release(f->dev, f->clipt);
 662
 663         /*
 664          * The zeroing of the filter rule below clears the filter valid,
 665          * pending, locked flags etc. so it's all we need for
 666          * this operation.
 667          */
 668         memset(f, 0, sizeof(*f));
 669 }
 670
 671 /**
 672  * t4_mk_filtdelwr - create a delete filter WR
 673  * @adap: adapter context
 674  * @ftid: the filter ID
 675  * @wr: the filter work request to populate
 676  * @qid: ingress queue to receive the delete notification
 677  *
 678  * Creates a filter work request to delete the supplied filter.  If @qid is
 679  * negative the delete notification is suppressed.
 680  */
 681 static void t4_mk_filtdelwr(struct adapter *adap, unsigned int ftid,
 682                             struct fw_filter2_wr *wr, int qid)
 683 {
 684         memset(wr, 0, sizeof(*wr));
 685         if (adap->params.filter2_wr_support)
 686                 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER2_WR));
 687         else
 688                 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
 689         wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16));
 690         wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) |
 691                                     V_FW_FILTER_WR_NOREPLY(qid < 0));
 692         wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER);
 693         if (qid >= 0)
 694                 wr->rx_chan_rx_rpl_iq =
 695                                 cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid));
 696 }
 697
 698 /**
 699  * Create FW work request to delete the filter at a specified index
 700  */
 701 static int del_filter_wr(struct rte_eth_dev *dev, unsigned int fidx)
 702 {
 703         struct adapter *adapter = ethdev2adap(dev);
 704         struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
 705         struct rte_mbuf *mbuf;
 706         struct fw_filter2_wr *fwr;
 707         struct sge_ctrl_txq *ctrlq;
 708         unsigned int port_id = ethdev2pinfo(dev)->port_id;
 709
 710         ctrlq = &adapter->sge.ctrlq[port_id];
 711         mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
 712         if (!mbuf)
 713                 return -ENOMEM;
 714
 715         mbuf->data_len = sizeof(*fwr);
 716         mbuf->pkt_len = mbuf->data_len;
 717
 718         fwr = rte_pktmbuf_mtod(mbuf, struct fw_filter2_wr *);
 719         t4_mk_filtdelwr(adapter, f->tid, fwr, adapter->sge.fw_evtq.abs_id);
 720
 721         /*
 722          * Mark the filter as "pending" and ship off the Filter Work Request.
 723          * When we get the Work Request Reply we'll clear the pending status.
 724          */
 725         f->pending = 1;
 726         t4_mgmt_tx(ctrlq, mbuf);
 727         return 0;
 728 }
 729
 730 static int set_filter_wr(struct rte_eth_dev *dev, unsigned int fidx)
 731 {
 732         struct adapter *adapter = ethdev2adap(dev);
 733         struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
 734         struct rte_mbuf *mbuf;
 735         struct fw_filter2_wr *fwr;
 736         struct sge_ctrl_txq *ctrlq;
 737         unsigned int port_id = ethdev2pinfo(dev)->port_id;
 738         int ret;
 739
 740         /*
 741          * If the new filter requires loopback Destination MAC and/or VLAN
 742          * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
 743          * the filter.
 744          */
 745         if (f->fs.newvlan) {
 746                 /* allocate L2T entry for new filter */
 747                 f->l2t = cxgbe_l2t_alloc_switching(f->dev, f->fs.vlan,
 748                                                    f->fs.eport, f->fs.dmac);
 749                 if (!f->l2t)
 750                         return -ENOMEM;
 751         }
 752
 753         ctrlq = &adapter->sge.ctrlq[port_id];
 754         mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
 755         if (!mbuf) {
 756                 ret = -ENOMEM;
 757                 goto out;
 758         }
 759
 760         mbuf->data_len = sizeof(*fwr);
 761         mbuf->pkt_len = mbuf->data_len;
 762
 763         fwr = rte_pktmbuf_mtod(mbuf, struct fw_filter2_wr *);
 764         memset(fwr, 0, sizeof(*fwr));
 765
 766         /*
 767          * Construct the work request to set the filter.
 768          */
 769         if (adapter->params.filter2_wr_support)
 770                 fwr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER2_WR));
 771         else
 772                 fwr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
 773         fwr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*fwr) / 16));
 774         fwr->tid_to_iq =
 775                 cpu_to_be32(V_FW_FILTER_WR_TID(f->tid) |
 776                             V_FW_FILTER_WR_RQTYPE(f->fs.type) |
 777                             V_FW_FILTER_WR_NOREPLY(0) |
 778                             V_FW_FILTER_WR_IQ(f->fs.iq));
 779         fwr->del_filter_to_l2tix =
 780                 cpu_to_be32(V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
 781                             V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
 782                             V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
 783                             V_FW_FILTER_WR_INSVLAN
 784                                 (f->fs.newvlan == VLAN_INSERT ||
 785                                  f->fs.newvlan == VLAN_REWRITE) |
 786                             V_FW_FILTER_WR_RMVLAN
 787                                 (f->fs.newvlan == VLAN_REMOVE ||
 788                                  f->fs.newvlan == VLAN_REWRITE) |
 789                             V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
 790                             V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
 791                             V_FW_FILTER_WR_PRIO(f->fs.prio) |
 792                             V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
 793         fwr->ethtype = cpu_to_be16(f->fs.val.ethtype);
 794         fwr->ethtypem = cpu_to_be16(f->fs.mask.ethtype);
 795         fwr->frag_to_ovlan_vldm =
 796                 (V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.ivlan_vld) |
 797                  V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.ivlan_vld) |
 798                  V_FW_FILTER_WR_OVLAN_VLD(f->fs.val.ovlan_vld) |
 799                  V_FW_FILTER_WR_OVLAN_VLDM(f->fs.mask.ovlan_vld));
 800         fwr->smac_sel = 0;
 801         fwr->rx_chan_rx_rpl_iq =
 802                 cpu_to_be16(V_FW_FILTER_WR_RX_CHAN(0) |
 803                             V_FW_FILTER_WR_RX_RPL_IQ(adapter->sge.fw_evtq.abs_id
 804                                                      ));
 805         fwr->maci_to_matchtypem =
 806                 cpu_to_be32(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
 807                             V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
 808                             V_FW_FILTER_WR_PORT(f->fs.val.iport) |
 809                             V_FW_FILTER_WR_PORTM(f->fs.mask.iport));
 810         fwr->ptcl = f->fs.val.proto;
 811         fwr->ptclm = f->fs.mask.proto;
 812         fwr->ttyp = f->fs.val.tos;
 813         fwr->ttypm = f->fs.mask.tos;
 814         fwr->ivlan = cpu_to_be16(f->fs.val.ivlan);
 815         fwr->ivlanm = cpu_to_be16(f->fs.mask.ivlan);
 816         fwr->ovlan = cpu_to_be16(f->fs.val.ovlan);
 817         fwr->ovlanm = cpu_to_be16(f->fs.mask.ovlan);
 818         rte_memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
 819         rte_memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
 820         rte_memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
 821         rte_memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
 822         fwr->lp = cpu_to_be16(f->fs.val.lport);
 823         fwr->lpm = cpu_to_be16(f->fs.mask.lport);
 824         fwr->fp = cpu_to_be16(f->fs.val.fport);
 825         fwr->fpm = cpu_to_be16(f->fs.mask.fport);
 826
 827         if (adapter->params.filter2_wr_support) {
 828                 fwr->filter_type_swapmac =
 829                          V_FW_FILTER2_WR_SWAPMAC(f->fs.swapmac);
 830                 fwr->natmode_to_ulp_type =
 831                         V_FW_FILTER2_WR_ULP_TYPE(f->fs.nat_mode ?
 832                                                  ULP_MODE_TCPDDP :
 833                                                  ULP_MODE_NONE) |
 834                         V_FW_FILTER2_WR_NATMODE(f->fs.nat_mode);
 835                 memcpy(fwr->newlip, f->fs.nat_lip, sizeof(fwr->newlip));
 836                 memcpy(fwr->newfip, f->fs.nat_fip, sizeof(fwr->newfip));
 837                 fwr->newlport = cpu_to_be16(f->fs.nat_lport);
 838                 fwr->newfport = cpu_to_be16(f->fs.nat_fport);
 839         }
 840
 841         /*
 842          * Mark the filter as "pending" and ship off the Filter Work Request.
 843          * When we get the Work Request Reply we'll clear the pending status.
 844          */
 845         f->pending = 1;
 846         t4_mgmt_tx(ctrlq, mbuf);
 847         return 0;
 848
 849 out:
 850         return ret;
 851 }
 852
 853 /**
 854  * Set the corresponding entries in the bitmap.
 855  */
 856 static int cxgbe_set_ftid(struct tid_info *t, u32 fidx, u8 nentries)
 857 {
 858         u32 i;
 859
 860         t4_os_lock(&t->ftid_lock);
 861         if (rte_bitmap_get(t->ftid_bmap, fidx)) {
 862                 t4_os_unlock(&t->ftid_lock);
 863                 return -EBUSY;
 864         }
 865
 866         for (i = fidx; i < fidx + nentries; i++)
 867                 rte_bitmap_set(t->ftid_bmap, i);
 868         t4_os_unlock(&t->ftid_lock);
 869         return 0;
 870 }
 871
 872 /**
 873  * Clear the corresponding entries in the bitmap.
 874  */
 875 static void cxgbe_clear_ftid(struct tid_info *t, u32 fidx, u8 nentries)
 876 {
 877         u32 i;
 878
 879         t4_os_lock(&t->ftid_lock);
 880         for (i = fidx; i < fidx + nentries; i++)
 881                 rte_bitmap_clear(t->ftid_bmap, i);
 882         t4_os_unlock(&t->ftid_lock);
 883 }
 884
 885 /**
 886  * Check a delete filter request for validity and send it to the hardware.
 887  * Return 0 on success, an error number otherwise.  We attach any provided
 888  * filter operation context to the internal filter specification in order to
 889  * facilitate signaling completion of the operation.
 890  */
 891 int cxgbe_del_filter(struct rte_eth_dev *dev, unsigned int filter_id,
 892                      struct ch_filter_specification *fs,
 893                      struct filter_ctx *ctx)
 894 {
 895         struct port_info *pi = dev->data->dev_private;
 896         struct adapter *adapter = pi->adapter;
 897         struct filter_entry *f;
 898         unsigned int chip_ver;
 899         u8 nentries;
 900         int ret;
 901
 902         if (is_hashfilter(adapter) && fs->cap)
 903                 return cxgbe_del_hash_filter(dev, filter_id, ctx);
 904
 905         if (filter_id >= adapter->tids.nftids)
 906                 return -ERANGE;
 907
 908         chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
 909
 910         /*
 911          * Ensure IPv6 filter id is aligned on the 2 slot boundary for T6,
 912          * and 4 slot boundary for cards below T6.
 913          */
 914         if (fs->type == FILTER_TYPE_IPV6) {
 915                 if (chip_ver < CHELSIO_T6)
 916                         filter_id &= ~(0x3);
 917                 else
 918                         filter_id &= ~(0x1);
 919         }
 920
 921         nentries = cxgbe_filter_slots(adapter, fs->type);
 922         ret = cxgbe_is_filter_set(&adapter->tids, filter_id, nentries);
 923         if (!ret) {
 924                 dev_warn(adap, "%s: could not find filter entry: %u\n",
 925                          __func__, filter_id);
 926                 return -EINVAL;
 927         }
 928
 929         f = &adapter->tids.ftid_tab[filter_id];
 930         ret = writable_filter(f);
 931         if (ret)
 932                 return ret;
 933
 934         if (f->valid) {
 935                 f->ctx = ctx;
 936                 cxgbe_clear_ftid(&adapter->tids,
 937                                  f->tid - adapter->tids.ftid_base,
 938                                  nentries);
 939                 return del_filter_wr(dev, filter_id);
 940         }
 941
 942         /*
 943          * If the caller has passed in a Completion Context then we need to
 944          * mark it as a successful completion so they don't stall waiting
 945          * for it.
 946          */
 947         if (ctx) {
 948                 ctx->result = 0;
 949                 t4_complete(&ctx->completion);
 950         }
 951
 952         return 0;
 953 }
 954
 955 /**
 956  * Check a Chelsio Filter Request for validity, convert it into our internal
 957  * format and send it to the hardware.  Return 0 on success, an error number
 958  * otherwise.  We attach any provided filter operation context to the internal
 959  * filter specification in order to facilitate signaling completion of the
 960  * operation.
 961  */
 962 int cxgbe_set_filter(struct rte_eth_dev *dev, unsigned int filter_id,
 963                      struct ch_filter_specification *fs,
 964                      struct filter_ctx *ctx)
 965 {
 966         struct port_info *pi = ethdev2pinfo(dev);
 967         struct adapter *adapter = pi->adapter;
 968         unsigned int fidx, iq;
 969         struct filter_entry *f;
 970         unsigned int chip_ver;
 971         u8 nentries, bitoff[16] = {0};
 972         int ret;
 973
 974         if (is_hashfilter(adapter) && fs->cap)
 975                 return cxgbe_set_hash_filter(dev, fs, ctx);
 976
 977         if (filter_id >= adapter->tids.nftids)
 978                 return -ERANGE;
 979
 980         chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
 981
 982         ret = cxgbe_validate_filter(adapter, fs);
 983         if (ret)
 984                 return ret;
 985
 986         /*
 987          * IPv6 filters occupy four slots and must be aligned on four-slot
 988          * boundaries for T5. On T6, IPv6 filters occupy two-slots and
 989          * must be aligned on two-slot boundaries.
 990          *
 991          * IPv4 filters only occupy a single slot and have no alignment
 992          * requirements.
 993          */
 994         fidx = filter_id;
 995         if (fs->type == FILTER_TYPE_IPV6) {
 996                 if (chip_ver < CHELSIO_T6)
 997                         fidx &= ~(0x3);
 998                 else
 999                         fidx &= ~(0x1);
1000         }
1001
1002         if (fidx != filter_id)
1003                 return -EINVAL;
1004
1005         nentries = cxgbe_filter_slots(adapter, fs->type);
1006         ret = cxgbe_is_filter_set(&adapter->tids, filter_id, nentries);
1007         if (ret)
1008                 return -EBUSY;
1009
1010         iq = get_filter_steerq(dev, fs);
1011
1012         /*
1013          * Check to make sure that provided filter index is not
1014          * already in use by someone else
1015          */
1016         f = &adapter->tids.ftid_tab[filter_id];
1017         if (f->valid)
1018                 return -EBUSY;
1019
1020         fidx = adapter->tids.ftid_base + filter_id;
1021         ret = cxgbe_set_ftid(&adapter->tids, filter_id, nentries);
1022         if (ret)
1023                 return ret;
1024
1025         /*
1026          * Check to make sure the filter requested is writable ...
1027          */
1028         ret = writable_filter(f);
1029         if (ret) {
1030                 /* Clear the bits we have set above */
1031                 cxgbe_clear_ftid(&adapter->tids, filter_id, nentries);
1032                 return ret;
1033         }
1034
1035         /*
1036          * Allocate a clip table entry only if we have non-zero IPv6 address
1037          */
1038         if (chip_ver > CHELSIO_T5 && fs->type &&
1039             memcmp(fs->val.lip, bitoff, sizeof(bitoff))) {
1040                 f->clipt = cxgbe_clip_alloc(dev, (u32 *)&fs->val.lip);
1041                 if (!f->clipt)
1042                         goto free_tid;
1043         }
1044
1045         /*
1046          * Convert the filter specification into our internal format.
1047          * We copy the PF/VF specification into the Outer VLAN field
1048          * here so the rest of the code -- including the interface to
1049          * the firmware -- doesn't have to constantly do these checks.
1050          */
1051         f->fs = *fs;
1052         f->fs.iq = iq;
1053         f->dev = dev;
1054
1055         /*
1056          * Attempt to set the filter.  If we don't succeed, we clear
1057          * it and return the failure.
1058          */
1059         f->ctx = ctx;
1060         f->tid = fidx; /* Save the actual tid */
1061         ret = set_filter_wr(dev, filter_id);
1062         if (ret)
1063                 goto free_tid;
1064
1065         return ret;
1066
1067 free_tid:
1068         cxgbe_clear_ftid(&adapter->tids, filter_id, nentries);
1069         clear_filter(f);
1070         return ret;
1071 }
1072
1073 /**
1074  * Handle a Hash filter write reply.
1075  */
1076 void cxgbe_hash_filter_rpl(struct adapter *adap,
1077                            const struct cpl_act_open_rpl *rpl)
1078 {
1079         struct tid_info *t = &adap->tids;
1080         struct filter_entry *f;
1081         struct filter_ctx *ctx = NULL;
1082         unsigned int tid = GET_TID(rpl);
1083         unsigned int ftid = G_TID_TID(G_AOPEN_ATID
1084                                       (be32_to_cpu(rpl->atid_status)));
1085         unsigned int status  = G_AOPEN_STATUS(be32_to_cpu(rpl->atid_status));
1086
1087         f = lookup_atid(t, ftid);
1088         if (!f) {
1089                 dev_warn(adap, "%s: could not find filter entry: %d\n",
1090                          __func__, ftid);
1091                 return;
1092         }
1093
1094         ctx = f->ctx;
1095         f->ctx = NULL;
1096
1097         switch (status) {
1098         case CPL_ERR_NONE: {
1099                 f->tid = tid;
1100                 f->pending = 0;  /* asynchronous setup completed */
1101                 f->valid = 1;
1102
1103                 cxgbe_insert_tid(t, f, f->tid, 0);
1104                 cxgbe_free_atid(t, ftid);
1105                 if (ctx) {
1106                         ctx->tid = f->tid;
1107                         ctx->result = 0;
1108                 }
1109                 if (f->fs.hitcnts)
1110                         set_tcb_field(adap, tid,
1111                                       W_TCB_TIMESTAMP,
1112                                       V_TCB_TIMESTAMP(M_TCB_TIMESTAMP) |
1113                                       V_TCB_T_RTT_TS_RECENT_AGE
1114                                               (M_TCB_T_RTT_TS_RECENT_AGE),
1115                                       V_TCB_TIMESTAMP(0ULL) |
1116                                       V_TCB_T_RTT_TS_RECENT_AGE(0ULL),
1117                                       1);
1118                 if (f->fs.newvlan == VLAN_INSERT ||
1119                     f->fs.newvlan == VLAN_REWRITE)
1120                         set_tcb_tflag(adap, tid, S_TF_CCTRL_RFR, 1, 1);
1121                 break;
1122         }
1123         default:
1124                 dev_warn(adap, "%s: filter creation failed with status = %u\n",
1125                          __func__, status);
1126
1127                 if (ctx) {
1128                         if (status == CPL_ERR_TCAM_FULL)
1129                                 ctx->result = -EAGAIN;
1130                         else
1131                                 ctx->result = -EINVAL;
1132                 }
1133
1134                 cxgbe_free_atid(t, ftid);
1135                 t4_os_free(f);
1136         }
1137
1138         if (ctx)
1139                 t4_complete(&ctx->completion);
1140 }
1141
1142 /**
1143  * Handle a LE-TCAM filter write/deletion reply.
1144  */
1145 void cxgbe_filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
1146 {
1147         struct filter_entry *f = NULL;
1148         unsigned int tid = GET_TID(rpl);
1149         int idx, max_fidx = adap->tids.nftids;
1150
1151         /* Get the corresponding filter entry for this tid */
1152         if (adap->tids.ftid_tab) {
1153                 /* Check this in normal filter region */
1154                 idx = tid - adap->tids.ftid_base;
1155                 if (idx >= max_fidx)
1156                         return;
1157
1158                 f = &adap->tids.ftid_tab[idx];
1159                 if (f->tid != tid)
1160                         return;
1161         }
1162
1163         /* We found the filter entry for this tid */
1164         if (f) {
1165                 unsigned int ret = G_COOKIE(rpl->cookie);
1166                 struct filter_ctx *ctx;
1167
1168                 /*
1169                  * Pull off any filter operation context attached to the
1170                  * filter.
1171                  */
1172                 ctx = f->ctx;
1173                 f->ctx = NULL;
1174
1175                 if (ret == FW_FILTER_WR_FLT_ADDED) {
1176                         f->pending = 0;  /* asynchronous setup completed */
1177                         f->valid = 1;
1178                         if (ctx) {
1179                                 ctx->tid = f->tid;
1180                                 ctx->result = 0;
1181                         }
1182                 } else if (ret == FW_FILTER_WR_FLT_DELETED) {
1183                         /*
1184                          * Clear the filter when we get confirmation from the
1185                          * hardware that the filter has been deleted.
1186                          */
1187                         clear_filter(f);
1188                         if (ctx)
1189                                 ctx->result = 0;
1190                 } else {
1191                         /*
1192                          * Something went wrong.  Issue a warning about the
1193                          * problem and clear everything out.
1194                          */
1195                         dev_warn(adap, "filter %u setup failed with error %u\n",
1196                                  idx, ret);
1197                         clear_filter(f);
1198                         if (ctx)
1199                                 ctx->result = -EINVAL;
1200                 }
1201
1202                 if (ctx)
1203                         t4_complete(&ctx->completion);
1204         }
1205 }
1206
1207 /*
1208  * Retrieve the packet count for the specified filter.
1209  */
1210 int cxgbe_get_filter_count(struct adapter *adapter, unsigned int fidx,
1211                            u64 *c, int hash, bool get_byte)
1212 {
1213         struct filter_entry *f;
1214         unsigned int tcb_base, tcbaddr;
1215         int ret;
1216
1217         tcb_base = t4_read_reg(adapter, A_TP_CMM_TCB_BASE);
1218         if (is_hashfilter(adapter) && hash) {
1219                 if (fidx < adapter->tids.ntids) {
1220                         f = adapter->tids.tid_tab[fidx];
1221                         if (!f)
1222                                 return -EINVAL;
1223
1224                         if (is_t5(adapter->params.chip)) {
1225                                 *c = 0;
1226                                 return 0;
1227                         }
1228                         tcbaddr = tcb_base + (fidx * TCB_SIZE);
1229                         goto get_count;
1230                 } else {
1231                         return -ERANGE;
1232                 }
1233         } else {
1234                 if (fidx >= adapter->tids.nftids)
1235                         return -ERANGE;
1236
1237                 f = &adapter->tids.ftid_tab[fidx];
1238                 if (!f->valid)
1239                         return -EINVAL;
1240
1241                 tcbaddr = tcb_base + f->tid * TCB_SIZE;
1242         }
1243
1244         f = &adapter->tids.ftid_tab[fidx];
1245         if (!f->valid)
1246                 return -EINVAL;
1247
1248 get_count:
1249         if (is_t5(adapter->params.chip) || is_t6(adapter->params.chip)) {
1250                 /*
1251                  * For T5, the Filter Packet Hit Count is maintained as a
1252                  * 32-bit Big Endian value in the TCB field {timestamp}.
1253                  * Similar to the craziness above, instead of the filter hit
1254                  * count showing up at offset 20 ((W_TCB_TIMESTAMP == 5) *
1255                  * sizeof(u32)), it actually shows up at offset 24.  Whacky.
1256                  */
1257                 if (get_byte) {
1258                         unsigned int word_offset = 4;
1259                         __be64 be64_byte_count;
1260
1261                         t4_os_lock(&adapter->win0_lock);
1262                         ret = t4_memory_rw(adapter, MEMWIN_NIC, MEM_EDC0,
1263                                            tcbaddr +
1264                                            (word_offset * sizeof(__be32)),
1265                                            sizeof(be64_byte_count),
1266                                            &be64_byte_count,
1267                                            T4_MEMORY_READ);
1268                         t4_os_unlock(&adapter->win0_lock);
1269                         if (ret < 0)
1270                                 return ret;
1271                         *c = be64_to_cpu(be64_byte_count);
1272                 } else {
1273                         unsigned int word_offset = 6;
1274                         __be32 be32_count;
1275
1276                         t4_os_lock(&adapter->win0_lock);
1277                         ret = t4_memory_rw(adapter, MEMWIN_NIC, MEM_EDC0,
1278                                            tcbaddr +
1279                                            (word_offset * sizeof(__be32)),
1280                                            sizeof(be32_count), &be32_count,
1281                                            T4_MEMORY_READ);
1282                         t4_os_unlock(&adapter->win0_lock);
1283                         if (ret < 0)
1284                                 return ret;
1285                         *c = (u64)be32_to_cpu(be32_count);
1286                 }
1287         }
1288         return 0;
1289 }
1290
1291 /*
1292  * Clear the packet count for the specified filter.
1293  */
1294 int cxgbe_clear_filter_count(struct adapter *adapter, unsigned int fidx,
1295                              int hash, bool clear_byte)
1296 {
1297         u64 tcb_mask = 0, tcb_val = 0;
1298         struct filter_entry *f = NULL;
1299         u16 tcb_word = 0;
1300
1301         if (is_hashfilter(adapter) && hash) {
1302                 if (fidx >= adapter->tids.ntids)
1303                         return -ERANGE;
1304
1305                 /* No hitcounts supported for T5 hashfilters */
1306                 if (is_t5(adapter->params.chip))
1307                         return 0;
1308
1309                 f = adapter->tids.tid_tab[fidx];
1310         } else {
1311                 if (fidx >= adapter->tids.nftids)
1312                         return -ERANGE;
1313
1314                 f = &adapter->tids.ftid_tab[fidx];
1315         }
1316
1317         if (!f || !f->valid)
1318                 return -EINVAL;
1319
1320         tcb_word = W_TCB_TIMESTAMP;
1321         tcb_mask = V_TCB_TIMESTAMP(M_TCB_TIMESTAMP);
1322         tcb_val = V_TCB_TIMESTAMP(0ULL);
1323
1324         set_tcb_field(adapter, f->tid, tcb_word, tcb_mask, tcb_val, 1);
1325
1326         if (clear_byte) {
1327                 tcb_word = W_TCB_T_RTT_TS_RECENT_AGE;
1328                 tcb_mask =
1329                         V_TCB_T_RTT_TS_RECENT_AGE(M_TCB_T_RTT_TS_RECENT_AGE) |
1330                         V_TCB_T_RTSEQ_RECENT(M_TCB_T_RTSEQ_RECENT);
1331                 tcb_val = V_TCB_T_RTT_TS_RECENT_AGE(0ULL) |
1332                           V_TCB_T_RTSEQ_RECENT(0ULL);
1333
1334                 set_tcb_field(adapter, f->tid, tcb_word, tcb_mask, tcb_val, 1);
1335         }
1336
1337         return 0;
1338 }
1339
1340 /**
1341  * Handle a Hash filter delete reply.
1342  */
1343 void cxgbe_hash_del_filter_rpl(struct adapter *adap,
1344                                const struct cpl_abort_rpl_rss *rpl)
1345 {
1346         struct tid_info *t = &adap->tids;
1347         struct filter_entry *f;
1348         struct filter_ctx *ctx = NULL;
1349         unsigned int tid = GET_TID(rpl);
1350
1351         f = lookup_tid(t, tid);
1352         if (!f) {
1353                 dev_warn(adap, "%s: could not find filter entry: %u\n",
1354                          __func__, tid);
1355                 return;
1356         }
1357
1358         ctx = f->ctx;
1359         f->ctx = NULL;
1360
1361         f->valid = 0;
1362
1363         if (f->clipt)
1364                 cxgbe_clip_release(f->dev, f->clipt);
1365
1366         cxgbe_remove_tid(t, 0, tid, 0);
1367         t4_os_free(f);
1368
1369         if (ctx) {
1370                 ctx->result = 0;
1371                 t4_complete(&ctx->completion);
1372         }
1373 }