drivers/net/cxgbe/cxgbe_filter.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Chelsio Communications.
   3  * All rights reserved.
   4  */
   5 #include <rte_net.h>
   6
   7 #include "base/common.h"
   8 #include "base/t4_tcb.h"
   9 #include "base/t4_regs.h"
  10 #include "cxgbe_filter.h"
  11 #include "clip_tbl.h"
  12 #include "l2t.h"
  13
  14 /**
  15  * Initialize Hash Filters
  16  */
  17 int cxgbe_init_hash_filter(struct adapter *adap)
  18 {
  19         unsigned int n_user_filters;
  20         unsigned int user_filter_perc;
  21         int ret;
  22         u32 params[7], val[7];
  23
  24 #define FW_PARAM_DEV(param) \
  25         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
  26         V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
  27
  28 #define FW_PARAM_PFVF(param) \
  29         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
  30         V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) |  \
  31         V_FW_PARAMS_PARAM_Y(0) | \
  32         V_FW_PARAMS_PARAM_Z(0))
  33
  34         params[0] = FW_PARAM_DEV(NTID);
  35         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
  36                               params, val);
  37         if (ret < 0)
  38                 return ret;
  39         adap->tids.ntids = val[0];
  40         adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
  41
  42         user_filter_perc = 100;
  43         n_user_filters = mult_frac(adap->tids.nftids,
  44                                    user_filter_perc,
  45                                    100);
  46
  47         adap->tids.nftids = n_user_filters;
  48         adap->params.hash_filter = 1;
  49         return 0;
  50 }
  51
  52 /**
  53  * Validate if the requested filter specification can be set by checking
  54  * if the requested features have been enabled
  55  */
  56 int cxgbe_validate_filter(struct adapter *adapter,
  57                           struct ch_filter_specification *fs)
  58 {
  59         u32 fconf, iconf;
  60
  61         /*
  62          * Check for unconfigured fields being used.
  63          */
  64         fconf = adapter->params.tp.vlan_pri_map;
  65
  66         iconf = adapter->params.tp.ingress_config;
  67
  68 #define S(_field) \
  69         (fs->val._field || fs->mask._field)
  70 #define U(_mask, _field) \
  71         (!(fconf & (_mask)) && S(_field))
  72
  73         if (U(F_PORT, iport) || U(F_ETHERTYPE, ethtype) ||
  74             U(F_PROTOCOL, proto) || U(F_MACMATCH, macidx) ||
  75             U(F_VLAN, ivlan_vld) || U(F_VNIC_ID, ovlan_vld) ||
  76             U(F_TOS, tos) || U(F_VNIC_ID, pfvf_vld))
  77                 return -EOPNOTSUPP;
  78
  79         /* Either OVLAN or PFVF match is enabled in hardware, but not both */
  80         if ((S(pfvf_vld) && !(iconf & F_VNIC)) ||
  81             (S(ovlan_vld) && (iconf & F_VNIC)))
  82                 return -EOPNOTSUPP;
  83
  84         /* To use OVLAN or PFVF, L4 encapsulation match must not be enabled */
  85         if ((S(ovlan_vld) && (iconf & F_USE_ENC_IDX)) ||
  86             (S(pfvf_vld) && (iconf & F_USE_ENC_IDX)))
  87                 return -EOPNOTSUPP;
  88
  89 #undef S
  90 #undef U
  91
  92         /*
  93          * If the user is requesting that the filter action loop
  94          * matching packets back out one of our ports, make sure that
  95          * the egress port is in range.
  96          */
  97         if (fs->action == FILTER_SWITCH &&
  98             fs->eport >= adapter->params.nports)
  99                 return -ERANGE;
 100
 101         /*
 102          * Don't allow various trivially obvious bogus out-of-range
 103          * values ...
 104          */
 105         if (fs->val.iport >= adapter->params.nports)
 106                 return -ERANGE;
 107
 108         if (!fs->cap && fs->nat_mode && !adapter->params.filter2_wr_support)
 109                 return -EOPNOTSUPP;
 110
 111         if (!fs->cap && fs->swapmac && !adapter->params.filter2_wr_support)
 112                 return -EOPNOTSUPP;
 113
 114         return 0;
 115 }
 116
 117 /**
 118  * Get the queue to which the traffic must be steered to.
 119  */
 120 static unsigned int get_filter_steerq(struct rte_eth_dev *dev,
 121                                       struct ch_filter_specification *fs)
 122 {
 123         struct port_info *pi = ethdev2pinfo(dev);
 124         struct adapter *adapter = pi->adapter;
 125         unsigned int iq;
 126
 127         /*
 128          * If the user has requested steering matching Ingress Packets
 129          * to a specific Queue Set, we need to make sure it's in range
 130          * for the port and map that into the Absolute Queue ID of the
 131          * Queue Set's Response Queue.
 132          */
 133         if (!fs->dirsteer) {
 134                 iq = 0;
 135         } else {
 136                 /*
 137                  * If the iq id is greater than the number of qsets,
 138                  * then assume it is an absolute qid.
 139                  */
 140                 if (fs->iq < pi->n_rx_qsets)
 141                         iq = adapter->sge.ethrxq[pi->first_qset +
 142                                                  fs->iq].rspq.abs_id;
 143                 else
 144                         iq = fs->iq;
 145         }
 146
 147         return iq;
 148 }
 149
 150 /* Return an error number if the indicated filter isn't writable ... */
 151 static int writable_filter(struct filter_entry *f)
 152 {
 153         if (f->locked)
 154                 return -EPERM;
 155         if (f->pending)
 156                 return -EBUSY;
 157
 158         return 0;
 159 }
 160
 161 /**
 162  * Send CPL_SET_TCB_FIELD message
 163  */
 164 static void set_tcb_field(struct adapter *adapter, unsigned int ftid,
 165                           u16 word, u64 mask, u64 val, int no_reply)
 166 {
 167         struct rte_mbuf *mbuf;
 168         struct cpl_set_tcb_field *req;
 169         struct sge_ctrl_txq *ctrlq;
 170
 171         ctrlq = &adapter->sge.ctrlq[0];
 172         mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
 173         WARN_ON(!mbuf);
 174
 175         mbuf->data_len = sizeof(*req);
 176         mbuf->pkt_len = mbuf->data_len;
 177
 178         req = rte_pktmbuf_mtod(mbuf, struct cpl_set_tcb_field *);
 179         memset(req, 0, sizeof(*req));
 180         INIT_TP_WR_MIT_CPL(req, CPL_SET_TCB_FIELD, ftid);
 181         req->reply_ctrl = cpu_to_be16(V_REPLY_CHAN(0) |
 182                                       V_QUEUENO(adapter->sge.fw_evtq.abs_id) |
 183                                       V_NO_REPLY(no_reply));
 184         req->word_cookie = cpu_to_be16(V_WORD(word) | V_COOKIE(ftid));
 185         req->mask = cpu_to_be64(mask);
 186         req->val = cpu_to_be64(val);
 187
 188         t4_mgmt_tx(ctrlq, mbuf);
 189 }
 190
 191 /**
 192  * Set one of the t_flags bits in the TCB.
 193  */
 194 static void set_tcb_tflag(struct adapter *adap, unsigned int ftid,
 195                           unsigned int bit_pos, unsigned int val, int no_reply)
 196 {
 197         set_tcb_field(adap, ftid,  W_TCB_T_FLAGS, 1ULL << bit_pos,
 198                       (unsigned long long)val << bit_pos, no_reply);
 199 }
 200
 201 /**
 202  * Build a CPL_SET_TCB_FIELD message as payload of a ULP_TX_PKT command.
 203  */
 204 static inline void mk_set_tcb_field_ulp(struct filter_entry *f,
 205                                         struct cpl_set_tcb_field *req,
 206                                         unsigned int word,
 207                                         u64 mask, u64 val, u8 cookie,
 208                                         int no_reply)
 209 {
 210         struct ulp_txpkt *txpkt = (struct ulp_txpkt *)req;
 211         struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1);
 212
 213         txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
 214                                       V_ULP_TXPKT_DEST(0));
 215         txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*req), 16));
 216         sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
 217         sc->len = cpu_to_be32(sizeof(*req) - sizeof(struct work_request_hdr));
 218         OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_SET_TCB_FIELD, f->tid));
 219         req->reply_ctrl = cpu_to_be16(V_NO_REPLY(no_reply) | V_REPLY_CHAN(0) |
 220                                       V_QUEUENO(0));
 221         req->word_cookie = cpu_to_be16(V_WORD(word) | V_COOKIE(cookie));
 222         req->mask = cpu_to_be64(mask);
 223         req->val = cpu_to_be64(val);
 224         sc = (struct ulptx_idata *)(req + 1);
 225         sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
 226         sc->len = cpu_to_be32(0);
 227 }
 228
 229 /**
 230  * IPv6 requires 2 slots on T6 and 4 slots for cards below T6.
 231  * IPv4 requires only 1 slot on all cards.
 232  */
 233 u8 cxgbe_filter_slots(struct adapter *adap, u8 family)
 234 {
 235         if (family == FILTER_TYPE_IPV6) {
 236                 if (CHELSIO_CHIP_VERSION(adap->params.chip) < CHELSIO_T6)
 237                         return 4;
 238
 239                 return 2;
 240         }
 241
 242         return 1;
 243 }
 244
 245 /**
 246  * Check if entries are already filled.
 247  */
 248 bool cxgbe_is_filter_set(struct tid_info *t, u32 fidx, u8 nentries)
 249 {
 250         bool result = FALSE;
 251         u32 i;
 252
 253         /* Ensure there's enough slots available. */
 254         t4_os_lock(&t->ftid_lock);
 255         for (i = fidx; i < fidx + nentries; i++) {
 256                 if (rte_bitmap_get(t->ftid_bmap, i)) {
 257                         result = TRUE;
 258                         break;
 259                 }
 260         }
 261         t4_os_unlock(&t->ftid_lock);
 262         return result;
 263 }
 264
 265 /**
 266  * Allocate available free entries.
 267  */
 268 int cxgbe_alloc_ftid(struct adapter *adap, u8 nentries)
 269 {
 270         struct tid_info *t = &adap->tids;
 271         int pos;
 272         int size = t->nftids;
 273
 274         t4_os_lock(&t->ftid_lock);
 275         if (nentries > 1)
 276                 pos = cxgbe_bitmap_find_free_region(t->ftid_bmap, size,
 277                                                     nentries);
 278         else
 279                 pos = cxgbe_find_first_zero_bit(t->ftid_bmap, size);
 280         t4_os_unlock(&t->ftid_lock);
 281
 282         return pos < size ? pos : -1;
 283 }
 284
 285 /**
 286  * Construct hash filter ntuple.
 287  */
 288 static u64 hash_filter_ntuple(const struct filter_entry *f)
 289 {
 290         struct adapter *adap = ethdev2adap(f->dev);
 291         struct tp_params *tp = &adap->params.tp;
 292         u64 ntuple = 0;
 293         u16 tcp_proto = IPPROTO_TCP; /* TCP Protocol Number */
 294
 295         if (tp->port_shift >= 0 && f->fs.mask.iport)
 296                 ntuple |= (u64)f->fs.val.iport << tp->port_shift;
 297
 298         if (tp->protocol_shift >= 0) {
 299                 if (!f->fs.val.proto)
 300                         ntuple |= (u64)tcp_proto << tp->protocol_shift;
 301                 else
 302                         ntuple |= (u64)f->fs.val.proto << tp->protocol_shift;
 303         }
 304
 305         if (tp->ethertype_shift >= 0 && f->fs.mask.ethtype)
 306                 ntuple |= (u64)(f->fs.val.ethtype) << tp->ethertype_shift;
 307         if (tp->macmatch_shift >= 0 && f->fs.mask.macidx)
 308                 ntuple |= (u64)(f->fs.val.macidx) << tp->macmatch_shift;
 309         if (tp->vlan_shift >= 0 && f->fs.mask.ivlan)
 310                 ntuple |= (u64)(F_FT_VLAN_VLD | f->fs.val.ivlan) <<
 311                           tp->vlan_shift;
 312         if (tp->vnic_shift >= 0) {
 313                 if ((adap->params.tp.ingress_config & F_VNIC) &&
 314                     f->fs.mask.pfvf_vld)
 315                         ntuple |= (u64)(f->fs.val.pfvf_vld << 16 |
 316                                         f->fs.val.pf << 13 | f->fs.val.vf) <<
 317                                         tp->vnic_shift;
 318                 else if (!(adap->params.tp.ingress_config & F_VNIC) &&
 319                          f->fs.mask.ovlan_vld)
 320                         ntuple |= (u64)(f->fs.val.ovlan_vld << 16 |
 321                                         f->fs.val.ovlan) << tp->vnic_shift;
 322         }
 323         if (tp->tos_shift >= 0 && f->fs.mask.tos)
 324                 ntuple |= (u64)f->fs.val.tos << tp->tos_shift;
 325
 326         return ntuple;
 327 }
 328
 329 /**
 330  * Build a CPL_ABORT_REQ message as payload of a ULP_TX_PKT command.
 331  */
 332 static void mk_abort_req_ulp(struct cpl_abort_req *abort_req,
 333                              unsigned int tid)
 334 {
 335         struct ulp_txpkt *txpkt = (struct ulp_txpkt *)abort_req;
 336         struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1);
 337
 338         txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
 339                                       V_ULP_TXPKT_DEST(0));
 340         txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*abort_req), 16));
 341         sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
 342         sc->len = cpu_to_be32(sizeof(*abort_req) -
 343                               sizeof(struct work_request_hdr));
 344         OPCODE_TID(abort_req) = cpu_to_be32(MK_OPCODE_TID(CPL_ABORT_REQ, tid));
 345         abort_req->rsvd0 = cpu_to_be32(0);
 346         abort_req->rsvd1 = 0;
 347         abort_req->cmd = CPL_ABORT_NO_RST;
 348         sc = (struct ulptx_idata *)(abort_req + 1);
 349         sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
 350         sc->len = cpu_to_be32(0);
 351 }
 352
 353 /**
 354  * Build a CPL_ABORT_RPL message as payload of a ULP_TX_PKT command.
 355  */
 356 static void mk_abort_rpl_ulp(struct cpl_abort_rpl *abort_rpl,
 357                              unsigned int tid)
 358 {
 359         struct ulp_txpkt *txpkt = (struct ulp_txpkt *)abort_rpl;
 360         struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1);
 361
 362         txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
 363                                       V_ULP_TXPKT_DEST(0));
 364         txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*abort_rpl), 16));
 365         sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
 366         sc->len = cpu_to_be32(sizeof(*abort_rpl) -
 367                               sizeof(struct work_request_hdr));
 368         OPCODE_TID(abort_rpl) = cpu_to_be32(MK_OPCODE_TID(CPL_ABORT_RPL, tid));
 369         abort_rpl->rsvd0 = cpu_to_be32(0);
 370         abort_rpl->rsvd1 = 0;
 371         abort_rpl->cmd = CPL_ABORT_NO_RST;
 372         sc = (struct ulptx_idata *)(abort_rpl + 1);
 373         sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
 374         sc->len = cpu_to_be32(0);
 375 }
 376
 377 /**
 378  * Delete the specified hash filter.
 379  */
 380 static int cxgbe_del_hash_filter(struct rte_eth_dev *dev,
 381                                  unsigned int filter_id,
 382                                  struct filter_ctx *ctx)
 383 {
 384         struct adapter *adapter = ethdev2adap(dev);
 385         struct tid_info *t = &adapter->tids;
 386         struct filter_entry *f;
 387         struct sge_ctrl_txq *ctrlq;
 388         unsigned int port_id = ethdev2pinfo(dev)->port_id;
 389         int ret;
 390
 391         if (filter_id > adapter->tids.ntids)
 392                 return -E2BIG;
 393
 394         f = lookup_tid(t, filter_id);
 395         if (!f) {
 396                 dev_err(adapter, "%s: no filter entry for filter_id = %d\n",
 397                         __func__, filter_id);
 398                 return -EINVAL;
 399         }
 400
 401         ret = writable_filter(f);
 402         if (ret)
 403                 return ret;
 404
 405         if (f->valid) {
 406                 unsigned int wrlen;
 407                 struct rte_mbuf *mbuf;
 408                 struct work_request_hdr *wr;
 409                 struct ulptx_idata *aligner;
 410                 struct cpl_set_tcb_field *req;
 411                 struct cpl_abort_req *abort_req;
 412                 struct cpl_abort_rpl *abort_rpl;
 413
 414                 f->ctx = ctx;
 415                 f->pending = 1;
 416
 417                 wrlen = cxgbe_roundup(sizeof(*wr) +
 418                                       (sizeof(*req) + sizeof(*aligner)) +
 419                                       sizeof(*abort_req) + sizeof(*abort_rpl),
 420                                       16);
 421
 422                 ctrlq = &adapter->sge.ctrlq[port_id];
 423                 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
 424                 if (!mbuf) {
 425                         dev_err(adapter, "%s: could not allocate skb ..\n",
 426                                 __func__);
 427                         goto out_err;
 428                 }
 429
 430                 mbuf->data_len = wrlen;
 431                 mbuf->pkt_len = mbuf->data_len;
 432
 433                 req = rte_pktmbuf_mtod(mbuf, struct cpl_set_tcb_field *);
 434                 INIT_ULPTX_WR(req, wrlen, 0, 0);
 435                 wr = (struct work_request_hdr *)req;
 436                 wr++;
 437                 req = (struct cpl_set_tcb_field *)wr;
 438                 mk_set_tcb_field_ulp(f, req, W_TCB_RSS_INFO,
 439                                 V_TCB_RSS_INFO(M_TCB_RSS_INFO),
 440                                 V_TCB_RSS_INFO(adapter->sge.fw_evtq.abs_id),
 441                                 0, 1);
 442                 aligner = (struct ulptx_idata *)(req + 1);
 443                 abort_req = (struct cpl_abort_req *)(aligner + 1);
 444                 mk_abort_req_ulp(abort_req, f->tid);
 445                 abort_rpl = (struct cpl_abort_rpl *)(abort_req + 1);
 446                 mk_abort_rpl_ulp(abort_rpl, f->tid);
 447                 t4_mgmt_tx(ctrlq, mbuf);
 448         }
 449         return 0;
 450
 451 out_err:
 452         return -ENOMEM;
 453 }
 454
 455 /**
 456  * Build a ACT_OPEN_REQ6 message for setting IPv6 hash filter.
 457  */
 458 static void mk_act_open_req6(struct filter_entry *f, struct rte_mbuf *mbuf,
 459                              unsigned int qid_filterid, struct adapter *adap)
 460 {
 461         struct cpl_t6_act_open_req6 *req = NULL;
 462         u64 local_lo, local_hi, peer_lo, peer_hi;
 463         u32 *lip = (u32 *)f->fs.val.lip;
 464         u32 *fip = (u32 *)f->fs.val.fip;
 465
 466         switch (CHELSIO_CHIP_VERSION(adap->params.chip)) {
 467         case CHELSIO_T6:
 468                 req = rte_pktmbuf_mtod(mbuf, struct cpl_t6_act_open_req6 *);
 469
 470                 INIT_TP_WR(req, 0);
 471                 break;
 472         default:
 473                 dev_err(adap, "%s: unsupported chip type!\n", __func__);
 474                 return;
 475         }
 476
 477         local_hi = ((u64)lip[1]) << 32 | lip[0];
 478         local_lo = ((u64)lip[3]) << 32 | lip[2];
 479         peer_hi = ((u64)fip[1]) << 32 | fip[0];
 480         peer_lo = ((u64)fip[3]) << 32 | fip[2];
 481
 482         OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_ACT_OPEN_REQ6,
 483                                                     qid_filterid));
 484         req->local_port = cpu_to_be16(f->fs.val.lport);
 485         req->peer_port = cpu_to_be16(f->fs.val.fport);
 486         req->local_ip_hi = local_hi;
 487         req->local_ip_lo = local_lo;
 488         req->peer_ip_hi = peer_hi;
 489         req->peer_ip_lo = peer_lo;
 490         req->opt0 = cpu_to_be64(V_NAGLE(f->fs.newvlan == VLAN_REMOVE ||
 491                                         f->fs.newvlan == VLAN_REWRITE) |
 492                                 V_DELACK(f->fs.hitcnts) |
 493                                 V_L2T_IDX(f->l2t ? f->l2t->idx : 0) |
 494                                 V_SMAC_SEL((cxgbe_port_viid(f->dev) & 0x7F)
 495                                            << 1) |
 496                                 V_TX_CHAN(f->fs.eport) |
 497                                 V_ULP_MODE(ULP_MODE_NONE) |
 498                                 F_TCAM_BYPASS | F_NON_OFFLOAD);
 499         req->params = cpu_to_be64(V_FILTER_TUPLE(hash_filter_ntuple(f)));
 500         req->opt2 = cpu_to_be32(F_RSS_QUEUE_VALID |
 501                             V_RSS_QUEUE(f->fs.iq) |
 502                             F_T5_OPT_2_VALID |
 503                             F_RX_CHANNEL |
 504                             V_SACK_EN(f->fs.swapmac) |
 505                             V_CONG_CNTRL((f->fs.action == FILTER_DROP) |
 506                                          (f->fs.dirsteer << 1)) |
 507                             V_CCTRL_ECN(f->fs.action == FILTER_SWITCH));
 508 }
 509
 510 /**
 511  * Build a ACT_OPEN_REQ message for setting IPv4 hash filter.
 512  */
 513 static void mk_act_open_req(struct filter_entry *f, struct rte_mbuf *mbuf,
 514                             unsigned int qid_filterid, struct adapter *adap)
 515 {
 516         struct cpl_t6_act_open_req *req = NULL;
 517
 518         switch (CHELSIO_CHIP_VERSION(adap->params.chip)) {
 519         case CHELSIO_T6:
 520                 req = rte_pktmbuf_mtod(mbuf, struct cpl_t6_act_open_req *);
 521
 522                 INIT_TP_WR(req, 0);
 523                 break;
 524         default:
 525                 dev_err(adap, "%s: unsupported chip type!\n", __func__);
 526                 return;
 527         }
 528
 529         OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_ACT_OPEN_REQ,
 530                                                     qid_filterid));
 531         req->local_port = cpu_to_be16(f->fs.val.lport);
 532         req->peer_port = cpu_to_be16(f->fs.val.fport);
 533         req->local_ip = f->fs.val.lip[0] | f->fs.val.lip[1] << 8 |
 534                         f->fs.val.lip[2] << 16 | f->fs.val.lip[3] << 24;
 535         req->peer_ip = f->fs.val.fip[0] | f->fs.val.fip[1] << 8 |
 536                         f->fs.val.fip[2] << 16 | f->fs.val.fip[3] << 24;
 537         req->opt0 = cpu_to_be64(V_NAGLE(f->fs.newvlan == VLAN_REMOVE ||
 538                                         f->fs.newvlan == VLAN_REWRITE) |
 539                                 V_DELACK(f->fs.hitcnts) |
 540                                 V_L2T_IDX(f->l2t ? f->l2t->idx : 0) |
 541                                 V_SMAC_SEL((cxgbe_port_viid(f->dev) & 0x7F)
 542                                            << 1) |
 543                                 V_TX_CHAN(f->fs.eport) |
 544                                 V_ULP_MODE(ULP_MODE_NONE) |
 545                                 F_TCAM_BYPASS | F_NON_OFFLOAD);
 546         req->params = cpu_to_be64(V_FILTER_TUPLE(hash_filter_ntuple(f)));
 547         req->opt2 = cpu_to_be32(F_RSS_QUEUE_VALID |
 548                             V_RSS_QUEUE(f->fs.iq) |
 549                             F_T5_OPT_2_VALID |
 550                             F_RX_CHANNEL |
 551                             V_SACK_EN(f->fs.swapmac) |
 552                             V_CONG_CNTRL((f->fs.action == FILTER_DROP) |
 553                                          (f->fs.dirsteer << 1)) |
 554                             V_CCTRL_ECN(f->fs.action == FILTER_SWITCH));
 555 }
 556
 557 /**
 558  * Set the specified hash filter.
 559  */
 560 static int cxgbe_set_hash_filter(struct rte_eth_dev *dev,
 561                                  struct ch_filter_specification *fs,
 562                                  struct filter_ctx *ctx)
 563 {
 564         struct port_info *pi = ethdev2pinfo(dev);
 565         struct adapter *adapter = pi->adapter;
 566         struct tid_info *t = &adapter->tids;
 567         struct filter_entry *f;
 568         struct rte_mbuf *mbuf;
 569         struct sge_ctrl_txq *ctrlq;
 570         unsigned int iq;
 571         int atid, size;
 572         int ret = 0;
 573
 574         ret = cxgbe_validate_filter(adapter, fs);
 575         if (ret)
 576                 return ret;
 577
 578         iq = get_filter_steerq(dev, fs);
 579
 580         ctrlq = &adapter->sge.ctrlq[pi->port_id];
 581
 582         f = t4_os_alloc(sizeof(*f));
 583         if (!f)
 584                 goto out_err;
 585
 586         f->fs = *fs;
 587         f->ctx = ctx;
 588         f->dev = dev;
 589         f->fs.iq = iq;
 590
 591         /*
 592          * If the new filter requires loopback Destination MAC and/or VLAN
 593          * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
 594          * the filter.
 595          */
 596         if (f->fs.newvlan == VLAN_INSERT ||
 597             f->fs.newvlan == VLAN_REWRITE) {
 598                 /* allocate L2T entry for new filter */
 599                 f->l2t = cxgbe_l2t_alloc_switching(dev, f->fs.vlan,
 600                                                    f->fs.eport, f->fs.dmac);
 601                 if (!f->l2t) {
 602                         ret = -ENOMEM;
 603                         goto out_err;
 604                 }
 605         }
 606
 607         atid = cxgbe_alloc_atid(t, f);
 608         if (atid < 0)
 609                 goto out_err;
 610
 611         if (f->fs.type == FILTER_TYPE_IPV6) {
 612                 /* IPv6 hash filter */
 613                 f->clipt = cxgbe_clip_alloc(f->dev, (u32 *)&f->fs.val.lip);
 614                 if (!f->clipt)
 615                         goto free_atid;
 616
 617                 size = sizeof(struct cpl_t6_act_open_req6);
 618                 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
 619                 if (!mbuf) {
 620                         ret = -ENOMEM;
 621                         goto free_clip;
 622                 }
 623
 624                 mbuf->data_len = size;
 625                 mbuf->pkt_len = mbuf->data_len;
 626
 627                 mk_act_open_req6(f, mbuf,
 628                                  ((adapter->sge.fw_evtq.abs_id << 14) | atid),
 629                                  adapter);
 630         } else {
 631                 /* IPv4 hash filter */
 632                 size = sizeof(struct cpl_t6_act_open_req);
 633                 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
 634                 if (!mbuf) {
 635                         ret = -ENOMEM;
 636                         goto free_atid;
 637                 }
 638
 639                 mbuf->data_len = size;
 640                 mbuf->pkt_len = mbuf->data_len;
 641
 642                 mk_act_open_req(f, mbuf,
 643                                 ((adapter->sge.fw_evtq.abs_id << 14) | atid),
 644                                 adapter);
 645         }
 646
 647         f->pending = 1;
 648         t4_mgmt_tx(ctrlq, mbuf);
 649         return 0;
 650
 651 free_clip:
 652         cxgbe_clip_release(f->dev, f->clipt);
 653 free_atid:
 654         cxgbe_free_atid(t, atid);
 655
 656 out_err:
 657         t4_os_free(f);
 658         return ret;
 659 }
 660
 661 /**
 662  * Clear a filter and release any of its resources that we own.  This also
 663  * clears the filter's "pending" status.
 664  */
 665 static void clear_filter(struct filter_entry *f)
 666 {
 667         if (f->clipt)
 668                 cxgbe_clip_release(f->dev, f->clipt);
 669
 670         /*
 671          * The zeroing of the filter rule below clears the filter valid,
 672          * pending, locked flags etc. so it's all we need for
 673          * this operation.
 674          */
 675         memset(f, 0, sizeof(*f));
 676 }
 677
 678 /**
 679  * t4_mk_filtdelwr - create a delete filter WR
 680  * @adap: adapter context
 681  * @ftid: the filter ID
 682  * @wr: the filter work request to populate
 683  * @qid: ingress queue to receive the delete notification
 684  *
 685  * Creates a filter work request to delete the supplied filter.  If @qid is
 686  * negative the delete notification is suppressed.
 687  */
 688 static void t4_mk_filtdelwr(struct adapter *adap, unsigned int ftid,
 689                             struct fw_filter2_wr *wr, int qid)
 690 {
 691         memset(wr, 0, sizeof(*wr));
 692         if (adap->params.filter2_wr_support)
 693                 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER2_WR));
 694         else
 695                 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
 696         wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16));
 697         wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) |
 698                                     V_FW_FILTER_WR_NOREPLY(qid < 0));
 699         wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER);
 700         if (qid >= 0)
 701                 wr->rx_chan_rx_rpl_iq =
 702                                 cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid));
 703 }
 704
 705 /**
 706  * Create FW work request to delete the filter at a specified index
 707  */
 708 static int del_filter_wr(struct rte_eth_dev *dev, unsigned int fidx)
 709 {
 710         struct adapter *adapter = ethdev2adap(dev);
 711         struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
 712         struct rte_mbuf *mbuf;
 713         struct fw_filter2_wr *fwr;
 714         struct sge_ctrl_txq *ctrlq;
 715         unsigned int port_id = ethdev2pinfo(dev)->port_id;
 716
 717         ctrlq = &adapter->sge.ctrlq[port_id];
 718         mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
 719         if (!mbuf)
 720                 return -ENOMEM;
 721
 722         mbuf->data_len = sizeof(*fwr);
 723         mbuf->pkt_len = mbuf->data_len;
 724
 725         fwr = rte_pktmbuf_mtod(mbuf, struct fw_filter2_wr *);
 726         t4_mk_filtdelwr(adapter, f->tid, fwr, adapter->sge.fw_evtq.abs_id);
 727
 728         /*
 729          * Mark the filter as "pending" and ship off the Filter Work Request.
 730          * When we get the Work Request Reply we'll clear the pending status.
 731          */
 732         f->pending = 1;
 733         t4_mgmt_tx(ctrlq, mbuf);
 734         return 0;
 735 }
 736
 737 static int set_filter_wr(struct rte_eth_dev *dev, unsigned int fidx)
 738 {
 739         struct adapter *adapter = ethdev2adap(dev);
 740         struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
 741         struct rte_mbuf *mbuf;
 742         struct fw_filter2_wr *fwr;
 743         struct sge_ctrl_txq *ctrlq;
 744         unsigned int port_id = ethdev2pinfo(dev)->port_id;
 745         int ret;
 746
 747         /*
 748          * If the new filter requires loopback Destination MAC and/or VLAN
 749          * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
 750          * the filter.
 751          */
 752         if (f->fs.newvlan) {
 753                 /* allocate L2T entry for new filter */
 754                 f->l2t = cxgbe_l2t_alloc_switching(f->dev, f->fs.vlan,
 755                                                    f->fs.eport, f->fs.dmac);
 756                 if (!f->l2t)
 757                         return -ENOMEM;
 758         }
 759
 760         ctrlq = &adapter->sge.ctrlq[port_id];
 761         mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
 762         if (!mbuf) {
 763                 ret = -ENOMEM;
 764                 goto out;
 765         }
 766
 767         mbuf->data_len = sizeof(*fwr);
 768         mbuf->pkt_len = mbuf->data_len;
 769
 770         fwr = rte_pktmbuf_mtod(mbuf, struct fw_filter2_wr *);
 771         memset(fwr, 0, sizeof(*fwr));
 772
 773         /*
 774          * Construct the work request to set the filter.
 775          */
 776         if (adapter->params.filter2_wr_support)
 777                 fwr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER2_WR));
 778         else
 779                 fwr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
 780         fwr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*fwr) / 16));
 781         fwr->tid_to_iq =
 782                 cpu_to_be32(V_FW_FILTER_WR_TID(f->tid) |
 783                             V_FW_FILTER_WR_RQTYPE(f->fs.type) |
 784                             V_FW_FILTER_WR_NOREPLY(0) |
 785                             V_FW_FILTER_WR_IQ(f->fs.iq));
 786         fwr->del_filter_to_l2tix =
 787                 cpu_to_be32(V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
 788                             V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
 789                             V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
 790                             V_FW_FILTER_WR_INSVLAN
 791                                 (f->fs.newvlan == VLAN_INSERT ||
 792                                  f->fs.newvlan == VLAN_REWRITE) |
 793                             V_FW_FILTER_WR_RMVLAN
 794                                 (f->fs.newvlan == VLAN_REMOVE ||
 795                                  f->fs.newvlan == VLAN_REWRITE) |
 796                             V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
 797                             V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
 798                             V_FW_FILTER_WR_PRIO(f->fs.prio) |
 799                             V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
 800         fwr->ethtype = cpu_to_be16(f->fs.val.ethtype);
 801         fwr->ethtypem = cpu_to_be16(f->fs.mask.ethtype);
 802         fwr->frag_to_ovlan_vldm =
 803                 (V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.ivlan_vld) |
 804                  V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.ivlan_vld) |
 805                  V_FW_FILTER_WR_OVLAN_VLD(f->fs.val.ovlan_vld) |
 806                  V_FW_FILTER_WR_OVLAN_VLDM(f->fs.mask.ovlan_vld));
 807         fwr->smac_sel = 0;
 808         fwr->rx_chan_rx_rpl_iq =
 809                 cpu_to_be16(V_FW_FILTER_WR_RX_CHAN(0) |
 810                             V_FW_FILTER_WR_RX_RPL_IQ(adapter->sge.fw_evtq.abs_id
 811                                                      ));
 812         fwr->maci_to_matchtypem =
 813                 cpu_to_be32(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
 814                             V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
 815                             V_FW_FILTER_WR_PORT(f->fs.val.iport) |
 816                             V_FW_FILTER_WR_PORTM(f->fs.mask.iport));
 817         fwr->ptcl = f->fs.val.proto;
 818         fwr->ptclm = f->fs.mask.proto;
 819         fwr->ttyp = f->fs.val.tos;
 820         fwr->ttypm = f->fs.mask.tos;
 821         fwr->ivlan = cpu_to_be16(f->fs.val.ivlan);
 822         fwr->ivlanm = cpu_to_be16(f->fs.mask.ivlan);
 823         fwr->ovlan = cpu_to_be16(f->fs.val.ovlan);
 824         fwr->ovlanm = cpu_to_be16(f->fs.mask.ovlan);
 825         rte_memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
 826         rte_memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
 827         rte_memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
 828         rte_memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
 829         fwr->lp = cpu_to_be16(f->fs.val.lport);
 830         fwr->lpm = cpu_to_be16(f->fs.mask.lport);
 831         fwr->fp = cpu_to_be16(f->fs.val.fport);
 832         fwr->fpm = cpu_to_be16(f->fs.mask.fport);
 833
 834         if (adapter->params.filter2_wr_support) {
 835                 fwr->filter_type_swapmac =
 836                          V_FW_FILTER2_WR_SWAPMAC(f->fs.swapmac);
 837                 fwr->natmode_to_ulp_type =
 838                         V_FW_FILTER2_WR_ULP_TYPE(f->fs.nat_mode ?
 839                                                  ULP_MODE_TCPDDP :
 840                                                  ULP_MODE_NONE) |
 841                         V_FW_FILTER2_WR_NATMODE(f->fs.nat_mode);
 842                 memcpy(fwr->newlip, f->fs.nat_lip, sizeof(fwr->newlip));
 843                 memcpy(fwr->newfip, f->fs.nat_fip, sizeof(fwr->newfip));
 844                 fwr->newlport = cpu_to_be16(f->fs.nat_lport);
 845                 fwr->newfport = cpu_to_be16(f->fs.nat_fport);
 846         }
 847
 848         /*
 849          * Mark the filter as "pending" and ship off the Filter Work Request.
 850          * When we get the Work Request Reply we'll clear the pending status.
 851          */
 852         f->pending = 1;
 853         t4_mgmt_tx(ctrlq, mbuf);
 854         return 0;
 855
 856 out:
 857         return ret;
 858 }
 859
 860 /**
 861  * Set the corresponding entries in the bitmap.
 862  */
 863 static int cxgbe_set_ftid(struct tid_info *t, u32 fidx, u8 nentries)
 864 {
 865         u32 i;
 866
 867         t4_os_lock(&t->ftid_lock);
 868         if (rte_bitmap_get(t->ftid_bmap, fidx)) {
 869                 t4_os_unlock(&t->ftid_lock);
 870                 return -EBUSY;
 871         }
 872
 873         for (i = fidx; i < fidx + nentries; i++)
 874                 rte_bitmap_set(t->ftid_bmap, i);
 875         t4_os_unlock(&t->ftid_lock);
 876         return 0;
 877 }
 878
 879 /**
 880  * Clear the corresponding entries in the bitmap.
 881  */
 882 static void cxgbe_clear_ftid(struct tid_info *t, u32 fidx, u8 nentries)
 883 {
 884         u32 i;
 885
 886         t4_os_lock(&t->ftid_lock);
 887         for (i = fidx; i < fidx + nentries; i++)
 888                 rte_bitmap_clear(t->ftid_bmap, i);
 889         t4_os_unlock(&t->ftid_lock);
 890 }
 891
 892 /**
 893  * Check a delete filter request for validity and send it to the hardware.
 894  * Return 0 on success, an error number otherwise.  We attach any provided
 895  * filter operation context to the internal filter specification in order to
 896  * facilitate signaling completion of the operation.
 897  */
 898 int cxgbe_del_filter(struct rte_eth_dev *dev, unsigned int filter_id,
 899                      struct ch_filter_specification *fs,
 900                      struct filter_ctx *ctx)
 901 {
 902         struct port_info *pi = dev->data->dev_private;
 903         struct adapter *adapter = pi->adapter;
 904         struct filter_entry *f;
 905         unsigned int chip_ver;
 906         u8 nentries;
 907         int ret;
 908
 909         if (is_hashfilter(adapter) && fs->cap)
 910                 return cxgbe_del_hash_filter(dev, filter_id, ctx);
 911
 912         if (filter_id >= adapter->tids.nftids)
 913                 return -ERANGE;
 914
 915         chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
 916
 917         /*
 918          * Ensure IPv6 filter id is aligned on the 2 slot boundary for T6,
 919          * and 4 slot boundary for cards below T6.
 920          */
 921         if (fs->type == FILTER_TYPE_IPV6) {
 922                 if (chip_ver < CHELSIO_T6)
 923                         filter_id &= ~(0x3);
 924                 else
 925                         filter_id &= ~(0x1);
 926         }
 927
 928         nentries = cxgbe_filter_slots(adapter, fs->type);
 929         ret = cxgbe_is_filter_set(&adapter->tids, filter_id, nentries);
 930         if (!ret) {
 931                 dev_warn(adap, "%s: could not find filter entry: %u\n",
 932                          __func__, filter_id);
 933                 return -EINVAL;
 934         }
 935
 936         f = &adapter->tids.ftid_tab[filter_id];
 937         ret = writable_filter(f);
 938         if (ret)
 939                 return ret;
 940
 941         if (f->valid) {
 942                 f->ctx = ctx;
 943                 cxgbe_clear_ftid(&adapter->tids,
 944                                  f->tid - adapter->tids.ftid_base,
 945                                  nentries);
 946                 return del_filter_wr(dev, filter_id);
 947         }
 948
 949         /*
 950          * If the caller has passed in a Completion Context then we need to
 951          * mark it as a successful completion so they don't stall waiting
 952          * for it.
 953          */
 954         if (ctx) {
 955                 ctx->result = 0;
 956                 t4_complete(&ctx->completion);
 957         }
 958
 959         return 0;
 960 }
 961
 962 /**
 963  * Check a Chelsio Filter Request for validity, convert it into our internal
 964  * format and send it to the hardware.  Return 0 on success, an error number
 965  * otherwise.  We attach any provided filter operation context to the internal
 966  * filter specification in order to facilitate signaling completion of the
 967  * operation.
 968  */
 969 int cxgbe_set_filter(struct rte_eth_dev *dev, unsigned int filter_id,
 970                      struct ch_filter_specification *fs,
 971                      struct filter_ctx *ctx)
 972 {
 973         struct port_info *pi = ethdev2pinfo(dev);
 974         struct adapter *adapter = pi->adapter;
 975         u8 nentries, bitoff[16] = {0};
 976         struct filter_entry *f;
 977         unsigned int chip_ver;
 978         unsigned int fidx, iq;
 979         u32 iconf;
 980         int ret;
 981
 982         if (is_hashfilter(adapter) && fs->cap)
 983                 return cxgbe_set_hash_filter(dev, fs, ctx);
 984
 985         if (filter_id >= adapter->tids.nftids)
 986                 return -ERANGE;
 987
 988         chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
 989
 990         ret = cxgbe_validate_filter(adapter, fs);
 991         if (ret)
 992                 return ret;
 993
 994         /*
 995          * IPv6 filters occupy four slots and must be aligned on four-slot
 996          * boundaries for T5. On T6, IPv6 filters occupy two-slots and
 997          * must be aligned on two-slot boundaries.
 998          *
 999          * IPv4 filters only occupy a single slot and have no alignment
1000          * requirements.
1001          */
1002         fidx = filter_id;
1003         if (fs->type == FILTER_TYPE_IPV6) {
1004                 if (chip_ver < CHELSIO_T6)
1005                         fidx &= ~(0x3);
1006                 else
1007                         fidx &= ~(0x1);
1008         }
1009
1010         if (fidx != filter_id)
1011                 return -EINVAL;
1012
1013         nentries = cxgbe_filter_slots(adapter, fs->type);
1014         ret = cxgbe_is_filter_set(&adapter->tids, filter_id, nentries);
1015         if (ret)
1016                 return -EBUSY;
1017
1018         iq = get_filter_steerq(dev, fs);
1019
1020         /*
1021          * Check to make sure that provided filter index is not
1022          * already in use by someone else
1023          */
1024         f = &adapter->tids.ftid_tab[filter_id];
1025         if (f->valid)
1026                 return -EBUSY;
1027
1028         fidx = adapter->tids.ftid_base + filter_id;
1029         ret = cxgbe_set_ftid(&adapter->tids, filter_id, nentries);
1030         if (ret)
1031                 return ret;
1032
1033         /*
1034          * Check to make sure the filter requested is writable ...
1035          */
1036         ret = writable_filter(f);
1037         if (ret) {
1038                 /* Clear the bits we have set above */
1039                 cxgbe_clear_ftid(&adapter->tids, filter_id, nentries);
1040                 return ret;
1041         }
1042
1043         /*
1044          * Allocate a clip table entry only if we have non-zero IPv6 address
1045          */
1046         if (chip_ver > CHELSIO_T5 && fs->type &&
1047             memcmp(fs->val.lip, bitoff, sizeof(bitoff))) {
1048                 f->clipt = cxgbe_clip_alloc(dev, (u32 *)&fs->val.lip);
1049                 if (!f->clipt)
1050                         goto free_tid;
1051         }
1052
1053         /*
1054          * Convert the filter specification into our internal format.
1055          * We copy the PF/VF specification into the Outer VLAN field
1056          * here so the rest of the code -- including the interface to
1057          * the firmware -- doesn't have to constantly do these checks.
1058          */
1059         f->fs = *fs;
1060         f->fs.iq = iq;
1061         f->dev = dev;
1062
1063         iconf = adapter->params.tp.ingress_config;
1064
1065         /* Either PFVF or OVLAN can be active, but not both
1066          * So, if PFVF is enabled, then overwrite the OVLAN
1067          * fields with PFVF fields before writing the spec
1068          * to hardware.
1069          */
1070         if (iconf & F_VNIC) {
1071                 f->fs.val.ovlan = fs->val.pf << 13 | fs->val.vf;
1072                 f->fs.mask.ovlan = fs->mask.pf << 13 | fs->mask.vf;
1073                 f->fs.val.ovlan_vld = fs->val.pfvf_vld;
1074                 f->fs.mask.ovlan_vld = fs->mask.pfvf_vld;
1075         }
1076
1077         /*
1078          * Attempt to set the filter.  If we don't succeed, we clear
1079          * it and return the failure.
1080          */
1081         f->ctx = ctx;
1082         f->tid = fidx; /* Save the actual tid */
1083         ret = set_filter_wr(dev, filter_id);
1084         if (ret)
1085                 goto free_tid;
1086
1087         return ret;
1088
1089 free_tid:
1090         cxgbe_clear_ftid(&adapter->tids, filter_id, nentries);
1091         clear_filter(f);
1092         return ret;
1093 }
1094
1095 /**
1096  * Handle a Hash filter write reply.
1097  */
1098 void cxgbe_hash_filter_rpl(struct adapter *adap,
1099                            const struct cpl_act_open_rpl *rpl)
1100 {
1101         struct tid_info *t = &adap->tids;
1102         struct filter_entry *f;
1103         struct filter_ctx *ctx = NULL;
1104         unsigned int tid = GET_TID(rpl);
1105         unsigned int ftid = G_TID_TID(G_AOPEN_ATID
1106                                       (be32_to_cpu(rpl->atid_status)));
1107         unsigned int status  = G_AOPEN_STATUS(be32_to_cpu(rpl->atid_status));
1108
1109         f = lookup_atid(t, ftid);
1110         if (!f) {
1111                 dev_warn(adap, "%s: could not find filter entry: %d\n",
1112                          __func__, ftid);
1113                 return;
1114         }
1115
1116         ctx = f->ctx;
1117         f->ctx = NULL;
1118
1119         switch (status) {
1120         case CPL_ERR_NONE: {
1121                 f->tid = tid;
1122                 f->pending = 0;  /* asynchronous setup completed */
1123                 f->valid = 1;
1124
1125                 cxgbe_insert_tid(t, f, f->tid, 0);
1126                 cxgbe_free_atid(t, ftid);
1127                 if (ctx) {
1128                         ctx->tid = f->tid;
1129                         ctx->result = 0;
1130                 }
1131                 if (f->fs.hitcnts)
1132                         set_tcb_field(adap, tid,
1133                                       W_TCB_TIMESTAMP,
1134                                       V_TCB_TIMESTAMP(M_TCB_TIMESTAMP) |
1135                                       V_TCB_T_RTT_TS_RECENT_AGE
1136                                               (M_TCB_T_RTT_TS_RECENT_AGE),
1137                                       V_TCB_TIMESTAMP(0ULL) |
1138                                       V_TCB_T_RTT_TS_RECENT_AGE(0ULL),
1139                                       1);
1140                 if (f->fs.newvlan == VLAN_INSERT ||
1141                     f->fs.newvlan == VLAN_REWRITE)
1142                         set_tcb_tflag(adap, tid, S_TF_CCTRL_RFR, 1, 1);
1143                 break;
1144         }
1145         default:
1146                 dev_warn(adap, "%s: filter creation failed with status = %u\n",
1147                          __func__, status);
1148
1149                 if (ctx) {
1150                         if (status == CPL_ERR_TCAM_FULL)
1151                                 ctx->result = -EAGAIN;
1152                         else
1153                                 ctx->result = -EINVAL;
1154                 }
1155
1156                 cxgbe_free_atid(t, ftid);
1157                 t4_os_free(f);
1158         }
1159
1160         if (ctx)
1161                 t4_complete(&ctx->completion);
1162 }
1163
1164 /**
1165  * Handle a LE-TCAM filter write/deletion reply.
1166  */
1167 void cxgbe_filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
1168 {
1169         struct filter_entry *f = NULL;
1170         unsigned int tid = GET_TID(rpl);
1171         int idx, max_fidx = adap->tids.nftids;
1172
1173         /* Get the corresponding filter entry for this tid */
1174         if (adap->tids.ftid_tab) {
1175                 /* Check this in normal filter region */
1176                 idx = tid - adap->tids.ftid_base;
1177                 if (idx >= max_fidx)
1178                         return;
1179
1180                 f = &adap->tids.ftid_tab[idx];
1181                 if (f->tid != tid)
1182                         return;
1183         }
1184
1185         /* We found the filter entry for this tid */
1186         if (f) {
1187                 unsigned int ret = G_COOKIE(rpl->cookie);
1188                 struct filter_ctx *ctx;
1189
1190                 /*
1191                  * Pull off any filter operation context attached to the
1192                  * filter.
1193                  */
1194                 ctx = f->ctx;
1195                 f->ctx = NULL;
1196
1197                 if (ret == FW_FILTER_WR_FLT_ADDED) {
1198                         f->pending = 0;  /* asynchronous setup completed */
1199                         f->valid = 1;
1200                         if (ctx) {
1201                                 ctx->tid = f->tid;
1202                                 ctx->result = 0;
1203                         }
1204                 } else if (ret == FW_FILTER_WR_FLT_DELETED) {
1205                         /*
1206                          * Clear the filter when we get confirmation from the
1207                          * hardware that the filter has been deleted.
1208                          */
1209                         clear_filter(f);
1210                         if (ctx)
1211                                 ctx->result = 0;
1212                 } else {
1213                         /*
1214                          * Something went wrong.  Issue a warning about the
1215                          * problem and clear everything out.
1216                          */
1217                         dev_warn(adap, "filter %u setup failed with error %u\n",
1218                                  idx, ret);
1219                         clear_filter(f);
1220                         if (ctx)
1221                                 ctx->result = -EINVAL;
1222                 }
1223
1224                 if (ctx)
1225                         t4_complete(&ctx->completion);
1226         }
1227 }
1228
1229 /*
1230  * Retrieve the packet count for the specified filter.
1231  */
1232 int cxgbe_get_filter_count(struct adapter *adapter, unsigned int fidx,
1233                            u64 *c, int hash, bool get_byte)
1234 {
1235         struct filter_entry *f;
1236         unsigned int tcb_base, tcbaddr;
1237         int ret;
1238
1239         tcb_base = t4_read_reg(adapter, A_TP_CMM_TCB_BASE);
1240         if (is_hashfilter(adapter) && hash) {
1241                 if (fidx < adapter->tids.ntids) {
1242                         f = adapter->tids.tid_tab[fidx];
1243                         if (!f)
1244                                 return -EINVAL;
1245
1246                         if (is_t5(adapter->params.chip)) {
1247                                 *c = 0;
1248                                 return 0;
1249                         }
1250                         tcbaddr = tcb_base + (fidx * TCB_SIZE);
1251                         goto get_count;
1252                 } else {
1253                         return -ERANGE;
1254                 }
1255         } else {
1256                 if (fidx >= adapter->tids.nftids)
1257                         return -ERANGE;
1258
1259                 f = &adapter->tids.ftid_tab[fidx];
1260                 if (!f->valid)
1261                         return -EINVAL;
1262
1263                 tcbaddr = tcb_base + f->tid * TCB_SIZE;
1264         }
1265
1266         f = &adapter->tids.ftid_tab[fidx];
1267         if (!f->valid)
1268                 return -EINVAL;
1269
1270 get_count:
1271         if (is_t5(adapter->params.chip) || is_t6(adapter->params.chip)) {
1272                 /*
1273                  * For T5, the Filter Packet Hit Count is maintained as a
1274                  * 32-bit Big Endian value in the TCB field {timestamp}.
1275                  * Similar to the craziness above, instead of the filter hit
1276                  * count showing up at offset 20 ((W_TCB_TIMESTAMP == 5) *
1277                  * sizeof(u32)), it actually shows up at offset 24.  Whacky.
1278                  */
1279                 if (get_byte) {
1280                         unsigned int word_offset = 4;
1281                         __be64 be64_byte_count;
1282
1283                         t4_os_lock(&adapter->win0_lock);
1284                         ret = t4_memory_rw(adapter, MEMWIN_NIC, MEM_EDC0,
1285                                            tcbaddr +
1286                                            (word_offset * sizeof(__be32)),
1287                                            sizeof(be64_byte_count),
1288                                            &be64_byte_count,
1289                                            T4_MEMORY_READ);
1290                         t4_os_unlock(&adapter->win0_lock);
1291                         if (ret < 0)
1292                                 return ret;
1293                         *c = be64_to_cpu(be64_byte_count);
1294                 } else {
1295                         unsigned int word_offset = 6;
1296                         __be32 be32_count;
1297
1298                         t4_os_lock(&adapter->win0_lock);
1299                         ret = t4_memory_rw(adapter, MEMWIN_NIC, MEM_EDC0,
1300                                            tcbaddr +
1301                                            (word_offset * sizeof(__be32)),
1302                                            sizeof(be32_count), &be32_count,
1303                                            T4_MEMORY_READ);
1304                         t4_os_unlock(&adapter->win0_lock);
1305                         if (ret < 0)
1306                                 return ret;
1307                         *c = (u64)be32_to_cpu(be32_count);
1308                 }
1309         }
1310         return 0;
1311 }
1312
1313 /*
1314  * Clear the packet count for the specified filter.
1315  */
1316 int cxgbe_clear_filter_count(struct adapter *adapter, unsigned int fidx,
1317                              int hash, bool clear_byte)
1318 {
1319         u64 tcb_mask = 0, tcb_val = 0;
1320         struct filter_entry *f = NULL;
1321         u16 tcb_word = 0;
1322
1323         if (is_hashfilter(adapter) && hash) {
1324                 if (fidx >= adapter->tids.ntids)
1325                         return -ERANGE;
1326
1327                 /* No hitcounts supported for T5 hashfilters */
1328                 if (is_t5(adapter->params.chip))
1329                         return 0;
1330
1331                 f = adapter->tids.tid_tab[fidx];
1332         } else {
1333                 if (fidx >= adapter->tids.nftids)
1334                         return -ERANGE;
1335
1336                 f = &adapter->tids.ftid_tab[fidx];
1337         }
1338
1339         if (!f || !f->valid)
1340                 return -EINVAL;
1341
1342         tcb_word = W_TCB_TIMESTAMP;
1343         tcb_mask = V_TCB_TIMESTAMP(M_TCB_TIMESTAMP);
1344         tcb_val = V_TCB_TIMESTAMP(0ULL);
1345
1346         set_tcb_field(adapter, f->tid, tcb_word, tcb_mask, tcb_val, 1);
1347
1348         if (clear_byte) {
1349                 tcb_word = W_TCB_T_RTT_TS_RECENT_AGE;
1350                 tcb_mask =
1351                         V_TCB_T_RTT_TS_RECENT_AGE(M_TCB_T_RTT_TS_RECENT_AGE) |
1352                         V_TCB_T_RTSEQ_RECENT(M_TCB_T_RTSEQ_RECENT);
1353                 tcb_val = V_TCB_T_RTT_TS_RECENT_AGE(0ULL) |
1354                           V_TCB_T_RTSEQ_RECENT(0ULL);
1355
1356                 set_tcb_field(adapter, f->tid, tcb_word, tcb_mask, tcb_val, 1);
1357         }
1358
1359         return 0;
1360 }
1361
1362 /**
1363  * Handle a Hash filter delete reply.
1364  */
1365 void cxgbe_hash_del_filter_rpl(struct adapter *adap,
1366                                const struct cpl_abort_rpl_rss *rpl)
1367 {
1368         struct tid_info *t = &adap->tids;
1369         struct filter_entry *f;
1370         struct filter_ctx *ctx = NULL;
1371         unsigned int tid = GET_TID(rpl);
1372
1373         f = lookup_tid(t, tid);
1374         if (!f) {
1375                 dev_warn(adap, "%s: could not find filter entry: %u\n",
1376                          __func__, tid);
1377                 return;
1378         }
1379
1380         ctx = f->ctx;
1381         f->ctx = NULL;
1382
1383         f->valid = 0;
1384
1385         if (f->clipt)
1386                 cxgbe_clip_release(f->dev, f->clipt);
1387
1388         cxgbe_remove_tid(t, 0, tid, 0);
1389         t4_os_free(f);
1390
1391         if (ctx) {
1392                 ctx->result = 0;
1393                 t4_complete(&ctx->completion);
1394         }
1395 }