drivers/net/cxgbe/cxgbe_filter.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Chelsio Communications.
   3  * All rights reserved.
   4  */
   5 #include <rte_net.h>
   6
   7 #include "base/common.h"
   8 #include "base/t4_tcb.h"
   9 #include "base/t4_regs.h"
  10 #include "cxgbe_filter.h"
  11 #include "clip_tbl.h"
  12 #include "l2t.h"
  13
  14 /**
  15  * Initialize Hash Filters
  16  */
  17 int cxgbe_init_hash_filter(struct adapter *adap)
  18 {
  19         unsigned int n_user_filters;
  20         unsigned int user_filter_perc;
  21         int ret;
  22         u32 params[7], val[7];
  23
  24 #define FW_PARAM_DEV(param) \
  25         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
  26         V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
  27
  28 #define FW_PARAM_PFVF(param) \
  29         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
  30         V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) |  \
  31         V_FW_PARAMS_PARAM_Y(0) | \
  32         V_FW_PARAMS_PARAM_Z(0))
  33
  34         params[0] = FW_PARAM_DEV(NTID);
  35         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
  36                               params, val);
  37         if (ret < 0)
  38                 return ret;
  39         adap->tids.ntids = val[0];
  40         adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
  41
  42         user_filter_perc = 100;
  43         n_user_filters = mult_frac(adap->tids.nftids,
  44                                    user_filter_perc,
  45                                    100);
  46
  47         adap->tids.nftids = n_user_filters;
  48         adap->params.hash_filter = 1;
  49         return 0;
  50 }
  51
  52 /**
  53  * Validate if the requested filter specification can be set by checking
  54  * if the requested features have been enabled
  55  */
  56 int cxgbe_validate_filter(struct adapter *adapter,
  57                           struct ch_filter_specification *fs)
  58 {
  59         u32 fconf;
  60
  61         /*
  62          * Check for unconfigured fields being used.
  63          */
  64         fconf = adapter->params.tp.vlan_pri_map;
  65
  66 #define S(_field) \
  67         (fs->val._field || fs->mask._field)
  68 #define U(_mask, _field) \
  69         (!(fconf & (_mask)) && S(_field))
  70
  71         if (U(F_PORT, iport) || U(F_ETHERTYPE, ethtype) ||
  72             U(F_PROTOCOL, proto) || U(F_MACMATCH, macidx) ||
  73             U(F_VLAN, ivlan_vld))
  74                 return -EOPNOTSUPP;
  75
  76 #undef S
  77 #undef U
  78
  79         /*
  80          * If the user is requesting that the filter action loop
  81          * matching packets back out one of our ports, make sure that
  82          * the egress port is in range.
  83          */
  84         if (fs->action == FILTER_SWITCH &&
  85             fs->eport >= adapter->params.nports)
  86                 return -ERANGE;
  87
  88         /*
  89          * Don't allow various trivially obvious bogus out-of-range
  90          * values ...
  91          */
  92         if (fs->val.iport >= adapter->params.nports)
  93                 return -ERANGE;
  94
  95         if (!fs->cap && fs->nat_mode && !adapter->params.filter2_wr_support)
  96                 return -EOPNOTSUPP;
  97
  98         if (!fs->cap && fs->swapmac && !adapter->params.filter2_wr_support)
  99                 return -EOPNOTSUPP;
 100
 101         return 0;
 102 }
 103
 104 /**
 105  * Get the queue to which the traffic must be steered to.
 106  */
 107 static unsigned int get_filter_steerq(struct rte_eth_dev *dev,
 108                                       struct ch_filter_specification *fs)
 109 {
 110         struct port_info *pi = ethdev2pinfo(dev);
 111         struct adapter *adapter = pi->adapter;
 112         unsigned int iq;
 113
 114         /*
 115          * If the user has requested steering matching Ingress Packets
 116          * to a specific Queue Set, we need to make sure it's in range
 117          * for the port and map that into the Absolute Queue ID of the
 118          * Queue Set's Response Queue.
 119          */
 120         if (!fs->dirsteer) {
 121                 iq = 0;
 122         } else {
 123                 /*
 124                  * If the iq id is greater than the number of qsets,
 125                  * then assume it is an absolute qid.
 126                  */
 127                 if (fs->iq < pi->n_rx_qsets)
 128                         iq = adapter->sge.ethrxq[pi->first_qset +
 129                                                  fs->iq].rspq.abs_id;
 130                 else
 131                         iq = fs->iq;
 132         }
 133
 134         return iq;
 135 }
 136
 137 /* Return an error number if the indicated filter isn't writable ... */
 138 static int writable_filter(struct filter_entry *f)
 139 {
 140         if (f->locked)
 141                 return -EPERM;
 142         if (f->pending)
 143                 return -EBUSY;
 144
 145         return 0;
 146 }
 147
 148 /**
 149  * Send CPL_SET_TCB_FIELD message
 150  */
 151 static void set_tcb_field(struct adapter *adapter, unsigned int ftid,
 152                           u16 word, u64 mask, u64 val, int no_reply)
 153 {
 154         struct rte_mbuf *mbuf;
 155         struct cpl_set_tcb_field *req;
 156         struct sge_ctrl_txq *ctrlq;
 157
 158         ctrlq = &adapter->sge.ctrlq[0];
 159         mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
 160         WARN_ON(!mbuf);
 161
 162         mbuf->data_len = sizeof(*req);
 163         mbuf->pkt_len = mbuf->data_len;
 164
 165         req = rte_pktmbuf_mtod(mbuf, struct cpl_set_tcb_field *);
 166         memset(req, 0, sizeof(*req));
 167         INIT_TP_WR_MIT_CPL(req, CPL_SET_TCB_FIELD, ftid);
 168         req->reply_ctrl = cpu_to_be16(V_REPLY_CHAN(0) |
 169                                       V_QUEUENO(adapter->sge.fw_evtq.abs_id) |
 170                                       V_NO_REPLY(no_reply));
 171         req->word_cookie = cpu_to_be16(V_WORD(word) | V_COOKIE(ftid));
 172         req->mask = cpu_to_be64(mask);
 173         req->val = cpu_to_be64(val);
 174
 175         t4_mgmt_tx(ctrlq, mbuf);
 176 }
 177
 178 /**
 179  * Set one of the t_flags bits in the TCB.
 180  */
 181 static void set_tcb_tflag(struct adapter *adap, unsigned int ftid,
 182                           unsigned int bit_pos, unsigned int val, int no_reply)
 183 {
 184         set_tcb_field(adap, ftid,  W_TCB_T_FLAGS, 1ULL << bit_pos,
 185                       (unsigned long long)val << bit_pos, no_reply);
 186 }
 187
 188 /**
 189  * Build a CPL_SET_TCB_FIELD message as payload of a ULP_TX_PKT command.
 190  */
 191 static inline void mk_set_tcb_field_ulp(struct filter_entry *f,
 192                                         struct cpl_set_tcb_field *req,
 193                                         unsigned int word,
 194                                         u64 mask, u64 val, u8 cookie,
 195                                         int no_reply)
 196 {
 197         struct ulp_txpkt *txpkt = (struct ulp_txpkt *)req;
 198         struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1);
 199
 200         txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
 201                                       V_ULP_TXPKT_DEST(0));
 202         txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*req), 16));
 203         sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
 204         sc->len = cpu_to_be32(sizeof(*req) - sizeof(struct work_request_hdr));
 205         OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_SET_TCB_FIELD, f->tid));
 206         req->reply_ctrl = cpu_to_be16(V_NO_REPLY(no_reply) | V_REPLY_CHAN(0) |
 207                                       V_QUEUENO(0));
 208         req->word_cookie = cpu_to_be16(V_WORD(word) | V_COOKIE(cookie));
 209         req->mask = cpu_to_be64(mask);
 210         req->val = cpu_to_be64(val);
 211         sc = (struct ulptx_idata *)(req + 1);
 212         sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
 213         sc->len = cpu_to_be32(0);
 214 }
 215
 216 /**
 217  * IPv6 requires 2 slots on T6 and 4 slots for cards below T6.
 218  * IPv4 requires only 1 slot on all cards.
 219  */
 220 u8 cxgbe_filter_slots(struct adapter *adap, u8 family)
 221 {
 222         if (family == FILTER_TYPE_IPV6) {
 223                 if (CHELSIO_CHIP_VERSION(adap->params.chip) < CHELSIO_T6)
 224                         return 4;
 225
 226                 return 2;
 227         }
 228
 229         return 1;
 230 }
 231
 232 /**
 233  * Check if entries are already filled.
 234  */
 235 bool cxgbe_is_filter_set(struct tid_info *t, u32 fidx, u8 nentries)
 236 {
 237         bool result = FALSE;
 238         u32 i;
 239
 240         /* Ensure there's enough slots available. */
 241         t4_os_lock(&t->ftid_lock);
 242         for (i = fidx; i < fidx + nentries; i++) {
 243                 if (rte_bitmap_get(t->ftid_bmap, i)) {
 244                         result = TRUE;
 245                         break;
 246                 }
 247         }
 248         t4_os_unlock(&t->ftid_lock);
 249         return result;
 250 }
 251
 252 /**
 253  * Allocate available free entries.
 254  */
 255 int cxgbe_alloc_ftid(struct adapter *adap, u8 nentries)
 256 {
 257         struct tid_info *t = &adap->tids;
 258         int pos;
 259         int size = t->nftids;
 260
 261         t4_os_lock(&t->ftid_lock);
 262         if (nentries > 1)
 263                 pos = cxgbe_bitmap_find_free_region(t->ftid_bmap, size,
 264                                                     nentries);
 265         else
 266                 pos = cxgbe_find_first_zero_bit(t->ftid_bmap, size);
 267         t4_os_unlock(&t->ftid_lock);
 268
 269         return pos < size ? pos : -1;
 270 }
 271
 272 /**
 273  * Construct hash filter ntuple.
 274  */
 275 static u64 hash_filter_ntuple(const struct filter_entry *f)
 276 {
 277         struct adapter *adap = ethdev2adap(f->dev);
 278         struct tp_params *tp = &adap->params.tp;
 279         u64 ntuple = 0;
 280         u16 tcp_proto = IPPROTO_TCP; /* TCP Protocol Number */
 281
 282         if (tp->port_shift >= 0 && f->fs.mask.iport)
 283                 ntuple |= (u64)f->fs.val.iport << tp->port_shift;
 284
 285         if (tp->protocol_shift >= 0) {
 286                 if (!f->fs.val.proto)
 287                         ntuple |= (u64)tcp_proto << tp->protocol_shift;
 288                 else
 289                         ntuple |= (u64)f->fs.val.proto << tp->protocol_shift;
 290         }
 291
 292         if (tp->ethertype_shift >= 0 && f->fs.mask.ethtype)
 293                 ntuple |= (u64)(f->fs.val.ethtype) << tp->ethertype_shift;
 294         if (tp->macmatch_shift >= 0 && f->fs.mask.macidx)
 295                 ntuple |= (u64)(f->fs.val.macidx) << tp->macmatch_shift;
 296         if (tp->vlan_shift >= 0 && f->fs.mask.ivlan)
 297                 ntuple |= (u64)(F_FT_VLAN_VLD | f->fs.val.ivlan) <<
 298                           tp->vlan_shift;
 299
 300         return ntuple;
 301 }
 302
 303 /**
 304  * Build a CPL_ABORT_REQ message as payload of a ULP_TX_PKT command.
 305  */
 306 static void mk_abort_req_ulp(struct cpl_abort_req *abort_req,
 307                              unsigned int tid)
 308 {
 309         struct ulp_txpkt *txpkt = (struct ulp_txpkt *)abort_req;
 310         struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1);
 311
 312         txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
 313                                       V_ULP_TXPKT_DEST(0));
 314         txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*abort_req), 16));
 315         sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
 316         sc->len = cpu_to_be32(sizeof(*abort_req) -
 317                               sizeof(struct work_request_hdr));
 318         OPCODE_TID(abort_req) = cpu_to_be32(MK_OPCODE_TID(CPL_ABORT_REQ, tid));
 319         abort_req->rsvd0 = cpu_to_be32(0);
 320         abort_req->rsvd1 = 0;
 321         abort_req->cmd = CPL_ABORT_NO_RST;
 322         sc = (struct ulptx_idata *)(abort_req + 1);
 323         sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
 324         sc->len = cpu_to_be32(0);
 325 }
 326
 327 /**
 328  * Build a CPL_ABORT_RPL message as payload of a ULP_TX_PKT command.
 329  */
 330 static void mk_abort_rpl_ulp(struct cpl_abort_rpl *abort_rpl,
 331                              unsigned int tid)
 332 {
 333         struct ulp_txpkt *txpkt = (struct ulp_txpkt *)abort_rpl;
 334         struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1);
 335
 336         txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
 337                                       V_ULP_TXPKT_DEST(0));
 338         txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*abort_rpl), 16));
 339         sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
 340         sc->len = cpu_to_be32(sizeof(*abort_rpl) -
 341                               sizeof(struct work_request_hdr));
 342         OPCODE_TID(abort_rpl) = cpu_to_be32(MK_OPCODE_TID(CPL_ABORT_RPL, tid));
 343         abort_rpl->rsvd0 = cpu_to_be32(0);
 344         abort_rpl->rsvd1 = 0;
 345         abort_rpl->cmd = CPL_ABORT_NO_RST;
 346         sc = (struct ulptx_idata *)(abort_rpl + 1);
 347         sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
 348         sc->len = cpu_to_be32(0);
 349 }
 350
 351 /**
 352  * Delete the specified hash filter.
 353  */
 354 static int cxgbe_del_hash_filter(struct rte_eth_dev *dev,
 355                                  unsigned int filter_id,
 356                                  struct filter_ctx *ctx)
 357 {
 358         struct adapter *adapter = ethdev2adap(dev);
 359         struct tid_info *t = &adapter->tids;
 360         struct filter_entry *f;
 361         struct sge_ctrl_txq *ctrlq;
 362         unsigned int port_id = ethdev2pinfo(dev)->port_id;
 363         int ret;
 364
 365         if (filter_id > adapter->tids.ntids)
 366                 return -E2BIG;
 367
 368         f = lookup_tid(t, filter_id);
 369         if (!f) {
 370                 dev_err(adapter, "%s: no filter entry for filter_id = %d\n",
 371                         __func__, filter_id);
 372                 return -EINVAL;
 373         }
 374
 375         ret = writable_filter(f);
 376         if (ret)
 377                 return ret;
 378
 379         if (f->valid) {
 380                 unsigned int wrlen;
 381                 struct rte_mbuf *mbuf;
 382                 struct work_request_hdr *wr;
 383                 struct ulptx_idata *aligner;
 384                 struct cpl_set_tcb_field *req;
 385                 struct cpl_abort_req *abort_req;
 386                 struct cpl_abort_rpl *abort_rpl;
 387
 388                 f->ctx = ctx;
 389                 f->pending = 1;
 390
 391                 wrlen = cxgbe_roundup(sizeof(*wr) +
 392                                       (sizeof(*req) + sizeof(*aligner)) +
 393                                       sizeof(*abort_req) + sizeof(*abort_rpl),
 394                                       16);
 395
 396                 ctrlq = &adapter->sge.ctrlq[port_id];
 397                 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
 398                 if (!mbuf) {
 399                         dev_err(adapter, "%s: could not allocate skb ..\n",
 400                                 __func__);
 401                         goto out_err;
 402                 }
 403
 404                 mbuf->data_len = wrlen;
 405                 mbuf->pkt_len = mbuf->data_len;
 406
 407                 req = rte_pktmbuf_mtod(mbuf, struct cpl_set_tcb_field *);
 408                 INIT_ULPTX_WR(req, wrlen, 0, 0);
 409                 wr = (struct work_request_hdr *)req;
 410                 wr++;
 411                 req = (struct cpl_set_tcb_field *)wr;
 412                 mk_set_tcb_field_ulp(f, req, W_TCB_RSS_INFO,
 413                                 V_TCB_RSS_INFO(M_TCB_RSS_INFO),
 414                                 V_TCB_RSS_INFO(adapter->sge.fw_evtq.abs_id),
 415                                 0, 1);
 416                 aligner = (struct ulptx_idata *)(req + 1);
 417                 abort_req = (struct cpl_abort_req *)(aligner + 1);
 418                 mk_abort_req_ulp(abort_req, f->tid);
 419                 abort_rpl = (struct cpl_abort_rpl *)(abort_req + 1);
 420                 mk_abort_rpl_ulp(abort_rpl, f->tid);
 421                 t4_mgmt_tx(ctrlq, mbuf);
 422         }
 423         return 0;
 424
 425 out_err:
 426         return -ENOMEM;
 427 }
 428
 429 /**
 430  * Build a ACT_OPEN_REQ6 message for setting IPv6 hash filter.
 431  */
 432 static void mk_act_open_req6(struct filter_entry *f, struct rte_mbuf *mbuf,
 433                              unsigned int qid_filterid, struct adapter *adap)
 434 {
 435         struct cpl_t6_act_open_req6 *req = NULL;
 436         u64 local_lo, local_hi, peer_lo, peer_hi;
 437         u32 *lip = (u32 *)f->fs.val.lip;
 438         u32 *fip = (u32 *)f->fs.val.fip;
 439
 440         switch (CHELSIO_CHIP_VERSION(adap->params.chip)) {
 441         case CHELSIO_T6:
 442                 req = rte_pktmbuf_mtod(mbuf, struct cpl_t6_act_open_req6 *);
 443
 444                 INIT_TP_WR(req, 0);
 445                 break;
 446         default:
 447                 dev_err(adap, "%s: unsupported chip type!\n", __func__);
 448                 return;
 449         }
 450
 451         local_hi = ((u64)lip[1]) << 32 | lip[0];
 452         local_lo = ((u64)lip[3]) << 32 | lip[2];
 453         peer_hi = ((u64)fip[1]) << 32 | fip[0];
 454         peer_lo = ((u64)fip[3]) << 32 | fip[2];
 455
 456         OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_ACT_OPEN_REQ6,
 457                                                     qid_filterid));
 458         req->local_port = cpu_to_be16(f->fs.val.lport);
 459         req->peer_port = cpu_to_be16(f->fs.val.fport);
 460         req->local_ip_hi = local_hi;
 461         req->local_ip_lo = local_lo;
 462         req->peer_ip_hi = peer_hi;
 463         req->peer_ip_lo = peer_lo;
 464         req->opt0 = cpu_to_be64(V_NAGLE(f->fs.newvlan == VLAN_REMOVE ||
 465                                         f->fs.newvlan == VLAN_REWRITE) |
 466                                 V_DELACK(f->fs.hitcnts) |
 467                                 V_L2T_IDX(f->l2t ? f->l2t->idx : 0) |
 468                                 V_SMAC_SEL((cxgbe_port_viid(f->dev) & 0x7F)
 469                                            << 1) |
 470                                 V_TX_CHAN(f->fs.eport) |
 471                                 V_ULP_MODE(ULP_MODE_NONE) |
 472                                 F_TCAM_BYPASS | F_NON_OFFLOAD);
 473         req->params = cpu_to_be64(V_FILTER_TUPLE(hash_filter_ntuple(f)));
 474         req->opt2 = cpu_to_be32(F_RSS_QUEUE_VALID |
 475                             V_RSS_QUEUE(f->fs.iq) |
 476                             F_T5_OPT_2_VALID |
 477                             F_RX_CHANNEL |
 478                             V_SACK_EN(f->fs.swapmac) |
 479                             V_CONG_CNTRL((f->fs.action == FILTER_DROP) |
 480                                          (f->fs.dirsteer << 1)) |
 481                             V_CCTRL_ECN(f->fs.action == FILTER_SWITCH));
 482 }
 483
 484 /**
 485  * Build a ACT_OPEN_REQ message for setting IPv4 hash filter.
 486  */
 487 static void mk_act_open_req(struct filter_entry *f, struct rte_mbuf *mbuf,
 488                             unsigned int qid_filterid, struct adapter *adap)
 489 {
 490         struct cpl_t6_act_open_req *req = NULL;
 491
 492         switch (CHELSIO_CHIP_VERSION(adap->params.chip)) {
 493         case CHELSIO_T6:
 494                 req = rte_pktmbuf_mtod(mbuf, struct cpl_t6_act_open_req *);
 495
 496                 INIT_TP_WR(req, 0);
 497                 break;
 498         default:
 499                 dev_err(adap, "%s: unsupported chip type!\n", __func__);
 500                 return;
 501         }
 502
 503         OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_ACT_OPEN_REQ,
 504                                                     qid_filterid));
 505         req->local_port = cpu_to_be16(f->fs.val.lport);
 506         req->peer_port = cpu_to_be16(f->fs.val.fport);
 507         req->local_ip = f->fs.val.lip[0] | f->fs.val.lip[1] << 8 |
 508                         f->fs.val.lip[2] << 16 | f->fs.val.lip[3] << 24;
 509         req->peer_ip = f->fs.val.fip[0] | f->fs.val.fip[1] << 8 |
 510                         f->fs.val.fip[2] << 16 | f->fs.val.fip[3] << 24;
 511         req->opt0 = cpu_to_be64(V_NAGLE(f->fs.newvlan == VLAN_REMOVE ||
 512                                         f->fs.newvlan == VLAN_REWRITE) |
 513                                 V_DELACK(f->fs.hitcnts) |
 514                                 V_L2T_IDX(f->l2t ? f->l2t->idx : 0) |
 515                                 V_SMAC_SEL((cxgbe_port_viid(f->dev) & 0x7F)
 516                                            << 1) |
 517                                 V_TX_CHAN(f->fs.eport) |
 518                                 V_ULP_MODE(ULP_MODE_NONE) |
 519                                 F_TCAM_BYPASS | F_NON_OFFLOAD);
 520         req->params = cpu_to_be64(V_FILTER_TUPLE(hash_filter_ntuple(f)));
 521         req->opt2 = cpu_to_be32(F_RSS_QUEUE_VALID |
 522                             V_RSS_QUEUE(f->fs.iq) |
 523                             F_T5_OPT_2_VALID |
 524                             F_RX_CHANNEL |
 525                             V_SACK_EN(f->fs.swapmac) |
 526                             V_CONG_CNTRL((f->fs.action == FILTER_DROP) |
 527                                          (f->fs.dirsteer << 1)) |
 528                             V_CCTRL_ECN(f->fs.action == FILTER_SWITCH));
 529 }
 530
 531 /**
 532  * Set the specified hash filter.
 533  */
 534 static int cxgbe_set_hash_filter(struct rte_eth_dev *dev,
 535                                  struct ch_filter_specification *fs,
 536                                  struct filter_ctx *ctx)
 537 {
 538         struct port_info *pi = ethdev2pinfo(dev);
 539         struct adapter *adapter = pi->adapter;
 540         struct tid_info *t = &adapter->tids;
 541         struct filter_entry *f;
 542         struct rte_mbuf *mbuf;
 543         struct sge_ctrl_txq *ctrlq;
 544         unsigned int iq;
 545         int atid, size;
 546         int ret = 0;
 547
 548         ret = cxgbe_validate_filter(adapter, fs);
 549         if (ret)
 550                 return ret;
 551
 552         iq = get_filter_steerq(dev, fs);
 553
 554         ctrlq = &adapter->sge.ctrlq[pi->port_id];
 555
 556         f = t4_os_alloc(sizeof(*f));
 557         if (!f)
 558                 goto out_err;
 559
 560         f->fs = *fs;
 561         f->ctx = ctx;
 562         f->dev = dev;
 563         f->fs.iq = iq;
 564
 565         /*
 566          * If the new filter requires loopback Destination MAC and/or VLAN
 567          * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
 568          * the filter.
 569          */
 570         if (f->fs.newvlan == VLAN_INSERT ||
 571             f->fs.newvlan == VLAN_REWRITE) {
 572                 /* allocate L2T entry for new filter */
 573                 f->l2t = cxgbe_l2t_alloc_switching(dev, f->fs.vlan,
 574                                                    f->fs.eport, f->fs.dmac);
 575                 if (!f->l2t) {
 576                         ret = -ENOMEM;
 577                         goto out_err;
 578                 }
 579         }
 580
 581         atid = cxgbe_alloc_atid(t, f);
 582         if (atid < 0)
 583                 goto out_err;
 584
 585         if (f->fs.type == FILTER_TYPE_IPV6) {
 586                 /* IPv6 hash filter */
 587                 f->clipt = cxgbe_clip_alloc(f->dev, (u32 *)&f->fs.val.lip);
 588                 if (!f->clipt)
 589                         goto free_atid;
 590
 591                 size = sizeof(struct cpl_t6_act_open_req6);
 592                 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
 593                 if (!mbuf) {
 594                         ret = -ENOMEM;
 595                         goto free_clip;
 596                 }
 597
 598                 mbuf->data_len = size;
 599                 mbuf->pkt_len = mbuf->data_len;
 600
 601                 mk_act_open_req6(f, mbuf,
 602                                  ((adapter->sge.fw_evtq.abs_id << 14) | atid),
 603                                  adapter);
 604         } else {
 605                 /* IPv4 hash filter */
 606                 size = sizeof(struct cpl_t6_act_open_req);
 607                 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
 608                 if (!mbuf) {
 609                         ret = -ENOMEM;
 610                         goto free_atid;
 611                 }
 612
 613                 mbuf->data_len = size;
 614                 mbuf->pkt_len = mbuf->data_len;
 615
 616                 mk_act_open_req(f, mbuf,
 617                                 ((adapter->sge.fw_evtq.abs_id << 14) | atid),
 618                                 adapter);
 619         }
 620
 621         f->pending = 1;
 622         t4_mgmt_tx(ctrlq, mbuf);
 623         return 0;
 624
 625 free_clip:
 626         cxgbe_clip_release(f->dev, f->clipt);
 627 free_atid:
 628         cxgbe_free_atid(t, atid);
 629
 630 out_err:
 631         t4_os_free(f);
 632         return ret;
 633 }
 634
 635 /**
 636  * Clear a filter and release any of its resources that we own.  This also
 637  * clears the filter's "pending" status.
 638  */
 639 static void clear_filter(struct filter_entry *f)
 640 {
 641         if (f->clipt)
 642                 cxgbe_clip_release(f->dev, f->clipt);
 643
 644         /*
 645          * The zeroing of the filter rule below clears the filter valid,
 646          * pending, locked flags etc. so it's all we need for
 647          * this operation.
 648          */
 649         memset(f, 0, sizeof(*f));
 650 }
 651
 652 /**
 653  * t4_mk_filtdelwr - create a delete filter WR
 654  * @adap: adapter context
 655  * @ftid: the filter ID
 656  * @wr: the filter work request to populate
 657  * @qid: ingress queue to receive the delete notification
 658  *
 659  * Creates a filter work request to delete the supplied filter.  If @qid is
 660  * negative the delete notification is suppressed.
 661  */
 662 static void t4_mk_filtdelwr(struct adapter *adap, unsigned int ftid,
 663                             struct fw_filter2_wr *wr, int qid)
 664 {
 665         memset(wr, 0, sizeof(*wr));
 666         if (adap->params.filter2_wr_support)
 667                 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER2_WR));
 668         else
 669                 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
 670         wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16));
 671         wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) |
 672                                     V_FW_FILTER_WR_NOREPLY(qid < 0));
 673         wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER);
 674         if (qid >= 0)
 675                 wr->rx_chan_rx_rpl_iq =
 676                                 cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid));
 677 }
 678
 679 /**
 680  * Create FW work request to delete the filter at a specified index
 681  */
 682 static int del_filter_wr(struct rte_eth_dev *dev, unsigned int fidx)
 683 {
 684         struct adapter *adapter = ethdev2adap(dev);
 685         struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
 686         struct rte_mbuf *mbuf;
 687         struct fw_filter2_wr *fwr;
 688         struct sge_ctrl_txq *ctrlq;
 689         unsigned int port_id = ethdev2pinfo(dev)->port_id;
 690
 691         ctrlq = &adapter->sge.ctrlq[port_id];
 692         mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
 693         if (!mbuf)
 694                 return -ENOMEM;
 695
 696         mbuf->data_len = sizeof(*fwr);
 697         mbuf->pkt_len = mbuf->data_len;
 698
 699         fwr = rte_pktmbuf_mtod(mbuf, struct fw_filter2_wr *);
 700         t4_mk_filtdelwr(adapter, f->tid, fwr, adapter->sge.fw_evtq.abs_id);
 701
 702         /*
 703          * Mark the filter as "pending" and ship off the Filter Work Request.
 704          * When we get the Work Request Reply we'll clear the pending status.
 705          */
 706         f->pending = 1;
 707         t4_mgmt_tx(ctrlq, mbuf);
 708         return 0;
 709 }
 710
 711 static int set_filter_wr(struct rte_eth_dev *dev, unsigned int fidx)
 712 {
 713         struct adapter *adapter = ethdev2adap(dev);
 714         struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
 715         struct rte_mbuf *mbuf;
 716         struct fw_filter2_wr *fwr;
 717         struct sge_ctrl_txq *ctrlq;
 718         unsigned int port_id = ethdev2pinfo(dev)->port_id;
 719         int ret;
 720
 721         /*
 722          * If the new filter requires loopback Destination MAC and/or VLAN
 723          * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
 724          * the filter.
 725          */
 726         if (f->fs.newvlan) {
 727                 /* allocate L2T entry for new filter */
 728                 f->l2t = cxgbe_l2t_alloc_switching(f->dev, f->fs.vlan,
 729                                                    f->fs.eport, f->fs.dmac);
 730                 if (!f->l2t)
 731                         return -ENOMEM;
 732         }
 733
 734         ctrlq = &adapter->sge.ctrlq[port_id];
 735         mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
 736         if (!mbuf) {
 737                 ret = -ENOMEM;
 738                 goto out;
 739         }
 740
 741         mbuf->data_len = sizeof(*fwr);
 742         mbuf->pkt_len = mbuf->data_len;
 743
 744         fwr = rte_pktmbuf_mtod(mbuf, struct fw_filter2_wr *);
 745         memset(fwr, 0, sizeof(*fwr));
 746
 747         /*
 748          * Construct the work request to set the filter.
 749          */
 750         if (adapter->params.filter2_wr_support)
 751                 fwr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER2_WR));
 752         else
 753                 fwr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
 754         fwr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*fwr) / 16));
 755         fwr->tid_to_iq =
 756                 cpu_to_be32(V_FW_FILTER_WR_TID(f->tid) |
 757                             V_FW_FILTER_WR_RQTYPE(f->fs.type) |
 758                             V_FW_FILTER_WR_NOREPLY(0) |
 759                             V_FW_FILTER_WR_IQ(f->fs.iq));
 760         fwr->del_filter_to_l2tix =
 761                 cpu_to_be32(V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
 762                             V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
 763                             V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
 764                             V_FW_FILTER_WR_INSVLAN
 765                                 (f->fs.newvlan == VLAN_INSERT ||
 766                                  f->fs.newvlan == VLAN_REWRITE) |
 767                             V_FW_FILTER_WR_RMVLAN
 768                                 (f->fs.newvlan == VLAN_REMOVE ||
 769                                  f->fs.newvlan == VLAN_REWRITE) |
 770                             V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
 771                             V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
 772                             V_FW_FILTER_WR_PRIO(f->fs.prio) |
 773                             V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
 774         fwr->ethtype = cpu_to_be16(f->fs.val.ethtype);
 775         fwr->ethtypem = cpu_to_be16(f->fs.mask.ethtype);
 776         fwr->frag_to_ovlan_vldm =
 777                 (V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.ivlan_vld) |
 778                  V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.ivlan_vld));
 779         fwr->smac_sel = 0;
 780         fwr->rx_chan_rx_rpl_iq =
 781                 cpu_to_be16(V_FW_FILTER_WR_RX_CHAN(0) |
 782                             V_FW_FILTER_WR_RX_RPL_IQ(adapter->sge.fw_evtq.abs_id
 783                                                      ));
 784         fwr->maci_to_matchtypem =
 785                 cpu_to_be32(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
 786                             V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
 787                             V_FW_FILTER_WR_PORT(f->fs.val.iport) |
 788                             V_FW_FILTER_WR_PORTM(f->fs.mask.iport));
 789         fwr->ptcl = f->fs.val.proto;
 790         fwr->ptclm = f->fs.mask.proto;
 791         fwr->ivlan = cpu_to_be16(f->fs.val.ivlan);
 792         fwr->ivlanm = cpu_to_be16(f->fs.mask.ivlan);
 793         rte_memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
 794         rte_memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
 795         rte_memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
 796         rte_memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
 797         fwr->lp = cpu_to_be16(f->fs.val.lport);
 798         fwr->lpm = cpu_to_be16(f->fs.mask.lport);
 799         fwr->fp = cpu_to_be16(f->fs.val.fport);
 800         fwr->fpm = cpu_to_be16(f->fs.mask.fport);
 801
 802         if (adapter->params.filter2_wr_support) {
 803                 fwr->filter_type_swapmac =
 804                          V_FW_FILTER2_WR_SWAPMAC(f->fs.swapmac);
 805                 fwr->natmode_to_ulp_type =
 806                         V_FW_FILTER2_WR_ULP_TYPE(f->fs.nat_mode ?
 807                                                  ULP_MODE_TCPDDP :
 808                                                  ULP_MODE_NONE) |
 809                         V_FW_FILTER2_WR_NATMODE(f->fs.nat_mode);
 810                 memcpy(fwr->newlip, f->fs.nat_lip, sizeof(fwr->newlip));
 811                 memcpy(fwr->newfip, f->fs.nat_fip, sizeof(fwr->newfip));
 812                 fwr->newlport = cpu_to_be16(f->fs.nat_lport);
 813                 fwr->newfport = cpu_to_be16(f->fs.nat_fport);
 814         }
 815
 816         /*
 817          * Mark the filter as "pending" and ship off the Filter Work Request.
 818          * When we get the Work Request Reply we'll clear the pending status.
 819          */
 820         f->pending = 1;
 821         t4_mgmt_tx(ctrlq, mbuf);
 822         return 0;
 823
 824 out:
 825         return ret;
 826 }
 827
 828 /**
 829  * Set the corresponding entries in the bitmap.
 830  */
 831 static int cxgbe_set_ftid(struct tid_info *t, u32 fidx, u8 nentries)
 832 {
 833         u32 i;
 834
 835         t4_os_lock(&t->ftid_lock);
 836         if (rte_bitmap_get(t->ftid_bmap, fidx)) {
 837                 t4_os_unlock(&t->ftid_lock);
 838                 return -EBUSY;
 839         }
 840
 841         for (i = fidx; i < fidx + nentries; i++)
 842                 rte_bitmap_set(t->ftid_bmap, i);
 843         t4_os_unlock(&t->ftid_lock);
 844         return 0;
 845 }
 846
 847 /**
 848  * Clear the corresponding entries in the bitmap.
 849  */
 850 static void cxgbe_clear_ftid(struct tid_info *t, u32 fidx, u8 nentries)
 851 {
 852         u32 i;
 853
 854         t4_os_lock(&t->ftid_lock);
 855         for (i = fidx; i < fidx + nentries; i++)
 856                 rte_bitmap_clear(t->ftid_bmap, i);
 857         t4_os_unlock(&t->ftid_lock);
 858 }
 859
 860 /**
 861  * Check a delete filter request for validity and send it to the hardware.
 862  * Return 0 on success, an error number otherwise.  We attach any provided
 863  * filter operation context to the internal filter specification in order to
 864  * facilitate signaling completion of the operation.
 865  */
 866 int cxgbe_del_filter(struct rte_eth_dev *dev, unsigned int filter_id,
 867                      struct ch_filter_specification *fs,
 868                      struct filter_ctx *ctx)
 869 {
 870         struct port_info *pi = dev->data->dev_private;
 871         struct adapter *adapter = pi->adapter;
 872         struct filter_entry *f;
 873         unsigned int chip_ver;
 874         u8 nentries;
 875         int ret;
 876
 877         if (is_hashfilter(adapter) && fs->cap)
 878                 return cxgbe_del_hash_filter(dev, filter_id, ctx);
 879
 880         if (filter_id >= adapter->tids.nftids)
 881                 return -ERANGE;
 882
 883         chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
 884
 885         /*
 886          * Ensure IPv6 filter id is aligned on the 2 slot boundary for T6,
 887          * and 4 slot boundary for cards below T6.
 888          */
 889         if (fs->type == FILTER_TYPE_IPV6) {
 890                 if (chip_ver < CHELSIO_T6)
 891                         filter_id &= ~(0x3);
 892                 else
 893                         filter_id &= ~(0x1);
 894         }
 895
 896         nentries = cxgbe_filter_slots(adapter, fs->type);
 897         ret = cxgbe_is_filter_set(&adapter->tids, filter_id, nentries);
 898         if (!ret) {
 899                 dev_warn(adap, "%s: could not find filter entry: %u\n",
 900                          __func__, filter_id);
 901                 return -EINVAL;
 902         }
 903
 904         f = &adapter->tids.ftid_tab[filter_id];
 905         ret = writable_filter(f);
 906         if (ret)
 907                 return ret;
 908
 909         if (f->valid) {
 910                 f->ctx = ctx;
 911                 cxgbe_clear_ftid(&adapter->tids,
 912                                  f->tid - adapter->tids.ftid_base,
 913                                  nentries);
 914                 return del_filter_wr(dev, filter_id);
 915         }
 916
 917         /*
 918          * If the caller has passed in a Completion Context then we need to
 919          * mark it as a successful completion so they don't stall waiting
 920          * for it.
 921          */
 922         if (ctx) {
 923                 ctx->result = 0;
 924                 t4_complete(&ctx->completion);
 925         }
 926
 927         return 0;
 928 }
 929
 930 /**
 931  * Check a Chelsio Filter Request for validity, convert it into our internal
 932  * format and send it to the hardware.  Return 0 on success, an error number
 933  * otherwise.  We attach any provided filter operation context to the internal
 934  * filter specification in order to facilitate signaling completion of the
 935  * operation.
 936  */
 937 int cxgbe_set_filter(struct rte_eth_dev *dev, unsigned int filter_id,
 938                      struct ch_filter_specification *fs,
 939                      struct filter_ctx *ctx)
 940 {
 941         struct port_info *pi = ethdev2pinfo(dev);
 942         struct adapter *adapter = pi->adapter;
 943         unsigned int fidx, iq;
 944         struct filter_entry *f;
 945         unsigned int chip_ver;
 946         u8 nentries, bitoff[16] = {0};
 947         int ret;
 948
 949         if (is_hashfilter(adapter) && fs->cap)
 950                 return cxgbe_set_hash_filter(dev, fs, ctx);
 951
 952         if (filter_id >= adapter->tids.nftids)
 953                 return -ERANGE;
 954
 955         chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
 956
 957         ret = cxgbe_validate_filter(adapter, fs);
 958         if (ret)
 959                 return ret;
 960
 961         /*
 962          * IPv6 filters occupy four slots and must be aligned on four-slot
 963          * boundaries for T5. On T6, IPv6 filters occupy two-slots and
 964          * must be aligned on two-slot boundaries.
 965          *
 966          * IPv4 filters only occupy a single slot and have no alignment
 967          * requirements.
 968          */
 969         fidx = filter_id;
 970         if (fs->type == FILTER_TYPE_IPV6) {
 971                 if (chip_ver < CHELSIO_T6)
 972                         fidx &= ~(0x3);
 973                 else
 974                         fidx &= ~(0x1);
 975         }
 976
 977         if (fidx != filter_id)
 978                 return -EINVAL;
 979
 980         nentries = cxgbe_filter_slots(adapter, fs->type);
 981         ret = cxgbe_is_filter_set(&adapter->tids, filter_id, nentries);
 982         if (ret)
 983                 return -EBUSY;
 984
 985         iq = get_filter_steerq(dev, fs);
 986
 987         /*
 988          * Check to make sure that provided filter index is not
 989          * already in use by someone else
 990          */
 991         f = &adapter->tids.ftid_tab[filter_id];
 992         if (f->valid)
 993                 return -EBUSY;
 994
 995         fidx = adapter->tids.ftid_base + filter_id;
 996         ret = cxgbe_set_ftid(&adapter->tids, filter_id, nentries);
 997         if (ret)
 998                 return ret;
 999
1000         /*
1001          * Check to make sure the filter requested is writable ...
1002          */
1003         ret = writable_filter(f);
1004         if (ret) {
1005                 /* Clear the bits we have set above */
1006                 cxgbe_clear_ftid(&adapter->tids, filter_id, nentries);
1007                 return ret;
1008         }
1009
1010         /*
1011          * Allocate a clip table entry only if we have non-zero IPv6 address
1012          */
1013         if (chip_ver > CHELSIO_T5 && fs->type &&
1014             memcmp(fs->val.lip, bitoff, sizeof(bitoff))) {
1015                 f->clipt = cxgbe_clip_alloc(dev, (u32 *)&fs->val.lip);
1016                 if (!f->clipt)
1017                         goto free_tid;
1018         }
1019
1020         /*
1021          * Convert the filter specification into our internal format.
1022          * We copy the PF/VF specification into the Outer VLAN field
1023          * here so the rest of the code -- including the interface to
1024          * the firmware -- doesn't have to constantly do these checks.
1025          */
1026         f->fs = *fs;
1027         f->fs.iq = iq;
1028         f->dev = dev;
1029
1030         /*
1031          * Attempt to set the filter.  If we don't succeed, we clear
1032          * it and return the failure.
1033          */
1034         f->ctx = ctx;
1035         f->tid = fidx; /* Save the actual tid */
1036         ret = set_filter_wr(dev, filter_id);
1037         if (ret)
1038                 goto free_tid;
1039
1040         return ret;
1041
1042 free_tid:
1043         cxgbe_clear_ftid(&adapter->tids, filter_id, nentries);
1044         clear_filter(f);
1045         return ret;
1046 }
1047
1048 /**
1049  * Handle a Hash filter write reply.
1050  */
1051 void cxgbe_hash_filter_rpl(struct adapter *adap,
1052                            const struct cpl_act_open_rpl *rpl)
1053 {
1054         struct tid_info *t = &adap->tids;
1055         struct filter_entry *f;
1056         struct filter_ctx *ctx = NULL;
1057         unsigned int tid = GET_TID(rpl);
1058         unsigned int ftid = G_TID_TID(G_AOPEN_ATID
1059                                       (be32_to_cpu(rpl->atid_status)));
1060         unsigned int status  = G_AOPEN_STATUS(be32_to_cpu(rpl->atid_status));
1061
1062         f = lookup_atid(t, ftid);
1063         if (!f) {
1064                 dev_warn(adap, "%s: could not find filter entry: %d\n",
1065                          __func__, ftid);
1066                 return;
1067         }
1068
1069         ctx = f->ctx;
1070         f->ctx = NULL;
1071
1072         switch (status) {
1073         case CPL_ERR_NONE: {
1074                 f->tid = tid;
1075                 f->pending = 0;  /* asynchronous setup completed */
1076                 f->valid = 1;
1077
1078                 cxgbe_insert_tid(t, f, f->tid, 0);
1079                 cxgbe_free_atid(t, ftid);
1080                 if (ctx) {
1081                         ctx->tid = f->tid;
1082                         ctx->result = 0;
1083                 }
1084                 if (f->fs.hitcnts)
1085                         set_tcb_field(adap, tid,
1086                                       W_TCB_TIMESTAMP,
1087                                       V_TCB_TIMESTAMP(M_TCB_TIMESTAMP) |
1088                                       V_TCB_T_RTT_TS_RECENT_AGE
1089                                               (M_TCB_T_RTT_TS_RECENT_AGE),
1090                                       V_TCB_TIMESTAMP(0ULL) |
1091                                       V_TCB_T_RTT_TS_RECENT_AGE(0ULL),
1092                                       1);
1093                 if (f->fs.newvlan == VLAN_INSERT ||
1094                     f->fs.newvlan == VLAN_REWRITE)
1095                         set_tcb_tflag(adap, tid, S_TF_CCTRL_RFR, 1, 1);
1096                 break;
1097         }
1098         default:
1099                 dev_warn(adap, "%s: filter creation failed with status = %u\n",
1100                          __func__, status);
1101
1102                 if (ctx) {
1103                         if (status == CPL_ERR_TCAM_FULL)
1104                                 ctx->result = -EAGAIN;
1105                         else
1106                                 ctx->result = -EINVAL;
1107                 }
1108
1109                 cxgbe_free_atid(t, ftid);
1110                 t4_os_free(f);
1111         }
1112
1113         if (ctx)
1114                 t4_complete(&ctx->completion);
1115 }
1116
1117 /**
1118  * Handle a LE-TCAM filter write/deletion reply.
1119  */
1120 void cxgbe_filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
1121 {
1122         struct filter_entry *f = NULL;
1123         unsigned int tid = GET_TID(rpl);
1124         int idx, max_fidx = adap->tids.nftids;
1125
1126         /* Get the corresponding filter entry for this tid */
1127         if (adap->tids.ftid_tab) {
1128                 /* Check this in normal filter region */
1129                 idx = tid - adap->tids.ftid_base;
1130                 if (idx >= max_fidx)
1131                         return;
1132
1133                 f = &adap->tids.ftid_tab[idx];
1134                 if (f->tid != tid)
1135                         return;
1136         }
1137
1138         /* We found the filter entry for this tid */
1139         if (f) {
1140                 unsigned int ret = G_COOKIE(rpl->cookie);
1141                 struct filter_ctx *ctx;
1142
1143                 /*
1144                  * Pull off any filter operation context attached to the
1145                  * filter.
1146                  */
1147                 ctx = f->ctx;
1148                 f->ctx = NULL;
1149
1150                 if (ret == FW_FILTER_WR_FLT_ADDED) {
1151                         f->pending = 0;  /* asynchronous setup completed */
1152                         f->valid = 1;
1153                         if (ctx) {
1154                                 ctx->tid = f->tid;
1155                                 ctx->result = 0;
1156                         }
1157                 } else if (ret == FW_FILTER_WR_FLT_DELETED) {
1158                         /*
1159                          * Clear the filter when we get confirmation from the
1160                          * hardware that the filter has been deleted.
1161                          */
1162                         clear_filter(f);
1163                         if (ctx)
1164                                 ctx->result = 0;
1165                 } else {
1166                         /*
1167                          * Something went wrong.  Issue a warning about the
1168                          * problem and clear everything out.
1169                          */
1170                         dev_warn(adap, "filter %u setup failed with error %u\n",
1171                                  idx, ret);
1172                         clear_filter(f);
1173                         if (ctx)
1174                                 ctx->result = -EINVAL;
1175                 }
1176
1177                 if (ctx)
1178                         t4_complete(&ctx->completion);
1179         }
1180 }
1181
1182 /*
1183  * Retrieve the packet count for the specified filter.
1184  */
1185 int cxgbe_get_filter_count(struct adapter *adapter, unsigned int fidx,
1186                            u64 *c, int hash, bool get_byte)
1187 {
1188         struct filter_entry *f;
1189         unsigned int tcb_base, tcbaddr;
1190         int ret;
1191
1192         tcb_base = t4_read_reg(adapter, A_TP_CMM_TCB_BASE);
1193         if (is_hashfilter(adapter) && hash) {
1194                 if (fidx < adapter->tids.ntids) {
1195                         f = adapter->tids.tid_tab[fidx];
1196                         if (!f)
1197                                 return -EINVAL;
1198
1199                         if (is_t5(adapter->params.chip)) {
1200                                 *c = 0;
1201                                 return 0;
1202                         }
1203                         tcbaddr = tcb_base + (fidx * TCB_SIZE);
1204                         goto get_count;
1205                 } else {
1206                         return -ERANGE;
1207                 }
1208         } else {
1209                 if (fidx >= adapter->tids.nftids)
1210                         return -ERANGE;
1211
1212                 f = &adapter->tids.ftid_tab[fidx];
1213                 if (!f->valid)
1214                         return -EINVAL;
1215
1216                 tcbaddr = tcb_base + f->tid * TCB_SIZE;
1217         }
1218
1219         f = &adapter->tids.ftid_tab[fidx];
1220         if (!f->valid)
1221                 return -EINVAL;
1222
1223 get_count:
1224         if (is_t5(adapter->params.chip) || is_t6(adapter->params.chip)) {
1225                 /*
1226                  * For T5, the Filter Packet Hit Count is maintained as a
1227                  * 32-bit Big Endian value in the TCB field {timestamp}.
1228                  * Similar to the craziness above, instead of the filter hit
1229                  * count showing up at offset 20 ((W_TCB_TIMESTAMP == 5) *
1230                  * sizeof(u32)), it actually shows up at offset 24.  Whacky.
1231                  */
1232                 if (get_byte) {
1233                         unsigned int word_offset = 4;
1234                         __be64 be64_byte_count;
1235
1236                         t4_os_lock(&adapter->win0_lock);
1237                         ret = t4_memory_rw(adapter, MEMWIN_NIC, MEM_EDC0,
1238                                            tcbaddr +
1239                                            (word_offset * sizeof(__be32)),
1240                                            sizeof(be64_byte_count),
1241                                            &be64_byte_count,
1242                                            T4_MEMORY_READ);
1243                         t4_os_unlock(&adapter->win0_lock);
1244                         if (ret < 0)
1245                                 return ret;
1246                         *c = be64_to_cpu(be64_byte_count);
1247                 } else {
1248                         unsigned int word_offset = 6;
1249                         __be32 be32_count;
1250
1251                         t4_os_lock(&adapter->win0_lock);
1252                         ret = t4_memory_rw(adapter, MEMWIN_NIC, MEM_EDC0,
1253                                            tcbaddr +
1254                                            (word_offset * sizeof(__be32)),
1255                                            sizeof(be32_count), &be32_count,
1256                                            T4_MEMORY_READ);
1257                         t4_os_unlock(&adapter->win0_lock);
1258                         if (ret < 0)
1259                                 return ret;
1260                         *c = (u64)be32_to_cpu(be32_count);
1261                 }
1262         }
1263         return 0;
1264 }
1265
1266 /*
1267  * Clear the packet count for the specified filter.
1268  */
1269 int cxgbe_clear_filter_count(struct adapter *adapter, unsigned int fidx,
1270                              int hash, bool clear_byte)
1271 {
1272         u64 tcb_mask = 0, tcb_val = 0;
1273         struct filter_entry *f = NULL;
1274         u16 tcb_word = 0;
1275
1276         if (is_hashfilter(adapter) && hash) {
1277                 if (fidx >= adapter->tids.ntids)
1278                         return -ERANGE;
1279
1280                 /* No hitcounts supported for T5 hashfilters */
1281                 if (is_t5(adapter->params.chip))
1282                         return 0;
1283
1284                 f = adapter->tids.tid_tab[fidx];
1285         } else {
1286                 if (fidx >= adapter->tids.nftids)
1287                         return -ERANGE;
1288
1289                 f = &adapter->tids.ftid_tab[fidx];
1290         }
1291
1292         if (!f || !f->valid)
1293                 return -EINVAL;
1294
1295         tcb_word = W_TCB_TIMESTAMP;
1296         tcb_mask = V_TCB_TIMESTAMP(M_TCB_TIMESTAMP);
1297         tcb_val = V_TCB_TIMESTAMP(0ULL);
1298
1299         set_tcb_field(adapter, f->tid, tcb_word, tcb_mask, tcb_val, 1);
1300
1301         if (clear_byte) {
1302                 tcb_word = W_TCB_T_RTT_TS_RECENT_AGE;
1303                 tcb_mask =
1304                         V_TCB_T_RTT_TS_RECENT_AGE(M_TCB_T_RTT_TS_RECENT_AGE) |
1305                         V_TCB_T_RTSEQ_RECENT(M_TCB_T_RTSEQ_RECENT);
1306                 tcb_val = V_TCB_T_RTT_TS_RECENT_AGE(0ULL) |
1307                           V_TCB_T_RTSEQ_RECENT(0ULL);
1308
1309                 set_tcb_field(adapter, f->tid, tcb_word, tcb_mask, tcb_val, 1);
1310         }
1311
1312         return 0;
1313 }
1314
1315 /**
1316  * Handle a Hash filter delete reply.
1317  */
1318 void cxgbe_hash_del_filter_rpl(struct adapter *adap,
1319                                const struct cpl_abort_rpl_rss *rpl)
1320 {
1321         struct tid_info *t = &adap->tids;
1322         struct filter_entry *f;
1323         struct filter_ctx *ctx = NULL;
1324         unsigned int tid = GET_TID(rpl);
1325
1326         f = lookup_tid(t, tid);
1327         if (!f) {
1328                 dev_warn(adap, "%s: could not find filter entry: %u\n",
1329                          __func__, tid);
1330                 return;
1331         }
1332
1333         ctx = f->ctx;
1334         f->ctx = NULL;
1335
1336         f->valid = 0;
1337
1338         if (f->clipt)
1339                 cxgbe_clip_release(f->dev, f->clipt);
1340
1341         cxgbe_remove_tid(t, 0, tid, 0);
1342         t4_os_free(f);
1343
1344         if (ctx) {
1345                 ctx->result = 0;
1346                 t4_complete(&ctx->completion);
1347         }
1348 }