1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Chelsio Communications.
5 #include "base/common.h"
6 #include "cxgbe_flow.h"
8 #define __CXGBE_FILL_FS(__v, __m, fs, elem, e) \
10 if ((fs)->mask.elem && ((fs)->val.elem != (__v))) \
11 return rte_flow_error_set(e, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, \
12 NULL, "Redefined match item with" \
13 " different values found"); \
14 (fs)->val.elem = (__v); \
15 (fs)->mask.elem = (__m); \
18 #define __CXGBE_FILL_FS_MEMCPY(__v, __m, fs, elem) \
20 memcpy(&(fs)->val.elem, &(__v), sizeof(__v)); \
21 memcpy(&(fs)->mask.elem, &(__m), sizeof(__m)); \
24 #define CXGBE_FILL_FS(v, m, elem) \
25 __CXGBE_FILL_FS(v, m, fs, elem, e)
27 #define CXGBE_FILL_FS_MEMCPY(v, m, elem) \
28 __CXGBE_FILL_FS_MEMCPY(v, m, fs, elem)
31 cxgbe_validate_item(const struct rte_flow_item *i, struct rte_flow_error *e)
33 /* rte_flow specification does not allow it. */
34 if (!i->spec && (i->mask || i->last))
35 return rte_flow_error_set(e, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM,
36 i, "last or mask given without spec");
38 * We don't support it.
39 * Although, we can support values in last as 0's or last == spec.
40 * But this will not provide user with any additional functionality
41 * and will only increase the complexity for us.
44 return rte_flow_error_set(e, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
45 i, "last is not supported by chelsio pmd");
50 * Apart from the 4-tuple IPv4/IPv6 - TCP/UDP information,
51 * there's only 40-bits available to store match fields.
52 * So, to save space, optimize filter spec for some common
53 * known fields that hardware can parse against incoming
54 * packets automatically.
57 cxgbe_tweak_filter_spec(struct adapter *adap,
58 struct ch_filter_specification *fs)
60 /* Save 16-bit ethertype field space, by setting corresponding
61 * 1-bit flags in the filter spec for common known ethertypes.
62 * When hardware sees these flags, it automatically infers and
63 * matches incoming packets against the corresponding ethertype.
65 if (fs->mask.ethtype == 0xffff) {
66 switch (fs->val.ethtype) {
67 case RTE_ETHER_TYPE_IPV4:
68 if (adap->params.tp.ethertype_shift < 0) {
69 fs->type = FILTER_TYPE_IPV4;
74 case RTE_ETHER_TYPE_IPV6:
75 if (adap->params.tp.ethertype_shift < 0) {
76 fs->type = FILTER_TYPE_IPV6;
81 case RTE_ETHER_TYPE_VLAN:
82 if (adap->params.tp.ethertype_shift < 0 &&
83 adap->params.tp.vlan_shift >= 0) {
84 fs->val.ivlan_vld = 1;
85 fs->mask.ivlan_vld = 1;
90 case RTE_ETHER_TYPE_QINQ:
91 if (adap->params.tp.ethertype_shift < 0 &&
92 adap->params.tp.vnic_shift >= 0) {
93 fs->val.ovlan_vld = 1;
94 fs->mask.ovlan_vld = 1;
106 cxgbe_fill_filter_region(struct adapter *adap,
107 struct ch_filter_specification *fs)
109 struct tp_params *tp = &adap->params.tp;
110 u64 hash_filter_mask = tp->hash_filter_mask;
115 if (!is_hashfilter(adap))
119 uint8_t biton[16] = {0xff, 0xff, 0xff, 0xff,
120 0xff, 0xff, 0xff, 0xff,
121 0xff, 0xff, 0xff, 0xff,
122 0xff, 0xff, 0xff, 0xff};
123 uint8_t bitoff[16] = {0};
125 if (!memcmp(fs->val.lip, bitoff, sizeof(bitoff)) ||
126 !memcmp(fs->val.fip, bitoff, sizeof(bitoff)) ||
127 memcmp(fs->mask.lip, biton, sizeof(biton)) ||
128 memcmp(fs->mask.fip, biton, sizeof(biton)))
131 uint32_t biton = 0xffffffff;
132 uint32_t bitoff = 0x0U;
134 if (!memcmp(fs->val.lip, &bitoff, sizeof(bitoff)) ||
135 !memcmp(fs->val.fip, &bitoff, sizeof(bitoff)) ||
136 memcmp(fs->mask.lip, &biton, sizeof(biton)) ||
137 memcmp(fs->mask.fip, &biton, sizeof(biton)))
141 if (!fs->val.lport || fs->mask.lport != 0xffff)
143 if (!fs->val.fport || fs->mask.fport != 0xffff)
146 if (tp->protocol_shift >= 0)
147 ntuple_mask |= (u64)fs->mask.proto << tp->protocol_shift;
148 if (tp->ethertype_shift >= 0)
149 ntuple_mask |= (u64)fs->mask.ethtype << tp->ethertype_shift;
150 if (tp->port_shift >= 0)
151 ntuple_mask |= (u64)fs->mask.iport << tp->port_shift;
152 if (tp->macmatch_shift >= 0)
153 ntuple_mask |= (u64)fs->mask.macidx << tp->macmatch_shift;
154 if (tp->vlan_shift >= 0 && fs->mask.ivlan_vld)
155 ntuple_mask |= (u64)(F_FT_VLAN_VLD | fs->mask.ivlan) <<
157 if (tp->vnic_shift >= 0) {
158 if (fs->mask.ovlan_vld)
159 ntuple_mask |= (u64)(fs->val.ovlan_vld << 16 |
160 fs->mask.ovlan) << tp->vnic_shift;
161 else if (fs->mask.pfvf_vld)
162 ntuple_mask |= (u64)((fs->mask.pfvf_vld << 16) |
163 (fs->mask.pf << 13)) <<
166 if (tp->tos_shift >= 0)
167 ntuple_mask |= (u64)fs->mask.tos << tp->tos_shift;
169 if (ntuple_mask != hash_filter_mask)
172 fs->cap = 1; /* use hash region */
176 ch_rte_parsetype_eth(const void *dmask, const struct rte_flow_item *item,
177 struct ch_filter_specification *fs,
178 struct rte_flow_error *e)
180 const struct rte_flow_item_eth *spec = item->spec;
181 const struct rte_flow_item_eth *umask = item->mask;
182 const struct rte_flow_item_eth *mask;
184 /* If user has not given any mask, then use chelsio supported mask. */
185 mask = umask ? umask : (const struct rte_flow_item_eth *)dmask;
190 /* we don't support SRC_MAC filtering*/
191 if (!rte_is_zero_ether_addr(&mask->src))
192 return rte_flow_error_set(e, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
194 "src mac filtering not supported");
196 if (!rte_is_zero_ether_addr(&mask->dst)) {
197 const u8 *addr = (const u8 *)&spec->dst.addr_bytes[0];
198 const u8 *m = (const u8 *)&mask->dst.addr_bytes[0];
199 struct rte_flow *flow = (struct rte_flow *)fs->private;
200 struct port_info *pi = (struct port_info *)
201 (flow->dev->data->dev_private);
204 idx = cxgbe_mpstcam_alloc(pi, addr, m);
206 return rte_flow_error_set(e, idx,
207 RTE_FLOW_ERROR_TYPE_ITEM,
208 NULL, "unable to allocate mac"
210 CXGBE_FILL_FS(idx, 0x1ff, macidx);
213 CXGBE_FILL_FS(be16_to_cpu(spec->type),
214 be16_to_cpu(mask->type), ethtype);
220 ch_rte_parsetype_port(const void *dmask, const struct rte_flow_item *item,
221 struct ch_filter_specification *fs,
222 struct rte_flow_error *e)
224 const struct rte_flow_item_phy_port *val = item->spec;
225 const struct rte_flow_item_phy_port *umask = item->mask;
226 const struct rte_flow_item_phy_port *mask;
228 mask = umask ? umask : (const struct rte_flow_item_phy_port *)dmask;
231 return 0; /* Wildcard, match all physical ports */
233 if (val->index > 0x7)
234 return rte_flow_error_set(e, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM,
236 "port index upto 0x7 is supported");
238 CXGBE_FILL_FS(val->index, mask->index, iport);
244 ch_rte_parsetype_vlan(const void *dmask, const struct rte_flow_item *item,
245 struct ch_filter_specification *fs,
246 struct rte_flow_error *e)
248 const struct rte_flow_item_vlan *spec = item->spec;
249 const struct rte_flow_item_vlan *umask = item->mask;
250 const struct rte_flow_item_vlan *mask;
252 /* If user has not given any mask, then use chelsio supported mask. */
253 mask = umask ? umask : (const struct rte_flow_item_vlan *)dmask;
255 if (!fs->mask.ethtype)
256 return rte_flow_error_set(e, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM,
258 "Can't parse VLAN item without knowing ethertype");
260 /* If ethertype is already set and is not VLAN (0x8100) or
261 * QINQ(0x88A8), then don't proceed further. Otherwise,
262 * reset the outer ethertype, so that it can be replaced by
263 * innermost ethertype. Note that hardware will automatically
264 * match against VLAN or QINQ packets, based on 'ivlan_vld' or
265 * 'ovlan_vld' bit set in Chelsio filter spec, respectively.
267 if (fs->mask.ethtype) {
268 if (fs->val.ethtype != RTE_ETHER_TYPE_VLAN &&
269 fs->val.ethtype != RTE_ETHER_TYPE_QINQ)
270 return rte_flow_error_set(e, EINVAL,
271 RTE_FLOW_ERROR_TYPE_ITEM,
273 "Ethertype must be 0x8100 or 0x88a8");
276 if (fs->val.ethtype == RTE_ETHER_TYPE_QINQ) {
277 CXGBE_FILL_FS(1, 1, ovlan_vld);
279 CXGBE_FILL_FS(be16_to_cpu(spec->tci),
280 be16_to_cpu(mask->tci), ovlan);
282 fs->mask.ethtype = 0;
285 } else if (fs->val.ethtype == RTE_ETHER_TYPE_VLAN) {
286 CXGBE_FILL_FS(1, 1, ivlan_vld);
288 CXGBE_FILL_FS(be16_to_cpu(spec->tci),
289 be16_to_cpu(mask->tci), ivlan);
291 fs->mask.ethtype = 0;
297 CXGBE_FILL_FS(be16_to_cpu(spec->inner_type),
298 be16_to_cpu(mask->inner_type), ethtype);
304 ch_rte_parsetype_pf(const void *dmask __rte_unused,
305 const struct rte_flow_item *item __rte_unused,
306 struct ch_filter_specification *fs,
307 struct rte_flow_error *e __rte_unused)
309 struct rte_flow *flow = (struct rte_flow *)fs->private;
310 struct rte_eth_dev *dev = flow->dev;
311 struct adapter *adap = ethdev2adap(dev);
313 CXGBE_FILL_FS(1, 1, pfvf_vld);
315 CXGBE_FILL_FS(adap->pf, 0x7, pf);
320 ch_rte_parsetype_udp(const void *dmask, const struct rte_flow_item *item,
321 struct ch_filter_specification *fs,
322 struct rte_flow_error *e)
324 const struct rte_flow_item_udp *val = item->spec;
325 const struct rte_flow_item_udp *umask = item->mask;
326 const struct rte_flow_item_udp *mask;
328 mask = umask ? umask : (const struct rte_flow_item_udp *)dmask;
330 if (mask->hdr.dgram_len || mask->hdr.dgram_cksum)
331 return rte_flow_error_set(e, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
333 "udp: only src/dst port supported");
335 CXGBE_FILL_FS(IPPROTO_UDP, 0xff, proto);
338 CXGBE_FILL_FS(be16_to_cpu(val->hdr.src_port),
339 be16_to_cpu(mask->hdr.src_port), fport);
340 CXGBE_FILL_FS(be16_to_cpu(val->hdr.dst_port),
341 be16_to_cpu(mask->hdr.dst_port), lport);
346 ch_rte_parsetype_tcp(const void *dmask, const struct rte_flow_item *item,
347 struct ch_filter_specification *fs,
348 struct rte_flow_error *e)
350 const struct rte_flow_item_tcp *val = item->spec;
351 const struct rte_flow_item_tcp *umask = item->mask;
352 const struct rte_flow_item_tcp *mask;
354 mask = umask ? umask : (const struct rte_flow_item_tcp *)dmask;
356 if (mask->hdr.sent_seq || mask->hdr.recv_ack || mask->hdr.data_off ||
357 mask->hdr.tcp_flags || mask->hdr.rx_win || mask->hdr.cksum ||
359 return rte_flow_error_set(e, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
361 "tcp: only src/dst port supported");
363 CXGBE_FILL_FS(IPPROTO_TCP, 0xff, proto);
366 CXGBE_FILL_FS(be16_to_cpu(val->hdr.src_port),
367 be16_to_cpu(mask->hdr.src_port), fport);
368 CXGBE_FILL_FS(be16_to_cpu(val->hdr.dst_port),
369 be16_to_cpu(mask->hdr.dst_port), lport);
374 ch_rte_parsetype_ipv4(const void *dmask, const struct rte_flow_item *item,
375 struct ch_filter_specification *fs,
376 struct rte_flow_error *e)
378 const struct rte_flow_item_ipv4 *val = item->spec;
379 const struct rte_flow_item_ipv4 *umask = item->mask;
380 const struct rte_flow_item_ipv4 *mask;
382 mask = umask ? umask : (const struct rte_flow_item_ipv4 *)dmask;
384 if (mask->hdr.time_to_live)
385 return rte_flow_error_set(e, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
386 item, "ttl is not supported");
388 if (fs->mask.ethtype &&
389 (fs->val.ethtype != RTE_ETHER_TYPE_IPV4))
390 return rte_flow_error_set(e, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM,
392 "Couldn't find IPv4 ethertype");
393 fs->type = FILTER_TYPE_IPV4;
395 return 0; /* ipv4 wild card */
397 CXGBE_FILL_FS(val->hdr.next_proto_id, mask->hdr.next_proto_id, proto);
398 CXGBE_FILL_FS_MEMCPY(val->hdr.dst_addr, mask->hdr.dst_addr, lip);
399 CXGBE_FILL_FS_MEMCPY(val->hdr.src_addr, mask->hdr.src_addr, fip);
400 CXGBE_FILL_FS(val->hdr.type_of_service, mask->hdr.type_of_service, tos);
406 ch_rte_parsetype_ipv6(const void *dmask, const struct rte_flow_item *item,
407 struct ch_filter_specification *fs,
408 struct rte_flow_error *e)
410 const struct rte_flow_item_ipv6 *val = item->spec;
411 const struct rte_flow_item_ipv6 *umask = item->mask;
412 const struct rte_flow_item_ipv6 *mask;
413 u32 vtc_flow, vtc_flow_mask;
415 mask = umask ? umask : (const struct rte_flow_item_ipv6 *)dmask;
417 vtc_flow_mask = be32_to_cpu(mask->hdr.vtc_flow);
419 if (vtc_flow_mask & RTE_IPV6_HDR_FL_MASK ||
420 mask->hdr.payload_len || mask->hdr.hop_limits)
421 return rte_flow_error_set(e, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
423 "flow/hop are not supported");
425 if (fs->mask.ethtype &&
426 (fs->val.ethtype != RTE_ETHER_TYPE_IPV6))
427 return rte_flow_error_set(e, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM,
429 "Couldn't find IPv6 ethertype");
430 fs->type = FILTER_TYPE_IPV6;
432 return 0; /* ipv6 wild card */
434 CXGBE_FILL_FS(val->hdr.proto, mask->hdr.proto, proto);
436 vtc_flow = be32_to_cpu(val->hdr.vtc_flow);
437 CXGBE_FILL_FS((vtc_flow & RTE_IPV6_HDR_TC_MASK) >>
438 RTE_IPV6_HDR_TC_SHIFT,
439 (vtc_flow_mask & RTE_IPV6_HDR_TC_MASK) >>
440 RTE_IPV6_HDR_TC_SHIFT,
443 CXGBE_FILL_FS_MEMCPY(val->hdr.dst_addr, mask->hdr.dst_addr, lip);
444 CXGBE_FILL_FS_MEMCPY(val->hdr.src_addr, mask->hdr.src_addr, fip);
450 cxgbe_rtef_parse_attr(struct rte_flow *flow, const struct rte_flow_attr *attr,
451 struct rte_flow_error *e)
454 return rte_flow_error_set(e, ENOTSUP, RTE_FLOW_ERROR_TYPE_ATTR,
455 attr, "attribute:<egress> is"
458 return rte_flow_error_set(e, ENOTSUP, RTE_FLOW_ERROR_TYPE_ATTR,
459 attr, "group parameter is"
462 flow->fidx = attr->priority ? attr->priority - 1 : FILTER_ID_MAX;
467 static inline int check_rxq(struct rte_eth_dev *dev, uint16_t rxq)
469 struct port_info *pi = ethdev2pinfo(dev);
471 if (rxq > pi->n_rx_qsets)
476 static int cxgbe_validate_fidxondel(struct filter_entry *f, unsigned int fidx)
478 struct adapter *adap = ethdev2adap(f->dev);
479 struct ch_filter_specification fs = f->fs;
482 if (fidx >= adap->tids.nftids) {
483 dev_err(adap, "invalid flow index %d.\n", fidx);
487 nentries = cxgbe_filter_slots(adap, fs.type);
488 if (!cxgbe_is_filter_set(&adap->tids, fidx, nentries)) {
489 dev_err(adap, "Already free fidx:%d f:%p\n", fidx, f);
497 cxgbe_validate_fidxonadd(struct ch_filter_specification *fs,
498 struct adapter *adap, unsigned int fidx)
502 nentries = cxgbe_filter_slots(adap, fs->type);
503 if (cxgbe_is_filter_set(&adap->tids, fidx, nentries)) {
504 dev_err(adap, "filter index: %d is busy.\n", fidx);
508 if (fidx >= adap->tids.nftids) {
509 dev_err(adap, "filter index (%u) >= max(%u)\n",
510 fidx, adap->tids.nftids);
518 cxgbe_verify_fidx(struct rte_flow *flow, unsigned int fidx, uint8_t del)
521 return 0; /* Hash filters */
522 return del ? cxgbe_validate_fidxondel(flow->f, fidx) :
523 cxgbe_validate_fidxonadd(&flow->fs,
524 ethdev2adap(flow->dev), fidx);
527 static int cxgbe_get_fidx(struct rte_flow *flow, unsigned int *fidx)
529 struct ch_filter_specification *fs = &flow->fs;
530 struct adapter *adap = ethdev2adap(flow->dev);
532 /* For tcam get the next available slot, if default value specified */
533 if (flow->fidx == FILTER_ID_MAX) {
537 nentries = cxgbe_filter_slots(adap, fs->type);
538 idx = cxgbe_alloc_ftid(adap, nentries);
540 dev_err(adap, "unable to get a filter index in tcam\n");
543 *fidx = (unsigned int)idx;
552 cxgbe_get_flow_item_index(const struct rte_flow_item items[], u32 type)
554 const struct rte_flow_item *i;
555 int j, index = -ENOENT;
557 for (i = items, j = 0; i->type != RTE_FLOW_ITEM_TYPE_END; i++, j++) {
558 if (i->type == type) {
568 ch_rte_parse_nat(uint8_t nmode, struct ch_filter_specification *fs)
571 * BIT_0 = [src_ip], BIT_1 = [dst_ip]
572 * BIT_2 = [src_port], BIT_3 = [dst_port]
574 * Only below cases are supported as per our spec.
578 fs->nat_mode = NAT_MODE_NONE;
581 fs->nat_mode = NAT_MODE_DIP;
584 fs->nat_mode = NAT_MODE_SIP_SP;
587 fs->nat_mode = NAT_MODE_DIP_SIP_SP;
590 fs->nat_mode = NAT_MODE_DIP_DP;
593 fs->nat_mode = NAT_MODE_DIP_DP_SIP;
596 fs->nat_mode = NAT_MODE_DIP_DP_SP;
599 fs->nat_mode = NAT_MODE_ALL;
609 ch_rte_parse_atype_switch(const struct rte_flow_action *a,
610 const struct rte_flow_item items[],
612 struct ch_filter_specification *fs,
613 struct rte_flow_error *e)
615 const struct rte_flow_action_of_set_vlan_vid *vlanid;
616 const struct rte_flow_action_of_set_vlan_pcp *vlanpcp;
617 const struct rte_flow_action_of_push_vlan *pushvlan;
618 const struct rte_flow_action_set_ipv4 *ipv4;
619 const struct rte_flow_action_set_ipv6 *ipv6;
620 const struct rte_flow_action_set_tp *tp_port;
621 const struct rte_flow_action_phy_port *port;
626 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
627 vlanid = (const struct rte_flow_action_of_set_vlan_vid *)
629 /* If explicitly asked to push a new VLAN header,
630 * then don't set rewrite mode. Otherwise, the
631 * incoming VLAN packets will get their VLAN fields
632 * rewritten, instead of adding an additional outer
635 if (fs->newvlan != VLAN_INSERT)
636 fs->newvlan = VLAN_REWRITE;
637 tmp_vlan = fs->vlan & 0xe000;
638 fs->vlan = (be16_to_cpu(vlanid->vlan_vid) & 0xfff) | tmp_vlan;
640 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
641 vlanpcp = (const struct rte_flow_action_of_set_vlan_pcp *)
643 /* If explicitly asked to push a new VLAN header,
644 * then don't set rewrite mode. Otherwise, the
645 * incoming VLAN packets will get their VLAN fields
646 * rewritten, instead of adding an additional outer
649 if (fs->newvlan != VLAN_INSERT)
650 fs->newvlan = VLAN_REWRITE;
651 tmp_vlan = fs->vlan & 0xfff;
652 fs->vlan = (vlanpcp->vlan_pcp << 13) | tmp_vlan;
654 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
655 pushvlan = (const struct rte_flow_action_of_push_vlan *)
657 if (be16_to_cpu(pushvlan->ethertype) != RTE_ETHER_TYPE_VLAN)
658 return rte_flow_error_set(e, EINVAL,
659 RTE_FLOW_ERROR_TYPE_ACTION, a,
660 "only ethertype 0x8100 "
661 "supported for push vlan.");
662 fs->newvlan = VLAN_INSERT;
664 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
665 fs->newvlan = VLAN_REMOVE;
667 case RTE_FLOW_ACTION_TYPE_PHY_PORT:
668 port = (const struct rte_flow_action_phy_port *)a->conf;
669 fs->eport = port->index;
671 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
672 item_index = cxgbe_get_flow_item_index(items,
673 RTE_FLOW_ITEM_TYPE_IPV4);
675 return rte_flow_error_set(e, EINVAL,
676 RTE_FLOW_ERROR_TYPE_ACTION, a,
677 "No RTE_FLOW_ITEM_TYPE_IPV4 "
680 ipv4 = (const struct rte_flow_action_set_ipv4 *)a->conf;
681 memcpy(fs->nat_fip, &ipv4->ipv4_addr, sizeof(ipv4->ipv4_addr));
684 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
685 item_index = cxgbe_get_flow_item_index(items,
686 RTE_FLOW_ITEM_TYPE_IPV4);
688 return rte_flow_error_set(e, EINVAL,
689 RTE_FLOW_ERROR_TYPE_ACTION, a,
690 "No RTE_FLOW_ITEM_TYPE_IPV4 "
693 ipv4 = (const struct rte_flow_action_set_ipv4 *)a->conf;
694 memcpy(fs->nat_lip, &ipv4->ipv4_addr, sizeof(ipv4->ipv4_addr));
697 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
698 item_index = cxgbe_get_flow_item_index(items,
699 RTE_FLOW_ITEM_TYPE_IPV6);
701 return rte_flow_error_set(e, EINVAL,
702 RTE_FLOW_ERROR_TYPE_ACTION, a,
703 "No RTE_FLOW_ITEM_TYPE_IPV6 "
706 ipv6 = (const struct rte_flow_action_set_ipv6 *)a->conf;
707 memcpy(fs->nat_fip, ipv6->ipv6_addr, sizeof(ipv6->ipv6_addr));
710 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
711 item_index = cxgbe_get_flow_item_index(items,
712 RTE_FLOW_ITEM_TYPE_IPV6);
714 return rte_flow_error_set(e, EINVAL,
715 RTE_FLOW_ERROR_TYPE_ACTION, a,
716 "No RTE_FLOW_ITEM_TYPE_IPV6 "
719 ipv6 = (const struct rte_flow_action_set_ipv6 *)a->conf;
720 memcpy(fs->nat_lip, ipv6->ipv6_addr, sizeof(ipv6->ipv6_addr));
723 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
724 item_index = cxgbe_get_flow_item_index(items,
725 RTE_FLOW_ITEM_TYPE_TCP);
726 if (item_index < 0) {
728 cxgbe_get_flow_item_index(items,
729 RTE_FLOW_ITEM_TYPE_UDP);
731 return rte_flow_error_set(e, EINVAL,
732 RTE_FLOW_ERROR_TYPE_ACTION, a,
733 "No RTE_FLOW_ITEM_TYPE_TCP or "
734 "RTE_FLOW_ITEM_TYPE_UDP found");
737 tp_port = (const struct rte_flow_action_set_tp *)a->conf;
738 fs->nat_fport = be16_to_cpu(tp_port->port);
741 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
742 item_index = cxgbe_get_flow_item_index(items,
743 RTE_FLOW_ITEM_TYPE_TCP);
744 if (item_index < 0) {
746 cxgbe_get_flow_item_index(items,
747 RTE_FLOW_ITEM_TYPE_UDP);
749 return rte_flow_error_set(e, EINVAL,
750 RTE_FLOW_ERROR_TYPE_ACTION, a,
751 "No RTE_FLOW_ITEM_TYPE_TCP or "
752 "RTE_FLOW_ITEM_TYPE_UDP found");
755 tp_port = (const struct rte_flow_action_set_tp *)a->conf;
756 fs->nat_lport = be16_to_cpu(tp_port->port);
759 case RTE_FLOW_ACTION_TYPE_MAC_SWAP:
760 item_index = cxgbe_get_flow_item_index(items,
761 RTE_FLOW_ITEM_TYPE_ETH);
763 return rte_flow_error_set(e, EINVAL,
764 RTE_FLOW_ERROR_TYPE_ACTION, a,
765 "No RTE_FLOW_ITEM_TYPE_ETH "
770 /* We are not supposed to come here */
771 return rte_flow_error_set(e, EINVAL,
772 RTE_FLOW_ERROR_TYPE_ACTION, a,
773 "Action not supported");
780 cxgbe_rtef_parse_actions(struct rte_flow *flow,
781 const struct rte_flow_item items[],
782 const struct rte_flow_action action[],
783 struct rte_flow_error *e)
785 struct ch_filter_specification *fs = &flow->fs;
786 uint8_t nmode = 0, nat_ipv4 = 0, nat_ipv6 = 0;
787 uint8_t vlan_set_vid = 0, vlan_set_pcp = 0;
788 const struct rte_flow_action_queue *q;
789 const struct rte_flow_action *a;
793 for (a = action; a->type != RTE_FLOW_ACTION_TYPE_END; a++) {
795 case RTE_FLOW_ACTION_TYPE_VOID:
797 case RTE_FLOW_ACTION_TYPE_DROP:
799 return rte_flow_error_set(e, EINVAL,
800 RTE_FLOW_ERROR_TYPE_ACTION, a,
801 "specify only 1 pass/drop");
802 fs->action = FILTER_DROP;
804 case RTE_FLOW_ACTION_TYPE_QUEUE:
805 q = (const struct rte_flow_action_queue *)a->conf;
807 return rte_flow_error_set(e, EINVAL,
808 RTE_FLOW_ERROR_TYPE_ACTION, q,
809 "specify rx queue index");
810 if (check_rxq(flow->dev, q->index))
811 return rte_flow_error_set(e, EINVAL,
812 RTE_FLOW_ERROR_TYPE_ACTION, q,
815 return rte_flow_error_set(e, EINVAL,
816 RTE_FLOW_ERROR_TYPE_ACTION, a,
817 "specify only 1 pass/drop");
818 fs->action = FILTER_PASS;
822 case RTE_FLOW_ACTION_TYPE_COUNT:
825 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
828 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
831 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
832 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
833 case RTE_FLOW_ACTION_TYPE_PHY_PORT:
834 case RTE_FLOW_ACTION_TYPE_MAC_SWAP:
835 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
836 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
839 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
840 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
843 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
844 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
846 /* We allow multiple switch actions, but switch is
847 * not compatible with either queue or drop
849 if (abit++ && fs->action != FILTER_SWITCH)
850 return rte_flow_error_set(e, EINVAL,
851 RTE_FLOW_ERROR_TYPE_ACTION, a,
852 "overlapping action specified");
853 if (nat_ipv4 && nat_ipv6)
854 return rte_flow_error_set(e, EINVAL,
855 RTE_FLOW_ERROR_TYPE_ACTION, a,
856 "Can't have one address ipv4 and the"
859 ret = ch_rte_parse_atype_switch(a, items, &nmode, fs,
863 fs->action = FILTER_SWITCH;
866 /* Not supported action : return error */
867 return rte_flow_error_set(e, ENOTSUP,
868 RTE_FLOW_ERROR_TYPE_ACTION,
869 a, "Action not supported");
873 if (fs->newvlan == VLAN_REWRITE && (!vlan_set_vid || !vlan_set_pcp))
874 return rte_flow_error_set(e, EINVAL,
875 RTE_FLOW_ERROR_TYPE_ACTION, a,
876 "Both OF_SET_VLAN_VID and "
877 "OF_SET_VLAN_PCP must be specified");
879 if (ch_rte_parse_nat(nmode, fs))
880 return rte_flow_error_set(e, EINVAL,
881 RTE_FLOW_ERROR_TYPE_ACTION, a,
882 "invalid settings for swich action");
886 static struct chrte_fparse parseitem[] = {
887 [RTE_FLOW_ITEM_TYPE_ETH] = {
888 .fptr = ch_rte_parsetype_eth,
889 .dmask = &(const struct rte_flow_item_eth){
890 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
891 .src.addr_bytes = "\x00\x00\x00\x00\x00\x00",
896 [RTE_FLOW_ITEM_TYPE_PHY_PORT] = {
897 .fptr = ch_rte_parsetype_port,
898 .dmask = &(const struct rte_flow_item_phy_port){
903 [RTE_FLOW_ITEM_TYPE_VLAN] = {
904 .fptr = ch_rte_parsetype_vlan,
905 .dmask = &(const struct rte_flow_item_vlan){
907 .inner_type = 0xffff,
911 [RTE_FLOW_ITEM_TYPE_IPV4] = {
912 .fptr = ch_rte_parsetype_ipv4,
913 .dmask = &(const struct rte_flow_item_ipv4) {
915 .src_addr = RTE_BE32(0xffffffff),
916 .dst_addr = RTE_BE32(0xffffffff),
917 .type_of_service = 0xff,
922 [RTE_FLOW_ITEM_TYPE_IPV6] = {
923 .fptr = ch_rte_parsetype_ipv6,
924 .dmask = &(const struct rte_flow_item_ipv6) {
927 "\xff\xff\xff\xff\xff\xff\xff\xff"
928 "\xff\xff\xff\xff\xff\xff\xff\xff",
930 "\xff\xff\xff\xff\xff\xff\xff\xff"
931 "\xff\xff\xff\xff\xff\xff\xff\xff",
932 .vtc_flow = RTE_BE32(0xff000000),
937 [RTE_FLOW_ITEM_TYPE_UDP] = {
938 .fptr = ch_rte_parsetype_udp,
939 .dmask = &rte_flow_item_udp_mask,
942 [RTE_FLOW_ITEM_TYPE_TCP] = {
943 .fptr = ch_rte_parsetype_tcp,
944 .dmask = &rte_flow_item_tcp_mask,
947 [RTE_FLOW_ITEM_TYPE_PF] = {
948 .fptr = ch_rte_parsetype_pf,
954 cxgbe_rtef_parse_items(struct rte_flow *flow,
955 const struct rte_flow_item items[],
956 struct rte_flow_error *e)
958 struct adapter *adap = ethdev2adap(flow->dev);
959 const struct rte_flow_item *i;
960 char repeat[ARRAY_SIZE(parseitem)] = {0};
962 for (i = items; i->type != RTE_FLOW_ITEM_TYPE_END; i++) {
963 struct chrte_fparse *idx;
966 if (i->type >= ARRAY_SIZE(parseitem))
967 return rte_flow_error_set(e, ENOTSUP,
968 RTE_FLOW_ERROR_TYPE_ITEM,
969 i, "Item not supported");
972 case RTE_FLOW_ITEM_TYPE_VOID:
975 /* check if item is repeated */
976 if (repeat[i->type] &&
977 i->type != RTE_FLOW_ITEM_TYPE_VLAN)
978 return rte_flow_error_set(e, ENOTSUP,
979 RTE_FLOW_ERROR_TYPE_ITEM, i,
980 "parse items cannot be repeated(except void/vlan)");
984 /* validate the item */
985 ret = cxgbe_validate_item(i, e);
989 idx = &flow->item_parser[i->type];
990 if (!idx || !idx->fptr) {
991 return rte_flow_error_set(e, ENOTSUP,
992 RTE_FLOW_ERROR_TYPE_ITEM, i,
993 "Item not supported");
995 ret = idx->fptr(idx->dmask, i, &flow->fs, e);
1002 cxgbe_fill_filter_region(adap, &flow->fs);
1003 cxgbe_tweak_filter_spec(adap, &flow->fs);
1009 cxgbe_flow_parse(struct rte_flow *flow,
1010 const struct rte_flow_attr *attr,
1011 const struct rte_flow_item item[],
1012 const struct rte_flow_action action[],
1013 struct rte_flow_error *e)
1016 /* parse user request into ch_filter_specification */
1017 ret = cxgbe_rtef_parse_attr(flow, attr, e);
1020 ret = cxgbe_rtef_parse_items(flow, item, e);
1023 return cxgbe_rtef_parse_actions(flow, item, action, e);
1026 static int __cxgbe_flow_create(struct rte_eth_dev *dev, struct rte_flow *flow)
1028 struct ch_filter_specification *fs = &flow->fs;
1029 struct adapter *adap = ethdev2adap(dev);
1030 struct tid_info *t = &adap->tids;
1031 struct filter_ctx ctx;
1035 if (cxgbe_get_fidx(flow, &fidx))
1037 if (cxgbe_verify_fidx(flow, fidx, 0))
1040 t4_init_completion(&ctx.completion);
1041 /* go create the filter */
1042 err = cxgbe_set_filter(dev, fidx, fs, &ctx);
1044 dev_err(adap, "Error %d while creating filter.\n", err);
1048 /* Poll the FW for reply */
1049 err = cxgbe_poll_for_completion(&adap->sge.fw_evtq,
1051 CXGBE_FLOW_POLL_CNT,
1054 dev_err(adap, "Filter set operation timed out (%d)\n", err);
1058 dev_err(adap, "Hardware error %d while creating the filter.\n",
1063 if (fs->cap) { /* to destroy the filter */
1064 flow->fidx = ctx.tid;
1065 flow->f = lookup_tid(t, ctx.tid);
1068 flow->f = &adap->tids.ftid_tab[fidx];
1074 static struct rte_flow *
1075 cxgbe_flow_create(struct rte_eth_dev *dev,
1076 const struct rte_flow_attr *attr,
1077 const struct rte_flow_item item[],
1078 const struct rte_flow_action action[],
1079 struct rte_flow_error *e)
1081 struct adapter *adap = ethdev2adap(dev);
1082 struct rte_flow *flow;
1085 flow = t4_os_alloc(sizeof(struct rte_flow));
1087 rte_flow_error_set(e, ENOMEM, RTE_FLOW_ERROR_TYPE_HANDLE,
1088 NULL, "Unable to allocate memory for"
1093 flow->item_parser = parseitem;
1095 flow->fs.private = (void *)flow;
1097 if (cxgbe_flow_parse(flow, attr, item, action, e)) {
1102 t4_os_lock(&adap->flow_lock);
1103 /* go, interact with cxgbe_filter */
1104 ret = __cxgbe_flow_create(dev, flow);
1105 t4_os_unlock(&adap->flow_lock);
1107 rte_flow_error_set(e, ret, RTE_FLOW_ERROR_TYPE_HANDLE,
1108 NULL, "Unable to create flow rule");
1113 flow->f->private = flow; /* Will be used during flush */
1118 static int __cxgbe_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
1120 struct adapter *adap = ethdev2adap(dev);
1121 struct filter_entry *f = flow->f;
1122 struct ch_filter_specification *fs;
1123 struct filter_ctx ctx;
1127 if (cxgbe_verify_fidx(flow, flow->fidx, 1))
1130 t4_init_completion(&ctx.completion);
1131 err = cxgbe_del_filter(dev, flow->fidx, fs, &ctx);
1133 dev_err(adap, "Error %d while deleting filter.\n", err);
1137 /* Poll the FW for reply */
1138 err = cxgbe_poll_for_completion(&adap->sge.fw_evtq,
1140 CXGBE_FLOW_POLL_CNT,
1143 dev_err(adap, "Filter delete operation timed out (%d)\n", err);
1147 dev_err(adap, "Hardware error %d while deleting the filter.\n",
1153 if (fs->mask.macidx) {
1154 struct port_info *pi = (struct port_info *)
1155 (dev->data->dev_private);
1158 ret = cxgbe_mpstcam_remove(pi, fs->val.macidx);
1167 cxgbe_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
1168 struct rte_flow_error *e)
1170 struct adapter *adap = ethdev2adap(dev);
1173 t4_os_lock(&adap->flow_lock);
1174 ret = __cxgbe_flow_destroy(dev, flow);
1175 t4_os_unlock(&adap->flow_lock);
1177 return rte_flow_error_set(e, ret, RTE_FLOW_ERROR_TYPE_HANDLE,
1178 flow, "error destroying filter.");
1183 static int __cxgbe_flow_query(struct rte_flow *flow, u64 *count,
1186 struct adapter *adap = ethdev2adap(flow->dev);
1187 struct ch_filter_specification fs = flow->f->fs;
1188 unsigned int fidx = flow->fidx;
1191 ret = cxgbe_get_filter_count(adap, fidx, count, fs.cap, 0);
1194 return cxgbe_get_filter_count(adap, fidx, byte_count, fs.cap, 1);
1198 cxgbe_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
1199 const struct rte_flow_action *action, void *data,
1200 struct rte_flow_error *e)
1202 struct adapter *adap = ethdev2adap(flow->dev);
1203 struct ch_filter_specification fs;
1204 struct rte_flow_query_count *c;
1205 struct filter_entry *f;
1213 if (action->type != RTE_FLOW_ACTION_TYPE_COUNT)
1214 return rte_flow_error_set(e, ENOTSUP,
1215 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1216 "only count supported for query");
1219 * This is a valid operation, Since we are allowed to do chelsio
1220 * specific operations in rte side of our code but not vise-versa
1222 * So, fs can be queried/modified here BUT rte_flow_query_count
1223 * cannot be worked on by the lower layer since we want to maintain
1224 * it as rte_flow agnostic.
1227 return rte_flow_error_set(e, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
1228 &fs, "filter hit counters were not"
1229 " enabled during filter creation");
1231 c = (struct rte_flow_query_count *)data;
1233 t4_os_lock(&adap->flow_lock);
1234 ret = __cxgbe_flow_query(flow, &c->hits, &c->bytes);
1236 rte_flow_error_set(e, -ret, RTE_FLOW_ERROR_TYPE_ACTION,
1237 f, "cxgbe pmd failed to perform query");
1241 /* Query was successful */
1245 cxgbe_clear_filter_count(adap, flow->fidx, f->fs.cap, true);
1248 t4_os_unlock(&adap->flow_lock);
1253 cxgbe_flow_validate(struct rte_eth_dev *dev,
1254 const struct rte_flow_attr *attr,
1255 const struct rte_flow_item item[],
1256 const struct rte_flow_action action[],
1257 struct rte_flow_error *e)
1259 struct adapter *adap = ethdev2adap(dev);
1260 struct rte_flow *flow;
1264 flow = t4_os_alloc(sizeof(struct rte_flow));
1266 return rte_flow_error_set(e, ENOMEM, RTE_FLOW_ERROR_TYPE_HANDLE,
1268 "Unable to allocate memory for filter_entry");
1270 flow->item_parser = parseitem;
1273 ret = cxgbe_flow_parse(flow, attr, item, action, e);
1279 if (cxgbe_validate_filter(adap, &flow->fs)) {
1281 return rte_flow_error_set(e, EINVAL, RTE_FLOW_ERROR_TYPE_HANDLE,
1283 "validation failed. Check f/w config file.");
1286 t4_os_lock(&adap->flow_lock);
1287 if (cxgbe_get_fidx(flow, &fidx)) {
1288 ret = rte_flow_error_set(e, ENOMEM, RTE_FLOW_ERROR_TYPE_HANDLE,
1289 NULL, "no memory in tcam.");
1293 if (cxgbe_verify_fidx(flow, fidx, 0)) {
1294 ret = rte_flow_error_set(e, EINVAL, RTE_FLOW_ERROR_TYPE_HANDLE,
1295 NULL, "validation failed");
1300 t4_os_unlock(&adap->flow_lock);
1306 * @ret : > 0 filter destroyed succsesfully
1307 * < 0 error destroying filter
1308 * == 1 filter not active / not found
1311 cxgbe_check_n_destroy(struct filter_entry *f, struct rte_eth_dev *dev)
1313 if (f && (f->valid || f->pending) &&
1314 f->dev == dev && /* Only if user has asked for this port */
1315 f->private) /* We (rte_flow) created this filter */
1316 return __cxgbe_flow_destroy(dev, (struct rte_flow *)f->private);
1320 static int cxgbe_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *e)
1322 struct adapter *adap = ethdev2adap(dev);
1326 t4_os_lock(&adap->flow_lock);
1327 if (adap->tids.ftid_tab) {
1328 struct filter_entry *f = &adap->tids.ftid_tab[0];
1330 for (i = 0; i < adap->tids.nftids; i++, f++) {
1331 ret = cxgbe_check_n_destroy(f, dev);
1333 rte_flow_error_set(e, ret,
1334 RTE_FLOW_ERROR_TYPE_HANDLE,
1336 "error destroying TCAM "
1343 if (is_hashfilter(adap) && adap->tids.tid_tab) {
1344 struct filter_entry *f;
1346 for (i = adap->tids.hash_base; i <= adap->tids.ntids; i++) {
1347 f = (struct filter_entry *)adap->tids.tid_tab[i];
1349 ret = cxgbe_check_n_destroy(f, dev);
1351 rte_flow_error_set(e, ret,
1352 RTE_FLOW_ERROR_TYPE_HANDLE,
1354 "error destroying HASH "
1362 t4_os_unlock(&adap->flow_lock);
1363 return ret >= 0 ? 0 : ret;
1366 static const struct rte_flow_ops cxgbe_flow_ops = {
1367 .validate = cxgbe_flow_validate,
1368 .create = cxgbe_flow_create,
1369 .destroy = cxgbe_flow_destroy,
1370 .flush = cxgbe_flow_flush,
1371 .query = cxgbe_flow_query,
1376 cxgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
1377 enum rte_filter_type filter_type,
1378 enum rte_filter_op filter_op,
1384 switch (filter_type) {
1385 case RTE_ETH_FILTER_GENERIC:
1386 if (filter_op != RTE_ETH_FILTER_GET)
1388 *(const void **)arg = &cxgbe_flow_ops;