drivers/net/cxgbe/cxgbe_main.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Chelsio Communications.
   3  * All rights reserved.
   4  */
   5
   6 #include <sys/queue.h>
   7 #include <stdio.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <string.h>
  11 #include <unistd.h>
  12 #include <stdarg.h>
  13 #include <inttypes.h>
  14 #include <netinet/in.h>
  15
  16 #include <rte_byteorder.h>
  17 #include <rte_common.h>
  18 #include <rte_cycles.h>
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_atomic.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_tailq.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <rte_ethdev_driver.h>
  31 #include <rte_ethdev_pci.h>
  32 #include <rte_random.h>
  33 #include <rte_dev.h>
  34 #include <rte_kvargs.h>
  35
  36 #include "base/common.h"
  37 #include "base/t4_regs.h"
  38 #include "base/t4_msg.h"
  39 #include "cxgbe.h"
  40 #include "cxgbe_pfvf.h"
  41 #include "clip_tbl.h"
  42 #include "l2t.h"
  43 #include "smt.h"
  44 #include "mps_tcam.h"
  45
  46 /**
  47  * Allocate a chunk of memory. The allocated memory is cleared.
  48  */
  49 void *t4_alloc_mem(size_t size)
  50 {
  51         return rte_zmalloc(NULL, size, 0);
  52 }
  53
  54 /**
  55  * Free memory allocated through t4_alloc_mem().
  56  */
  57 void t4_free_mem(void *addr)
  58 {
  59         rte_free(addr);
  60 }
  61
  62 /*
  63  * Response queue handler for the FW event queue.
  64  */
  65 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
  66                           __rte_unused const struct pkt_gl *gl)
  67 {
  68         u8 opcode = ((const struct rss_header *)rsp)->opcode;
  69
  70         rsp++;                                          /* skip RSS header */
  71
  72         /*
  73          * FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
  74          */
  75         if (unlikely(opcode == CPL_FW4_MSG &&
  76                      ((const struct cpl_fw4_msg *)rsp)->type ==
  77                       FW_TYPE_RSSCPL)) {
  78                 rsp++;
  79                 opcode = ((const struct rss_header *)rsp)->opcode;
  80                 rsp++;
  81                 if (opcode != CPL_SGE_EGR_UPDATE) {
  82                         dev_err(q->adapter, "unexpected FW4/CPL %#x on FW event queue\n",
  83                                 opcode);
  84                         goto out;
  85                 }
  86         }
  87
  88         if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
  89                 /* do nothing */
  90         } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
  91                 const struct cpl_fw6_msg *msg = (const void *)rsp;
  92
  93                 t4_handle_fw_rpl(q->adapter, msg->data);
  94         } else if (opcode == CPL_ABORT_RPL_RSS) {
  95                 const struct cpl_abort_rpl_rss *p = (const void *)rsp;
  96
  97                 cxgbe_hash_del_filter_rpl(q->adapter, p);
  98         } else if (opcode == CPL_SET_TCB_RPL) {
  99                 const struct cpl_set_tcb_rpl *p = (const void *)rsp;
 100
 101                 cxgbe_filter_rpl(q->adapter, p);
 102         } else if (opcode == CPL_ACT_OPEN_RPL) {
 103                 const struct cpl_act_open_rpl *p = (const void *)rsp;
 104
 105                 cxgbe_hash_filter_rpl(q->adapter, p);
 106         } else if (opcode == CPL_L2T_WRITE_RPL) {
 107                 const struct cpl_l2t_write_rpl *p = (const void *)rsp;
 108
 109                 cxgbe_do_l2t_write_rpl(q->adapter, p);
 110         } else if (opcode == CPL_SMT_WRITE_RPL) {
 111                 const struct cpl_smt_write_rpl *p = (const void *)rsp;
 112
 113                 cxgbe_do_smt_write_rpl(q->adapter, p);
 114         } else {
 115                 dev_err(adapter, "unexpected CPL %#x on FW event queue\n",
 116                         opcode);
 117         }
 118 out:
 119         return 0;
 120 }
 121
 122 /**
 123  * Setup sge control queues to pass control information.
 124  */
 125 int cxgbe_setup_sge_ctrl_txq(struct adapter *adapter)
 126 {
 127         struct sge *s = &adapter->sge;
 128         int err = 0, i = 0;
 129
 130         for_each_port(adapter, i) {
 131                 struct port_info *pi = adap2pinfo(adapter, i);
 132                 char name[RTE_ETH_NAME_MAX_LEN];
 133                 struct sge_ctrl_txq *q = &s->ctrlq[i];
 134
 135                 q->q.size = 1024;
 136                 err = t4_sge_alloc_ctrl_txq(adapter, q,
 137                                             adapter->eth_dev,  i,
 138                                             s->fw_evtq.cntxt_id,
 139                                             rte_socket_id());
 140                 if (err) {
 141                         dev_err(adapter, "Failed to alloc ctrl txq. Err: %d",
 142                                 err);
 143                         goto out;
 144                 }
 145                 snprintf(name, sizeof(name), "%s_ctrl_pool_%d",
 146                          pi->eth_dev->device->driver->name,
 147                          pi->eth_dev->data->port_id);
 148                 q->mb_pool = rte_pktmbuf_pool_create(name, s->ctrlq[i].q.size,
 149                                                      RTE_CACHE_LINE_SIZE,
 150                                                      RTE_MBUF_PRIV_ALIGN,
 151                                                      RTE_MBUF_DEFAULT_BUF_SIZE,
 152                                                      SOCKET_ID_ANY);
 153                 if (!q->mb_pool) {
 154                         err = -rte_errno;
 155                         dev_err(adapter,
 156                                 "Can't create ctrl pool for port %d. Err: %d\n",
 157                                 pi->eth_dev->data->port_id, err);
 158                         goto out;
 159                 }
 160         }
 161         return 0;
 162 out:
 163         t4_free_sge_resources(adapter);
 164         return err;
 165 }
 166
 167 /**
 168  * cxgbe_poll_for_completion: Poll rxq for completion
 169  * @q: rxq to poll
 170  * @ms: milliseconds to delay
 171  * @cnt: number of times to poll
 172  * @c: completion to check for 'done' status
 173  *
 174  * Polls the rxq for reples until completion is done or the count
 175  * expires.
 176  */
 177 int cxgbe_poll_for_completion(struct sge_rspq *q, unsigned int ms,
 178                               unsigned int cnt, struct t4_completion *c)
 179 {
 180         unsigned int i;
 181         unsigned int work_done, budget = 32;
 182
 183         if (!c)
 184                 return -EINVAL;
 185
 186         for (i = 0; i < cnt; i++) {
 187                 cxgbe_poll(q, NULL, budget, &work_done);
 188                 t4_os_lock(&c->lock);
 189                 if (c->done) {
 190                         t4_os_unlock(&c->lock);
 191                         return 0;
 192                 }
 193                 t4_os_unlock(&c->lock);
 194                 rte_delay_ms(ms);
 195         }
 196         return -ETIMEDOUT;
 197 }
 198
 199 int cxgbe_setup_sge_fwevtq(struct adapter *adapter)
 200 {
 201         struct sge *s = &adapter->sge;
 202         int err = 0;
 203         int msi_idx = 0;
 204
 205         err = t4_sge_alloc_rxq(adapter, &s->fw_evtq, true, adapter->eth_dev,
 206                                msi_idx, NULL, fwevtq_handler, -1, NULL, 0,
 207                                rte_socket_id());
 208         return err;
 209 }
 210
 211 static int closest_timer(const struct sge *s, int time)
 212 {
 213         unsigned int i, match = 0;
 214         int delta, min_delta = INT_MAX;
 215
 216         for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
 217                 delta = time - s->timer_val[i];
 218                 if (delta < 0)
 219                         delta = -delta;
 220                 if (delta < min_delta) {
 221                         min_delta = delta;
 222                         match = i;
 223                 }
 224         }
 225         return match;
 226 }
 227
 228 static int closest_thres(const struct sge *s, int thres)
 229 {
 230         unsigned int i, match = 0;
 231         int delta, min_delta = INT_MAX;
 232
 233         for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
 234                 delta = thres - s->counter_val[i];
 235                 if (delta < 0)
 236                         delta = -delta;
 237                 if (delta < min_delta) {
 238                         min_delta = delta;
 239                         match = i;
 240                 }
 241         }
 242         return match;
 243 }
 244
 245 /**
 246  * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
 247  * @q: the Rx queue
 248  * @us: the hold-off time in us, or 0 to disable timer
 249  * @cnt: the hold-off packet count, or 0 to disable counter
 250  *
 251  * Sets an Rx queue's interrupt hold-off time and packet count.  At least
 252  * one of the two needs to be enabled for the queue to generate interrupts.
 253  */
 254 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
 255                                unsigned int cnt)
 256 {
 257         struct adapter *adap = q->adapter;
 258         unsigned int timer_val;
 259
 260         if (cnt) {
 261                 int err;
 262                 u32 v, new_idx;
 263
 264                 new_idx = closest_thres(&adap->sge, cnt);
 265                 if (q->desc && q->pktcnt_idx != new_idx) {
 266                         /* the queue has already been created, update it */
 267                         v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
 268                             V_FW_PARAMS_PARAM_X(
 269                             FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
 270                             V_FW_PARAMS_PARAM_YZ(q->cntxt_id);
 271                         err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
 272                                             &v, &new_idx);
 273                         if (err)
 274                                 return err;
 275                 }
 276                 q->pktcnt_idx = new_idx;
 277         }
 278
 279         timer_val = (us == 0) ? X_TIMERREG_RESTART_COUNTER :
 280                                 closest_timer(&adap->sge, us);
 281
 282         if ((us | cnt) == 0)
 283                 q->intr_params = V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX);
 284         else
 285                 q->intr_params = V_QINTR_TIMER_IDX(timer_val) |
 286                                  V_QINTR_CNT_EN(cnt > 0);
 287         return 0;
 288 }
 289
 290 /**
 291  * Allocate an active-open TID and set it to the supplied value.
 292  */
 293 int cxgbe_alloc_atid(struct tid_info *t, void *data)
 294 {
 295         int atid = -1;
 296
 297         t4_os_lock(&t->atid_lock);
 298         if (t->afree) {
 299                 union aopen_entry *p = t->afree;
 300
 301                 atid = p - t->atid_tab;
 302                 t->afree = p->next;
 303                 p->data = data;
 304                 t->atids_in_use++;
 305         }
 306         t4_os_unlock(&t->atid_lock);
 307         return atid;
 308 }
 309
 310 /**
 311  * Release an active-open TID.
 312  */
 313 void cxgbe_free_atid(struct tid_info *t, unsigned int atid)
 314 {
 315         union aopen_entry *p = &t->atid_tab[atid];
 316
 317         t4_os_lock(&t->atid_lock);
 318         p->next = t->afree;
 319         t->afree = p;
 320         t->atids_in_use--;
 321         t4_os_unlock(&t->atid_lock);
 322 }
 323
 324 /**
 325  * Populate a TID_RELEASE WR.  Caller must properly size the skb.
 326  */
 327 static void mk_tid_release(struct rte_mbuf *mbuf, unsigned int tid)
 328 {
 329         struct cpl_tid_release *req;
 330
 331         req = rte_pktmbuf_mtod(mbuf, struct cpl_tid_release *);
 332         INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid);
 333 }
 334
 335 /**
 336  * Release a TID and inform HW.  If we are unable to allocate the release
 337  * message we defer to a work queue.
 338  */
 339 void cxgbe_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid,
 340                       unsigned short family)
 341 {
 342         struct rte_mbuf *mbuf;
 343         struct adapter *adap = container_of(t, struct adapter, tids);
 344
 345         WARN_ON(tid >= t->ntids);
 346
 347         if (t->tid_tab[tid]) {
 348                 t->tid_tab[tid] = NULL;
 349                 rte_atomic32_dec(&t->conns_in_use);
 350                 if (t->hash_base && tid >= t->hash_base) {
 351                         if (family == FILTER_TYPE_IPV4)
 352                                 rte_atomic32_dec(&t->hash_tids_in_use);
 353                 } else {
 354                         if (family == FILTER_TYPE_IPV4)
 355                                 rte_atomic32_dec(&t->tids_in_use);
 356                 }
 357         }
 358
 359         mbuf = rte_pktmbuf_alloc((&adap->sge.ctrlq[chan])->mb_pool);
 360         if (mbuf) {
 361                 mbuf->data_len = sizeof(struct cpl_tid_release);
 362                 mbuf->pkt_len = mbuf->data_len;
 363                 mk_tid_release(mbuf, tid);
 364                 t4_mgmt_tx(&adap->sge.ctrlq[chan], mbuf);
 365         }
 366 }
 367
 368 /**
 369  * Insert a TID.
 370  */
 371 void cxgbe_insert_tid(struct tid_info *t, void *data, unsigned int tid,
 372                       unsigned short family)
 373 {
 374         t->tid_tab[tid] = data;
 375         if (t->hash_base && tid >= t->hash_base) {
 376                 if (family == FILTER_TYPE_IPV4)
 377                         rte_atomic32_inc(&t->hash_tids_in_use);
 378         } else {
 379                 if (family == FILTER_TYPE_IPV4)
 380                         rte_atomic32_inc(&t->tids_in_use);
 381         }
 382
 383         rte_atomic32_inc(&t->conns_in_use);
 384 }
 385
 386 /**
 387  * Free TID tables.
 388  */
 389 static void tid_free(struct tid_info *t)
 390 {
 391         if (t->tid_tab) {
 392                 if (t->ftid_bmap)
 393                         rte_bitmap_free(t->ftid_bmap);
 394
 395                 if (t->ftid_bmap_array)
 396                         t4_os_free(t->ftid_bmap_array);
 397
 398                 t4_os_free(t->tid_tab);
 399         }
 400
 401         memset(t, 0, sizeof(struct tid_info));
 402 }
 403
 404 /**
 405  * Allocate and initialize the TID tables.  Returns 0 on success.
 406  */
 407 static int tid_init(struct tid_info *t)
 408 {
 409         size_t size;
 410         unsigned int ftid_bmap_size;
 411         unsigned int natids = t->natids;
 412         unsigned int max_ftids = t->nftids;
 413
 414         ftid_bmap_size = rte_bitmap_get_memory_footprint(t->nftids);
 415         size = t->ntids * sizeof(*t->tid_tab) +
 416                 max_ftids * sizeof(*t->ftid_tab) +
 417                 natids * sizeof(*t->atid_tab);
 418
 419         t->tid_tab = t4_os_alloc(size);
 420         if (!t->tid_tab)
 421                 return -ENOMEM;
 422
 423         t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
 424         t->ftid_tab = (struct filter_entry *)&t->atid_tab[t->natids];
 425         t->ftid_bmap_array = t4_os_alloc(ftid_bmap_size);
 426         if (!t->ftid_bmap_array) {
 427                 tid_free(t);
 428                 return -ENOMEM;
 429         }
 430
 431         t4_os_lock_init(&t->atid_lock);
 432         t4_os_lock_init(&t->ftid_lock);
 433
 434         t->afree = NULL;
 435         t->atids_in_use = 0;
 436         rte_atomic32_init(&t->tids_in_use);
 437         rte_atomic32_set(&t->tids_in_use, 0);
 438         rte_atomic32_init(&t->conns_in_use);
 439         rte_atomic32_set(&t->conns_in_use, 0);
 440
 441         /* Setup the free list for atid_tab and clear the stid bitmap. */
 442         if (natids) {
 443                 while (--natids)
 444                         t->atid_tab[natids - 1].next = &t->atid_tab[natids];
 445                 t->afree = t->atid_tab;
 446         }
 447
 448         t->ftid_bmap = rte_bitmap_init(t->nftids, t->ftid_bmap_array,
 449                                        ftid_bmap_size);
 450         if (!t->ftid_bmap) {
 451                 tid_free(t);
 452                 return -ENOMEM;
 453         }
 454
 455         return 0;
 456 }
 457
 458 static inline bool is_x_1g_port(const struct link_config *lc)
 459 {
 460         return (lc->pcaps & FW_PORT_CAP32_SPEED_1G) != 0;
 461 }
 462
 463 static inline bool is_x_10g_port(const struct link_config *lc)
 464 {
 465         unsigned int speeds, high_speeds;
 466
 467         speeds = V_FW_PORT_CAP32_SPEED(G_FW_PORT_CAP32_SPEED(lc->pcaps));
 468         high_speeds = speeds &
 469                       ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G);
 470
 471         return high_speeds != 0;
 472 }
 473
 474 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
 475                       unsigned int us, unsigned int cnt,
 476                       unsigned int size, unsigned int iqe_size)
 477 {
 478         q->adapter = adap;
 479         cxgb4_set_rspq_intr_params(q, us, cnt);
 480         q->iqe_len = iqe_size;
 481         q->size = size;
 482 }
 483
 484 int cxgbe_cfg_queue_count(struct rte_eth_dev *eth_dev)
 485 {
 486         struct port_info *pi = eth_dev->data->dev_private;
 487         struct adapter *adap = pi->adapter;
 488         struct sge *s = &adap->sge;
 489         unsigned int max_queues = s->max_ethqsets / adap->params.nports;
 490
 491         if ((eth_dev->data->nb_rx_queues < 1) ||
 492             (eth_dev->data->nb_tx_queues < 1))
 493                 return -EINVAL;
 494
 495         if ((eth_dev->data->nb_rx_queues > max_queues) ||
 496             (eth_dev->data->nb_tx_queues > max_queues))
 497                 return -EINVAL;
 498
 499         if (eth_dev->data->nb_rx_queues > pi->rss_size)
 500                 return -EINVAL;
 501
 502         /* We must configure RSS, since config has changed*/
 503         pi->flags &= ~PORT_RSS_DONE;
 504
 505         pi->n_rx_qsets = eth_dev->data->nb_rx_queues;
 506         pi->n_tx_qsets = eth_dev->data->nb_tx_queues;
 507
 508         return 0;
 509 }
 510
 511 void cxgbe_cfg_queues(struct rte_eth_dev *eth_dev)
 512 {
 513         struct port_info *pi = eth_dev->data->dev_private;
 514         struct adapter *adap = pi->adapter;
 515         struct sge *s = &adap->sge;
 516         unsigned int i, nb_ports = 0, qidx = 0;
 517         unsigned int q_per_port = 0;
 518
 519         if (!(adap->flags & CFG_QUEUES)) {
 520                 for_each_port(adap, i) {
 521                         struct port_info *tpi = adap2pinfo(adap, i);
 522
 523                         nb_ports += (is_x_10g_port(&tpi->link_cfg)) ||
 524                                      is_x_1g_port(&tpi->link_cfg) ? 1 : 0;
 525                 }
 526
 527                 /*
 528                  * We default up to # of cores queues per 1G/10G port.
 529                  */
 530                 if (nb_ports)
 531                         q_per_port = (s->max_ethqsets -
 532                                      (adap->params.nports - nb_ports)) /
 533                                      nb_ports;
 534
 535                 if (q_per_port > rte_lcore_count())
 536                         q_per_port = rte_lcore_count();
 537
 538                 for_each_port(adap, i) {
 539                         struct port_info *pi = adap2pinfo(adap, i);
 540
 541                         pi->first_qset = qidx;
 542
 543                         /* Initially n_rx_qsets == n_tx_qsets */
 544                         pi->n_rx_qsets = (is_x_10g_port(&pi->link_cfg) ||
 545                                           is_x_1g_port(&pi->link_cfg)) ?
 546                                           q_per_port : 1;
 547                         pi->n_tx_qsets = pi->n_rx_qsets;
 548
 549                         if (pi->n_rx_qsets > pi->rss_size)
 550                                 pi->n_rx_qsets = pi->rss_size;
 551
 552                         qidx += pi->n_rx_qsets;
 553                 }
 554
 555                 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
 556                         struct sge_eth_rxq *r = &s->ethrxq[i];
 557
 558                         init_rspq(adap, &r->rspq, 5, 32, 1024, 64);
 559                         r->usembufs = 1;
 560                         r->fl.size = (r->usembufs ? 1024 : 72);
 561                 }
 562
 563                 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
 564                         s->ethtxq[i].q.size = 1024;
 565
 566                 init_rspq(adap, &adap->sge.fw_evtq, 0, 0, 1024, 64);
 567                 adap->flags |= CFG_QUEUES;
 568         }
 569 }
 570
 571 void cxgbe_stats_get(struct port_info *pi, struct port_stats *stats)
 572 {
 573         t4_get_port_stats_offset(pi->adapter, pi->tx_chan, stats,
 574                                  &pi->stats_base);
 575 }
 576
 577 void cxgbe_stats_reset(struct port_info *pi)
 578 {
 579         t4_clr_port_stats(pi->adapter, pi->tx_chan);
 580 }
 581
 582 static void setup_memwin(struct adapter *adap)
 583 {
 584         u32 mem_win0_base;
 585
 586         /* For T5, only relative offset inside the PCIe BAR is passed */
 587         mem_win0_base = MEMWIN0_BASE;
 588
 589         /*
 590          * Set up memory window for accessing adapter memory ranges.  (Read
 591          * back MA register to ensure that changes propagate before we attempt
 592          * to use the new values.)
 593          */
 594         t4_write_reg(adap,
 595                      PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
 596                                          MEMWIN_NIC),
 597                      mem_win0_base | V_BIR(0) |
 598                      V_WINDOW(ilog2(MEMWIN0_APERTURE) - X_WINDOW_SHIFT));
 599         t4_read_reg(adap,
 600                     PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
 601                                         MEMWIN_NIC));
 602 }
 603
 604 int cxgbe_init_rss(struct adapter *adap)
 605 {
 606         unsigned int i;
 607
 608         if (is_pf4(adap)) {
 609                 int err;
 610
 611                 err = t4_init_rss_mode(adap, adap->mbox);
 612                 if (err)
 613                         return err;
 614         }
 615
 616         for_each_port(adap, i) {
 617                 struct port_info *pi = adap2pinfo(adap, i);
 618
 619                 pi->rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
 620                 if (!pi->rss)
 621                         return -ENOMEM;
 622
 623                 pi->rss_hf = CXGBE_RSS_HF_ALL;
 624         }
 625         return 0;
 626 }
 627
 628 /**
 629  * Dump basic information about the adapter.
 630  */
 631 void cxgbe_print_adapter_info(struct adapter *adap)
 632 {
 633         /**
 634          * Hardware/Firmware/etc. Version/Revision IDs.
 635          */
 636         t4_dump_version_info(adap);
 637 }
 638
 639 void cxgbe_print_port_info(struct adapter *adap)
 640 {
 641         int i;
 642         char buf[80];
 643         struct rte_pci_addr *loc = &adap->pdev->addr;
 644
 645         for_each_port(adap, i) {
 646                 const struct port_info *pi = adap2pinfo(adap, i);
 647                 char *bufp = buf;
 648
 649                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M)
 650                         bufp += sprintf(bufp, "100M/");
 651                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G)
 652                         bufp += sprintf(bufp, "1G/");
 653                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G)
 654                         bufp += sprintf(bufp, "10G/");
 655                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G)
 656                         bufp += sprintf(bufp, "25G/");
 657                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G)
 658                         bufp += sprintf(bufp, "40G/");
 659                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G)
 660                         bufp += sprintf(bufp, "50G/");
 661                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G)
 662                         bufp += sprintf(bufp, "100G/");
 663                 if (bufp != buf)
 664                         --bufp;
 665                 sprintf(bufp, "BASE-%s",
 666                         t4_get_port_type_description(
 667                                         (enum fw_port_type)pi->port_type));
 668
 669                 dev_info(adap,
 670                          " " PCI_PRI_FMT " Chelsio rev %d %s %s\n",
 671                          loc->domain, loc->bus, loc->devid, loc->function,
 672                          CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
 673                          (adap->flags & USING_MSIX) ? " MSI-X" :
 674                          (adap->flags & USING_MSI) ? " MSI" : "");
 675         }
 676 }
 677
 678 static int check_devargs_handler(const char *key, const char *value, void *p)
 679 {
 680         if (!strncmp(key, CXGBE_DEVARG_CMN_KEEP_OVLAN, strlen(key)) ||
 681             !strncmp(key, CXGBE_DEVARG_CMN_TX_MODE_LATENCY, strlen(key)) ||
 682             !strncmp(key, CXGBE_DEVARG_VF_FORCE_LINK_UP, strlen(key))) {
 683                 if (!strncmp(value, "1", 1)) {
 684                         bool *dst_val = (bool *)p;
 685
 686                         *dst_val = true;
 687                 }
 688         }
 689
 690         return 0;
 691 }
 692
 693 static int cxgbe_get_devargs(struct rte_devargs *devargs, const char *key,
 694                              void *p)
 695 {
 696         struct rte_kvargs *kvlist;
 697         int ret = 0;
 698
 699         if (!devargs)
 700                 return 0;
 701
 702         kvlist = rte_kvargs_parse(devargs->args, NULL);
 703         if (!kvlist)
 704                 return 0;
 705
 706         if (!rte_kvargs_count(kvlist, key))
 707                 goto out;
 708
 709         ret = rte_kvargs_process(kvlist, key, check_devargs_handler, p);
 710
 711 out:
 712         rte_kvargs_free(kvlist);
 713
 714         return ret;
 715 }
 716
 717 static void cxgbe_get_devargs_int(struct adapter *adap, bool *dst,
 718                                   const char *key, bool default_value)
 719 {
 720         struct rte_pci_device *pdev = adap->pdev;
 721         int ret;
 722         bool devarg_value = default_value;
 723
 724         *dst = default_value;
 725         if (!pdev)
 726                 return;
 727
 728         ret = cxgbe_get_devargs(pdev->device.devargs, key, &devarg_value);
 729         if (ret)
 730                 return;
 731
 732         *dst = devarg_value;
 733 }
 734
 735 void cxgbe_process_devargs(struct adapter *adap)
 736 {
 737         cxgbe_get_devargs_int(adap, &adap->devargs.keep_ovlan,
 738                               CXGBE_DEVARG_CMN_KEEP_OVLAN, false);
 739         cxgbe_get_devargs_int(adap, &adap->devargs.tx_mode_latency,
 740                               CXGBE_DEVARG_CMN_TX_MODE_LATENCY, false);
 741         cxgbe_get_devargs_int(adap, &adap->devargs.force_link_up,
 742                               CXGBE_DEVARG_VF_FORCE_LINK_UP, false);
 743 }
 744
 745 static void configure_vlan_types(struct adapter *adapter)
 746 {
 747         int i;
 748
 749         for_each_port(adapter, i) {
 750                 /* OVLAN Type 0x88a8 */
 751                 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN0),
 752                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 753                                  V_OVLAN_ETYPE(M_OVLAN_ETYPE),
 754                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 755                                  V_OVLAN_ETYPE(0x88a8));
 756                 /* OVLAN Type 0x9100 */
 757                 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN1),
 758                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 759                                  V_OVLAN_ETYPE(M_OVLAN_ETYPE),
 760                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 761                                  V_OVLAN_ETYPE(0x9100));
 762
 763                 /* IVLAN 0X8100 */
 764                 t4_set_reg_field(adapter, MPS_PORT_RX_IVLAN(i),
 765                                  V_IVLAN_ETYPE(M_IVLAN_ETYPE),
 766                                  V_IVLAN_ETYPE(0x8100));
 767
 768                 t4_set_reg_field(adapter, MPS_PORT_RX_CTL(i),
 769                                  F_OVLAN_EN0 | F_OVLAN_EN1 |
 770                                  F_IVLAN_EN,
 771                                  F_OVLAN_EN0 | F_OVLAN_EN1 |
 772                                  F_IVLAN_EN);
 773         }
 774
 775         t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG, V_RM_OVLAN(1),
 776                                V_RM_OVLAN(!adapter->devargs.keep_ovlan));
 777 }
 778
 779 static void configure_pcie_ext_tag(struct adapter *adapter)
 780 {
 781         u16 v;
 782         int pos = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
 783
 784         if (!pos)
 785                 return;
 786
 787         if (pos > 0) {
 788                 t4_os_pci_read_cfg2(adapter, pos + PCI_EXP_DEVCTL, &v);
 789                 v |= PCI_EXP_DEVCTL_EXT_TAG;
 790                 t4_os_pci_write_cfg2(adapter, pos + PCI_EXP_DEVCTL, v);
 791                 if (is_t6(adapter->params.chip)) {
 792                         t4_set_reg_field(adapter, A_PCIE_CFG2,
 793                                          V_T6_TOTMAXTAG(M_T6_TOTMAXTAG),
 794                                          V_T6_TOTMAXTAG(7));
 795                         t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
 796                                          V_T6_MINTAG(M_T6_MINTAG),
 797                                          V_T6_MINTAG(8));
 798                 } else {
 799                         t4_set_reg_field(adapter, A_PCIE_CFG2,
 800                                          V_TOTMAXTAG(M_TOTMAXTAG),
 801                                          V_TOTMAXTAG(3));
 802                         t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
 803                                          V_MINTAG(M_MINTAG),
 804                                          V_MINTAG(8));
 805                 }
 806         }
 807 }
 808
 809 /* Figure out how many Queue Sets we can support */
 810 void cxgbe_configure_max_ethqsets(struct adapter *adapter)
 811 {
 812         unsigned int ethqsets;
 813
 814         /*
 815          * We need to reserve an Ingress Queue for the Asynchronous Firmware
 816          * Event Queue.
 817          *
 818          * For each Queue Set, we'll need the ability to allocate two Egress
 819          * Contexts -- one for the Ingress Queue Free List and one for the TX
 820          * Ethernet Queue.
 821          */
 822         if (is_pf4(adapter)) {
 823                 struct pf_resources *pfres = &adapter->params.pfres;
 824
 825                 ethqsets = pfres->niqflint - 1;
 826                 if (pfres->neq < ethqsets * 2)
 827                         ethqsets = pfres->neq / 2;
 828         } else {
 829                 struct vf_resources *vfres = &adapter->params.vfres;
 830
 831                 ethqsets = vfres->niqflint - 1;
 832                 if (vfres->nethctrl != ethqsets)
 833                         ethqsets = min(vfres->nethctrl, ethqsets);
 834                 if (vfres->neq < ethqsets * 2)
 835                         ethqsets = vfres->neq / 2;
 836         }
 837
 838         if (ethqsets > MAX_ETH_QSETS)
 839                 ethqsets = MAX_ETH_QSETS;
 840         adapter->sge.max_ethqsets = ethqsets;
 841 }
 842
 843 /*
 844  * Tweak configuration based on system architecture, etc.  Most of these have
 845  * defaults assigned to them by Firmware Configuration Files (if we're using
 846  * them) but need to be explicitly set if we're using hard-coded
 847  * initialization. So these are essentially common tweaks/settings for
 848  * Configuration Files and hard-coded initialization ...
 849  */
 850 static int adap_init0_tweaks(struct adapter *adapter)
 851 {
 852         u8 rx_dma_offset;
 853
 854         /*
 855          * Fix up various Host-Dependent Parameters like Page Size, Cache
 856          * Line Size, etc.  The firmware default is for a 4KB Page Size and
 857          * 64B Cache Line Size ...
 858          */
 859         t4_fixup_host_params_compat(adapter, CXGBE_PAGE_SIZE, L1_CACHE_BYTES,
 860                                     T5_LAST_REV);
 861
 862         /*
 863          * Keep the chip default offset to deliver Ingress packets into our
 864          * DMA buffers to zero
 865          */
 866         rx_dma_offset = 0;
 867         t4_set_reg_field(adapter, A_SGE_CONTROL, V_PKTSHIFT(M_PKTSHIFT),
 868                          V_PKTSHIFT(rx_dma_offset));
 869
 870         t4_set_reg_field(adapter, A_SGE_FLM_CFG,
 871                          V_CREDITCNT(M_CREDITCNT) | M_CREDITCNTPACKING,
 872                          V_CREDITCNT(3) | V_CREDITCNTPACKING(1));
 873
 874         t4_set_reg_field(adapter, A_SGE_INGRESS_RX_THRESHOLD,
 875                          V_THRESHOLD_3(M_THRESHOLD_3), V_THRESHOLD_3(32U));
 876
 877         t4_set_reg_field(adapter, A_SGE_CONTROL2, V_IDMAARBROUNDROBIN(1U),
 878                          V_IDMAARBROUNDROBIN(1U));
 879
 880         /*
 881          * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
 882          * adds the pseudo header itself.
 883          */
 884         t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG,
 885                                F_CSUM_HAS_PSEUDO_HDR, 0);
 886
 887         return 0;
 888 }
 889
 890 /*
 891  * Attempt to initialize the adapter via a Firmware Configuration File.
 892  */
 893 static int adap_init0_config(struct adapter *adapter, int reset)
 894 {
 895         struct fw_caps_config_cmd caps_cmd;
 896         unsigned long mtype = 0, maddr = 0;
 897         u32 finiver, finicsum, cfcsum;
 898         int ret;
 899         int config_issued = 0;
 900         int cfg_addr;
 901         char config_name[20];
 902
 903         /*
 904          * Reset device if necessary.
 905          */
 906         if (reset) {
 907                 ret = t4_fw_reset(adapter, adapter->mbox,
 908                                   F_PIORSTMODE | F_PIORST);
 909                 if (ret < 0) {
 910                         dev_warn(adapter, "Firmware reset failed, error %d\n",
 911                                  -ret);
 912                         goto bye;
 913                 }
 914         }
 915
 916         cfg_addr = t4_flash_cfg_addr(adapter);
 917         if (cfg_addr < 0) {
 918                 ret = cfg_addr;
 919                 dev_warn(adapter, "Finding address for firmware config file in flash failed, error %d\n",
 920                          -ret);
 921                 goto bye;
 922         }
 923
 924         strcpy(config_name, "On Flash");
 925         mtype = FW_MEMTYPE_CF_FLASH;
 926         maddr = cfg_addr;
 927
 928         /*
 929          * Issue a Capability Configuration command to the firmware to get it
 930          * to parse the Configuration File.  We don't use t4_fw_config_file()
 931          * because we want the ability to modify various features after we've
 932          * processed the configuration file ...
 933          */
 934         memset(&caps_cmd, 0, sizeof(caps_cmd));
 935         caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
 936                                            F_FW_CMD_REQUEST | F_FW_CMD_READ);
 937         caps_cmd.cfvalid_to_len16 =
 938                 cpu_to_be32(F_FW_CAPS_CONFIG_CMD_CFVALID |
 939                             V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
 940                             V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
 941                             FW_LEN16(caps_cmd));
 942         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
 943                          &caps_cmd);
 944         /*
 945          * If the CAPS_CONFIG failed with an ENOENT (for a Firmware
 946          * Configuration File in FLASH), our last gasp effort is to use the
 947          * Firmware Configuration File which is embedded in the firmware.  A
 948          * very few early versions of the firmware didn't have one embedded
 949          * but we can ignore those.
 950          */
 951         if (ret == -ENOENT) {
 952                 dev_info(adapter, "%s: Going for embedded config in firmware..\n",
 953                          __func__);
 954
 955                 memset(&caps_cmd, 0, sizeof(caps_cmd));
 956                 caps_cmd.op_to_write =
 957                         cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
 958                                     F_FW_CMD_REQUEST | F_FW_CMD_READ);
 959                 caps_cmd.cfvalid_to_len16 = cpu_to_be32(FW_LEN16(caps_cmd));
 960                 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
 961                                  sizeof(caps_cmd), &caps_cmd);
 962                 strcpy(config_name, "Firmware Default");
 963         }
 964
 965         config_issued = 1;
 966         if (ret < 0)
 967                 goto bye;
 968
 969         finiver = be32_to_cpu(caps_cmd.finiver);
 970         finicsum = be32_to_cpu(caps_cmd.finicsum);
 971         cfcsum = be32_to_cpu(caps_cmd.cfcsum);
 972         if (finicsum != cfcsum)
 973                 dev_warn(adapter, "Configuration File checksum mismatch: [fini] csum=%#x, computed csum=%#x\n",
 974                          finicsum, cfcsum);
 975
 976         /*
 977          * If we're a pure NIC driver then disable all offloading facilities.
 978          * This will allow the firmware to optimize aspects of the hardware
 979          * configuration which will result in improved performance.
 980          */
 981         caps_cmd.niccaps &= cpu_to_be16(~FW_CAPS_CONFIG_NIC_ETHOFLD);
 982         caps_cmd.toecaps = 0;
 983         caps_cmd.iscsicaps = 0;
 984         caps_cmd.rdmacaps = 0;
 985         caps_cmd.fcoecaps = 0;
 986
 987         /*
 988          * And now tell the firmware to use the configuration we just loaded.
 989          */
 990         caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
 991                                            F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
 992         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
 993         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
 994                          NULL);
 995         if (ret < 0) {
 996                 dev_warn(adapter, "Unable to finalize Firmware Capabilities %d\n",
 997                          -ret);
 998                 goto bye;
 999         }
1000
1001         /*
1002          * Tweak configuration based on system architecture, etc.
1003          */
1004         ret = adap_init0_tweaks(adapter);
1005         if (ret < 0) {
1006                 dev_warn(adapter, "Unable to do init0-tweaks %d\n", -ret);
1007                 goto bye;
1008         }
1009
1010         /*
1011          * And finally tell the firmware to initialize itself using the
1012          * parameters from the Configuration File.
1013          */
1014         ret = t4_fw_initialize(adapter, adapter->mbox);
1015         if (ret < 0) {
1016                 dev_warn(adapter, "Initializing Firmware failed, error %d\n",
1017                          -ret);
1018                 goto bye;
1019         }
1020
1021         /*
1022          * Return successfully and note that we're operating with parameters
1023          * not supplied by the driver, rather than from hard-wired
1024          * initialization constants buried in the driver.
1025          */
1026         dev_info(adapter,
1027                  "Successfully configured using Firmware Configuration File \"%s\", version %#x, computed checksum %#x\n",
1028                  config_name, finiver, cfcsum);
1029
1030         return 0;
1031
1032         /*
1033          * Something bad happened.  Return the error ...  (If the "error"
1034          * is that there's no Configuration File on the adapter we don't
1035          * want to issue a warning since this is fairly common.)
1036          */
1037 bye:
1038         if (config_issued && ret != -ENOENT)
1039                 dev_warn(adapter, "\"%s\" configuration file error %d\n",
1040                          config_name, -ret);
1041
1042         dev_debug(adapter, "%s: returning ret = %d ..\n", __func__, ret);
1043         return ret;
1044 }
1045
1046 static int adap_init0(struct adapter *adap)
1047 {
1048         struct fw_caps_config_cmd caps_cmd;
1049         int ret = 0;
1050         u32 v, port_vec;
1051         enum dev_state state;
1052         u32 params[7], val[7];
1053         int reset = 1;
1054         int mbox = adap->mbox;
1055
1056         /*
1057          * Contact FW, advertising Master capability.
1058          */
1059         ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state);
1060         if (ret < 0) {
1061                 dev_err(adap, "%s: could not connect to FW, error %d\n",
1062                         __func__, -ret);
1063                 goto bye;
1064         }
1065
1066         CXGBE_DEBUG_MBOX(adap, "%s: adap->mbox = %d; ret = %d\n", __func__,
1067                          adap->mbox, ret);
1068
1069         if (ret == mbox)
1070                 adap->flags |= MASTER_PF;
1071
1072         if (state == DEV_STATE_INIT) {
1073                 /*
1074                  * Force halt and reset FW because a previous instance may have
1075                  * exited abnormally without properly shutting down
1076                  */
1077                 ret = t4_fw_halt(adap, adap->mbox, reset);
1078                 if (ret < 0) {
1079                         dev_err(adap, "Failed to halt. Exit.\n");
1080                         goto bye;
1081                 }
1082
1083                 ret = t4_fw_restart(adap, adap->mbox, reset);
1084                 if (ret < 0) {
1085                         dev_err(adap, "Failed to restart. Exit.\n");
1086                         goto bye;
1087                 }
1088                 state = (enum dev_state)((unsigned)state & ~DEV_STATE_INIT);
1089         }
1090
1091         t4_get_version_info(adap);
1092
1093         ret = t4_get_core_clock(adap, &adap->params.vpd);
1094         if (ret < 0) {
1095                 dev_err(adap, "%s: could not get core clock, error %d\n",
1096                         __func__, -ret);
1097                 goto bye;
1098         }
1099
1100         /*
1101          * If the firmware is initialized already (and we're not forcing a
1102          * master initialization), note that we're living with existing
1103          * adapter parameters.  Otherwise, it's time to try initializing the
1104          * adapter ...
1105          */
1106         if (state == DEV_STATE_INIT) {
1107                 dev_info(adap, "Coming up as %s: Adapter already initialized\n",
1108                          adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
1109         } else {
1110                 dev_info(adap, "Coming up as MASTER: Initializing adapter\n");
1111
1112                 ret = adap_init0_config(adap, reset);
1113                 if (ret == -ENOENT) {
1114                         dev_err(adap,
1115                                 "No Configuration File present on adapter. Using hard-wired configuration parameters.\n");
1116                         goto bye;
1117                 }
1118         }
1119         if (ret < 0) {
1120                 dev_err(adap, "could not initialize adapter, error %d\n", -ret);
1121                 goto bye;
1122         }
1123
1124         /* Now that we've successfully configured and initialized the adapter
1125          * (or found it already initialized), we can ask the Firmware what
1126          * resources it has provisioned for us.
1127          */
1128         ret = t4_get_pfres(adap);
1129         if (ret) {
1130                 dev_err(adap->pdev_dev,
1131                         "Unable to retrieve resource provisioning info\n");
1132                 goto bye;
1133         }
1134
1135         /* Find out what ports are available to us. */
1136         v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
1137             V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC);
1138         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
1139         if (ret < 0) {
1140                 dev_err(adap, "%s: failure in t4_query_params; error = %d\n",
1141                         __func__, ret);
1142                 goto bye;
1143         }
1144
1145         adap->params.nports = hweight32(port_vec);
1146         adap->params.portvec = port_vec;
1147
1148         dev_debug(adap, "%s: adap->params.nports = %u\n", __func__,
1149                   adap->params.nports);
1150
1151         /*
1152          * Give the SGE code a chance to pull in anything that it needs ...
1153          * Note that this must be called after we retrieve our VPD parameters
1154          * in order to know how to convert core ticks to seconds, etc.
1155          */
1156         ret = t4_sge_init(adap);
1157         if (ret < 0) {
1158                 dev_err(adap, "t4_sge_init failed with error %d\n",
1159                         -ret);
1160                 goto bye;
1161         }
1162
1163         /*
1164          * Grab some of our basic fundamental operating parameters.
1165          */
1166         params[0] = CXGBE_FW_PARAM_PFVF(L2T_START);
1167         params[1] = CXGBE_FW_PARAM_PFVF(L2T_END);
1168         params[2] = CXGBE_FW_PARAM_PFVF(FILTER_START);
1169         params[3] = CXGBE_FW_PARAM_PFVF(FILTER_END);
1170         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 4, params, val);
1171         if (ret < 0)
1172                 goto bye;
1173         adap->l2t_start = val[0];
1174         adap->l2t_end = val[1];
1175         adap->tids.ftid_base = val[2];
1176         adap->tids.nftids = val[3] - val[2] + 1;
1177
1178         params[0] = CXGBE_FW_PARAM_PFVF(CLIP_START);
1179         params[1] = CXGBE_FW_PARAM_PFVF(CLIP_END);
1180         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
1181         if (ret < 0)
1182                 goto bye;
1183         adap->clipt_start = val[0];
1184         adap->clipt_end = val[1];
1185
1186         /*
1187          * Get device capabilities so we can determine what resources we need
1188          * to manage.
1189          */
1190         memset(&caps_cmd, 0, sizeof(caps_cmd));
1191         caps_cmd.op_to_write = htonl(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
1192                                      F_FW_CMD_REQUEST | F_FW_CMD_READ);
1193         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
1194         ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
1195                          &caps_cmd);
1196         if (ret < 0)
1197                 goto bye;
1198
1199         if ((caps_cmd.niccaps & cpu_to_be16(FW_CAPS_CONFIG_NIC_HASHFILTER)) &&
1200             is_t6(adap->params.chip)) {
1201                 if (cxgbe_init_hash_filter(adap) < 0)
1202                         goto bye;
1203         }
1204
1205         /* See if FW supports FW_FILTER2 work request */
1206         if (is_t4(adap->params.chip)) {
1207                 adap->params.filter2_wr_support = 0;
1208         } else {
1209                 params[0] = CXGBE_FW_PARAM_DEV(FILTER2_WR);
1210                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
1211                                       1, params, val);
1212                 adap->params.filter2_wr_support = (ret == 0 && val[0] != 0);
1213         }
1214
1215         /* Check if FW supports returning vin.
1216          * If this is not supported, driver will interpret
1217          * these values from viid.
1218          */
1219         params[0] = CXGBE_FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN);
1220         ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
1221                               1, params, val);
1222         adap->params.viid_smt_extn_support = (ret == 0 && val[0] != 0);
1223
1224         /* query tid-related parameters */
1225         params[0] = CXGBE_FW_PARAM_DEV(NTID);
1226         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
1227                               params, val);
1228         if (ret < 0)
1229                 goto bye;
1230         adap->tids.ntids = val[0];
1231         adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
1232
1233         /* If we're running on newer firmware, let it know that we're
1234          * prepared to deal with encapsulated CPL messages.  Older
1235          * firmware won't understand this and we'll just get
1236          * unencapsulated messages ...
1237          */
1238         params[0] = CXGBE_FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
1239         val[0] = 1;
1240         (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
1241
1242         /*
1243          * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
1244          * capability.  Earlier versions of the firmware didn't have the
1245          * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
1246          * permission to use ULPTX MEMWRITE DSGL.
1247          */
1248         if (is_t4(adap->params.chip)) {
1249                 adap->params.ulptx_memwrite_dsgl = false;
1250         } else {
1251                 params[0] = CXGBE_FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
1252                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
1253                                       1, params, val);
1254                 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
1255         }
1256
1257         /* Query for max number of packets that can be coalesced for Tx */
1258         params[0] = CXGBE_FW_PARAM_PFVF(MAX_PKTS_PER_ETH_TX_PKTS_WR);
1259         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
1260         if (!ret && val[0] > 0)
1261                 adap->params.max_tx_coalesce_num = val[0];
1262         else
1263                 adap->params.max_tx_coalesce_num = ETH_COALESCE_PKT_NUM;
1264
1265         /*
1266          * The MTU/MSS Table is initialized by now, so load their values.  If
1267          * we're initializing the adapter, then we'll make any modifications
1268          * we want to the MTU/MSS Table and also initialize the congestion
1269          * parameters.
1270          */
1271         t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
1272         if (state != DEV_STATE_INIT) {
1273                 int i;
1274
1275                 /*
1276                  * The default MTU Table contains values 1492 and 1500.
1277                  * However, for TCP, it's better to have two values which are
1278                  * a multiple of 8 +/- 4 bytes apart near this popular MTU.
1279                  * This allows us to have a TCP Data Payload which is a
1280                  * multiple of 8 regardless of what combination of TCP Options
1281                  * are in use (always a multiple of 4 bytes) which is
1282                  * important for performance reasons.  For instance, if no
1283                  * options are in use, then we have a 20-byte IP header and a
1284                  * 20-byte TCP header.  In this case, a 1500-byte MSS would
1285                  * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
1286                  * which is not a multiple of 8.  So using an MSS of 1488 in
1287                  * this case results in a TCP Data Payload of 1448 bytes which
1288                  * is a multiple of 8.  On the other hand, if 12-byte TCP Time
1289                  * Stamps have been negotiated, then an MTU of 1500 bytes
1290                  * results in a TCP Data Payload of 1448 bytes which, as
1291                  * above, is a multiple of 8 bytes ...
1292                  */
1293                 for (i = 0; i < NMTUS; i++)
1294                         if (adap->params.mtus[i] == 1492) {
1295                                 adap->params.mtus[i] = 1488;
1296                                 break;
1297                         }
1298
1299                 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
1300                              adap->params.b_wnd);
1301         }
1302         t4_init_sge_params(adap);
1303         t4_init_tp_params(adap);
1304         configure_pcie_ext_tag(adap);
1305         configure_vlan_types(adap);
1306         cxgbe_configure_max_ethqsets(adap);
1307
1308         adap->params.drv_memwin = MEMWIN_NIC;
1309         adap->flags |= FW_OK;
1310         dev_debug(adap, "%s: returning zero..\n", __func__);
1311         return 0;
1312
1313         /*
1314          * Something bad happened.  If a command timed out or failed with EIO
1315          * FW does not operate within its spec or something catastrophic
1316          * happened to HW/FW, stop issuing commands.
1317          */
1318 bye:
1319         if (ret != -ETIMEDOUT && ret != -EIO)
1320                 t4_fw_bye(adap, adap->mbox);
1321         return ret;
1322 }
1323
1324 /**
1325  * t4_os_portmod_changed - handle port module changes
1326  * @adap: the adapter associated with the module change
1327  * @port_id: the port index whose module status has changed
1328  *
1329  * This is the OS-dependent handler for port module changes.  It is
1330  * invoked when a port module is removed or inserted for any OS-specific
1331  * processing.
1332  */
1333 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
1334 {
1335         static const char * const mod_str[] = {
1336                 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
1337         };
1338
1339         const struct port_info *pi = adap2pinfo(adap, port_id);
1340
1341         if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
1342                 dev_info(adap, "Port%d: port module unplugged\n", pi->port_id);
1343         else if (pi->mod_type < ARRAY_SIZE(mod_str))
1344                 dev_info(adap, "Port%d: %s port module inserted\n", pi->port_id,
1345                          mod_str[pi->mod_type]);
1346         else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
1347                 dev_info(adap, "Port%d: unsupported port module inserted\n",
1348                          pi->port_id);
1349         else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
1350                 dev_info(adap, "Port%d: unknown port module inserted\n",
1351                          pi->port_id);
1352         else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
1353                 dev_info(adap, "Port%d: transceiver module error\n",
1354                          pi->port_id);
1355         else
1356                 dev_info(adap, "Port%d: unknown module type %d inserted\n",
1357                          pi->port_id, pi->mod_type);
1358 }
1359
1360 bool cxgbe_force_linkup(struct adapter *adap)
1361 {
1362         if (is_pf4(adap))
1363                 return false;   /* force_linkup not required for pf driver */
1364
1365         return adap->devargs.force_link_up;
1366 }
1367
1368 /**
1369  * link_start - enable a port
1370  * @dev: the port to enable
1371  *
1372  * Performs the MAC and PHY actions needed to enable a port.
1373  */
1374 int cxgbe_link_start(struct port_info *pi)
1375 {
1376         struct adapter *adapter = pi->adapter;
1377         u64 conf_offloads;
1378         unsigned int mtu;
1379         int ret;
1380
1381         mtu = pi->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1382               (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN);
1383
1384         conf_offloads = pi->eth_dev->data->dev_conf.rxmode.offloads;
1385
1386         /*
1387          * We do not set address filters and promiscuity here, the stack does
1388          * that step explicitly.
1389          */
1390         ret = t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, -1, -1, -1,
1391                             !!(conf_offloads & DEV_RX_OFFLOAD_VLAN_STRIP),
1392                             true);
1393         if (ret == 0) {
1394                 ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt,
1395                                 (u8 *)&pi->eth_dev->data->mac_addrs[0]);
1396                 if (ret >= 0) {
1397                         pi->xact_addr_filt = ret;
1398                         ret = 0;
1399                 }
1400         }
1401         if (ret == 0 && is_pf4(adapter))
1402                 ret = t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
1403                                     &pi->link_cfg);
1404         if (ret == 0) {
1405                 /*
1406                  * Enabling a Virtual Interface can result in an interrupt
1407                  * during the processing of the VI Enable command and, in some
1408                  * paths, result in an attempt to issue another command in the
1409                  * interrupt context.  Thus, we disable interrupts during the
1410                  * course of the VI Enable command ...
1411                  */
1412                 ret = t4_enable_vi_params(adapter, adapter->mbox, pi->viid,
1413                                           true, true, false);
1414         }
1415
1416         if (ret == 0 && cxgbe_force_linkup(adapter))
1417                 pi->eth_dev->data->dev_link.link_status = ETH_LINK_UP;
1418         return ret;
1419 }
1420
1421 /**
1422  * cxgbe_write_rss_conf - flash the RSS configuration for a given port
1423  * @pi: the port
1424  * @rss_hf: Hash configuration to apply
1425  */
1426 int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t rss_hf)
1427 {
1428         struct adapter *adapter = pi->adapter;
1429         const struct sge_eth_rxq *rxq;
1430         u64 flags = 0;
1431         u16 rss;
1432         int err;
1433
1434         /*  Should never be called before setting up sge eth rx queues */
1435         if (!(adapter->flags & FULL_INIT_DONE)) {
1436                 dev_err(adap, "%s No RXQs available on port %d\n",
1437                         __func__, pi->port_id);
1438                 return -EINVAL;
1439         }
1440
1441         /* Don't allow unsupported hash functions */
1442         if (rss_hf & ~CXGBE_RSS_HF_ALL)
1443                 return -EINVAL;
1444
1445         if (rss_hf & CXGBE_RSS_HF_IPV4_MASK)
1446                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
1447
1448         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1449                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
1450
1451         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1452                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
1453                          F_FW_RSS_VI_CONFIG_CMD_UDPEN;
1454
1455         if (rss_hf & CXGBE_RSS_HF_IPV6_MASK)
1456                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
1457
1458         if (rss_hf & CXGBE_RSS_HF_TCP_IPV6_MASK)
1459                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
1460                          F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
1461
1462         if (rss_hf & CXGBE_RSS_HF_UDP_IPV6_MASK)
1463                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
1464                          F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
1465                          F_FW_RSS_VI_CONFIG_CMD_UDPEN;
1466
1467         rxq = &adapter->sge.ethrxq[pi->first_qset];
1468         rss = rxq[0].rspq.abs_id;
1469
1470         /* If Tunnel All Lookup isn't specified in the global RSS
1471          * Configuration, then we need to specify a default Ingress
1472          * Queue for any ingress packets which aren't hashed.  We'll
1473          * use our first ingress queue ...
1474          */
1475         err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
1476                                flags, rss);
1477         return err;
1478 }
1479
1480 /**
1481  * cxgbe_write_rss - write the RSS table for a given port
1482  * @pi: the port
1483  * @queues: array of queue indices for RSS
1484  *
1485  * Sets up the portion of the HW RSS table for the port's VI to distribute
1486  * packets to the Rx queues in @queues.
1487  */
1488 int cxgbe_write_rss(const struct port_info *pi, const u16 *queues)
1489 {
1490         u16 *rss;
1491         int i, err;
1492         struct adapter *adapter = pi->adapter;
1493         const struct sge_eth_rxq *rxq;
1494
1495         /*  Should never be called before setting up sge eth rx queues */
1496         BUG_ON(!(adapter->flags & FULL_INIT_DONE));
1497
1498         rxq = &adapter->sge.ethrxq[pi->first_qset];
1499         rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
1500         if (!rss)
1501                 return -ENOMEM;
1502
1503         /* map the queue indices to queue ids */
1504         for (i = 0; i < pi->rss_size; i++, queues++)
1505                 rss[i] = rxq[*queues].rspq.abs_id;
1506
1507         err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
1508                                   pi->rss_size, rss, pi->rss_size);
1509         rte_free(rss);
1510         return err;
1511 }
1512
1513 /**
1514  * setup_rss - configure RSS
1515  * @adapter: the adapter
1516  *
1517  * Sets up RSS to distribute packets to multiple receive queues.  We
1518  * configure the RSS CPU lookup table to distribute to the number of HW
1519  * receive queues, and the response queue lookup table to narrow that
1520  * down to the response queues actually configured for each port.
1521  * We always configure the RSS mapping for all ports since the mapping
1522  * table has plenty of entries.
1523  */
1524 int cxgbe_setup_rss(struct port_info *pi)
1525 {
1526         int j, err;
1527         struct adapter *adapter = pi->adapter;
1528
1529         dev_debug(adapter, "%s:  pi->rss_size = %u; pi->n_rx_qsets = %u\n",
1530                   __func__, pi->rss_size, pi->n_rx_qsets);
1531
1532         if (!(pi->flags & PORT_RSS_DONE)) {
1533                 if (adapter->flags & FULL_INIT_DONE) {
1534                         /* Fill default values with equal distribution */
1535                         for (j = 0; j < pi->rss_size; j++)
1536                                 pi->rss[j] = j % pi->n_rx_qsets;
1537
1538                         err = cxgbe_write_rss(pi, pi->rss);
1539                         if (err)
1540                                 return err;
1541
1542                         err = cxgbe_write_rss_conf(pi, pi->rss_hf);
1543                         if (err)
1544                                 return err;
1545                         pi->flags |= PORT_RSS_DONE;
1546                 }
1547         }
1548         return 0;
1549 }
1550
1551 /*
1552  * Enable NAPI scheduling and interrupt generation for all Rx queues.
1553  */
1554 static void enable_rx(struct adapter *adap, struct sge_rspq *q)
1555 {
1556         /* 0-increment GTS to start the timer and enable interrupts */
1557         t4_write_reg(adap, is_pf4(adap) ? MYPF_REG(A_SGE_PF_GTS) :
1558                                           T4VF_SGE_BASE_ADDR + A_SGE_VF_GTS,
1559                      V_SEINTARM(q->intr_params) |
1560                      V_INGRESSQID(q->cntxt_id));
1561 }
1562
1563 void cxgbe_enable_rx_queues(struct port_info *pi)
1564 {
1565         struct adapter *adap = pi->adapter;
1566         struct sge *s = &adap->sge;
1567         unsigned int i;
1568
1569         for (i = 0; i < pi->n_rx_qsets; i++)
1570                 enable_rx(adap, &s->ethrxq[pi->first_qset + i].rspq);
1571 }
1572
1573 /**
1574  * fw_caps_to_speed_caps - translate Firmware Port Caps to Speed Caps.
1575  * @port_type: Firmware Port Type
1576  * @fw_caps: Firmware Port Capabilities
1577  * @speed_caps: Device Info Speed Capabilities
1578  *
1579  * Translate a Firmware Port Capabilities specification to Device Info
1580  * Speed Capabilities.
1581  */
1582 static void fw_caps_to_speed_caps(enum fw_port_type port_type,
1583                                   unsigned int fw_caps,
1584                                   u32 *speed_caps)
1585 {
1586 #define SET_SPEED(__speed_name) \
1587         do { \
1588                 *speed_caps |= ETH_LINK_ ## __speed_name; \
1589         } while (0)
1590
1591 #define FW_CAPS_TO_SPEED(__fw_name) \
1592         do { \
1593                 if (fw_caps & FW_PORT_CAP32_ ## __fw_name) \
1594                         SET_SPEED(__fw_name); \
1595         } while (0)
1596
1597         switch (port_type) {
1598         case FW_PORT_TYPE_BT_SGMII:
1599         case FW_PORT_TYPE_BT_XFI:
1600         case FW_PORT_TYPE_BT_XAUI:
1601                 FW_CAPS_TO_SPEED(SPEED_100M);
1602                 FW_CAPS_TO_SPEED(SPEED_1G);
1603                 FW_CAPS_TO_SPEED(SPEED_10G);
1604                 break;
1605
1606         case FW_PORT_TYPE_KX4:
1607         case FW_PORT_TYPE_KX:
1608         case FW_PORT_TYPE_FIBER_XFI:
1609         case FW_PORT_TYPE_FIBER_XAUI:
1610         case FW_PORT_TYPE_SFP:
1611         case FW_PORT_TYPE_QSFP_10G:
1612         case FW_PORT_TYPE_QSA:
1613                 FW_CAPS_TO_SPEED(SPEED_1G);
1614                 FW_CAPS_TO_SPEED(SPEED_10G);
1615                 break;
1616
1617         case FW_PORT_TYPE_KR:
1618                 SET_SPEED(SPEED_10G);
1619                 break;
1620
1621         case FW_PORT_TYPE_BP_AP:
1622         case FW_PORT_TYPE_BP4_AP:
1623                 SET_SPEED(SPEED_1G);
1624                 SET_SPEED(SPEED_10G);
1625                 break;
1626
1627         case FW_PORT_TYPE_BP40_BA:
1628         case FW_PORT_TYPE_QSFP:
1629                 SET_SPEED(SPEED_40G);
1630                 break;
1631
1632         case FW_PORT_TYPE_CR_QSFP:
1633         case FW_PORT_TYPE_SFP28:
1634         case FW_PORT_TYPE_KR_SFP28:
1635                 FW_CAPS_TO_SPEED(SPEED_1G);
1636                 FW_CAPS_TO_SPEED(SPEED_10G);
1637                 FW_CAPS_TO_SPEED(SPEED_25G);
1638                 break;
1639
1640         case FW_PORT_TYPE_CR2_QSFP:
1641                 SET_SPEED(SPEED_50G);
1642                 break;
1643
1644         case FW_PORT_TYPE_KR4_100G:
1645         case FW_PORT_TYPE_CR4_QSFP:
1646                 FW_CAPS_TO_SPEED(SPEED_25G);
1647                 FW_CAPS_TO_SPEED(SPEED_40G);
1648                 FW_CAPS_TO_SPEED(SPEED_50G);
1649                 FW_CAPS_TO_SPEED(SPEED_100G);
1650                 break;
1651
1652         default:
1653                 break;
1654         }
1655
1656 #undef FW_CAPS_TO_SPEED
1657 #undef SET_SPEED
1658 }
1659
1660 /**
1661  * cxgbe_get_speed_caps - Fetch supported speed capabilities
1662  * @pi: Underlying port's info
1663  * @speed_caps: Device Info speed capabilities
1664  *
1665  * Fetch supported speed capabilities of the underlying port.
1666  */
1667 void cxgbe_get_speed_caps(struct port_info *pi, u32 *speed_caps)
1668 {
1669         *speed_caps = 0;
1670
1671         fw_caps_to_speed_caps(pi->port_type, pi->link_cfg.pcaps,
1672                               speed_caps);
1673
1674         if (!(pi->link_cfg.pcaps & FW_PORT_CAP32_ANEG))
1675                 *speed_caps |= ETH_LINK_SPEED_FIXED;
1676 }
1677
1678 /**
1679  * cxgbe_set_link_status - Set device link up or down.
1680  * @pi: Underlying port's info
1681  * @status: 0 - down, 1 - up
1682  *
1683  * Set the device link up or down.
1684  */
1685 int cxgbe_set_link_status(struct port_info *pi, bool status)
1686 {
1687         struct adapter *adapter = pi->adapter;
1688         int err = 0;
1689
1690         err = t4_enable_vi(adapter, adapter->mbox, pi->viid, status, status);
1691         if (err) {
1692                 dev_err(adapter, "%s: disable_vi failed: %d\n", __func__, err);
1693                 return err;
1694         }
1695
1696         if (!status)
1697                 t4_reset_link_config(adapter, pi->pidx);
1698
1699         return 0;
1700 }
1701
1702 /**
1703  * cxgb_up - enable the adapter
1704  * @adap: adapter being enabled
1705  *
1706  * Called when the first port is enabled, this function performs the
1707  * actions necessary to make an adapter operational, such as completing
1708  * the initialization of HW modules, and enabling interrupts.
1709  */
1710 int cxgbe_up(struct adapter *adap)
1711 {
1712         enable_rx(adap, &adap->sge.fw_evtq);
1713         t4_sge_tx_monitor_start(adap);
1714         if (is_pf4(adap))
1715                 t4_intr_enable(adap);
1716         adap->flags |= FULL_INIT_DONE;
1717
1718         /* TODO: deadman watchdog ?? */
1719         return 0;
1720 }
1721
1722 /*
1723  * Close the port
1724  */
1725 int cxgbe_down(struct port_info *pi)
1726 {
1727         return cxgbe_set_link_status(pi, false);
1728 }
1729
1730 /*
1731  * Release resources when all the ports have been stopped.
1732  */
1733 void cxgbe_close(struct adapter *adapter)
1734 {
1735         struct port_info *pi;
1736         int i;
1737
1738         if (adapter->flags & FULL_INIT_DONE) {
1739                 tid_free(&adapter->tids);
1740                 t4_cleanup_mpstcam(adapter);
1741                 t4_cleanup_clip_tbl(adapter);
1742                 t4_cleanup_l2t(adapter);
1743                 t4_cleanup_smt(adapter);
1744                 if (is_pf4(adapter))
1745                         t4_intr_disable(adapter);
1746                 t4_sge_tx_monitor_stop(adapter);
1747                 t4_free_sge_resources(adapter);
1748                 for_each_port(adapter, i) {
1749                         pi = adap2pinfo(adapter, i);
1750                         if (pi->viid != 0)
1751                                 t4_free_vi(adapter, adapter->mbox,
1752                                            adapter->pf, 0, pi->viid);
1753                         rte_eth_dev_release_port(pi->eth_dev);
1754                 }
1755                 adapter->flags &= ~FULL_INIT_DONE;
1756         }
1757
1758         if (is_pf4(adapter) && (adapter->flags & FW_OK))
1759                 t4_fw_bye(adapter, adapter->mbox);
1760 }
1761
1762 static void adap_smt_index(struct adapter *adapter, u32 *smt_start_idx,
1763                            u32 *smt_size)
1764 {
1765         u32 params[2], smt_val[2];
1766         int ret;
1767
1768         params[0] = CXGBE_FW_PARAM_PFVF(GET_SMT_START);
1769         params[1] = CXGBE_FW_PARAM_PFVF(GET_SMT_SIZE);
1770
1771         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
1772                               2, params, smt_val);
1773
1774         /* if FW doesn't recognize this command then set it to default setting
1775          * which is start index as 0 and size as 256.
1776          */
1777         if (ret < 0) {
1778                 *smt_start_idx = 0;
1779                 *smt_size = SMT_SIZE;
1780         } else {
1781                 *smt_start_idx = smt_val[0];
1782                 /* smt size can be zero, if nsmt is not yet configured in
1783                  * the config file or set as zero, then configure all the
1784                  * remaining entries to this PF itself.
1785                  */
1786                 if (!smt_val[1])
1787                         *smt_size = SMT_SIZE - *smt_start_idx;
1788                 else
1789                         *smt_size = smt_val[1];
1790         }
1791 }
1792
1793 int cxgbe_probe(struct adapter *adapter)
1794 {
1795         u32 smt_start_idx, smt_size;
1796         struct port_info *pi;
1797         int func, i;
1798         int err = 0;
1799         u32 whoami;
1800         int chip;
1801
1802         whoami = t4_read_reg(adapter, A_PL_WHOAMI);
1803         chip = t4_get_chip_type(adapter,
1804                         CHELSIO_PCI_ID_VER(adapter->pdev->id.device_id));
1805         if (chip < 0)
1806                 return chip;
1807
1808         func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ?
1809                G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
1810
1811         adapter->mbox = func;
1812         adapter->pf = func;
1813
1814         t4_os_lock_init(&adapter->mbox_lock);
1815         TAILQ_INIT(&adapter->mbox_list);
1816         t4_os_lock_init(&adapter->win0_lock);
1817
1818         err = t4_prep_adapter(adapter);
1819         if (err)
1820                 return err;
1821
1822         setup_memwin(adapter);
1823         err = adap_init0(adapter);
1824         if (err) {
1825                 dev_err(adapter, "%s: Adapter initialization failed, error %d\n",
1826                         __func__, err);
1827                 goto out_free;
1828         }
1829
1830         if (!is_t4(adapter->params.chip)) {
1831                 /*
1832                  * The userspace doorbell BAR is split evenly into doorbell
1833                  * regions, each associated with an egress queue.  If this
1834                  * per-queue region is large enough (at least UDBS_SEG_SIZE)
1835                  * then it can be used to submit a tx work request with an
1836                  * implied doorbell.  Enable write combining on the BAR if
1837                  * there is room for such work requests.
1838                  */
1839                 int s_qpp, qpp, num_seg;
1840
1841                 s_qpp = (S_QUEUESPERPAGEPF0 +
1842                         (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) *
1843                         adapter->pf);
1844                 qpp = 1 << ((t4_read_reg(adapter,
1845                                 A_SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp)
1846                                 & M_QUEUESPERPAGEPF0);
1847                 num_seg = CXGBE_PAGE_SIZE / UDBS_SEG_SIZE;
1848                 if (qpp > num_seg)
1849                         dev_warn(adapter, "Incorrect SGE EGRESS QUEUES_PER_PAGE configuration, continuing in debug mode\n");
1850
1851                 adapter->bar2 = (void *)adapter->pdev->mem_resource[2].addr;
1852                 if (!adapter->bar2) {
1853                         dev_err(adapter, "cannot map device bar2 region\n");
1854                         err = -ENOMEM;
1855                         goto out_free;
1856                 }
1857                 t4_write_reg(adapter, A_SGE_STAT_CFG, V_STATSOURCE_T5(7) |
1858                              V_STATMODE(0));
1859         }
1860
1861         for_each_port(adapter, i) {
1862                 const unsigned int numa_node = rte_socket_id();
1863                 char name[RTE_ETH_NAME_MAX_LEN];
1864                 struct rte_eth_dev *eth_dev;
1865
1866                 snprintf(name, sizeof(name), "%s_%d",
1867                          adapter->pdev->device.name, i);
1868
1869                 if (i == 0) {
1870                         /* First port is already allocated by DPDK */
1871                         eth_dev = adapter->eth_dev;
1872                         goto allocate_mac;
1873                 }
1874
1875                 /*
1876                  * now do all data allocation - for eth_dev structure,
1877                  * and internal (private) data for the remaining ports
1878                  */
1879
1880                 /* reserve an ethdev entry */
1881                 eth_dev = rte_eth_dev_allocate(name);
1882                 if (!eth_dev)
1883                         goto out_free;
1884
1885                 eth_dev->data->dev_private =
1886                         rte_zmalloc_socket(name, sizeof(struct port_info),
1887                                            RTE_CACHE_LINE_SIZE, numa_node);
1888                 if (!eth_dev->data->dev_private)
1889                         goto out_free;
1890
1891 allocate_mac:
1892                 pi = eth_dev->data->dev_private;
1893                 adapter->port[i] = pi;
1894                 pi->eth_dev = eth_dev;
1895                 pi->adapter = adapter;
1896                 pi->xact_addr_filt = -1;
1897                 pi->port_id = i;
1898                 pi->pidx = i;
1899
1900                 pi->eth_dev->device = &adapter->pdev->device;
1901                 pi->eth_dev->dev_ops = adapter->eth_dev->dev_ops;
1902                 pi->eth_dev->tx_pkt_burst = adapter->eth_dev->tx_pkt_burst;
1903                 pi->eth_dev->rx_pkt_burst = adapter->eth_dev->rx_pkt_burst;
1904
1905                 rte_eth_copy_pci_info(pi->eth_dev, adapter->pdev);
1906
1907                 pi->eth_dev->data->mac_addrs = rte_zmalloc(name,
1908                                                         RTE_ETHER_ADDR_LEN, 0);
1909                 if (!pi->eth_dev->data->mac_addrs) {
1910                         dev_err(adapter, "%s: Mem allocation failed for storing mac addr, aborting\n",
1911                                 __func__);
1912                         err = -1;
1913                         goto out_free;
1914                 }
1915
1916                 if (i > 0) {
1917                         /* First port will be notified by upper layer */
1918                         rte_eth_dev_probing_finish(eth_dev);
1919                 }
1920         }
1921
1922         if (adapter->flags & FW_OK) {
1923                 err = t4_port_init(adapter, adapter->mbox, adapter->pf, 0);
1924                 if (err) {
1925                         dev_err(adapter, "%s: t4_port_init failed with err %d\n",
1926                                 __func__, err);
1927                         goto out_free;
1928                 }
1929         }
1930
1931         cxgbe_cfg_queues(adapter->eth_dev);
1932
1933         cxgbe_print_adapter_info(adapter);
1934         cxgbe_print_port_info(adapter);
1935
1936         adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
1937                                           adapter->clipt_end);
1938         if (!adapter->clipt) {
1939                 /* We tolerate a lack of clip_table, giving up some
1940                  * functionality
1941                  */
1942                 dev_warn(adapter, "could not allocate CLIP. Continuing\n");
1943         }
1944
1945         adap_smt_index(adapter, &smt_start_idx, &smt_size);
1946         adapter->smt = t4_init_smt(smt_start_idx, smt_size);
1947         if (!adapter->smt)
1948                 dev_warn(adapter, "could not allocate SMT, continuing\n");
1949
1950         adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end);
1951         if (!adapter->l2t) {
1952                 /* We tolerate a lack of L2T, giving up some functionality */
1953                 dev_warn(adapter, "could not allocate L2T. Continuing\n");
1954         }
1955
1956         if (tid_init(&adapter->tids) < 0) {
1957                 /* Disable filtering support */
1958                 dev_warn(adapter, "could not allocate TID table, "
1959                          "filter support disabled. Continuing\n");
1960         }
1961
1962         t4_os_lock_init(&adapter->flow_lock);
1963
1964         adapter->mpstcam = t4_init_mpstcam(adapter);
1965         if (!adapter->mpstcam)
1966                 dev_warn(adapter, "could not allocate mps tcam table."
1967                          " Continuing\n");
1968
1969         if (is_hashfilter(adapter)) {
1970                 if (t4_read_reg(adapter, A_LE_DB_CONFIG) & F_HASHEN) {
1971                         u32 hash_base, hash_reg;
1972
1973                         hash_reg = A_LE_DB_TID_HASHBASE;
1974                         hash_base = t4_read_reg(adapter, hash_reg);
1975                         adapter->tids.hash_base = hash_base / 4;
1976                 }
1977         } else {
1978                 /* Disable hash filtering support */
1979                 dev_warn(adapter,
1980                          "Maskless filter support disabled. Continuing\n");
1981         }
1982
1983         err = cxgbe_init_rss(adapter);
1984         if (err)
1985                 goto out_free;
1986
1987         return 0;
1988
1989 out_free:
1990         for_each_port(adapter, i) {
1991                 pi = adap2pinfo(adapter, i);
1992                 if (pi->viid != 0)
1993                         t4_free_vi(adapter, adapter->mbox, adapter->pf,
1994                                    0, pi->viid);
1995                 rte_eth_dev_release_port(pi->eth_dev);
1996         }
1997
1998         if (adapter->flags & FW_OK)
1999                 t4_fw_bye(adapter, adapter->mbox);
2000         return -err;
2001 }