drivers/net/cxgbe/cxgbe_main.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Chelsio Communications.
   3  * All rights reserved.
   4  */
   5
   6 #include <sys/queue.h>
   7 #include <stdio.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <string.h>
  11 #include <unistd.h>
  12 #include <stdarg.h>
  13 #include <inttypes.h>
  14 #include <netinet/in.h>
  15
  16 #include <rte_byteorder.h>
  17 #include <rte_common.h>
  18 #include <rte_cycles.h>
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_branch_prediction.h>
  24 #include <rte_memory.h>
  25 #include <rte_tailq.h>
  26 #include <rte_eal.h>
  27 #include <rte_alarm.h>
  28 #include <rte_ether.h>
  29 #include <ethdev_driver.h>
  30 #include <ethdev_pci.h>
  31 #include <rte_random.h>
  32 #include <rte_dev.h>
  33 #include <rte_kvargs.h>
  34
  35 #include "base/common.h"
  36 #include "base/t4_regs.h"
  37 #include "base/t4_msg.h"
  38 #include "cxgbe.h"
  39 #include "cxgbe_pfvf.h"
  40 #include "clip_tbl.h"
  41 #include "l2t.h"
  42 #include "smt.h"
  43 #include "mps_tcam.h"
  44
  45 static const u16 cxgbe_filter_mode_features[] = {
  46         (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_ETHERTYPE |
  47          F_PROTOCOL | F_PORT),
  48         (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_ETHERTYPE |
  49          F_PROTOCOL | F_FCOE),
  50         (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_ETHERTYPE | F_TOS |
  51          F_PORT),
  52         (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_ETHERTYPE | F_TOS |
  53          F_FCOE),
  54         (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_ETHERTYPE | F_PORT |
  55          F_FCOE),
  56         (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_PROTOCOL | F_TOS |
  57          F_PORT | F_FCOE),
  58         (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_PROTOCOL | F_VLAN |
  59          F_FCOE),
  60         (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_PROTOCOL | F_VNIC_ID |
  61          F_FCOE),
  62         (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_TOS | F_VLAN |
  63          F_FCOE),
  64         (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_TOS | F_VNIC_ID |
  65          F_FCOE),
  66         (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_VLAN | F_PORT |
  67          F_FCOE),
  68         (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_VNIC_ID | F_PORT |
  69          F_FCOE),
  70         (F_FRAGMENTATION | F_MPSHITTYPE | F_ETHERTYPE | F_PROTOCOL | F_TOS |
  71          F_PORT | F_FCOE),
  72         (F_FRAGMENTATION | F_MPSHITTYPE | F_ETHERTYPE | F_VLAN | F_PORT),
  73         (F_FRAGMENTATION | F_MPSHITTYPE | F_ETHERTYPE | F_VLAN | F_FCOE),
  74         (F_FRAGMENTATION | F_MPSHITTYPE | F_ETHERTYPE | F_VNIC_ID | F_PORT),
  75         (F_FRAGMENTATION | F_MPSHITTYPE | F_ETHERTYPE | F_VNIC_ID | F_FCOE),
  76         (F_FRAGMENTATION | F_MPSHITTYPE | F_PROTOCOL | F_TOS | F_VLAN | F_PORT),
  77         (F_FRAGMENTATION | F_MPSHITTYPE | F_PROTOCOL | F_TOS | F_VLAN | F_FCOE),
  78         (F_FRAGMENTATION | F_MPSHITTYPE | F_PROTOCOL | F_TOS | F_VNIC_ID |
  79          F_PORT),
  80         (F_FRAGMENTATION | F_MPSHITTYPE | F_PROTOCOL | F_TOS | F_VNIC_ID |
  81          F_FCOE),
  82         (F_FRAGMENTATION | F_MPSHITTYPE | F_PROTOCOL | F_VLAN | F_PORT |
  83          F_FCOE),
  84         (F_FRAGMENTATION | F_MPSHITTYPE | F_PROTOCOL | F_VNIC_ID | F_PORT |
  85          F_FCOE),
  86         (F_FRAGMENTATION | F_MPSHITTYPE | F_TOS | F_VLAN | F_PORT | F_FCOE),
  87         (F_FRAGMENTATION | F_MPSHITTYPE | F_TOS | F_VNIC_ID | F_PORT | F_FCOE),
  88         (F_FRAGMENTATION | F_MPSHITTYPE | F_VLAN | F_VNIC_ID | F_FCOE),
  89         (F_FRAGMENTATION | F_MACMATCH | F_ETHERTYPE | F_PROTOCOL | F_PORT |
  90          F_FCOE),
  91         (F_FRAGMENTATION | F_MACMATCH | F_ETHERTYPE | F_TOS | F_PORT | F_FCOE),
  92         (F_FRAGMENTATION | F_MACMATCH | F_PROTOCOL | F_VLAN | F_PORT | F_FCOE),
  93         (F_FRAGMENTATION | F_MACMATCH | F_PROTOCOL | F_VNIC_ID | F_PORT |
  94          F_FCOE),
  95         (F_FRAGMENTATION | F_MACMATCH | F_TOS | F_VLAN | F_PORT | F_FCOE),
  96         (F_FRAGMENTATION | F_MACMATCH | F_TOS | F_VNIC_ID | F_PORT | F_FCOE),
  97         (F_FRAGMENTATION | F_ETHERTYPE | F_VLAN | F_PORT | F_FCOE),
  98         (F_FRAGMENTATION | F_ETHERTYPE | F_VNIC_ID | F_PORT | F_FCOE),
  99         (F_FRAGMENTATION | F_PROTOCOL | F_TOS | F_VLAN | F_FCOE),
 100         (F_FRAGMENTATION | F_PROTOCOL | F_TOS | F_VNIC_ID | F_FCOE),
 101         (F_FRAGMENTATION | F_VLAN | F_VNIC_ID | F_PORT | F_FCOE),
 102         (F_MPSHITTYPE | F_MACMATCH | F_ETHERTYPE | F_PROTOCOL | F_PORT |
 103          F_FCOE),
 104         (F_MPSHITTYPE | F_MACMATCH | F_ETHERTYPE | F_TOS | F_PORT | F_FCOE),
 105         (F_MPSHITTYPE | F_MACMATCH | F_PROTOCOL | F_VLAN | F_PORT),
 106         (F_MPSHITTYPE | F_MACMATCH | F_PROTOCOL | F_VNIC_ID | F_PORT),
 107         (F_MPSHITTYPE | F_MACMATCH | F_TOS | F_VLAN | F_PORT),
 108         (F_MPSHITTYPE | F_MACMATCH | F_TOS | F_VNIC_ID | F_PORT),
 109         (F_MPSHITTYPE | F_ETHERTYPE | F_VLAN | F_PORT | F_FCOE),
 110         (F_MPSHITTYPE | F_ETHERTYPE | F_VNIC_ID | F_PORT | F_FCOE),
 111         (F_MPSHITTYPE | F_PROTOCOL | F_TOS | F_VLAN | F_PORT | F_FCOE),
 112         (F_MPSHITTYPE | F_PROTOCOL | F_TOS | F_VNIC_ID | F_PORT | F_FCOE),
 113         (F_MPSHITTYPE | F_VLAN | F_VNIC_ID | F_PORT),
 114 };
 115
 116 /**
 117  * Allocate a chunk of memory. The allocated memory is cleared.
 118  */
 119 void *t4_alloc_mem(size_t size)
 120 {
 121         return rte_zmalloc(NULL, size, 0);
 122 }
 123
 124 /**
 125  * Free memory allocated through t4_alloc_mem().
 126  */
 127 void t4_free_mem(void *addr)
 128 {
 129         rte_free(addr);
 130 }
 131
 132 /*
 133  * Response queue handler for the FW event queue.
 134  */
 135 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
 136                           __rte_unused const struct pkt_gl *gl)
 137 {
 138         u8 opcode = ((const struct rss_header *)rsp)->opcode;
 139
 140         rsp++;                                          /* skip RSS header */
 141
 142         /*
 143          * FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
 144          */
 145         if (unlikely(opcode == CPL_FW4_MSG &&
 146                      ((const struct cpl_fw4_msg *)rsp)->type ==
 147                       FW_TYPE_RSSCPL)) {
 148                 rsp++;
 149                 opcode = ((const struct rss_header *)rsp)->opcode;
 150                 rsp++;
 151                 if (opcode != CPL_SGE_EGR_UPDATE) {
 152                         dev_err(q->adapter, "unexpected FW4/CPL %#x on FW event queue\n",
 153                                 opcode);
 154                         goto out;
 155                 }
 156         }
 157
 158         if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
 159                 /* do nothing */
 160         } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
 161                 const struct cpl_fw6_msg *msg = (const void *)rsp;
 162
 163                 t4_handle_fw_rpl(q->adapter, msg->data);
 164         } else if (opcode == CPL_ABORT_RPL_RSS) {
 165                 const struct cpl_abort_rpl_rss *p = (const void *)rsp;
 166
 167                 cxgbe_hash_del_filter_rpl(q->adapter, p);
 168         } else if (opcode == CPL_SET_TCB_RPL) {
 169                 const struct cpl_set_tcb_rpl *p = (const void *)rsp;
 170
 171                 cxgbe_filter_rpl(q->adapter, p);
 172         } else if (opcode == CPL_ACT_OPEN_RPL) {
 173                 const struct cpl_act_open_rpl *p = (const void *)rsp;
 174
 175                 cxgbe_hash_filter_rpl(q->adapter, p);
 176         } else if (opcode == CPL_L2T_WRITE_RPL) {
 177                 const struct cpl_l2t_write_rpl *p = (const void *)rsp;
 178
 179                 cxgbe_do_l2t_write_rpl(q->adapter, p);
 180         } else if (opcode == CPL_SMT_WRITE_RPL) {
 181                 const struct cpl_smt_write_rpl *p = (const void *)rsp;
 182
 183                 cxgbe_do_smt_write_rpl(q->adapter, p);
 184         } else {
 185                 dev_err(adapter, "unexpected CPL %#x on FW event queue\n",
 186                         opcode);
 187         }
 188 out:
 189         return 0;
 190 }
 191
 192 /**
 193  * Setup sge control queues to pass control information.
 194  */
 195 int cxgbe_setup_sge_ctrl_txq(struct adapter *adapter)
 196 {
 197         struct sge *s = &adapter->sge;
 198         int err = 0, i = 0;
 199
 200         for_each_port(adapter, i) {
 201                 struct port_info *pi = adap2pinfo(adapter, i);
 202                 char name[RTE_ETH_NAME_MAX_LEN];
 203                 struct sge_ctrl_txq *q = &s->ctrlq[i];
 204
 205                 q->q.size = 1024;
 206                 err = t4_sge_alloc_ctrl_txq(adapter, q,
 207                                             adapter->eth_dev,  i,
 208                                             s->fw_evtq.cntxt_id,
 209                                             rte_socket_id());
 210                 if (err) {
 211                         dev_err(adapter, "Failed to alloc ctrl txq. Err: %d",
 212                                 err);
 213                         goto out;
 214                 }
 215                 snprintf(name, sizeof(name), "%s_ctrl_pool_%d",
 216                          pi->eth_dev->device->driver->name,
 217                          pi->eth_dev->data->port_id);
 218                 q->mb_pool = rte_pktmbuf_pool_create(name, s->ctrlq[i].q.size,
 219                                                      RTE_CACHE_LINE_SIZE,
 220                                                      RTE_MBUF_PRIV_ALIGN,
 221                                                      RTE_MBUF_DEFAULT_BUF_SIZE,
 222                                                      SOCKET_ID_ANY);
 223                 if (!q->mb_pool) {
 224                         err = -rte_errno;
 225                         dev_err(adapter,
 226                                 "Can't create ctrl pool for port %d. Err: %d\n",
 227                                 pi->eth_dev->data->port_id, err);
 228                         goto out;
 229                 }
 230         }
 231         return 0;
 232 out:
 233         t4_free_sge_resources(adapter);
 234         return err;
 235 }
 236
 237 /**
 238  * cxgbe_poll_for_completion: Poll rxq for completion
 239  * @q: rxq to poll
 240  * @ms: milliseconds to delay
 241  * @cnt: number of times to poll
 242  * @c: completion to check for 'done' status
 243  *
 244  * Polls the rxq for reples until completion is done or the count
 245  * expires.
 246  */
 247 int cxgbe_poll_for_completion(struct sge_rspq *q, unsigned int ms,
 248                               unsigned int cnt, struct t4_completion *c)
 249 {
 250         unsigned int i;
 251         unsigned int work_done, budget = 32;
 252
 253         if (!c)
 254                 return -EINVAL;
 255
 256         for (i = 0; i < cnt; i++) {
 257                 cxgbe_poll(q, NULL, budget, &work_done);
 258                 t4_os_lock(&c->lock);
 259                 if (c->done) {
 260                         t4_os_unlock(&c->lock);
 261                         return 0;
 262                 }
 263                 t4_os_unlock(&c->lock);
 264                 rte_delay_ms(ms);
 265         }
 266         return -ETIMEDOUT;
 267 }
 268
 269 int cxgbe_setup_sge_fwevtq(struct adapter *adapter)
 270 {
 271         struct sge *s = &adapter->sge;
 272         int err = 0;
 273         int msi_idx = 0;
 274
 275         err = t4_sge_alloc_rxq(adapter, &s->fw_evtq, true, adapter->eth_dev,
 276                                msi_idx, NULL, fwevtq_handler, -1, NULL, 0,
 277                                rte_socket_id());
 278         return err;
 279 }
 280
 281 static int closest_timer(const struct sge *s, int time)
 282 {
 283         unsigned int i, match = 0;
 284         int delta, min_delta = INT_MAX;
 285
 286         for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
 287                 delta = time - s->timer_val[i];
 288                 if (delta < 0)
 289                         delta = -delta;
 290                 if (delta < min_delta) {
 291                         min_delta = delta;
 292                         match = i;
 293                 }
 294         }
 295         return match;
 296 }
 297
 298 static int closest_thres(const struct sge *s, int thres)
 299 {
 300         unsigned int i, match = 0;
 301         int delta, min_delta = INT_MAX;
 302
 303         for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
 304                 delta = thres - s->counter_val[i];
 305                 if (delta < 0)
 306                         delta = -delta;
 307                 if (delta < min_delta) {
 308                         min_delta = delta;
 309                         match = i;
 310                 }
 311         }
 312         return match;
 313 }
 314
 315 /**
 316  * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
 317  * @q: the Rx queue
 318  * @us: the hold-off time in us, or 0 to disable timer
 319  * @cnt: the hold-off packet count, or 0 to disable counter
 320  *
 321  * Sets an Rx queue's interrupt hold-off time and packet count.  At least
 322  * one of the two needs to be enabled for the queue to generate interrupts.
 323  */
 324 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
 325                                unsigned int cnt)
 326 {
 327         struct adapter *adap = q->adapter;
 328         unsigned int timer_val;
 329
 330         if (cnt) {
 331                 int err;
 332                 u32 v, new_idx;
 333
 334                 new_idx = closest_thres(&adap->sge, cnt);
 335                 if (q->desc && q->pktcnt_idx != new_idx) {
 336                         /* the queue has already been created, update it */
 337                         v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
 338                             V_FW_PARAMS_PARAM_X(
 339                             FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
 340                             V_FW_PARAMS_PARAM_YZ(q->cntxt_id);
 341                         err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
 342                                             &v, &new_idx);
 343                         if (err)
 344                                 return err;
 345                 }
 346                 q->pktcnt_idx = new_idx;
 347         }
 348
 349         timer_val = (us == 0) ? X_TIMERREG_RESTART_COUNTER :
 350                                 closest_timer(&adap->sge, us);
 351
 352         if ((us | cnt) == 0)
 353                 q->intr_params = V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX);
 354         else
 355                 q->intr_params = V_QINTR_TIMER_IDX(timer_val) |
 356                                  V_QINTR_CNT_EN(cnt > 0);
 357         return 0;
 358 }
 359
 360 /**
 361  * Allocate an active-open TID and set it to the supplied value.
 362  */
 363 int cxgbe_alloc_atid(struct tid_info *t, void *data)
 364 {
 365         int atid = -1;
 366
 367         t4_os_lock(&t->atid_lock);
 368         if (t->afree) {
 369                 union aopen_entry *p = t->afree;
 370
 371                 atid = p - t->atid_tab;
 372                 t->afree = p->next;
 373                 p->data = data;
 374                 t->atids_in_use++;
 375         }
 376         t4_os_unlock(&t->atid_lock);
 377         return atid;
 378 }
 379
 380 /**
 381  * Release an active-open TID.
 382  */
 383 void cxgbe_free_atid(struct tid_info *t, unsigned int atid)
 384 {
 385         union aopen_entry *p = &t->atid_tab[atid];
 386
 387         t4_os_lock(&t->atid_lock);
 388         p->next = t->afree;
 389         t->afree = p;
 390         t->atids_in_use--;
 391         t4_os_unlock(&t->atid_lock);
 392 }
 393
 394 /**
 395  * Populate a TID_RELEASE WR.  Caller must properly size the skb.
 396  */
 397 static void mk_tid_release(struct rte_mbuf *mbuf, unsigned int tid)
 398 {
 399         struct cpl_tid_release *req;
 400
 401         req = rte_pktmbuf_mtod(mbuf, struct cpl_tid_release *);
 402         INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid);
 403 }
 404
 405 /**
 406  * Release a TID and inform HW.  If we are unable to allocate the release
 407  * message we defer to a work queue.
 408  */
 409 void cxgbe_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid,
 410                       unsigned short family)
 411 {
 412         struct rte_mbuf *mbuf;
 413         struct adapter *adap = container_of(t, struct adapter, tids);
 414
 415         WARN_ON(tid >= t->ntids);
 416
 417         if (t->tid_tab[tid]) {
 418                 t->tid_tab[tid] = NULL;
 419                 __atomic_sub_fetch(&t->conns_in_use, 1, __ATOMIC_RELAXED);
 420                 if (t->hash_base && tid >= t->hash_base) {
 421                         if (family == FILTER_TYPE_IPV4)
 422                                 __atomic_sub_fetch(&t->hash_tids_in_use, 1,
 423                                                    __ATOMIC_RELAXED);
 424                 } else {
 425                         if (family == FILTER_TYPE_IPV4)
 426                                 __atomic_sub_fetch(&t->tids_in_use, 1,
 427                                                    __ATOMIC_RELAXED);
 428                 }
 429         }
 430
 431         mbuf = rte_pktmbuf_alloc((&adap->sge.ctrlq[chan])->mb_pool);
 432         if (mbuf) {
 433                 mbuf->data_len = sizeof(struct cpl_tid_release);
 434                 mbuf->pkt_len = mbuf->data_len;
 435                 mk_tid_release(mbuf, tid);
 436                 t4_mgmt_tx(&adap->sge.ctrlq[chan], mbuf);
 437         }
 438 }
 439
 440 /**
 441  * Insert a TID.
 442  */
 443 void cxgbe_insert_tid(struct tid_info *t, void *data, unsigned int tid,
 444                       unsigned short family)
 445 {
 446         t->tid_tab[tid] = data;
 447         if (t->hash_base && tid >= t->hash_base) {
 448                 if (family == FILTER_TYPE_IPV4)
 449                         __atomic_add_fetch(&t->hash_tids_in_use, 1,
 450                                            __ATOMIC_RELAXED);
 451         } else {
 452                 if (family == FILTER_TYPE_IPV4)
 453                         __atomic_add_fetch(&t->tids_in_use, 1,
 454                                            __ATOMIC_RELAXED);
 455         }
 456
 457         __atomic_add_fetch(&t->conns_in_use, 1, __ATOMIC_RELAXED);
 458 }
 459
 460 /**
 461  * Free TID tables.
 462  */
 463 static void tid_free(struct tid_info *t)
 464 {
 465         if (t->tid_tab) {
 466                 if (t->ftid_bmap)
 467                         rte_bitmap_free(t->ftid_bmap);
 468
 469                 if (t->ftid_bmap_array)
 470                         t4_os_free(t->ftid_bmap_array);
 471
 472                 t4_os_free(t->tid_tab);
 473         }
 474
 475         memset(t, 0, sizeof(struct tid_info));
 476 }
 477
 478 /**
 479  * Allocate and initialize the TID tables.  Returns 0 on success.
 480  */
 481 static int tid_init(struct tid_info *t)
 482 {
 483         size_t size;
 484         unsigned int ftid_bmap_size;
 485         unsigned int natids = t->natids;
 486         unsigned int max_ftids = t->nftids;
 487
 488         ftid_bmap_size = rte_bitmap_get_memory_footprint(t->nftids);
 489         size = t->ntids * sizeof(*t->tid_tab) +
 490                 max_ftids * sizeof(*t->ftid_tab) +
 491                 natids * sizeof(*t->atid_tab);
 492
 493         t->tid_tab = t4_os_alloc(size);
 494         if (!t->tid_tab)
 495                 return -ENOMEM;
 496
 497         t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
 498         t->ftid_tab = (struct filter_entry *)&t->atid_tab[t->natids];
 499         t->ftid_bmap_array = t4_os_alloc(ftid_bmap_size);
 500         if (!t->ftid_bmap_array) {
 501                 tid_free(t);
 502                 return -ENOMEM;
 503         }
 504
 505         t4_os_lock_init(&t->atid_lock);
 506         t4_os_lock_init(&t->ftid_lock);
 507
 508         t->afree = NULL;
 509         t->atids_in_use = 0;
 510         t->tids_in_use = 0;
 511         t->conns_in_use = 0;
 512
 513         /* Setup the free list for atid_tab and clear the stid bitmap. */
 514         if (natids) {
 515                 while (--natids)
 516                         t->atid_tab[natids - 1].next = &t->atid_tab[natids];
 517                 t->afree = t->atid_tab;
 518         }
 519
 520         t->ftid_bmap = rte_bitmap_init(t->nftids, t->ftid_bmap_array,
 521                                        ftid_bmap_size);
 522         if (!t->ftid_bmap) {
 523                 tid_free(t);
 524                 return -ENOMEM;
 525         }
 526
 527         return 0;
 528 }
 529
 530 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
 531                       unsigned int us, unsigned int cnt,
 532                       unsigned int size, unsigned int iqe_size)
 533 {
 534         q->adapter = adap;
 535         cxgb4_set_rspq_intr_params(q, us, cnt);
 536         q->iqe_len = iqe_size;
 537         q->size = size;
 538 }
 539
 540 int cxgbe_cfg_queue_count(struct rte_eth_dev *eth_dev)
 541 {
 542         struct port_info *temp_pi, *pi = eth_dev->data->dev_private;
 543         struct adapter *adap = pi->adapter;
 544         u16 first_txq = 0, first_rxq = 0;
 545         struct sge *s = &adap->sge;
 546         u16 i, max_rxqs, max_txqs;
 547
 548         max_rxqs = s->max_ethqsets;
 549         max_txqs = s->max_ethqsets;
 550         for_each_port(adap, i) {
 551                 temp_pi = adap2pinfo(adap, i);
 552                 if (i == pi->port_id)
 553                         break;
 554
 555                 if (max_rxqs <= temp_pi->n_rx_qsets ||
 556                     max_txqs <= temp_pi->n_tx_qsets)
 557                         return -ENOMEM;
 558
 559                 first_rxq += temp_pi->n_rx_qsets;
 560                 first_txq += temp_pi->n_tx_qsets;
 561                 max_rxqs -= temp_pi->n_rx_qsets;
 562                 max_txqs -= temp_pi->n_tx_qsets;
 563         }
 564
 565         if ((eth_dev->data->nb_rx_queues < 1) ||
 566             (eth_dev->data->nb_tx_queues < 1))
 567                 return -EINVAL;
 568
 569         if (eth_dev->data->nb_rx_queues > max_rxqs ||
 570             eth_dev->data->nb_tx_queues > max_txqs)
 571                 return -EINVAL;
 572
 573         /* We must configure RSS, since config has changed*/
 574         pi->flags &= ~PORT_RSS_DONE;
 575
 576         pi->n_rx_qsets = eth_dev->data->nb_rx_queues;
 577         pi->n_tx_qsets = eth_dev->data->nb_tx_queues;
 578         pi->first_rxqset = first_rxq;
 579         pi->first_txqset = first_txq;
 580
 581         return 0;
 582 }
 583
 584 void cxgbe_cfg_queues_free(struct adapter *adap)
 585 {
 586         if (adap->sge.ethtxq) {
 587                 rte_free(adap->sge.ethtxq);
 588                 adap->sge.ethtxq = NULL;
 589         }
 590
 591         if (adap->sge.ethrxq) {
 592                 rte_free(adap->sge.ethrxq);
 593                 adap->sge.ethrxq = NULL;
 594         }
 595
 596         adap->flags &= ~CFG_QUEUES;
 597 }
 598
 599 int cxgbe_cfg_queues(struct rte_eth_dev *eth_dev)
 600 {
 601         struct port_info *pi = eth_dev->data->dev_private;
 602         struct adapter *adap = pi->adapter;
 603         struct sge *s = &adap->sge;
 604         u16 i;
 605
 606         if (!(adap->flags & CFG_QUEUES)) {
 607                 s->ethrxq = rte_calloc_socket(NULL, s->max_ethqsets,
 608                                               sizeof(struct sge_eth_rxq), 0,
 609                                               rte_socket_id());
 610                 if (!s->ethrxq)
 611                         return -ENOMEM;
 612
 613                 s->ethtxq = rte_calloc_socket(NULL, s->max_ethqsets,
 614                                               sizeof(struct sge_eth_txq), 0,
 615                                               rte_socket_id());
 616                 if (!s->ethtxq) {
 617                         rte_free(s->ethrxq);
 618                         s->ethrxq = NULL;
 619                         return -ENOMEM;
 620                 }
 621
 622                 for (i = 0; i < s->max_ethqsets; i++) {
 623                         struct sge_eth_rxq *r = &s->ethrxq[i];
 624                         struct sge_eth_txq *t = &s->ethtxq[i];
 625
 626                         init_rspq(adap, &r->rspq, 5, 32, 1024, 64);
 627                         r->usembufs = 1;
 628                         r->fl.size = (r->usembufs ? 1024 : 72);
 629
 630                         t->q.size = 1024;
 631                 }
 632
 633                 init_rspq(adap, &adap->sge.fw_evtq, 0, 0, 1024, 64);
 634                 adap->flags |= CFG_QUEUES;
 635         }
 636
 637         return 0;
 638 }
 639
 640 void cxgbe_stats_get(struct port_info *pi, struct port_stats *stats)
 641 {
 642         t4_get_port_stats_offset(pi->adapter, pi->tx_chan, stats,
 643                                  &pi->stats_base);
 644 }
 645
 646 void cxgbe_stats_reset(struct port_info *pi)
 647 {
 648         t4_clr_port_stats(pi->adapter, pi->tx_chan);
 649 }
 650
 651 static void setup_memwin(struct adapter *adap)
 652 {
 653         u32 mem_win0_base;
 654
 655         /* For T5, only relative offset inside the PCIe BAR is passed */
 656         mem_win0_base = MEMWIN0_BASE;
 657
 658         /*
 659          * Set up memory window for accessing adapter memory ranges.  (Read
 660          * back MA register to ensure that changes propagate before we attempt
 661          * to use the new values.)
 662          */
 663         t4_write_reg(adap,
 664                      PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
 665                                          MEMWIN_NIC),
 666                      mem_win0_base | V_BIR(0) |
 667                      V_WINDOW(ilog2(MEMWIN0_APERTURE) - X_WINDOW_SHIFT));
 668         t4_read_reg(adap,
 669                     PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
 670                                         MEMWIN_NIC));
 671 }
 672
 673 int cxgbe_init_rss(struct adapter *adap)
 674 {
 675         unsigned int i;
 676
 677         if (is_pf4(adap)) {
 678                 int err;
 679
 680                 err = t4_init_rss_mode(adap, adap->mbox);
 681                 if (err)
 682                         return err;
 683         }
 684
 685         for_each_port(adap, i) {
 686                 struct port_info *pi = adap2pinfo(adap, i);
 687
 688                 pi->rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
 689                 if (!pi->rss)
 690                         return -ENOMEM;
 691
 692                 pi->rss_hf = CXGBE_RSS_HF_ALL;
 693         }
 694         return 0;
 695 }
 696
 697 /**
 698  * Dump basic information about the adapter.
 699  */
 700 void cxgbe_print_adapter_info(struct adapter *adap)
 701 {
 702         /**
 703          * Hardware/Firmware/etc. Version/Revision IDs.
 704          */
 705         t4_dump_version_info(adap);
 706 }
 707
 708 void cxgbe_print_port_info(struct adapter *adap)
 709 {
 710         int i;
 711         char buf[80];
 712         struct rte_pci_addr *loc = &adap->pdev->addr;
 713
 714         for_each_port(adap, i) {
 715                 const struct port_info *pi = adap2pinfo(adap, i);
 716                 char *bufp = buf;
 717
 718                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M)
 719                         bufp += sprintf(bufp, "100M/");
 720                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G)
 721                         bufp += sprintf(bufp, "1G/");
 722                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G)
 723                         bufp += sprintf(bufp, "10G/");
 724                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G)
 725                         bufp += sprintf(bufp, "25G/");
 726                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G)
 727                         bufp += sprintf(bufp, "40G/");
 728                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G)
 729                         bufp += sprintf(bufp, "50G/");
 730                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G)
 731                         bufp += sprintf(bufp, "100G/");
 732                 if (bufp != buf)
 733                         --bufp;
 734                 sprintf(bufp, "BASE-%s",
 735                         t4_get_port_type_description(
 736                                 (enum fw_port_type)pi->link_cfg.port_type));
 737
 738                 dev_info(adap,
 739                          " " PCI_PRI_FMT " Chelsio rev %d %s %s\n",
 740                          loc->domain, loc->bus, loc->devid, loc->function,
 741                          CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
 742                          (adap->flags & USING_MSIX) ? " MSI-X" :
 743                          (adap->flags & USING_MSI) ? " MSI" : "");
 744         }
 745 }
 746
 747 static int check_devargs_handler(const char *key, const char *value, void *p)
 748 {
 749         if (!strncmp(key, CXGBE_DEVARG_CMN_KEEP_OVLAN, strlen(key)) ||
 750             !strncmp(key, CXGBE_DEVARG_CMN_TX_MODE_LATENCY, strlen(key)) ||
 751             !strncmp(key, CXGBE_DEVARG_VF_FORCE_LINK_UP, strlen(key))) {
 752                 if (!strncmp(value, "1", 1)) {
 753                         bool *dst_val = (bool *)p;
 754
 755                         *dst_val = true;
 756                 }
 757         }
 758
 759         if (!strncmp(key, CXGBE_DEVARG_PF_FILTER_MODE, strlen(key)) ||
 760             !strncmp(key, CXGBE_DEVARG_PF_FILTER_MASK, strlen(key))) {
 761                 u32 *dst_val = (u32 *)p;
 762                 char *endptr = NULL;
 763                 u32 arg_val;
 764
 765                 arg_val = strtoul(value, &endptr, 16);
 766                 if (errno || endptr == value)
 767                         return -EINVAL;
 768
 769                 *dst_val = arg_val;
 770         }
 771
 772         return 0;
 773 }
 774
 775 static int cxgbe_get_devargs(struct rte_devargs *devargs, const char *key,
 776                              void *p)
 777 {
 778         struct rte_kvargs *kvlist;
 779         int ret = 0;
 780
 781         if (!devargs)
 782                 return 0;
 783
 784         kvlist = rte_kvargs_parse(devargs->args, NULL);
 785         if (!kvlist)
 786                 return 0;
 787
 788         if (!rte_kvargs_count(kvlist, key))
 789                 goto out;
 790
 791         ret = rte_kvargs_process(kvlist, key, check_devargs_handler, p);
 792
 793 out:
 794         rte_kvargs_free(kvlist);
 795
 796         return ret;
 797 }
 798
 799 static void cxgbe_get_devargs_int(struct adapter *adap, bool *dst,
 800                                   const char *key, bool default_value)
 801 {
 802         struct rte_pci_device *pdev = adap->pdev;
 803         int ret;
 804         bool devarg_value = default_value;
 805
 806         *dst = default_value;
 807         if (!pdev)
 808                 return;
 809
 810         ret = cxgbe_get_devargs(pdev->device.devargs, key, &devarg_value);
 811         if (ret)
 812                 return;
 813
 814         *dst = devarg_value;
 815 }
 816
 817 static void cxgbe_get_devargs_u32(struct adapter *adap, u32 *dst,
 818                                   const char *key, u32 default_value)
 819 {
 820         struct rte_pci_device *pdev = adap->pdev;
 821         u32 devarg_value = default_value;
 822         int ret;
 823
 824         *dst = default_value;
 825         if (!pdev)
 826                 return;
 827
 828         ret = cxgbe_get_devargs(pdev->device.devargs, key, &devarg_value);
 829         if (ret)
 830                 return;
 831
 832         *dst = devarg_value;
 833 }
 834
 835 void cxgbe_process_devargs(struct adapter *adap)
 836 {
 837         cxgbe_get_devargs_int(adap, &adap->devargs.keep_ovlan,
 838                               CXGBE_DEVARG_CMN_KEEP_OVLAN, false);
 839         cxgbe_get_devargs_int(adap, &adap->devargs.tx_mode_latency,
 840                               CXGBE_DEVARG_CMN_TX_MODE_LATENCY, false);
 841         cxgbe_get_devargs_int(adap, &adap->devargs.force_link_up,
 842                               CXGBE_DEVARG_VF_FORCE_LINK_UP, false);
 843         cxgbe_get_devargs_u32(adap, &adap->devargs.filtermode,
 844                               CXGBE_DEVARG_PF_FILTER_MODE, 0);
 845         cxgbe_get_devargs_u32(adap, &adap->devargs.filtermask,
 846                               CXGBE_DEVARG_PF_FILTER_MASK, 0);
 847 }
 848
 849 static void configure_vlan_types(struct adapter *adapter)
 850 {
 851         int i;
 852
 853         for_each_port(adapter, i) {
 854                 /* OVLAN Type 0x88a8 */
 855                 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN0),
 856                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 857                                  V_OVLAN_ETYPE(M_OVLAN_ETYPE),
 858                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 859                                  V_OVLAN_ETYPE(0x88a8));
 860                 /* OVLAN Type 0x9100 */
 861                 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN1),
 862                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 863                                  V_OVLAN_ETYPE(M_OVLAN_ETYPE),
 864                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 865                                  V_OVLAN_ETYPE(0x9100));
 866
 867                 /* IVLAN 0X8100 */
 868                 t4_set_reg_field(adapter, MPS_PORT_RX_IVLAN(i),
 869                                  V_IVLAN_ETYPE(M_IVLAN_ETYPE),
 870                                  V_IVLAN_ETYPE(0x8100));
 871
 872                 t4_set_reg_field(adapter, MPS_PORT_RX_CTL(i),
 873                                  F_OVLAN_EN0 | F_OVLAN_EN1 |
 874                                  F_IVLAN_EN,
 875                                  F_OVLAN_EN0 | F_OVLAN_EN1 |
 876                                  F_IVLAN_EN);
 877         }
 878
 879         t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG, V_RM_OVLAN(1),
 880                                V_RM_OVLAN(!adapter->devargs.keep_ovlan));
 881 }
 882
 883 static int cxgbe_get_filter_vnic_mode_from_devargs(u32 val)
 884 {
 885         u32 vnic_mode;
 886
 887         vnic_mode = val & (CXGBE_DEVARGS_FILTER_MODE_PF_VF |
 888                            CXGBE_DEVARGS_FILTER_MODE_VLAN_OUTER);
 889         if (vnic_mode) {
 890                 switch (vnic_mode) {
 891                 case CXGBE_DEVARGS_FILTER_MODE_VLAN_OUTER:
 892                         return CXGBE_FILTER_VNIC_MODE_OVLAN;
 893                 case CXGBE_DEVARGS_FILTER_MODE_PF_VF:
 894                         return CXGBE_FILTER_VNIC_MODE_PFVF;
 895                 default:
 896                         return -EINVAL;
 897                 }
 898         }
 899
 900         return CXGBE_FILTER_VNIC_MODE_NONE;
 901 }
 902
 903 static int cxgbe_get_filter_mode_from_devargs(u32 val, bool closest_match)
 904 {
 905         int vnic_mode, fmode = 0;
 906         bool found = false;
 907         u8 i;
 908
 909         if (val >= CXGBE_DEVARGS_FILTER_MODE_MAX) {
 910                 pr_err("Unsupported flags set in filter mode. Must be < 0x%x\n",
 911                        CXGBE_DEVARGS_FILTER_MODE_MAX);
 912                 return -ERANGE;
 913         }
 914
 915         vnic_mode = cxgbe_get_filter_vnic_mode_from_devargs(val);
 916         if (vnic_mode < 0) {
 917                 pr_err("Unsupported Vnic-mode, more than 1 Vnic-mode selected\n");
 918                 return vnic_mode;
 919         }
 920
 921         if (vnic_mode)
 922                 fmode |= F_VNIC_ID;
 923         if (val & CXGBE_DEVARGS_FILTER_MODE_PHYSICAL_PORT)
 924                 fmode |= F_PORT;
 925         if (val & CXGBE_DEVARGS_FILTER_MODE_ETHERNET_DSTMAC)
 926                 fmode |= F_MACMATCH;
 927         if (val & CXGBE_DEVARGS_FILTER_MODE_ETHERNET_ETHTYPE)
 928                 fmode |= F_ETHERTYPE;
 929         if (val & CXGBE_DEVARGS_FILTER_MODE_VLAN_INNER)
 930                 fmode |= F_VLAN;
 931         if (val & CXGBE_DEVARGS_FILTER_MODE_IP_TOS)
 932                 fmode |= F_TOS;
 933         if (val & CXGBE_DEVARGS_FILTER_MODE_IP_PROTOCOL)
 934                 fmode |= F_PROTOCOL;
 935
 936         for (i = 0; i < ARRAY_SIZE(cxgbe_filter_mode_features); i++) {
 937                 if ((cxgbe_filter_mode_features[i] & fmode) == fmode) {
 938                         found = true;
 939                         break;
 940                 }
 941         }
 942
 943         if (!found)
 944                 return -EINVAL;
 945
 946         return closest_match ? cxgbe_filter_mode_features[i] : fmode;
 947 }
 948
 949 static int configure_filter_mode_mask(struct adapter *adap)
 950 {
 951         u32 params[2], val[2], nparams = 0;
 952         int ret;
 953
 954         if (!adap->devargs.filtermode && !adap->devargs.filtermask)
 955                 return 0;
 956
 957         if (!adap->devargs.filtermode || !adap->devargs.filtermask) {
 958                 pr_err("Unsupported, Provide both filtermode and filtermask devargs\n");
 959                 return -EINVAL;
 960         }
 961
 962         if (adap->devargs.filtermask & ~adap->devargs.filtermode) {
 963                 pr_err("Unsupported, filtermask (0x%x) must be subset of filtermode (0x%x)\n",
 964                        adap->devargs.filtermask, adap->devargs.filtermode);
 965
 966                 return -EINVAL;
 967         }
 968
 969         params[0] = CXGBE_FW_PARAM_DEV(FILTER) |
 970                     V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_MODE_MASK);
 971
 972         ret = cxgbe_get_filter_mode_from_devargs(adap->devargs.filtermode,
 973                                                  true);
 974         if (ret < 0) {
 975                 pr_err("Unsupported filtermode devargs combination:0x%x\n",
 976                        adap->devargs.filtermode);
 977                 return ret;
 978         }
 979
 980         val[0] = V_FW_PARAMS_PARAM_FILTER_MODE(ret);
 981
 982         ret = cxgbe_get_filter_mode_from_devargs(adap->devargs.filtermask,
 983                                                  false);
 984         if (ret < 0) {
 985                 pr_err("Unsupported filtermask devargs combination:0x%x\n",
 986                        adap->devargs.filtermask);
 987                 return ret;
 988         }
 989
 990         val[0] |= V_FW_PARAMS_PARAM_FILTER_MASK(ret);
 991
 992         nparams++;
 993
 994         ret = cxgbe_get_filter_vnic_mode_from_devargs(adap->devargs.filtermode);
 995         if (ret < 0)
 996                 return ret;
 997
 998         if (ret) {
 999                 params[1] = CXGBE_FW_PARAM_DEV(FILTER) |
1000                             V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_VNIC_MODE);
1001
1002                 val[1] = ret - 1;
1003
1004                 nparams++;
1005         }
1006
1007         return t4_set_params(adap, adap->mbox, adap->pf, 0, nparams,
1008                              params, val);
1009 }
1010
1011 static void configure_pcie_ext_tag(struct adapter *adapter)
1012 {
1013         u16 v;
1014         int pos = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
1015
1016         if (!pos)
1017                 return;
1018
1019         if (pos > 0) {
1020                 t4_os_pci_read_cfg2(adapter, pos + PCI_EXP_DEVCTL, &v);
1021                 v |= PCI_EXP_DEVCTL_EXT_TAG;
1022                 t4_os_pci_write_cfg2(adapter, pos + PCI_EXP_DEVCTL, v);
1023                 if (is_t6(adapter->params.chip)) {
1024                         t4_set_reg_field(adapter, A_PCIE_CFG2,
1025                                          V_T6_TOTMAXTAG(M_T6_TOTMAXTAG),
1026                                          V_T6_TOTMAXTAG(7));
1027                         t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
1028                                          V_T6_MINTAG(M_T6_MINTAG),
1029                                          V_T6_MINTAG(8));
1030                 } else {
1031                         t4_set_reg_field(adapter, A_PCIE_CFG2,
1032                                          V_TOTMAXTAG(M_TOTMAXTAG),
1033                                          V_TOTMAXTAG(3));
1034                         t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
1035                                          V_MINTAG(M_MINTAG),
1036                                          V_MINTAG(8));
1037                 }
1038         }
1039 }
1040
1041 /* Figure out how many Queue Sets we can support */
1042 void cxgbe_configure_max_ethqsets(struct adapter *adapter)
1043 {
1044         unsigned int ethqsets, reserved;
1045
1046         /* We need to reserve an Ingress Queue for the Asynchronous Firmware
1047          * Event Queue and 1 Control Queue per port.
1048          *
1049          * For each Queue Set, we'll need the ability to allocate two Egress
1050          * Contexts -- one for the Ingress Queue Free List and one for the TX
1051          * Ethernet Queue.
1052          */
1053         reserved = max(adapter->params.nports, 1);
1054         if (is_pf4(adapter)) {
1055                 struct pf_resources *pfres = &adapter->params.pfres;
1056
1057                 ethqsets = min(pfres->niqflint, pfres->nethctrl);
1058                 if (ethqsets > (pfres->neq / 2))
1059                         ethqsets = pfres->neq / 2;
1060         } else {
1061                 struct vf_resources *vfres = &adapter->params.vfres;
1062
1063                 ethqsets = min(vfres->niqflint, vfres->nethctrl);
1064                 if (ethqsets > (vfres->neq / 2))
1065                         ethqsets = vfres->neq / 2;
1066         }
1067
1068         ethqsets -= reserved;
1069         adapter->sge.max_ethqsets = ethqsets;
1070 }
1071
1072 /*
1073  * Tweak configuration based on system architecture, etc.  Most of these have
1074  * defaults assigned to them by Firmware Configuration Files (if we're using
1075  * them) but need to be explicitly set if we're using hard-coded
1076  * initialization. So these are essentially common tweaks/settings for
1077  * Configuration Files and hard-coded initialization ...
1078  */
1079 static int adap_init0_tweaks(struct adapter *adapter)
1080 {
1081         u8 rx_dma_offset;
1082
1083         /*
1084          * Fix up various Host-Dependent Parameters like Page Size, Cache
1085          * Line Size, etc.  The firmware default is for a 4KB Page Size and
1086          * 64B Cache Line Size ...
1087          */
1088         t4_fixup_host_params_compat(adapter, CXGBE_PAGE_SIZE, L1_CACHE_BYTES,
1089                                     T5_LAST_REV);
1090
1091         /*
1092          * Keep the chip default offset to deliver Ingress packets into our
1093          * DMA buffers to zero
1094          */
1095         rx_dma_offset = 0;
1096         t4_set_reg_field(adapter, A_SGE_CONTROL, V_PKTSHIFT(M_PKTSHIFT),
1097                          V_PKTSHIFT(rx_dma_offset));
1098
1099         t4_set_reg_field(adapter, A_SGE_FLM_CFG,
1100                          V_CREDITCNT(M_CREDITCNT) | M_CREDITCNTPACKING,
1101                          V_CREDITCNT(3) | V_CREDITCNTPACKING(1));
1102
1103         t4_set_reg_field(adapter, A_SGE_INGRESS_RX_THRESHOLD,
1104                          V_THRESHOLD_3(M_THRESHOLD_3), V_THRESHOLD_3(32U));
1105
1106         t4_set_reg_field(adapter, A_SGE_CONTROL2, V_IDMAARBROUNDROBIN(1U),
1107                          V_IDMAARBROUNDROBIN(1U));
1108
1109         /*
1110          * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
1111          * adds the pseudo header itself.
1112          */
1113         t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG,
1114                                F_CSUM_HAS_PSEUDO_HDR, 0);
1115
1116         return 0;
1117 }
1118
1119 /*
1120  * Attempt to initialize the adapter via a Firmware Configuration File.
1121  */
1122 static int adap_init0_config(struct adapter *adapter, int reset)
1123 {
1124         u32 finiver, finicsum, cfcsum, param, val;
1125         struct fw_caps_config_cmd caps_cmd;
1126         unsigned long mtype = 0, maddr = 0;
1127         u8 config_issued = 0;
1128         char config_name[20];
1129         int cfg_addr, ret;
1130
1131         /*
1132          * Reset device if necessary.
1133          */
1134         if (reset) {
1135                 ret = t4_fw_reset(adapter, adapter->mbox,
1136                                   F_PIORSTMODE | F_PIORST);
1137                 if (ret < 0) {
1138                         dev_warn(adapter, "Firmware reset failed, error %d\n",
1139                                  -ret);
1140                         goto bye;
1141                 }
1142         }
1143
1144         cfg_addr = t4_flash_cfg_addr(adapter);
1145         if (cfg_addr < 0) {
1146                 ret = cfg_addr;
1147                 dev_warn(adapter, "Finding address for firmware config file in flash failed, error %d\n",
1148                          -ret);
1149                 goto bye;
1150         }
1151
1152         strcpy(config_name, "On Flash");
1153         mtype = FW_MEMTYPE_CF_FLASH;
1154         maddr = cfg_addr;
1155
1156         /* Enable HASH filter region when support is available. */
1157         val = 1;
1158         param = CXGBE_FW_PARAM_DEV(HASHFILTER_WITH_OFLD);
1159         t4_set_params(adapter, adapter->mbox, adapter->pf, 0, 1,
1160                       &param, &val);
1161
1162         /*
1163          * Issue a Capability Configuration command to the firmware to get it
1164          * to parse the Configuration File.  We don't use t4_fw_config_file()
1165          * because we want the ability to modify various features after we've
1166          * processed the configuration file ...
1167          */
1168         memset(&caps_cmd, 0, sizeof(caps_cmd));
1169         caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
1170                                            F_FW_CMD_REQUEST | F_FW_CMD_READ);
1171         caps_cmd.cfvalid_to_len16 =
1172                 cpu_to_be32(F_FW_CAPS_CONFIG_CMD_CFVALID |
1173                             V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
1174                             V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
1175                             FW_LEN16(caps_cmd));
1176         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
1177                          &caps_cmd);
1178         /*
1179          * If the CAPS_CONFIG failed with an ENOENT (for a Firmware
1180          * Configuration File in FLASH), our last gasp effort is to use the
1181          * Firmware Configuration File which is embedded in the firmware.  A
1182          * very few early versions of the firmware didn't have one embedded
1183          * but we can ignore those.
1184          */
1185         if (ret == -ENOENT) {
1186                 dev_info(adapter, "%s: Going for embedded config in firmware..\n",
1187                          __func__);
1188
1189                 memset(&caps_cmd, 0, sizeof(caps_cmd));
1190                 caps_cmd.op_to_write =
1191                         cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
1192                                     F_FW_CMD_REQUEST | F_FW_CMD_READ);
1193                 caps_cmd.cfvalid_to_len16 = cpu_to_be32(FW_LEN16(caps_cmd));
1194                 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
1195                                  sizeof(caps_cmd), &caps_cmd);
1196                 strcpy(config_name, "Firmware Default");
1197         }
1198
1199         config_issued = 1;
1200         if (ret < 0)
1201                 goto bye;
1202
1203         finiver = be32_to_cpu(caps_cmd.finiver);
1204         finicsum = be32_to_cpu(caps_cmd.finicsum);
1205         cfcsum = be32_to_cpu(caps_cmd.cfcsum);
1206         if (finicsum != cfcsum)
1207                 dev_warn(adapter, "Configuration File checksum mismatch: [fini] csum=%#x, computed csum=%#x\n",
1208                          finicsum, cfcsum);
1209
1210         /*
1211          * If we're a pure NIC driver then disable all offloading facilities.
1212          * This will allow the firmware to optimize aspects of the hardware
1213          * configuration which will result in improved performance.
1214          */
1215         caps_cmd.niccaps &= cpu_to_be16(~FW_CAPS_CONFIG_NIC_ETHOFLD);
1216         caps_cmd.toecaps = 0;
1217         caps_cmd.iscsicaps = 0;
1218         caps_cmd.rdmacaps = 0;
1219         caps_cmd.fcoecaps = 0;
1220         caps_cmd.cryptocaps = 0;
1221
1222         /*
1223          * And now tell the firmware to use the configuration we just loaded.
1224          */
1225         caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
1226                                            F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
1227         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
1228         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
1229                          NULL);
1230         if (ret < 0) {
1231                 dev_warn(adapter, "Unable to finalize Firmware Capabilities %d\n",
1232                          -ret);
1233                 goto bye;
1234         }
1235
1236         /*
1237          * Tweak configuration based on system architecture, etc.
1238          */
1239         ret = adap_init0_tweaks(adapter);
1240         if (ret < 0) {
1241                 dev_warn(adapter, "Unable to do init0-tweaks %d\n", -ret);
1242                 goto bye;
1243         }
1244
1245         /*
1246          * And finally tell the firmware to initialize itself using the
1247          * parameters from the Configuration File.
1248          */
1249         ret = t4_fw_initialize(adapter, adapter->mbox);
1250         if (ret < 0) {
1251                 dev_warn(adapter, "Initializing Firmware failed, error %d\n",
1252                          -ret);
1253                 goto bye;
1254         }
1255
1256         /*
1257          * Return successfully and note that we're operating with parameters
1258          * not supplied by the driver, rather than from hard-wired
1259          * initialization constants buried in the driver.
1260          */
1261         dev_info(adapter,
1262                  "Successfully configured using Firmware Configuration File \"%s\", version %#x, computed checksum %#x\n",
1263                  config_name, finiver, cfcsum);
1264
1265         return 0;
1266
1267         /*
1268          * Something bad happened.  Return the error ...  (If the "error"
1269          * is that there's no Configuration File on the adapter we don't
1270          * want to issue a warning since this is fairly common.)
1271          */
1272 bye:
1273         if (config_issued && ret != -ENOENT)
1274                 dev_warn(adapter, "\"%s\" configuration file error %d\n",
1275                          config_name, -ret);
1276
1277         dev_debug(adapter, "%s: returning ret = %d ..\n", __func__, ret);
1278         return ret;
1279 }
1280
1281 static int adap_init0(struct adapter *adap)
1282 {
1283         struct fw_caps_config_cmd caps_cmd;
1284         int ret = 0;
1285         u32 v, port_vec;
1286         enum dev_state state;
1287         u32 params[7], val[7];
1288         int reset = 1;
1289         int mbox = adap->mbox;
1290
1291         /*
1292          * Contact FW, advertising Master capability.
1293          */
1294         ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state);
1295         if (ret < 0) {
1296                 dev_err(adap, "%s: could not connect to FW, error %d\n",
1297                         __func__, -ret);
1298                 goto bye;
1299         }
1300
1301         CXGBE_DEBUG_MBOX(adap, "%s: adap->mbox = %d; ret = %d\n", __func__,
1302                          adap->mbox, ret);
1303
1304         if (ret == mbox)
1305                 adap->flags |= MASTER_PF;
1306
1307         if (state == DEV_STATE_INIT) {
1308                 /*
1309                  * Force halt and reset FW because a previous instance may have
1310                  * exited abnormally without properly shutting down
1311                  */
1312                 ret = t4_fw_halt(adap, adap->mbox, reset);
1313                 if (ret < 0) {
1314                         dev_err(adap, "Failed to halt. Exit.\n");
1315                         goto bye;
1316                 }
1317
1318                 ret = t4_fw_restart(adap, adap->mbox, reset);
1319                 if (ret < 0) {
1320                         dev_err(adap, "Failed to restart. Exit.\n");
1321                         goto bye;
1322                 }
1323                 state = (enum dev_state)((unsigned)state & ~DEV_STATE_INIT);
1324         }
1325
1326         t4_get_version_info(adap);
1327
1328         ret = t4_get_core_clock(adap, &adap->params.vpd);
1329         if (ret < 0) {
1330                 dev_err(adap, "%s: could not get core clock, error %d\n",
1331                         __func__, -ret);
1332                 goto bye;
1333         }
1334
1335         /*
1336          * If the firmware is initialized already (and we're not forcing a
1337          * master initialization), note that we're living with existing
1338          * adapter parameters.  Otherwise, it's time to try initializing the
1339          * adapter ...
1340          */
1341         if (state == DEV_STATE_INIT) {
1342                 dev_info(adap, "Coming up as %s: Adapter already initialized\n",
1343                          adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
1344         } else {
1345                 dev_info(adap, "Coming up as MASTER: Initializing adapter\n");
1346
1347                 ret = adap_init0_config(adap, reset);
1348                 if (ret == -ENOENT) {
1349                         dev_err(adap,
1350                                 "No Configuration File present on adapter. Using hard-wired configuration parameters.\n");
1351                         goto bye;
1352                 }
1353         }
1354         if (ret < 0) {
1355                 dev_err(adap, "could not initialize adapter, error %d\n", -ret);
1356                 goto bye;
1357         }
1358
1359         /* Now that we've successfully configured and initialized the adapter
1360          * (or found it already initialized), we can ask the Firmware what
1361          * resources it has provisioned for us.
1362          */
1363         ret = t4_get_pfres(adap);
1364         if (ret) {
1365                 dev_err(adap->pdev_dev,
1366                         "Unable to retrieve resource provisioning info\n");
1367                 goto bye;
1368         }
1369
1370         /* Find out what ports are available to us. */
1371         v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
1372             V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC);
1373         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
1374         if (ret < 0) {
1375                 dev_err(adap, "%s: failure in t4_query_params; error = %d\n",
1376                         __func__, ret);
1377                 goto bye;
1378         }
1379
1380         adap->params.nports = hweight32(port_vec);
1381         adap->params.portvec = port_vec;
1382
1383         dev_debug(adap, "%s: adap->params.nports = %u\n", __func__,
1384                   adap->params.nports);
1385
1386         /*
1387          * Give the SGE code a chance to pull in anything that it needs ...
1388          * Note that this must be called after we retrieve our VPD parameters
1389          * in order to know how to convert core ticks to seconds, etc.
1390          */
1391         ret = t4_sge_init(adap);
1392         if (ret < 0) {
1393                 dev_err(adap, "t4_sge_init failed with error %d\n",
1394                         -ret);
1395                 goto bye;
1396         }
1397
1398         /*
1399          * Grab some of our basic fundamental operating parameters.
1400          */
1401         params[0] = CXGBE_FW_PARAM_PFVF(L2T_START);
1402         params[1] = CXGBE_FW_PARAM_PFVF(L2T_END);
1403         params[2] = CXGBE_FW_PARAM_PFVF(FILTER_START);
1404         params[3] = CXGBE_FW_PARAM_PFVF(FILTER_END);
1405         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 4, params, val);
1406         if (ret < 0)
1407                 goto bye;
1408         adap->l2t_start = val[0];
1409         adap->l2t_end = val[1];
1410         adap->tids.ftid_base = val[2];
1411         adap->tids.nftids = val[3] - val[2] + 1;
1412
1413         params[0] = CXGBE_FW_PARAM_PFVF(CLIP_START);
1414         params[1] = CXGBE_FW_PARAM_PFVF(CLIP_END);
1415         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
1416         if (ret < 0)
1417                 goto bye;
1418         adap->clipt_start = val[0];
1419         adap->clipt_end = val[1];
1420
1421         /*
1422          * Get device capabilities so we can determine what resources we need
1423          * to manage.
1424          */
1425         memset(&caps_cmd, 0, sizeof(caps_cmd));
1426         caps_cmd.op_to_write = htonl(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
1427                                      F_FW_CMD_REQUEST | F_FW_CMD_READ);
1428         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
1429         ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
1430                          &caps_cmd);
1431         if (ret < 0)
1432                 goto bye;
1433
1434         if ((caps_cmd.niccaps & cpu_to_be16(FW_CAPS_CONFIG_NIC_HASHFILTER)) &&
1435             is_t6(adap->params.chip)) {
1436                 if (cxgbe_init_hash_filter(adap) < 0)
1437                         goto bye;
1438         }
1439
1440         /* See if FW supports FW_FILTER2 work request */
1441         if (is_t4(adap->params.chip)) {
1442                 adap->params.filter2_wr_support = 0;
1443         } else {
1444                 params[0] = CXGBE_FW_PARAM_DEV(FILTER2_WR);
1445                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
1446                                       1, params, val);
1447                 adap->params.filter2_wr_support = (ret == 0 && val[0] != 0);
1448         }
1449
1450         /* Check if FW supports returning vin.
1451          * If this is not supported, driver will interpret
1452          * these values from viid.
1453          */
1454         params[0] = CXGBE_FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN);
1455         ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
1456                               1, params, val);
1457         adap->params.viid_smt_extn_support = (ret == 0 && val[0] != 0);
1458
1459         /* query tid-related parameters */
1460         params[0] = CXGBE_FW_PARAM_DEV(NTID);
1461         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
1462                               params, val);
1463         if (ret < 0)
1464                 goto bye;
1465         adap->tids.ntids = val[0];
1466         adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
1467
1468         /* If we're running on newer firmware, let it know that we're
1469          * prepared to deal with encapsulated CPL messages.  Older
1470          * firmware won't understand this and we'll just get
1471          * unencapsulated messages ...
1472          */
1473         params[0] = CXGBE_FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
1474         val[0] = 1;
1475         (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
1476
1477         /*
1478          * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
1479          * capability.  Earlier versions of the firmware didn't have the
1480          * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
1481          * permission to use ULPTX MEMWRITE DSGL.
1482          */
1483         if (is_t4(adap->params.chip)) {
1484                 adap->params.ulptx_memwrite_dsgl = false;
1485         } else {
1486                 params[0] = CXGBE_FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
1487                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
1488                                       1, params, val);
1489                 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
1490         }
1491
1492         /* Query for max number of packets that can be coalesced for Tx */
1493         params[0] = CXGBE_FW_PARAM_PFVF(MAX_PKTS_PER_ETH_TX_PKTS_WR);
1494         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
1495         if (!ret && val[0] > 0)
1496                 adap->params.max_tx_coalesce_num = val[0];
1497         else
1498                 adap->params.max_tx_coalesce_num = ETH_COALESCE_PKT_NUM;
1499
1500         params[0] = CXGBE_FW_PARAM_DEV(VI_ENABLE_INGRESS_AFTER_LINKUP);
1501         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
1502         adap->params.vi_enable_rx = (ret == 0 && val[0] != 0);
1503
1504         /* Read the RAW MPS entries. In T6, the last 2 TCAM entries
1505          * are reserved for RAW MAC addresses (rawf = 2, one per port).
1506          */
1507         if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
1508                 params[0] = CXGBE_FW_PARAM_PFVF(RAWF_START);
1509                 params[1] = CXGBE_FW_PARAM_PFVF(RAWF_END);
1510                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
1511                                       params, val);
1512                 if (ret == 0) {
1513                         adap->params.rawf_start = val[0];
1514                         adap->params.rawf_size = val[1] - val[0] + 1;
1515                 }
1516         }
1517
1518         /*
1519          * The MTU/MSS Table is initialized by now, so load their values.  If
1520          * we're initializing the adapter, then we'll make any modifications
1521          * we want to the MTU/MSS Table and also initialize the congestion
1522          * parameters.
1523          */
1524         t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
1525         if (state != DEV_STATE_INIT) {
1526                 int i;
1527
1528                 /*
1529                  * The default MTU Table contains values 1492 and 1500.
1530                  * However, for TCP, it's better to have two values which are
1531                  * a multiple of 8 +/- 4 bytes apart near this popular MTU.
1532                  * This allows us to have a TCP Data Payload which is a
1533                  * multiple of 8 regardless of what combination of TCP Options
1534                  * are in use (always a multiple of 4 bytes) which is
1535                  * important for performance reasons.  For instance, if no
1536                  * options are in use, then we have a 20-byte IP header and a
1537                  * 20-byte TCP header.  In this case, a 1500-byte MSS would
1538                  * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
1539                  * which is not a multiple of 8.  So using an MSS of 1488 in
1540                  * this case results in a TCP Data Payload of 1448 bytes which
1541                  * is a multiple of 8.  On the other hand, if 12-byte TCP Time
1542                  * Stamps have been negotiated, then an MTU of 1500 bytes
1543                  * results in a TCP Data Payload of 1448 bytes which, as
1544                  * above, is a multiple of 8 bytes ...
1545                  */
1546                 for (i = 0; i < NMTUS; i++)
1547                         if (adap->params.mtus[i] == 1492) {
1548                                 adap->params.mtus[i] = 1488;
1549                                 break;
1550                         }
1551
1552                 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
1553                              adap->params.b_wnd);
1554         }
1555         t4_init_sge_params(adap);
1556         ret = configure_filter_mode_mask(adap);
1557         if (ret < 0)
1558                 goto bye;
1559         t4_init_tp_params(adap);
1560         configure_pcie_ext_tag(adap);
1561         configure_vlan_types(adap);
1562         cxgbe_configure_max_ethqsets(adap);
1563
1564         adap->params.drv_memwin = MEMWIN_NIC;
1565         adap->flags |= FW_OK;
1566         dev_debug(adap, "%s: returning zero..\n", __func__);
1567         return 0;
1568
1569         /*
1570          * Something bad happened.  If a command timed out or failed with EIO
1571          * FW does not operate within its spec or something catastrophic
1572          * happened to HW/FW, stop issuing commands.
1573          */
1574 bye:
1575         if (ret != -ETIMEDOUT && ret != -EIO)
1576                 t4_fw_bye(adap, adap->mbox);
1577         return ret;
1578 }
1579
1580 /**
1581  * t4_os_portmod_changed - handle port module changes
1582  * @adap: the adapter associated with the module change
1583  * @port_id: the port index whose module status has changed
1584  *
1585  * This is the OS-dependent handler for port module changes.  It is
1586  * invoked when a port module is removed or inserted for any OS-specific
1587  * processing.
1588  */
1589 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
1590 {
1591         static const char * const mod_str[] = {
1592                 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
1593         };
1594
1595         const struct port_info *pi = adap2pinfo(adap, port_id);
1596
1597         if (pi->link_cfg.mod_type == FW_PORT_MOD_TYPE_NONE)
1598                 dev_info(adap, "Port%d: port module unplugged\n", pi->port_id);
1599         else if (pi->link_cfg.mod_type < ARRAY_SIZE(mod_str))
1600                 dev_info(adap, "Port%d: %s port module inserted\n", pi->port_id,
1601                          mod_str[pi->link_cfg.mod_type]);
1602         else if (pi->link_cfg.mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
1603                 dev_info(adap, "Port%d: unsupported port module inserted\n",
1604                          pi->port_id);
1605         else if (pi->link_cfg.mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
1606                 dev_info(adap, "Port%d: unknown port module inserted\n",
1607                          pi->port_id);
1608         else if (pi->link_cfg.mod_type == FW_PORT_MOD_TYPE_ERROR)
1609                 dev_info(adap, "Port%d: transceiver module error\n",
1610                          pi->port_id);
1611         else
1612                 dev_info(adap, "Port%d: unknown module type %d inserted\n",
1613                          pi->port_id, pi->link_cfg.mod_type);
1614 }
1615
1616 void t4_os_link_changed(struct adapter *adap, int port_id)
1617 {
1618         struct port_info *pi = adap2pinfo(adap, port_id);
1619
1620         /* If link status has not changed or if firmware doesn't
1621          * support enabling/disabling VI's Rx path during runtime,
1622          * then return.
1623          */
1624         if (adap->params.vi_enable_rx == 0 ||
1625             pi->vi_en_rx == pi->link_cfg.link_ok)
1626                 return;
1627
1628         /* Don't enable VI Rx path, if link has been administratively
1629          * turned off.
1630          */
1631         if (pi->vi_en_tx == 0 && pi->vi_en_rx == 0)
1632                 return;
1633
1634         /* When link goes down, disable the port's Rx path to drop
1635          * Rx traffic closer to the wire, instead of processing it
1636          * further in the Rx pipeline. The Rx path will be re-enabled
1637          * once the link up message comes in firmware event queue.
1638          */
1639         pi->vi_en_rx = pi->link_cfg.link_ok;
1640         t4_enable_vi(adap, adap->mbox, pi->viid, pi->vi_en_rx, pi->vi_en_tx);
1641 }
1642
1643 bool cxgbe_force_linkup(struct adapter *adap)
1644 {
1645         if (is_pf4(adap))
1646                 return false;   /* force_linkup not required for pf driver */
1647
1648         return adap->devargs.force_link_up;
1649 }
1650
1651 /**
1652  * link_start - enable a port
1653  * @dev: the port to enable
1654  *
1655  * Performs the MAC and PHY actions needed to enable a port.
1656  */
1657 int cxgbe_link_start(struct port_info *pi)
1658 {
1659         struct adapter *adapter = pi->adapter;
1660         u64 conf_offloads;
1661         unsigned int mtu;
1662         int ret;
1663
1664         mtu = pi->eth_dev->data->mtu;
1665
1666         conf_offloads = pi->eth_dev->data->dev_conf.rxmode.offloads;
1667
1668         /*
1669          * We do not set address filters and promiscuity here, the stack does
1670          * that step explicitly.
1671          */
1672         ret = t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, -1, -1, -1,
1673                             !!(conf_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP),
1674                             true);
1675         if (ret == 0) {
1676                 ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt,
1677                                 (u8 *)&pi->eth_dev->data->mac_addrs[0]);
1678                 if (ret >= 0) {
1679                         pi->xact_addr_filt = ret;
1680                         ret = 0;
1681                 }
1682         }
1683         if (ret == 0 && is_pf4(adapter))
1684                 ret = t4_link_l1cfg(pi, pi->link_cfg.admin_caps);
1685         if (ret == 0) {
1686                 /* Disable VI Rx until link up message is received in
1687                  * firmware event queue, if firmware supports enabling/
1688                  * disabling VI Rx at runtime.
1689                  */
1690                 pi->vi_en_rx = adapter->params.vi_enable_rx ? 0 : 1;
1691                 pi->vi_en_tx = 1;
1692                 ret = t4_enable_vi_params(adapter, adapter->mbox, pi->viid,
1693                                           pi->vi_en_rx, pi->vi_en_tx, false);
1694         }
1695
1696         if (ret == 0 && cxgbe_force_linkup(adapter))
1697                 pi->eth_dev->data->dev_link.link_status = RTE_ETH_LINK_UP;
1698         return ret;
1699 }
1700
1701 /**
1702  * cxgbe_write_rss_conf - flash the RSS configuration for a given port
1703  * @pi: the port
1704  * @rss_hf: Hash configuration to apply
1705  */
1706 int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t rss_hf)
1707 {
1708         struct adapter *adapter = pi->adapter;
1709         const struct sge_eth_rxq *rxq;
1710         u64 flags = 0;
1711         u16 rss;
1712         int err;
1713
1714         /*  Should never be called before setting up sge eth rx queues */
1715         if (!(adapter->flags & FULL_INIT_DONE)) {
1716                 dev_err(adap, "%s No RXQs available on port %d\n",
1717                         __func__, pi->port_id);
1718                 return -EINVAL;
1719         }
1720
1721         /* Don't allow unsupported hash functions */
1722         if (rss_hf & ~CXGBE_RSS_HF_ALL)
1723                 return -EINVAL;
1724
1725         if (rss_hf & CXGBE_RSS_HF_IPV4_MASK)
1726                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
1727
1728         if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_TCP)
1729                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
1730
1731         if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_UDP)
1732                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
1733                          F_FW_RSS_VI_CONFIG_CMD_UDPEN;
1734
1735         if (rss_hf & CXGBE_RSS_HF_IPV6_MASK)
1736                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
1737
1738         if (rss_hf & CXGBE_RSS_HF_TCP_IPV6_MASK)
1739                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
1740                          F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
1741
1742         if (rss_hf & CXGBE_RSS_HF_UDP_IPV6_MASK)
1743                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
1744                          F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
1745                          F_FW_RSS_VI_CONFIG_CMD_UDPEN;
1746
1747         rxq = &adapter->sge.ethrxq[pi->first_rxqset];
1748         rss = rxq[0].rspq.abs_id;
1749
1750         /* If Tunnel All Lookup isn't specified in the global RSS
1751          * Configuration, then we need to specify a default Ingress
1752          * Queue for any ingress packets which aren't hashed.  We'll
1753          * use our first ingress queue ...
1754          */
1755         err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
1756                                flags, rss);
1757         return err;
1758 }
1759
1760 /**
1761  * cxgbe_write_rss - write the RSS table for a given port
1762  * @pi: the port
1763  * @queues: array of queue indices for RSS
1764  *
1765  * Sets up the portion of the HW RSS table for the port's VI to distribute
1766  * packets to the Rx queues in @queues.
1767  */
1768 int cxgbe_write_rss(const struct port_info *pi, const u16 *queues)
1769 {
1770         u16 *rss;
1771         int i, err;
1772         struct adapter *adapter = pi->adapter;
1773         const struct sge_eth_rxq *rxq;
1774
1775         /*  Should never be called before setting up sge eth rx queues */
1776         BUG_ON(!(adapter->flags & FULL_INIT_DONE));
1777
1778         rxq = &adapter->sge.ethrxq[pi->first_rxqset];
1779         rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
1780         if (!rss)
1781                 return -ENOMEM;
1782
1783         /* map the queue indices to queue ids */
1784         for (i = 0; i < pi->rss_size; i++, queues++)
1785                 rss[i] = rxq[*queues].rspq.abs_id;
1786
1787         err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
1788                                   pi->rss_size, rss, pi->rss_size);
1789         rte_free(rss);
1790         return err;
1791 }
1792
1793 /**
1794  * setup_rss - configure RSS
1795  * @adapter: the adapter
1796  *
1797  * Sets up RSS to distribute packets to multiple receive queues.  We
1798  * configure the RSS CPU lookup table to distribute to the number of HW
1799  * receive queues, and the response queue lookup table to narrow that
1800  * down to the response queues actually configured for each port.
1801  * We always configure the RSS mapping for all ports since the mapping
1802  * table has plenty of entries.
1803  */
1804 int cxgbe_setup_rss(struct port_info *pi)
1805 {
1806         int j, err;
1807         struct adapter *adapter = pi->adapter;
1808
1809         dev_debug(adapter, "%s:  pi->rss_size = %u; pi->n_rx_qsets = %u\n",
1810                   __func__, pi->rss_size, pi->n_rx_qsets);
1811
1812         if (!(pi->flags & PORT_RSS_DONE)) {
1813                 if (adapter->flags & FULL_INIT_DONE) {
1814                         /* Fill default values with equal distribution */
1815                         for (j = 0; j < pi->rss_size; j++)
1816                                 pi->rss[j] = j % pi->n_rx_qsets;
1817
1818                         err = cxgbe_write_rss(pi, pi->rss);
1819                         if (err)
1820                                 return err;
1821
1822                         err = cxgbe_write_rss_conf(pi, pi->rss_hf);
1823                         if (err)
1824                                 return err;
1825                         pi->flags |= PORT_RSS_DONE;
1826                 }
1827         }
1828         return 0;
1829 }
1830
1831 /*
1832  * Enable NAPI scheduling and interrupt generation for all Rx queues.
1833  */
1834 static void enable_rx(struct adapter *adap, struct sge_rspq *q)
1835 {
1836         /* 0-increment GTS to start the timer and enable interrupts */
1837         t4_write_reg(adap, is_pf4(adap) ? MYPF_REG(A_SGE_PF_GTS) :
1838                                           T4VF_SGE_BASE_ADDR + A_SGE_VF_GTS,
1839                      V_SEINTARM(q->intr_params) |
1840                      V_INGRESSQID(q->cntxt_id));
1841 }
1842
1843 void cxgbe_enable_rx_queues(struct port_info *pi)
1844 {
1845         struct adapter *adap = pi->adapter;
1846         struct sge *s = &adap->sge;
1847         unsigned int i;
1848
1849         for (i = 0; i < pi->n_rx_qsets; i++)
1850                 enable_rx(adap, &s->ethrxq[pi->first_rxqset + i].rspq);
1851 }
1852
1853 /**
1854  * fw_caps_to_speed_caps - translate Firmware Port Caps to Speed Caps.
1855  * @port_type: Firmware Port Type
1856  * @fw_caps: Firmware Port Capabilities
1857  * @speed_caps: Device Info Speed Capabilities
1858  *
1859  * Translate a Firmware Port Capabilities specification to Device Info
1860  * Speed Capabilities.
1861  */
1862 static void fw_caps_to_speed_caps(enum fw_port_type port_type,
1863                                   unsigned int fw_caps,
1864                                   u32 *speed_caps)
1865 {
1866 #define SET_SPEED(__speed_name) \
1867         do { \
1868                 *speed_caps |= RTE_ETH_LINK_ ## __speed_name; \
1869         } while (0)
1870
1871 #define FW_CAPS_TO_SPEED(__fw_name) \
1872         do { \
1873                 if (fw_caps & FW_PORT_CAP32_ ## __fw_name) \
1874                         SET_SPEED(__fw_name); \
1875         } while (0)
1876
1877         switch (port_type) {
1878         case FW_PORT_TYPE_BT_SGMII:
1879         case FW_PORT_TYPE_BT_XFI:
1880         case FW_PORT_TYPE_BT_XAUI:
1881                 FW_CAPS_TO_SPEED(SPEED_100M);
1882                 FW_CAPS_TO_SPEED(SPEED_1G);
1883                 FW_CAPS_TO_SPEED(SPEED_10G);
1884                 break;
1885
1886         case FW_PORT_TYPE_KX4:
1887         case FW_PORT_TYPE_KX:
1888         case FW_PORT_TYPE_FIBER_XFI:
1889         case FW_PORT_TYPE_FIBER_XAUI:
1890         case FW_PORT_TYPE_SFP:
1891         case FW_PORT_TYPE_QSFP_10G:
1892         case FW_PORT_TYPE_QSA:
1893                 FW_CAPS_TO_SPEED(SPEED_1G);
1894                 FW_CAPS_TO_SPEED(SPEED_10G);
1895                 break;
1896
1897         case FW_PORT_TYPE_KR:
1898                 SET_SPEED(SPEED_10G);
1899                 break;
1900
1901         case FW_PORT_TYPE_BP_AP:
1902         case FW_PORT_TYPE_BP4_AP:
1903                 SET_SPEED(SPEED_1G);
1904                 SET_SPEED(SPEED_10G);
1905                 break;
1906
1907         case FW_PORT_TYPE_BP40_BA:
1908         case FW_PORT_TYPE_QSFP:
1909                 SET_SPEED(SPEED_40G);
1910                 break;
1911
1912         case FW_PORT_TYPE_CR_QSFP:
1913         case FW_PORT_TYPE_SFP28:
1914         case FW_PORT_TYPE_KR_SFP28:
1915                 FW_CAPS_TO_SPEED(SPEED_1G);
1916                 FW_CAPS_TO_SPEED(SPEED_10G);
1917                 FW_CAPS_TO_SPEED(SPEED_25G);
1918                 break;
1919
1920         case FW_PORT_TYPE_CR2_QSFP:
1921                 SET_SPEED(SPEED_50G);
1922                 break;
1923
1924         case FW_PORT_TYPE_KR4_100G:
1925         case FW_PORT_TYPE_CR4_QSFP:
1926                 FW_CAPS_TO_SPEED(SPEED_25G);
1927                 FW_CAPS_TO_SPEED(SPEED_40G);
1928                 FW_CAPS_TO_SPEED(SPEED_50G);
1929                 FW_CAPS_TO_SPEED(SPEED_100G);
1930                 break;
1931
1932         default:
1933                 break;
1934         }
1935
1936 #undef FW_CAPS_TO_SPEED
1937 #undef SET_SPEED
1938 }
1939
1940 /**
1941  * cxgbe_get_speed_caps - Fetch supported speed capabilities
1942  * @pi: Underlying port's info
1943  * @speed_caps: Device Info speed capabilities
1944  *
1945  * Fetch supported speed capabilities of the underlying port.
1946  */
1947 void cxgbe_get_speed_caps(struct port_info *pi, u32 *speed_caps)
1948 {
1949         *speed_caps = 0;
1950
1951         fw_caps_to_speed_caps(pi->link_cfg.port_type, pi->link_cfg.pcaps,
1952                               speed_caps);
1953
1954         if (!(pi->link_cfg.pcaps & FW_PORT_CAP32_ANEG))
1955                 *speed_caps |= RTE_ETH_LINK_SPEED_FIXED;
1956 }
1957
1958 /**
1959  * cxgbe_set_link_status - Set device link up or down.
1960  * @pi: Underlying port's info
1961  * @status: 0 - down, 1 - up
1962  *
1963  * Set the device link up or down.
1964  */
1965 int cxgbe_set_link_status(struct port_info *pi, bool status)
1966 {
1967         struct adapter *adapter = pi->adapter;
1968         int err = 0;
1969
1970         /* Wait for link up message from firmware to enable Rx path,
1971          * if firmware supports enabling/disabling VI Rx at runtime.
1972          */
1973         pi->vi_en_rx = adapter->params.vi_enable_rx ? 0 : status;
1974         pi->vi_en_tx = status;
1975         err = t4_enable_vi(adapter, adapter->mbox, pi->viid, pi->vi_en_rx,
1976                            pi->vi_en_tx);
1977         if (err) {
1978                 dev_err(adapter, "%s: disable_vi failed: %d\n", __func__, err);
1979                 return err;
1980         }
1981
1982         if (!status)
1983                 t4_reset_link_config(adapter, pi->pidx);
1984
1985         return 0;
1986 }
1987
1988 /**
1989  * cxgb_up - enable the adapter
1990  * @adap: adapter being enabled
1991  *
1992  * Called when the first port is enabled, this function performs the
1993  * actions necessary to make an adapter operational, such as completing
1994  * the initialization of HW modules, and enabling interrupts.
1995  */
1996 int cxgbe_up(struct adapter *adap)
1997 {
1998         enable_rx(adap, &adap->sge.fw_evtq);
1999         t4_sge_tx_monitor_start(adap);
2000         if (is_pf4(adap))
2001                 t4_intr_enable(adap);
2002         adap->flags |= FULL_INIT_DONE;
2003
2004         /* TODO: deadman watchdog ?? */
2005         return 0;
2006 }
2007
2008 /*
2009  * Close the port
2010  */
2011 int cxgbe_down(struct port_info *pi)
2012 {
2013         return cxgbe_set_link_status(pi, false);
2014 }
2015
2016 /*
2017  * Release resources when all the ports have been stopped.
2018  */
2019 void cxgbe_close(struct adapter *adapter)
2020 {
2021         if (adapter->flags & FULL_INIT_DONE) {
2022                 tid_free(&adapter->tids);
2023                 t4_cleanup_mpstcam(adapter);
2024                 t4_cleanup_clip_tbl(adapter);
2025                 t4_cleanup_l2t(adapter);
2026                 t4_cleanup_smt(adapter);
2027                 if (is_pf4(adapter))
2028                         t4_intr_disable(adapter);
2029                 t4_sge_tx_monitor_stop(adapter);
2030                 t4_free_sge_resources(adapter);
2031                 adapter->flags &= ~FULL_INIT_DONE;
2032         }
2033
2034         cxgbe_cfg_queues_free(adapter);
2035
2036         if (is_pf4(adapter) && (adapter->flags & FW_OK))
2037                 t4_fw_bye(adapter, adapter->mbox);
2038 }
2039
2040 static void adap_smt_index(struct adapter *adapter, u32 *smt_start_idx,
2041                            u32 *smt_size)
2042 {
2043         u32 params[2], smt_val[2];
2044         int ret;
2045
2046         params[0] = CXGBE_FW_PARAM_PFVF(GET_SMT_START);
2047         params[1] = CXGBE_FW_PARAM_PFVF(GET_SMT_SIZE);
2048
2049         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2050                               2, params, smt_val);
2051
2052         /* if FW doesn't recognize this command then set it to default setting
2053          * which is start index as 0 and size as 256.
2054          */
2055         if (ret < 0) {
2056                 *smt_start_idx = 0;
2057                 *smt_size = SMT_SIZE;
2058         } else {
2059                 *smt_start_idx = smt_val[0];
2060                 /* smt size can be zero, if nsmt is not yet configured in
2061                  * the config file or set as zero, then configure all the
2062                  * remaining entries to this PF itself.
2063                  */
2064                 if (!smt_val[1])
2065                         *smt_size = SMT_SIZE - *smt_start_idx;
2066                 else
2067                         *smt_size = smt_val[1];
2068         }
2069 }
2070
2071 int cxgbe_probe(struct adapter *adapter)
2072 {
2073         u32 smt_start_idx, smt_size;
2074         struct port_info *pi;
2075         int func, i;
2076         int err = 0;
2077         u32 whoami;
2078         int chip;
2079
2080         whoami = t4_read_reg(adapter, A_PL_WHOAMI);
2081         chip = t4_get_chip_type(adapter,
2082                         CHELSIO_PCI_ID_VER(adapter->pdev->id.device_id));
2083         if (chip < 0)
2084                 return chip;
2085
2086         func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ?
2087                G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
2088
2089         adapter->mbox = func;
2090         adapter->pf = func;
2091
2092         t4_os_lock_init(&adapter->mbox_lock);
2093         TAILQ_INIT(&adapter->mbox_list);
2094         t4_os_lock_init(&adapter->win0_lock);
2095
2096         err = t4_prep_adapter(adapter);
2097         if (err)
2098                 return err;
2099
2100         setup_memwin(adapter);
2101         err = adap_init0(adapter);
2102         if (err) {
2103                 dev_err(adapter, "%s: Adapter initialization failed, error %d\n",
2104                         __func__, err);
2105                 goto out_free;
2106         }
2107
2108         if (!is_t4(adapter->params.chip)) {
2109                 /*
2110                  * The userspace doorbell BAR is split evenly into doorbell
2111                  * regions, each associated with an egress queue.  If this
2112                  * per-queue region is large enough (at least UDBS_SEG_SIZE)
2113                  * then it can be used to submit a tx work request with an
2114                  * implied doorbell.  Enable write combining on the BAR if
2115                  * there is room for such work requests.
2116                  */
2117                 int s_qpp, qpp, num_seg;
2118
2119                 s_qpp = (S_QUEUESPERPAGEPF0 +
2120                         (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) *
2121                         adapter->pf);
2122                 qpp = 1 << ((t4_read_reg(adapter,
2123                                 A_SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp)
2124                                 & M_QUEUESPERPAGEPF0);
2125                 num_seg = CXGBE_PAGE_SIZE / UDBS_SEG_SIZE;
2126                 if (qpp > num_seg)
2127                         dev_warn(adapter, "Incorrect SGE EGRESS QUEUES_PER_PAGE configuration, continuing in debug mode\n");
2128
2129                 adapter->bar2 = (void *)adapter->pdev->mem_resource[2].addr;
2130                 if (!adapter->bar2) {
2131                         dev_err(adapter, "cannot map device bar2 region\n");
2132                         err = -ENOMEM;
2133                         goto out_free;
2134                 }
2135                 t4_write_reg(adapter, A_SGE_STAT_CFG, V_STATSOURCE_T5(7) |
2136                              V_STATMODE(0));
2137         }
2138
2139         for_each_port(adapter, i) {
2140                 const unsigned int numa_node = rte_socket_id();
2141                 char name[RTE_ETH_NAME_MAX_LEN];
2142                 struct rte_eth_dev *eth_dev;
2143
2144                 snprintf(name, sizeof(name), "%s_%d",
2145                          adapter->pdev->device.name, i);
2146
2147                 if (i == 0) {
2148                         /* First port is already allocated by DPDK */
2149                         eth_dev = adapter->eth_dev;
2150                         goto allocate_mac;
2151                 }
2152
2153                 /*
2154                  * now do all data allocation - for eth_dev structure,
2155                  * and internal (private) data for the remaining ports
2156                  */
2157
2158                 /* reserve an ethdev entry */
2159                 eth_dev = rte_eth_dev_allocate(name);
2160                 if (!eth_dev)
2161                         goto out_free;
2162
2163                 eth_dev->data->dev_private =
2164                         rte_zmalloc_socket(name, sizeof(struct port_info),
2165                                            RTE_CACHE_LINE_SIZE, numa_node);
2166                 if (!eth_dev->data->dev_private)
2167                         goto out_free;
2168
2169 allocate_mac:
2170                 pi = eth_dev->data->dev_private;
2171                 adapter->port[i] = pi;
2172                 pi->eth_dev = eth_dev;
2173                 pi->adapter = adapter;
2174                 pi->xact_addr_filt = -1;
2175                 pi->port_id = i;
2176                 pi->pidx = i;
2177
2178                 pi->eth_dev->device = &adapter->pdev->device;
2179                 pi->eth_dev->dev_ops = adapter->eth_dev->dev_ops;
2180                 pi->eth_dev->tx_pkt_burst = adapter->eth_dev->tx_pkt_burst;
2181                 pi->eth_dev->rx_pkt_burst = adapter->eth_dev->rx_pkt_burst;
2182
2183                 rte_eth_copy_pci_info(pi->eth_dev, adapter->pdev);
2184
2185                 pi->eth_dev->data->mac_addrs = rte_zmalloc(name,
2186                                                         RTE_ETHER_ADDR_LEN, 0);
2187                 if (!pi->eth_dev->data->mac_addrs) {
2188                         dev_err(adapter, "%s: Mem allocation failed for storing mac addr, aborting\n",
2189                                 __func__);
2190                         err = -1;
2191                         goto out_free;
2192                 }
2193
2194                 if (i > 0) {
2195                         /* First port will be notified by upper layer */
2196                         rte_eth_dev_probing_finish(eth_dev);
2197                 }
2198         }
2199
2200         if (adapter->flags & FW_OK) {
2201                 err = t4_port_init(adapter, adapter->mbox, adapter->pf, 0);
2202                 if (err) {
2203                         dev_err(adapter, "%s: t4_port_init failed with err %d\n",
2204                                 __func__, err);
2205                         goto out_free;
2206                 }
2207         }
2208
2209         err = cxgbe_cfg_queues(adapter->eth_dev);
2210         if (err)
2211                 goto out_free;
2212
2213         cxgbe_print_adapter_info(adapter);
2214         cxgbe_print_port_info(adapter);
2215
2216         adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
2217                                           adapter->clipt_end);
2218         if (!adapter->clipt) {
2219                 /* We tolerate a lack of clip_table, giving up some
2220                  * functionality
2221                  */
2222                 dev_warn(adapter, "could not allocate CLIP. Continuing\n");
2223         }
2224
2225         adap_smt_index(adapter, &smt_start_idx, &smt_size);
2226         adapter->smt = t4_init_smt(smt_start_idx, smt_size);
2227         if (!adapter->smt)
2228                 dev_warn(adapter, "could not allocate SMT, continuing\n");
2229
2230         adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end);
2231         if (!adapter->l2t) {
2232                 /* We tolerate a lack of L2T, giving up some functionality */
2233                 dev_warn(adapter, "could not allocate L2T. Continuing\n");
2234         }
2235
2236         if (tid_init(&adapter->tids) < 0) {
2237                 /* Disable filtering support */
2238                 dev_warn(adapter, "could not allocate TID table, "
2239                          "filter support disabled. Continuing\n");
2240         }
2241
2242         t4_os_lock_init(&adapter->flow_lock);
2243
2244         adapter->mpstcam = t4_init_mpstcam(adapter);
2245         if (!adapter->mpstcam)
2246                 dev_warn(adapter, "could not allocate mps tcam table."
2247                          " Continuing\n");
2248
2249         if (is_hashfilter(adapter)) {
2250                 if (t4_read_reg(adapter, A_LE_DB_CONFIG) & F_HASHEN) {
2251                         u32 hash_base, hash_reg;
2252
2253                         hash_reg = A_LE_DB_TID_HASHBASE;
2254                         hash_base = t4_read_reg(adapter, hash_reg);
2255                         adapter->tids.hash_base = hash_base / 4;
2256                 }
2257         } else {
2258                 /* Disable hash filtering support */
2259                 dev_warn(adapter,
2260                          "Maskless filter support disabled. Continuing\n");
2261         }
2262
2263         err = cxgbe_init_rss(adapter);
2264         if (err)
2265                 goto out_free;
2266
2267         return 0;
2268
2269 out_free:
2270         cxgbe_cfg_queues_free(adapter);
2271
2272         for_each_port(adapter, i) {
2273                 pi = adap2pinfo(adapter, i);
2274                 if (pi->viid != 0)
2275                         t4_free_vi(adapter, adapter->mbox, adapter->pf,
2276                                    0, pi->viid);
2277                 rte_eth_dev_release_port(pi->eth_dev);
2278         }
2279
2280         if (adapter->flags & FW_OK)
2281                 t4_fw_bye(adapter, adapter->mbox);
2282         return -err;
2283 }