drivers/net/cxgbe/cxgbe_main.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Chelsio Communications.
   3  * All rights reserved.
   4  */
   5
   6 #include <sys/queue.h>
   7 #include <stdio.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <string.h>
  11 #include <unistd.h>
  12 #include <stdarg.h>
  13 #include <inttypes.h>
  14 #include <netinet/in.h>
  15
  16 #include <rte_byteorder.h>
  17 #include <rte_common.h>
  18 #include <rte_cycles.h>
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_atomic.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_tailq.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <rte_ethdev_driver.h>
  31 #include <rte_ethdev_pci.h>
  32 #include <rte_random.h>
  33 #include <rte_dev.h>
  34 #include <rte_kvargs.h>
  35
  36 #include "common.h"
  37 #include "t4_regs.h"
  38 #include "t4_msg.h"
  39 #include "cxgbe.h"
  40
  41 /**
  42  * Allocate a chunk of memory. The allocated memory is cleared.
  43  */
  44 void *t4_alloc_mem(size_t size)
  45 {
  46         return rte_zmalloc(NULL, size, 0);
  47 }
  48
  49 /**
  50  * Free memory allocated through t4_alloc_mem().
  51  */
  52 void t4_free_mem(void *addr)
  53 {
  54         rte_free(addr);
  55 }
  56
  57 /*
  58  * Response queue handler for the FW event queue.
  59  */
  60 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
  61                           __rte_unused const struct pkt_gl *gl)
  62 {
  63         u8 opcode = ((const struct rss_header *)rsp)->opcode;
  64
  65         rsp++;                                          /* skip RSS header */
  66
  67         /*
  68          * FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
  69          */
  70         if (unlikely(opcode == CPL_FW4_MSG &&
  71                      ((const struct cpl_fw4_msg *)rsp)->type ==
  72                       FW_TYPE_RSSCPL)) {
  73                 rsp++;
  74                 opcode = ((const struct rss_header *)rsp)->opcode;
  75                 rsp++;
  76                 if (opcode != CPL_SGE_EGR_UPDATE) {
  77                         dev_err(q->adapter, "unexpected FW4/CPL %#x on FW event queue\n",
  78                                 opcode);
  79                         goto out;
  80                 }
  81         }
  82
  83         if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
  84                 /* do nothing */
  85         } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
  86                 const struct cpl_fw6_msg *msg = (const void *)rsp;
  87
  88                 t4_handle_fw_rpl(q->adapter, msg->data);
  89         } else {
  90                 dev_err(adapter, "unexpected CPL %#x on FW event queue\n",
  91                         opcode);
  92         }
  93 out:
  94         return 0;
  95 }
  96
  97 int setup_sge_fwevtq(struct adapter *adapter)
  98 {
  99         struct sge *s = &adapter->sge;
 100         int err = 0;
 101         int msi_idx = 0;
 102
 103         err = t4_sge_alloc_rxq(adapter, &s->fw_evtq, true, adapter->eth_dev,
 104                                msi_idx, NULL, fwevtq_handler, -1, NULL, 0,
 105                                rte_socket_id());
 106         return err;
 107 }
 108
 109 static int closest_timer(const struct sge *s, int time)
 110 {
 111         unsigned int i, match = 0;
 112         int delta, min_delta = INT_MAX;
 113
 114         for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
 115                 delta = time - s->timer_val[i];
 116                 if (delta < 0)
 117                         delta = -delta;
 118                 if (delta < min_delta) {
 119                         min_delta = delta;
 120                         match = i;
 121                 }
 122         }
 123         return match;
 124 }
 125
 126 static int closest_thres(const struct sge *s, int thres)
 127 {
 128         unsigned int i, match = 0;
 129         int delta, min_delta = INT_MAX;
 130
 131         for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
 132                 delta = thres - s->counter_val[i];
 133                 if (delta < 0)
 134                         delta = -delta;
 135                 if (delta < min_delta) {
 136                         min_delta = delta;
 137                         match = i;
 138                 }
 139         }
 140         return match;
 141 }
 142
 143 /**
 144  * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
 145  * @q: the Rx queue
 146  * @us: the hold-off time in us, or 0 to disable timer
 147  * @cnt: the hold-off packet count, or 0 to disable counter
 148  *
 149  * Sets an Rx queue's interrupt hold-off time and packet count.  At least
 150  * one of the two needs to be enabled for the queue to generate interrupts.
 151  */
 152 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
 153                                unsigned int cnt)
 154 {
 155         struct adapter *adap = q->adapter;
 156         unsigned int timer_val;
 157
 158         if (cnt) {
 159                 int err;
 160                 u32 v, new_idx;
 161
 162                 new_idx = closest_thres(&adap->sge, cnt);
 163                 if (q->desc && q->pktcnt_idx != new_idx) {
 164                         /* the queue has already been created, update it */
 165                         v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
 166                             V_FW_PARAMS_PARAM_X(
 167                             FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
 168                             V_FW_PARAMS_PARAM_YZ(q->cntxt_id);
 169                         err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
 170                                             &v, &new_idx);
 171                         if (err)
 172                                 return err;
 173                 }
 174                 q->pktcnt_idx = new_idx;
 175         }
 176
 177         timer_val = (us == 0) ? X_TIMERREG_RESTART_COUNTER :
 178                                 closest_timer(&adap->sge, us);
 179
 180         if ((us | cnt) == 0)
 181                 q->intr_params = V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX);
 182         else
 183                 q->intr_params = V_QINTR_TIMER_IDX(timer_val) |
 184                                  V_QINTR_CNT_EN(cnt > 0);
 185         return 0;
 186 }
 187
 188 /**
 189  * Free TID tables.
 190  */
 191 static void tid_free(struct tid_info *t)
 192 {
 193         if (t->tid_tab) {
 194                 if (t->ftid_bmap)
 195                         rte_bitmap_free(t->ftid_bmap);
 196
 197                 if (t->ftid_bmap_array)
 198                         t4_os_free(t->ftid_bmap_array);
 199
 200                 t4_os_free(t->tid_tab);
 201         }
 202
 203         memset(t, 0, sizeof(struct tid_info));
 204 }
 205
 206 /**
 207  * Allocate and initialize the TID tables.  Returns 0 on success.
 208  */
 209 static int tid_init(struct tid_info *t)
 210 {
 211         size_t size;
 212         unsigned int ftid_bmap_size;
 213         unsigned int max_ftids = t->nftids;
 214
 215         ftid_bmap_size = rte_bitmap_get_memory_footprint(t->nftids);
 216         size = t->ntids * sizeof(*t->tid_tab) +
 217                 max_ftids * sizeof(*t->ftid_tab);
 218
 219         t->tid_tab = t4_os_alloc(size);
 220         if (!t->tid_tab)
 221                 return -ENOMEM;
 222
 223         t->ftid_tab = (struct filter_entry *)&t->tid_tab[t->ntids];
 224         t->ftid_bmap_array = t4_os_alloc(ftid_bmap_size);
 225         if (!t->ftid_bmap_array) {
 226                 tid_free(t);
 227                 return -ENOMEM;
 228         }
 229
 230         t4_os_lock_init(&t->ftid_lock);
 231         t->ftid_bmap = rte_bitmap_init(t->nftids, t->ftid_bmap_array,
 232                                        ftid_bmap_size);
 233         if (!t->ftid_bmap) {
 234                 tid_free(t);
 235                 return -ENOMEM;
 236         }
 237
 238         return 0;
 239 }
 240
 241 static inline bool is_x_1g_port(const struct link_config *lc)
 242 {
 243         return (lc->pcaps & FW_PORT_CAP32_SPEED_1G) != 0;
 244 }
 245
 246 static inline bool is_x_10g_port(const struct link_config *lc)
 247 {
 248         unsigned int speeds, high_speeds;
 249
 250         speeds = V_FW_PORT_CAP32_SPEED(G_FW_PORT_CAP32_SPEED(lc->pcaps));
 251         high_speeds = speeds &
 252                       ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G);
 253
 254         return high_speeds != 0;
 255 }
 256
 257 inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
 258                       unsigned int us, unsigned int cnt,
 259                       unsigned int size, unsigned int iqe_size)
 260 {
 261         q->adapter = adap;
 262         cxgb4_set_rspq_intr_params(q, us, cnt);
 263         q->iqe_len = iqe_size;
 264         q->size = size;
 265 }
 266
 267 int cfg_queue_count(struct rte_eth_dev *eth_dev)
 268 {
 269         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 270         struct adapter *adap = pi->adapter;
 271         struct sge *s = &adap->sge;
 272         unsigned int max_queues = s->max_ethqsets / adap->params.nports;
 273
 274         if ((eth_dev->data->nb_rx_queues < 1) ||
 275             (eth_dev->data->nb_tx_queues < 1))
 276                 return -EINVAL;
 277
 278         if ((eth_dev->data->nb_rx_queues > max_queues) ||
 279             (eth_dev->data->nb_tx_queues > max_queues))
 280                 return -EINVAL;
 281
 282         if (eth_dev->data->nb_rx_queues > pi->rss_size)
 283                 return -EINVAL;
 284
 285         /* We must configure RSS, since config has changed*/
 286         pi->flags &= ~PORT_RSS_DONE;
 287
 288         pi->n_rx_qsets = eth_dev->data->nb_rx_queues;
 289         pi->n_tx_qsets = eth_dev->data->nb_tx_queues;
 290
 291         return 0;
 292 }
 293
 294 void cfg_queues(struct rte_eth_dev *eth_dev)
 295 {
 296         struct rte_config *config = rte_eal_get_configuration();
 297         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 298         struct adapter *adap = pi->adapter;
 299         struct sge *s = &adap->sge;
 300         unsigned int i, nb_ports = 0, qidx = 0;
 301         unsigned int q_per_port = 0;
 302
 303         if (!(adap->flags & CFG_QUEUES)) {
 304                 for_each_port(adap, i) {
 305                         struct port_info *tpi = adap2pinfo(adap, i);
 306
 307                         nb_ports += (is_x_10g_port(&tpi->link_cfg)) ||
 308                                      is_x_1g_port(&tpi->link_cfg) ? 1 : 0;
 309                 }
 310
 311                 /*
 312                  * We default up to # of cores queues per 1G/10G port.
 313                  */
 314                 if (nb_ports)
 315                         q_per_port = (MAX_ETH_QSETS -
 316                                      (adap->params.nports - nb_ports)) /
 317                                      nb_ports;
 318
 319                 if (q_per_port > config->lcore_count)
 320                         q_per_port = config->lcore_count;
 321
 322                 for_each_port(adap, i) {
 323                         struct port_info *pi = adap2pinfo(adap, i);
 324
 325                         pi->first_qset = qidx;
 326
 327                         /* Initially n_rx_qsets == n_tx_qsets */
 328                         pi->n_rx_qsets = (is_x_10g_port(&pi->link_cfg) ||
 329                                           is_x_1g_port(&pi->link_cfg)) ?
 330                                           q_per_port : 1;
 331                         pi->n_tx_qsets = pi->n_rx_qsets;
 332
 333                         if (pi->n_rx_qsets > pi->rss_size)
 334                                 pi->n_rx_qsets = pi->rss_size;
 335
 336                         qidx += pi->n_rx_qsets;
 337                 }
 338
 339                 s->max_ethqsets = qidx;
 340
 341                 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
 342                         struct sge_eth_rxq *r = &s->ethrxq[i];
 343
 344                         init_rspq(adap, &r->rspq, 5, 32, 1024, 64);
 345                         r->usembufs = 1;
 346                         r->fl.size = (r->usembufs ? 1024 : 72);
 347                 }
 348
 349                 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
 350                         s->ethtxq[i].q.size = 1024;
 351
 352                 init_rspq(adap, &adap->sge.fw_evtq, 0, 0, 1024, 64);
 353                 adap->flags |= CFG_QUEUES;
 354         }
 355 }
 356
 357 void cxgbe_stats_get(struct port_info *pi, struct port_stats *stats)
 358 {
 359         t4_get_port_stats_offset(pi->adapter, pi->tx_chan, stats,
 360                                  &pi->stats_base);
 361 }
 362
 363 void cxgbe_stats_reset(struct port_info *pi)
 364 {
 365         t4_clr_port_stats(pi->adapter, pi->tx_chan);
 366 }
 367
 368 static void setup_memwin(struct adapter *adap)
 369 {
 370         u32 mem_win0_base;
 371
 372         /* For T5, only relative offset inside the PCIe BAR is passed */
 373         mem_win0_base = MEMWIN0_BASE;
 374
 375         /*
 376          * Set up memory window for accessing adapter memory ranges.  (Read
 377          * back MA register to ensure that changes propagate before we attempt
 378          * to use the new values.)
 379          */
 380         t4_write_reg(adap,
 381                      PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
 382                                          MEMWIN_NIC),
 383                      mem_win0_base | V_BIR(0) |
 384                      V_WINDOW(ilog2(MEMWIN0_APERTURE) - X_WINDOW_SHIFT));
 385         t4_read_reg(adap,
 386                     PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
 387                                         MEMWIN_NIC));
 388 }
 389
 390 int init_rss(struct adapter *adap)
 391 {
 392         unsigned int i;
 393
 394         if (is_pf4(adap)) {
 395                 int err;
 396
 397                 err = t4_init_rss_mode(adap, adap->mbox);
 398                 if (err)
 399                         return err;
 400         }
 401
 402         for_each_port(adap, i) {
 403                 struct port_info *pi = adap2pinfo(adap, i);
 404
 405                 pi->rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
 406                 if (!pi->rss)
 407                         return -ENOMEM;
 408
 409                 pi->rss_hf = CXGBE_RSS_HF_ALL;
 410         }
 411         return 0;
 412 }
 413
 414 /**
 415  * Dump basic information about the adapter.
 416  */
 417 void print_adapter_info(struct adapter *adap)
 418 {
 419         /**
 420          * Hardware/Firmware/etc. Version/Revision IDs.
 421          */
 422         t4_dump_version_info(adap);
 423 }
 424
 425 void print_port_info(struct adapter *adap)
 426 {
 427         int i;
 428         char buf[80];
 429         struct rte_pci_addr *loc = &adap->pdev->addr;
 430
 431         for_each_port(adap, i) {
 432                 const struct port_info *pi = adap2pinfo(adap, i);
 433                 char *bufp = buf;
 434
 435                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M)
 436                         bufp += sprintf(bufp, "100M/");
 437                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G)
 438                         bufp += sprintf(bufp, "1G/");
 439                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G)
 440                         bufp += sprintf(bufp, "10G/");
 441                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G)
 442                         bufp += sprintf(bufp, "25G/");
 443                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G)
 444                         bufp += sprintf(bufp, "40G/");
 445                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G)
 446                         bufp += sprintf(bufp, "50G/");
 447                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G)
 448                         bufp += sprintf(bufp, "100G/");
 449                 if (bufp != buf)
 450                         --bufp;
 451                 sprintf(bufp, "BASE-%s",
 452                         t4_get_port_type_description(
 453                                         (enum fw_port_type)pi->port_type));
 454
 455                 dev_info(adap,
 456                          " " PCI_PRI_FMT " Chelsio rev %d %s %s\n",
 457                          loc->domain, loc->bus, loc->devid, loc->function,
 458                          CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
 459                          (adap->flags & USING_MSIX) ? " MSI-X" :
 460                          (adap->flags & USING_MSI) ? " MSI" : "");
 461         }
 462 }
 463
 464 static int
 465 check_devargs_handler(__rte_unused const char *key, const char *value,
 466                       __rte_unused void *opaque)
 467 {
 468         if (strcmp(value, "1"))
 469                 return -1;
 470
 471         return 0;
 472 }
 473
 474 int cxgbe_get_devargs(struct rte_devargs *devargs, const char *key)
 475 {
 476         struct rte_kvargs *kvlist;
 477
 478         if (!devargs)
 479                 return 0;
 480
 481         kvlist = rte_kvargs_parse(devargs->args, NULL);
 482         if (!kvlist)
 483                 return 0;
 484
 485         if (!rte_kvargs_count(kvlist, key)) {
 486                 rte_kvargs_free(kvlist);
 487                 return 0;
 488         }
 489
 490         if (rte_kvargs_process(kvlist, key,
 491                                check_devargs_handler, NULL) < 0) {
 492                 rte_kvargs_free(kvlist);
 493                 return 0;
 494         }
 495         rte_kvargs_free(kvlist);
 496
 497         return 1;
 498 }
 499
 500 static void configure_vlan_types(struct adapter *adapter)
 501 {
 502         struct rte_pci_device *pdev = adapter->pdev;
 503         int i;
 504
 505         for_each_port(adapter, i) {
 506                 /* OVLAN Type 0x88a8 */
 507                 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN0),
 508                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 509                                  V_OVLAN_ETYPE(M_OVLAN_ETYPE),
 510                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 511                                  V_OVLAN_ETYPE(0x88a8));
 512                 /* OVLAN Type 0x9100 */
 513                 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN1),
 514                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 515                                  V_OVLAN_ETYPE(M_OVLAN_ETYPE),
 516                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 517                                  V_OVLAN_ETYPE(0x9100));
 518                 /* OVLAN Type 0x8100 */
 519                 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN2),
 520                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 521                                  V_OVLAN_ETYPE(M_OVLAN_ETYPE),
 522                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 523                                  V_OVLAN_ETYPE(0x8100));
 524
 525                 /* IVLAN 0X8100 */
 526                 t4_set_reg_field(adapter, MPS_PORT_RX_IVLAN(i),
 527                                  V_IVLAN_ETYPE(M_IVLAN_ETYPE),
 528                                  V_IVLAN_ETYPE(0x8100));
 529
 530                 t4_set_reg_field(adapter, MPS_PORT_RX_CTL(i),
 531                                  F_OVLAN_EN0 | F_OVLAN_EN1 |
 532                                  F_OVLAN_EN2 | F_IVLAN_EN,
 533                                  F_OVLAN_EN0 | F_OVLAN_EN1 |
 534                                  F_OVLAN_EN2 | F_IVLAN_EN);
 535         }
 536
 537         if (cxgbe_get_devargs(pdev->device.devargs, CXGBE_DEVARG_KEEP_OVLAN))
 538                 t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG,
 539                                        V_RM_OVLAN(1), V_RM_OVLAN(0));
 540 }
 541
 542 static void configure_pcie_ext_tag(struct adapter *adapter)
 543 {
 544         u16 v;
 545         int pos = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
 546
 547         if (!pos)
 548                 return;
 549
 550         if (pos > 0) {
 551                 t4_os_pci_read_cfg2(adapter, pos + PCI_EXP_DEVCTL, &v);
 552                 v |= PCI_EXP_DEVCTL_EXT_TAG;
 553                 t4_os_pci_write_cfg2(adapter, pos + PCI_EXP_DEVCTL, v);
 554                 if (is_t6(adapter->params.chip)) {
 555                         t4_set_reg_field(adapter, A_PCIE_CFG2,
 556                                          V_T6_TOTMAXTAG(M_T6_TOTMAXTAG),
 557                                          V_T6_TOTMAXTAG(7));
 558                         t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
 559                                          V_T6_MINTAG(M_T6_MINTAG),
 560                                          V_T6_MINTAG(8));
 561                 } else {
 562                         t4_set_reg_field(adapter, A_PCIE_CFG2,
 563                                          V_TOTMAXTAG(M_TOTMAXTAG),
 564                                          V_TOTMAXTAG(3));
 565                         t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
 566                                          V_MINTAG(M_MINTAG),
 567                                          V_MINTAG(8));
 568                 }
 569         }
 570 }
 571
 572 /*
 573  * Tweak configuration based on system architecture, etc.  Most of these have
 574  * defaults assigned to them by Firmware Configuration Files (if we're using
 575  * them) but need to be explicitly set if we're using hard-coded
 576  * initialization. So these are essentially common tweaks/settings for
 577  * Configuration Files and hard-coded initialization ...
 578  */
 579 static int adap_init0_tweaks(struct adapter *adapter)
 580 {
 581         u8 rx_dma_offset;
 582
 583         /*
 584          * Fix up various Host-Dependent Parameters like Page Size, Cache
 585          * Line Size, etc.  The firmware default is for a 4KB Page Size and
 586          * 64B Cache Line Size ...
 587          */
 588         t4_fixup_host_params_compat(adapter, CXGBE_PAGE_SIZE, L1_CACHE_BYTES,
 589                                     T5_LAST_REV);
 590
 591         /*
 592          * Keep the chip default offset to deliver Ingress packets into our
 593          * DMA buffers to zero
 594          */
 595         rx_dma_offset = 0;
 596         t4_set_reg_field(adapter, A_SGE_CONTROL, V_PKTSHIFT(M_PKTSHIFT),
 597                          V_PKTSHIFT(rx_dma_offset));
 598
 599         t4_set_reg_field(adapter, A_SGE_FLM_CFG,
 600                          V_CREDITCNT(M_CREDITCNT) | M_CREDITCNTPACKING,
 601                          V_CREDITCNT(3) | V_CREDITCNTPACKING(1));
 602
 603         t4_set_reg_field(adapter, A_SGE_INGRESS_RX_THRESHOLD,
 604                          V_THRESHOLD_3(M_THRESHOLD_3), V_THRESHOLD_3(32U));
 605
 606         t4_set_reg_field(adapter, A_SGE_CONTROL2, V_IDMAARBROUNDROBIN(1U),
 607                          V_IDMAARBROUNDROBIN(1U));
 608
 609         /*
 610          * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
 611          * adds the pseudo header itself.
 612          */
 613         t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG,
 614                                F_CSUM_HAS_PSEUDO_HDR, 0);
 615
 616         return 0;
 617 }
 618
 619 /*
 620  * Attempt to initialize the adapter via a Firmware Configuration File.
 621  */
 622 static int adap_init0_config(struct adapter *adapter, int reset)
 623 {
 624         struct fw_caps_config_cmd caps_cmd;
 625         unsigned long mtype = 0, maddr = 0;
 626         u32 finiver, finicsum, cfcsum;
 627         int ret;
 628         int config_issued = 0;
 629         int cfg_addr;
 630         char config_name[20];
 631
 632         /*
 633          * Reset device if necessary.
 634          */
 635         if (reset) {
 636                 ret = t4_fw_reset(adapter, adapter->mbox,
 637                                   F_PIORSTMODE | F_PIORST);
 638                 if (ret < 0) {
 639                         dev_warn(adapter, "Firmware reset failed, error %d\n",
 640                                  -ret);
 641                         goto bye;
 642                 }
 643         }
 644
 645         cfg_addr = t4_flash_cfg_addr(adapter);
 646         if (cfg_addr < 0) {
 647                 ret = cfg_addr;
 648                 dev_warn(adapter, "Finding address for firmware config file in flash failed, error %d\n",
 649                          -ret);
 650                 goto bye;
 651         }
 652
 653         strcpy(config_name, "On Flash");
 654         mtype = FW_MEMTYPE_CF_FLASH;
 655         maddr = cfg_addr;
 656
 657         /*
 658          * Issue a Capability Configuration command to the firmware to get it
 659          * to parse the Configuration File.  We don't use t4_fw_config_file()
 660          * because we want the ability to modify various features after we've
 661          * processed the configuration file ...
 662          */
 663         memset(&caps_cmd, 0, sizeof(caps_cmd));
 664         caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
 665                                            F_FW_CMD_REQUEST | F_FW_CMD_READ);
 666         caps_cmd.cfvalid_to_len16 =
 667                 cpu_to_be32(F_FW_CAPS_CONFIG_CMD_CFVALID |
 668                             V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
 669                             V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
 670                             FW_LEN16(caps_cmd));
 671         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
 672                          &caps_cmd);
 673         /*
 674          * If the CAPS_CONFIG failed with an ENOENT (for a Firmware
 675          * Configuration File in FLASH), our last gasp effort is to use the
 676          * Firmware Configuration File which is embedded in the firmware.  A
 677          * very few early versions of the firmware didn't have one embedded
 678          * but we can ignore those.
 679          */
 680         if (ret == -ENOENT) {
 681                 dev_info(adapter, "%s: Going for embedded config in firmware..\n",
 682                          __func__);
 683
 684                 memset(&caps_cmd, 0, sizeof(caps_cmd));
 685                 caps_cmd.op_to_write =
 686                         cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
 687                                     F_FW_CMD_REQUEST | F_FW_CMD_READ);
 688                 caps_cmd.cfvalid_to_len16 = cpu_to_be32(FW_LEN16(caps_cmd));
 689                 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
 690                                  sizeof(caps_cmd), &caps_cmd);
 691                 strcpy(config_name, "Firmware Default");
 692         }
 693
 694         config_issued = 1;
 695         if (ret < 0)
 696                 goto bye;
 697
 698         finiver = be32_to_cpu(caps_cmd.finiver);
 699         finicsum = be32_to_cpu(caps_cmd.finicsum);
 700         cfcsum = be32_to_cpu(caps_cmd.cfcsum);
 701         if (finicsum != cfcsum)
 702                 dev_warn(adapter, "Configuration File checksum mismatch: [fini] csum=%#x, computed csum=%#x\n",
 703                          finicsum, cfcsum);
 704
 705         /*
 706          * If we're a pure NIC driver then disable all offloading facilities.
 707          * This will allow the firmware to optimize aspects of the hardware
 708          * configuration which will result in improved performance.
 709          */
 710         caps_cmd.niccaps &= cpu_to_be16(~(FW_CAPS_CONFIG_NIC_HASHFILTER |
 711                                           FW_CAPS_CONFIG_NIC_ETHOFLD));
 712         caps_cmd.toecaps = 0;
 713         caps_cmd.iscsicaps = 0;
 714         caps_cmd.rdmacaps = 0;
 715         caps_cmd.fcoecaps = 0;
 716
 717         /*
 718          * And now tell the firmware to use the configuration we just loaded.
 719          */
 720         caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
 721                                            F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
 722         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
 723         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
 724                          NULL);
 725         if (ret < 0) {
 726                 dev_warn(adapter, "Unable to finalize Firmware Capabilities %d\n",
 727                          -ret);
 728                 goto bye;
 729         }
 730
 731         /*
 732          * Tweak configuration based on system architecture, etc.
 733          */
 734         ret = adap_init0_tweaks(adapter);
 735         if (ret < 0) {
 736                 dev_warn(adapter, "Unable to do init0-tweaks %d\n", -ret);
 737                 goto bye;
 738         }
 739
 740         /*
 741          * And finally tell the firmware to initialize itself using the
 742          * parameters from the Configuration File.
 743          */
 744         ret = t4_fw_initialize(adapter, adapter->mbox);
 745         if (ret < 0) {
 746                 dev_warn(adapter, "Initializing Firmware failed, error %d\n",
 747                          -ret);
 748                 goto bye;
 749         }
 750
 751         /*
 752          * Return successfully and note that we're operating with parameters
 753          * not supplied by the driver, rather than from hard-wired
 754          * initialization constants buried in the driver.
 755          */
 756         dev_info(adapter,
 757                  "Successfully configured using Firmware Configuration File \"%s\", version %#x, computed checksum %#x\n",
 758                  config_name, finiver, cfcsum);
 759
 760         return 0;
 761
 762         /*
 763          * Something bad happened.  Return the error ...  (If the "error"
 764          * is that there's no Configuration File on the adapter we don't
 765          * want to issue a warning since this is fairly common.)
 766          */
 767 bye:
 768         if (config_issued && ret != -ENOENT)
 769                 dev_warn(adapter, "\"%s\" configuration file error %d\n",
 770                          config_name, -ret);
 771
 772         dev_debug(adapter, "%s: returning ret = %d ..\n", __func__, ret);
 773         return ret;
 774 }
 775
 776 static int adap_init0(struct adapter *adap)
 777 {
 778         struct fw_caps_config_cmd caps_cmd;
 779         int ret = 0;
 780         u32 v, port_vec;
 781         enum dev_state state;
 782         u32 params[7], val[7];
 783         int reset = 1;
 784         int mbox = adap->mbox;
 785
 786         /*
 787          * Contact FW, advertising Master capability.
 788          */
 789         ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state);
 790         if (ret < 0) {
 791                 dev_err(adap, "%s: could not connect to FW, error %d\n",
 792                         __func__, -ret);
 793                 goto bye;
 794         }
 795
 796         CXGBE_DEBUG_MBOX(adap, "%s: adap->mbox = %d; ret = %d\n", __func__,
 797                          adap->mbox, ret);
 798
 799         if (ret == mbox)
 800                 adap->flags |= MASTER_PF;
 801
 802         if (state == DEV_STATE_INIT) {
 803                 /*
 804                  * Force halt and reset FW because a previous instance may have
 805                  * exited abnormally without properly shutting down
 806                  */
 807                 ret = t4_fw_halt(adap, adap->mbox, reset);
 808                 if (ret < 0) {
 809                         dev_err(adap, "Failed to halt. Exit.\n");
 810                         goto bye;
 811                 }
 812
 813                 ret = t4_fw_restart(adap, adap->mbox, reset);
 814                 if (ret < 0) {
 815                         dev_err(adap, "Failed to restart. Exit.\n");
 816                         goto bye;
 817                 }
 818                 state = (enum dev_state)((unsigned)state & ~DEV_STATE_INIT);
 819         }
 820
 821         t4_get_version_info(adap);
 822
 823         ret = t4_get_core_clock(adap, &adap->params.vpd);
 824         if (ret < 0) {
 825                 dev_err(adap, "%s: could not get core clock, error %d\n",
 826                         __func__, -ret);
 827                 goto bye;
 828         }
 829
 830         /*
 831          * If the firmware is initialized already (and we're not forcing a
 832          * master initialization), note that we're living with existing
 833          * adapter parameters.  Otherwise, it's time to try initializing the
 834          * adapter ...
 835          */
 836         if (state == DEV_STATE_INIT) {
 837                 dev_info(adap, "Coming up as %s: Adapter already initialized\n",
 838                          adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
 839         } else {
 840                 dev_info(adap, "Coming up as MASTER: Initializing adapter\n");
 841
 842                 ret = adap_init0_config(adap, reset);
 843                 if (ret == -ENOENT) {
 844                         dev_err(adap,
 845                                 "No Configuration File present on adapter. Using hard-wired configuration parameters.\n");
 846                         goto bye;
 847                 }
 848         }
 849         if (ret < 0) {
 850                 dev_err(adap, "could not initialize adapter, error %d\n", -ret);
 851                 goto bye;
 852         }
 853
 854         /* Find out what ports are available to us. */
 855         v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
 856             V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC);
 857         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
 858         if (ret < 0) {
 859                 dev_err(adap, "%s: failure in t4_query_params; error = %d\n",
 860                         __func__, ret);
 861                 goto bye;
 862         }
 863
 864         adap->params.nports = hweight32(port_vec);
 865         adap->params.portvec = port_vec;
 866
 867         dev_debug(adap, "%s: adap->params.nports = %u\n", __func__,
 868                   adap->params.nports);
 869
 870         /*
 871          * Give the SGE code a chance to pull in anything that it needs ...
 872          * Note that this must be called after we retrieve our VPD parameters
 873          * in order to know how to convert core ticks to seconds, etc.
 874          */
 875         ret = t4_sge_init(adap);
 876         if (ret < 0) {
 877                 dev_err(adap, "t4_sge_init failed with error %d\n",
 878                         -ret);
 879                 goto bye;
 880         }
 881
 882         /*
 883          * Grab some of our basic fundamental operating parameters.
 884          */
 885 #define FW_PARAM_DEV(param) \
 886         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
 887          V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
 888
 889 #define FW_PARAM_PFVF(param) \
 890         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
 891          V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) |  \
 892          V_FW_PARAMS_PARAM_Y(0) | \
 893          V_FW_PARAMS_PARAM_Z(0))
 894
 895         params[0] = FW_PARAM_PFVF(FILTER_START);
 896         params[1] = FW_PARAM_PFVF(FILTER_END);
 897         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
 898         if (ret < 0)
 899                 goto bye;
 900         adap->tids.ftid_base = val[0];
 901         adap->tids.nftids = val[1] - val[0] + 1;
 902
 903         /*
 904          * Get device capabilities so we can determine what resources we need
 905          * to manage.
 906          */
 907         memset(&caps_cmd, 0, sizeof(caps_cmd));
 908         caps_cmd.op_to_write = htonl(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
 909                                      F_FW_CMD_REQUEST | F_FW_CMD_READ);
 910         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
 911         ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
 912                          &caps_cmd);
 913         if (ret < 0)
 914                 goto bye;
 915
 916         /* query tid-related parameters */
 917         params[0] = FW_PARAM_DEV(NTID);
 918         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
 919                               params, val);
 920         if (ret < 0)
 921                 goto bye;
 922         adap->tids.ntids = val[0];
 923
 924         /* If we're running on newer firmware, let it know that we're
 925          * prepared to deal with encapsulated CPL messages.  Older
 926          * firmware won't understand this and we'll just get
 927          * unencapsulated messages ...
 928          */
 929         params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
 930         val[0] = 1;
 931         (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
 932
 933         /*
 934          * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
 935          * capability.  Earlier versions of the firmware didn't have the
 936          * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
 937          * permission to use ULPTX MEMWRITE DSGL.
 938          */
 939         if (is_t4(adap->params.chip)) {
 940                 adap->params.ulptx_memwrite_dsgl = false;
 941         } else {
 942                 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
 943                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
 944                                       1, params, val);
 945                 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
 946         }
 947
 948         /*
 949          * The MTU/MSS Table is initialized by now, so load their values.  If
 950          * we're initializing the adapter, then we'll make any modifications
 951          * we want to the MTU/MSS Table and also initialize the congestion
 952          * parameters.
 953          */
 954         t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
 955         if (state != DEV_STATE_INIT) {
 956                 int i;
 957
 958                 /*
 959                  * The default MTU Table contains values 1492 and 1500.
 960                  * However, for TCP, it's better to have two values which are
 961                  * a multiple of 8 +/- 4 bytes apart near this popular MTU.
 962                  * This allows us to have a TCP Data Payload which is a
 963                  * multiple of 8 regardless of what combination of TCP Options
 964                  * are in use (always a multiple of 4 bytes) which is
 965                  * important for performance reasons.  For instance, if no
 966                  * options are in use, then we have a 20-byte IP header and a
 967                  * 20-byte TCP header.  In this case, a 1500-byte MSS would
 968                  * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
 969                  * which is not a multiple of 8.  So using an MSS of 1488 in
 970                  * this case results in a TCP Data Payload of 1448 bytes which
 971                  * is a multiple of 8.  On the other hand, if 12-byte TCP Time
 972                  * Stamps have been negotiated, then an MTU of 1500 bytes
 973                  * results in a TCP Data Payload of 1448 bytes which, as
 974                  * above, is a multiple of 8 bytes ...
 975                  */
 976                 for (i = 0; i < NMTUS; i++)
 977                         if (adap->params.mtus[i] == 1492) {
 978                                 adap->params.mtus[i] = 1488;
 979                                 break;
 980                         }
 981
 982                 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
 983                              adap->params.b_wnd);
 984         }
 985         t4_init_sge_params(adap);
 986         t4_init_tp_params(adap);
 987         configure_pcie_ext_tag(adap);
 988         configure_vlan_types(adap);
 989
 990         adap->params.drv_memwin = MEMWIN_NIC;
 991         adap->flags |= FW_OK;
 992         dev_debug(adap, "%s: returning zero..\n", __func__);
 993         return 0;
 994
 995         /*
 996          * Something bad happened.  If a command timed out or failed with EIO
 997          * FW does not operate within its spec or something catastrophic
 998          * happened to HW/FW, stop issuing commands.
 999          */
1000 bye:
1001         if (ret != -ETIMEDOUT && ret != -EIO)
1002                 t4_fw_bye(adap, adap->mbox);
1003         return ret;
1004 }
1005
1006 /**
1007  * t4_os_portmod_changed - handle port module changes
1008  * @adap: the adapter associated with the module change
1009  * @port_id: the port index whose module status has changed
1010  *
1011  * This is the OS-dependent handler for port module changes.  It is
1012  * invoked when a port module is removed or inserted for any OS-specific
1013  * processing.
1014  */
1015 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
1016 {
1017         static const char * const mod_str[] = {
1018                 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
1019         };
1020
1021         const struct port_info *pi = adap2pinfo(adap, port_id);
1022
1023         if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
1024                 dev_info(adap, "Port%d: port module unplugged\n", pi->port_id);
1025         else if (pi->mod_type < ARRAY_SIZE(mod_str))
1026                 dev_info(adap, "Port%d: %s port module inserted\n", pi->port_id,
1027                          mod_str[pi->mod_type]);
1028         else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
1029                 dev_info(adap, "Port%d: unsupported port module inserted\n",
1030                          pi->port_id);
1031         else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
1032                 dev_info(adap, "Port%d: unknown port module inserted\n",
1033                          pi->port_id);
1034         else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
1035                 dev_info(adap, "Port%d: transceiver module error\n",
1036                          pi->port_id);
1037         else
1038                 dev_info(adap, "Port%d: unknown module type %d inserted\n",
1039                          pi->port_id, pi->mod_type);
1040 }
1041
1042 inline bool force_linkup(struct adapter *adap)
1043 {
1044         struct rte_pci_device *pdev = adap->pdev;
1045
1046         if (is_pf4(adap))
1047                 return false;   /* force_linkup not required for pf driver*/
1048         if (!cxgbe_get_devargs(pdev->device.devargs,
1049                                CXGBE_DEVARG_FORCE_LINK_UP))
1050                 return false;
1051         return true;
1052 }
1053
1054 /**
1055  * link_start - enable a port
1056  * @dev: the port to enable
1057  *
1058  * Performs the MAC and PHY actions needed to enable a port.
1059  */
1060 int link_start(struct port_info *pi)
1061 {
1062         struct adapter *adapter = pi->adapter;
1063         int ret;
1064         unsigned int mtu;
1065
1066         mtu = pi->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1067               (ETHER_HDR_LEN + ETHER_CRC_LEN);
1068
1069         /*
1070          * We do not set address filters and promiscuity here, the stack does
1071          * that step explicitly.
1072          */
1073         ret = t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, -1, -1,
1074                             -1, 1, true);
1075         if (ret == 0) {
1076                 ret = t4_change_mac(adapter, adapter->mbox, pi->viid,
1077                                     pi->xact_addr_filt,
1078                                     (u8 *)&pi->eth_dev->data->mac_addrs[0],
1079                                     true, true);
1080                 if (ret >= 0) {
1081                         pi->xact_addr_filt = ret;
1082                         ret = 0;
1083                 }
1084         }
1085         if (ret == 0 && is_pf4(adapter))
1086                 ret = t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
1087                                     &pi->link_cfg);
1088         if (ret == 0) {
1089                 /*
1090                  * Enabling a Virtual Interface can result in an interrupt
1091                  * during the processing of the VI Enable command and, in some
1092                  * paths, result in an attempt to issue another command in the
1093                  * interrupt context.  Thus, we disable interrupts during the
1094                  * course of the VI Enable command ...
1095                  */
1096                 ret = t4_enable_vi_params(adapter, adapter->mbox, pi->viid,
1097                                           true, true, false);
1098         }
1099
1100         if (ret == 0 && force_linkup(adapter))
1101                 pi->eth_dev->data->dev_link.link_status = ETH_LINK_UP;
1102         return ret;
1103 }
1104
1105 /**
1106  * cxgbe_write_rss_conf - flash the RSS configuration for a given port
1107  * @pi: the port
1108  * @rss_hf: Hash configuration to apply
1109  */
1110 int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t rss_hf)
1111 {
1112         struct adapter *adapter = pi->adapter;
1113         const struct sge_eth_rxq *rxq;
1114         u64 flags = 0;
1115         u16 rss;
1116         int err;
1117
1118         /*  Should never be called before setting up sge eth rx queues */
1119         if (!(adapter->flags & FULL_INIT_DONE)) {
1120                 dev_err(adap, "%s No RXQs available on port %d\n",
1121                         __func__, pi->port_id);
1122                 return -EINVAL;
1123         }
1124
1125         /* Don't allow unsupported hash functions */
1126         if (rss_hf & ~CXGBE_RSS_HF_ALL)
1127                 return -EINVAL;
1128
1129         if (rss_hf & ETH_RSS_IPV4)
1130                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
1131
1132         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1133                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
1134
1135         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1136                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
1137                          F_FW_RSS_VI_CONFIG_CMD_UDPEN;
1138
1139         if (rss_hf & ETH_RSS_IPV6)
1140                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
1141
1142         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1143                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
1144
1145         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1146                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
1147                          F_FW_RSS_VI_CONFIG_CMD_UDPEN;
1148
1149         rxq = &adapter->sge.ethrxq[pi->first_qset];
1150         rss = rxq[0].rspq.abs_id;
1151
1152         /* If Tunnel All Lookup isn't specified in the global RSS
1153          * Configuration, then we need to specify a default Ingress
1154          * Queue for any ingress packets which aren't hashed.  We'll
1155          * use our first ingress queue ...
1156          */
1157         err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
1158                                flags, rss);
1159         return err;
1160 }
1161
1162 /**
1163  * cxgbe_write_rss - write the RSS table for a given port
1164  * @pi: the port
1165  * @queues: array of queue indices for RSS
1166  *
1167  * Sets up the portion of the HW RSS table for the port's VI to distribute
1168  * packets to the Rx queues in @queues.
1169  */
1170 int cxgbe_write_rss(const struct port_info *pi, const u16 *queues)
1171 {
1172         u16 *rss;
1173         int i, err;
1174         struct adapter *adapter = pi->adapter;
1175         const struct sge_eth_rxq *rxq;
1176
1177         /*  Should never be called before setting up sge eth rx queues */
1178         BUG_ON(!(adapter->flags & FULL_INIT_DONE));
1179
1180         rxq = &adapter->sge.ethrxq[pi->first_qset];
1181         rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
1182         if (!rss)
1183                 return -ENOMEM;
1184
1185         /* map the queue indices to queue ids */
1186         for (i = 0; i < pi->rss_size; i++, queues++)
1187                 rss[i] = rxq[*queues].rspq.abs_id;
1188
1189         err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
1190                                   pi->rss_size, rss, pi->rss_size);
1191         rte_free(rss);
1192         return err;
1193 }
1194
1195 /**
1196  * setup_rss - configure RSS
1197  * @adapter: the adapter
1198  *
1199  * Sets up RSS to distribute packets to multiple receive queues.  We
1200  * configure the RSS CPU lookup table to distribute to the number of HW
1201  * receive queues, and the response queue lookup table to narrow that
1202  * down to the response queues actually configured for each port.
1203  * We always configure the RSS mapping for all ports since the mapping
1204  * table has plenty of entries.
1205  */
1206 int setup_rss(struct port_info *pi)
1207 {
1208         int j, err;
1209         struct adapter *adapter = pi->adapter;
1210
1211         dev_debug(adapter, "%s:  pi->rss_size = %u; pi->n_rx_qsets = %u\n",
1212                   __func__, pi->rss_size, pi->n_rx_qsets);
1213
1214         if (!(pi->flags & PORT_RSS_DONE)) {
1215                 if (adapter->flags & FULL_INIT_DONE) {
1216                         /* Fill default values with equal distribution */
1217                         for (j = 0; j < pi->rss_size; j++)
1218                                 pi->rss[j] = j % pi->n_rx_qsets;
1219
1220                         err = cxgbe_write_rss(pi, pi->rss);
1221                         if (err)
1222                                 return err;
1223
1224                         err = cxgbe_write_rss_conf(pi, pi->rss_hf);
1225                         if (err)
1226                                 return err;
1227                         pi->flags |= PORT_RSS_DONE;
1228                 }
1229         }
1230         return 0;
1231 }
1232
1233 /*
1234  * Enable NAPI scheduling and interrupt generation for all Rx queues.
1235  */
1236 static void enable_rx(struct adapter *adap, struct sge_rspq *q)
1237 {
1238         /* 0-increment GTS to start the timer and enable interrupts */
1239         t4_write_reg(adap, is_pf4(adap) ? MYPF_REG(A_SGE_PF_GTS) :
1240                                           T4VF_SGE_BASE_ADDR + A_SGE_VF_GTS,
1241                      V_SEINTARM(q->intr_params) |
1242                      V_INGRESSQID(q->cntxt_id));
1243 }
1244
1245 void cxgbe_enable_rx_queues(struct port_info *pi)
1246 {
1247         struct adapter *adap = pi->adapter;
1248         struct sge *s = &adap->sge;
1249         unsigned int i;
1250
1251         for (i = 0; i < pi->n_rx_qsets; i++)
1252                 enable_rx(adap, &s->ethrxq[pi->first_qset + i].rspq);
1253 }
1254
1255 /**
1256  * fw_caps_to_speed_caps - translate Firmware Port Caps to Speed Caps.
1257  * @port_type: Firmware Port Type
1258  * @fw_caps: Firmware Port Capabilities
1259  * @speed_caps: Device Info Speed Capabilities
1260  *
1261  * Translate a Firmware Port Capabilities specification to Device Info
1262  * Speed Capabilities.
1263  */
1264 static void fw_caps_to_speed_caps(enum fw_port_type port_type,
1265                                   unsigned int fw_caps,
1266                                   u32 *speed_caps)
1267 {
1268 #define SET_SPEED(__speed_name) \
1269         do { \
1270                 *speed_caps |= ETH_LINK_ ## __speed_name; \
1271         } while (0)
1272
1273 #define FW_CAPS_TO_SPEED(__fw_name) \
1274         do { \
1275                 if (fw_caps & FW_PORT_CAP32_ ## __fw_name) \
1276                         SET_SPEED(__fw_name); \
1277         } while (0)
1278
1279         switch (port_type) {
1280         case FW_PORT_TYPE_BT_SGMII:
1281         case FW_PORT_TYPE_BT_XFI:
1282         case FW_PORT_TYPE_BT_XAUI:
1283                 FW_CAPS_TO_SPEED(SPEED_100M);
1284                 FW_CAPS_TO_SPEED(SPEED_1G);
1285                 FW_CAPS_TO_SPEED(SPEED_10G);
1286                 break;
1287
1288         case FW_PORT_TYPE_KX4:
1289         case FW_PORT_TYPE_KX:
1290         case FW_PORT_TYPE_FIBER_XFI:
1291         case FW_PORT_TYPE_FIBER_XAUI:
1292         case FW_PORT_TYPE_SFP:
1293         case FW_PORT_TYPE_QSFP_10G:
1294         case FW_PORT_TYPE_QSA:
1295                 FW_CAPS_TO_SPEED(SPEED_1G);
1296                 FW_CAPS_TO_SPEED(SPEED_10G);
1297                 break;
1298
1299         case FW_PORT_TYPE_KR:
1300                 SET_SPEED(SPEED_10G);
1301                 break;
1302
1303         case FW_PORT_TYPE_BP_AP:
1304         case FW_PORT_TYPE_BP4_AP:
1305                 SET_SPEED(SPEED_1G);
1306                 SET_SPEED(SPEED_10G);
1307                 break;
1308
1309         case FW_PORT_TYPE_BP40_BA:
1310         case FW_PORT_TYPE_QSFP:
1311                 SET_SPEED(SPEED_40G);
1312                 break;
1313
1314         case FW_PORT_TYPE_CR_QSFP:
1315         case FW_PORT_TYPE_SFP28:
1316         case FW_PORT_TYPE_KR_SFP28:
1317                 FW_CAPS_TO_SPEED(SPEED_1G);
1318                 FW_CAPS_TO_SPEED(SPEED_10G);
1319                 FW_CAPS_TO_SPEED(SPEED_25G);
1320                 break;
1321
1322         case FW_PORT_TYPE_CR2_QSFP:
1323                 SET_SPEED(SPEED_50G);
1324                 break;
1325
1326         case FW_PORT_TYPE_KR4_100G:
1327         case FW_PORT_TYPE_CR4_QSFP:
1328                 FW_CAPS_TO_SPEED(SPEED_25G);
1329                 FW_CAPS_TO_SPEED(SPEED_40G);
1330                 FW_CAPS_TO_SPEED(SPEED_50G);
1331                 FW_CAPS_TO_SPEED(SPEED_100G);
1332                 break;
1333
1334         default:
1335                 break;
1336         }
1337
1338 #undef FW_CAPS_TO_SPEED
1339 #undef SET_SPEED
1340 }
1341
1342 /**
1343  * cxgbe_get_speed_caps - Fetch supported speed capabilities
1344  * @pi: Underlying port's info
1345  * @speed_caps: Device Info speed capabilities
1346  *
1347  * Fetch supported speed capabilities of the underlying port.
1348  */
1349 void cxgbe_get_speed_caps(struct port_info *pi, u32 *speed_caps)
1350 {
1351         *speed_caps = 0;
1352
1353         fw_caps_to_speed_caps(pi->port_type, pi->link_cfg.pcaps,
1354                               speed_caps);
1355
1356         if (!(pi->link_cfg.pcaps & FW_PORT_CAP32_ANEG))
1357                 *speed_caps |= ETH_LINK_SPEED_FIXED;
1358 }
1359
1360 /**
1361  * cxgb_up - enable the adapter
1362  * @adap: adapter being enabled
1363  *
1364  * Called when the first port is enabled, this function performs the
1365  * actions necessary to make an adapter operational, such as completing
1366  * the initialization of HW modules, and enabling interrupts.
1367  */
1368 int cxgbe_up(struct adapter *adap)
1369 {
1370         enable_rx(adap, &adap->sge.fw_evtq);
1371         t4_sge_tx_monitor_start(adap);
1372         if (is_pf4(adap))
1373                 t4_intr_enable(adap);
1374         adap->flags |= FULL_INIT_DONE;
1375
1376         /* TODO: deadman watchdog ?? */
1377         return 0;
1378 }
1379
1380 /*
1381  * Close the port
1382  */
1383 int cxgbe_down(struct port_info *pi)
1384 {
1385         struct adapter *adapter = pi->adapter;
1386         int err = 0;
1387
1388         err = t4_enable_vi(adapter, adapter->mbox, pi->viid, false, false);
1389         if (err) {
1390                 dev_err(adapter, "%s: disable_vi failed: %d\n", __func__, err);
1391                 return err;
1392         }
1393
1394         t4_reset_link_config(adapter, pi->pidx);
1395         return 0;
1396 }
1397
1398 /*
1399  * Release resources when all the ports have been stopped.
1400  */
1401 void cxgbe_close(struct adapter *adapter)
1402 {
1403         struct port_info *pi;
1404         int i;
1405
1406         if (adapter->flags & FULL_INIT_DONE) {
1407                 if (is_pf4(adapter))
1408                         t4_intr_disable(adapter);
1409                 tid_free(&adapter->tids);
1410                 t4_sge_tx_monitor_stop(adapter);
1411                 t4_free_sge_resources(adapter);
1412                 for_each_port(adapter, i) {
1413                         pi = adap2pinfo(adapter, i);
1414                         if (pi->viid != 0)
1415                                 t4_free_vi(adapter, adapter->mbox,
1416                                            adapter->pf, 0, pi->viid);
1417                         rte_free(pi->eth_dev->data->mac_addrs);
1418                         /* Skip first port since it'll be freed by DPDK stack */
1419                         if (i) {
1420                                 rte_free(pi->eth_dev->data->dev_private);
1421                                 rte_eth_dev_release_port(pi->eth_dev);
1422                         }
1423                 }
1424                 adapter->flags &= ~FULL_INIT_DONE;
1425         }
1426
1427         if (is_pf4(adapter) && (adapter->flags & FW_OK))
1428                 t4_fw_bye(adapter, adapter->mbox);
1429 }
1430
1431 int cxgbe_probe(struct adapter *adapter)
1432 {
1433         struct port_info *pi;
1434         int chip;
1435         int func, i;
1436         int err = 0;
1437         u32 whoami;
1438
1439         whoami = t4_read_reg(adapter, A_PL_WHOAMI);
1440         chip = t4_get_chip_type(adapter,
1441                         CHELSIO_PCI_ID_VER(adapter->pdev->id.device_id));
1442         if (chip < 0)
1443                 return chip;
1444
1445         func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ?
1446                G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
1447
1448         adapter->mbox = func;
1449         adapter->pf = func;
1450
1451         t4_os_lock_init(&adapter->mbox_lock);
1452         TAILQ_INIT(&adapter->mbox_list);
1453
1454         err = t4_prep_adapter(adapter);
1455         if (err)
1456                 return err;
1457
1458         setup_memwin(adapter);
1459         err = adap_init0(adapter);
1460         if (err) {
1461                 dev_err(adapter, "%s: Adapter initialization failed, error %d\n",
1462                         __func__, err);
1463                 goto out_free;
1464         }
1465
1466         if (!is_t4(adapter->params.chip)) {
1467                 /*
1468                  * The userspace doorbell BAR is split evenly into doorbell
1469                  * regions, each associated with an egress queue.  If this
1470                  * per-queue region is large enough (at least UDBS_SEG_SIZE)
1471                  * then it can be used to submit a tx work request with an
1472                  * implied doorbell.  Enable write combining on the BAR if
1473                  * there is room for such work requests.
1474                  */
1475                 int s_qpp, qpp, num_seg;
1476
1477                 s_qpp = (S_QUEUESPERPAGEPF0 +
1478                         (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) *
1479                         adapter->pf);
1480                 qpp = 1 << ((t4_read_reg(adapter,
1481                                 A_SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp)
1482                                 & M_QUEUESPERPAGEPF0);
1483                 num_seg = CXGBE_PAGE_SIZE / UDBS_SEG_SIZE;
1484                 if (qpp > num_seg)
1485                         dev_warn(adapter, "Incorrect SGE EGRESS QUEUES_PER_PAGE configuration, continuing in debug mode\n");
1486
1487                 adapter->bar2 = (void *)adapter->pdev->mem_resource[2].addr;
1488                 if (!adapter->bar2) {
1489                         dev_err(adapter, "cannot map device bar2 region\n");
1490                         err = -ENOMEM;
1491                         goto out_free;
1492                 }
1493                 t4_write_reg(adapter, A_SGE_STAT_CFG, V_STATSOURCE_T5(7) |
1494                              V_STATMODE(0));
1495         }
1496
1497         for_each_port(adapter, i) {
1498                 const unsigned int numa_node = rte_socket_id();
1499                 char name[RTE_ETH_NAME_MAX_LEN];
1500                 struct rte_eth_dev *eth_dev;
1501
1502                 snprintf(name, sizeof(name), "%s_%d",
1503                          adapter->pdev->device.name, i);
1504
1505                 if (i == 0) {
1506                         /* First port is already allocated by DPDK */
1507                         eth_dev = adapter->eth_dev;
1508                         goto allocate_mac;
1509                 }
1510
1511                 /*
1512                  * now do all data allocation - for eth_dev structure,
1513                  * and internal (private) data for the remaining ports
1514                  */
1515
1516                 /* reserve an ethdev entry */
1517                 eth_dev = rte_eth_dev_allocate(name);
1518                 if (!eth_dev)
1519                         goto out_free;
1520
1521                 eth_dev->data->dev_private =
1522                         rte_zmalloc_socket(name, sizeof(struct port_info),
1523                                            RTE_CACHE_LINE_SIZE, numa_node);
1524                 if (!eth_dev->data->dev_private)
1525                         goto out_free;
1526
1527 allocate_mac:
1528                 pi = (struct port_info *)eth_dev->data->dev_private;
1529                 adapter->port[i] = pi;
1530                 pi->eth_dev = eth_dev;
1531                 pi->adapter = adapter;
1532                 pi->xact_addr_filt = -1;
1533                 pi->port_id = i;
1534                 pi->pidx = i;
1535
1536                 pi->eth_dev->device = &adapter->pdev->device;
1537                 pi->eth_dev->dev_ops = adapter->eth_dev->dev_ops;
1538                 pi->eth_dev->tx_pkt_burst = adapter->eth_dev->tx_pkt_burst;
1539                 pi->eth_dev->rx_pkt_burst = adapter->eth_dev->rx_pkt_burst;
1540
1541                 rte_eth_copy_pci_info(pi->eth_dev, adapter->pdev);
1542
1543                 pi->eth_dev->data->mac_addrs = rte_zmalloc(name,
1544                                                            ETHER_ADDR_LEN, 0);
1545                 if (!pi->eth_dev->data->mac_addrs) {
1546                         dev_err(adapter, "%s: Mem allocation failed for storing mac addr, aborting\n",
1547                                 __func__);
1548                         err = -1;
1549                         goto out_free;
1550                 }
1551
1552                 if (i > 0) {
1553                         /* First port will be notified by upper layer */
1554                         rte_eth_dev_probing_finish(eth_dev);
1555                 }
1556         }
1557
1558         if (adapter->flags & FW_OK) {
1559                 err = t4_port_init(adapter, adapter->mbox, adapter->pf, 0);
1560                 if (err) {
1561                         dev_err(adapter, "%s: t4_port_init failed with err %d\n",
1562                                 __func__, err);
1563                         goto out_free;
1564                 }
1565         }
1566
1567         cfg_queues(adapter->eth_dev);
1568
1569         print_adapter_info(adapter);
1570         print_port_info(adapter);
1571
1572         if (tid_init(&adapter->tids) < 0) {
1573                 /* Disable filtering support */
1574                 dev_warn(adapter, "could not allocate TID table, "
1575                          "filter support disabled. Continuing\n");
1576         }
1577
1578         err = init_rss(adapter);
1579         if (err)
1580                 goto out_free;
1581
1582         return 0;
1583
1584 out_free:
1585         for_each_port(adapter, i) {
1586                 pi = adap2pinfo(adapter, i);
1587                 if (pi->viid != 0)
1588                         t4_free_vi(adapter, adapter->mbox, adapter->pf,
1589                                    0, pi->viid);
1590                 /* Skip first port since it'll be de-allocated by DPDK */
1591                 if (i == 0)
1592                         continue;
1593                 if (pi->eth_dev) {
1594                         if (pi->eth_dev->data->dev_private)
1595                                 rte_free(pi->eth_dev->data->dev_private);
1596                         rte_eth_dev_release_port(pi->eth_dev);
1597                 }
1598         }
1599
1600         if (adapter->flags & FW_OK)
1601                 t4_fw_bye(adapter, adapter->mbox);
1602         return -err;
1603 }