drivers/net/cxgbe/cxgbe_main.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Chelsio Communications.
   3  * All rights reserved.
   4  */
   5
   6 #include <sys/queue.h>
   7 #include <stdio.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <string.h>
  11 #include <unistd.h>
  12 #include <stdarg.h>
  13 #include <inttypes.h>
  14 #include <netinet/in.h>
  15
  16 #include <rte_byteorder.h>
  17 #include <rte_common.h>
  18 #include <rte_cycles.h>
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_atomic.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_tailq.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <rte_ethdev_driver.h>
  31 #include <rte_ethdev_pci.h>
  32 #include <rte_random.h>
  33 #include <rte_dev.h>
  34 #include <rte_kvargs.h>
  35
  36 #include "common.h"
  37 #include "t4_regs.h"
  38 #include "t4_msg.h"
  39 #include "cxgbe.h"
  40
  41 /*
  42  * Response queue handler for the FW event queue.
  43  */
  44 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
  45                           __rte_unused const struct pkt_gl *gl)
  46 {
  47         u8 opcode = ((const struct rss_header *)rsp)->opcode;
  48
  49         rsp++;                                          /* skip RSS header */
  50
  51         /*
  52          * FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
  53          */
  54         if (unlikely(opcode == CPL_FW4_MSG &&
  55                      ((const struct cpl_fw4_msg *)rsp)->type ==
  56                       FW_TYPE_RSSCPL)) {
  57                 rsp++;
  58                 opcode = ((const struct rss_header *)rsp)->opcode;
  59                 rsp++;
  60                 if (opcode != CPL_SGE_EGR_UPDATE) {
  61                         dev_err(q->adapter, "unexpected FW4/CPL %#x on FW event queue\n",
  62                                 opcode);
  63                         goto out;
  64                 }
  65         }
  66
  67         if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
  68                 /* do nothing */
  69         } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
  70                 const struct cpl_fw6_msg *msg = (const void *)rsp;
  71
  72                 t4_handle_fw_rpl(q->adapter, msg->data);
  73         } else {
  74                 dev_err(adapter, "unexpected CPL %#x on FW event queue\n",
  75                         opcode);
  76         }
  77 out:
  78         return 0;
  79 }
  80
  81 int setup_sge_fwevtq(struct adapter *adapter)
  82 {
  83         struct sge *s = &adapter->sge;
  84         int err = 0;
  85         int msi_idx = 0;
  86
  87         err = t4_sge_alloc_rxq(adapter, &s->fw_evtq, true, adapter->eth_dev,
  88                                msi_idx, NULL, fwevtq_handler, -1, NULL, 0,
  89                                rte_socket_id());
  90         return err;
  91 }
  92
  93 static int closest_timer(const struct sge *s, int time)
  94 {
  95         unsigned int i, match = 0;
  96         int delta, min_delta = INT_MAX;
  97
  98         for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
  99                 delta = time - s->timer_val[i];
 100                 if (delta < 0)
 101                         delta = -delta;
 102                 if (delta < min_delta) {
 103                         min_delta = delta;
 104                         match = i;
 105                 }
 106         }
 107         return match;
 108 }
 109
 110 static int closest_thres(const struct sge *s, int thres)
 111 {
 112         unsigned int i, match = 0;
 113         int delta, min_delta = INT_MAX;
 114
 115         for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
 116                 delta = thres - s->counter_val[i];
 117                 if (delta < 0)
 118                         delta = -delta;
 119                 if (delta < min_delta) {
 120                         min_delta = delta;
 121                         match = i;
 122                 }
 123         }
 124         return match;
 125 }
 126
 127 /**
 128  * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
 129  * @q: the Rx queue
 130  * @us: the hold-off time in us, or 0 to disable timer
 131  * @cnt: the hold-off packet count, or 0 to disable counter
 132  *
 133  * Sets an Rx queue's interrupt hold-off time and packet count.  At least
 134  * one of the two needs to be enabled for the queue to generate interrupts.
 135  */
 136 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
 137                                unsigned int cnt)
 138 {
 139         struct adapter *adap = q->adapter;
 140         unsigned int timer_val;
 141
 142         if (cnt) {
 143                 int err;
 144                 u32 v, new_idx;
 145
 146                 new_idx = closest_thres(&adap->sge, cnt);
 147                 if (q->desc && q->pktcnt_idx != new_idx) {
 148                         /* the queue has already been created, update it */
 149                         v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
 150                             V_FW_PARAMS_PARAM_X(
 151                             FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
 152                             V_FW_PARAMS_PARAM_YZ(q->cntxt_id);
 153                         err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
 154                                             &v, &new_idx);
 155                         if (err)
 156                                 return err;
 157                 }
 158                 q->pktcnt_idx = new_idx;
 159         }
 160
 161         timer_val = (us == 0) ? X_TIMERREG_RESTART_COUNTER :
 162                                 closest_timer(&adap->sge, us);
 163
 164         if ((us | cnt) == 0)
 165                 q->intr_params = V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX);
 166         else
 167                 q->intr_params = V_QINTR_TIMER_IDX(timer_val) |
 168                                  V_QINTR_CNT_EN(cnt > 0);
 169         return 0;
 170 }
 171
 172 static inline bool is_x_1g_port(const struct link_config *lc)
 173 {
 174         return (lc->pcaps & FW_PORT_CAP32_SPEED_1G) != 0;
 175 }
 176
 177 static inline bool is_x_10g_port(const struct link_config *lc)
 178 {
 179         unsigned int speeds, high_speeds;
 180
 181         speeds = V_FW_PORT_CAP32_SPEED(G_FW_PORT_CAP32_SPEED(lc->pcaps));
 182         high_speeds = speeds &
 183                       ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G);
 184
 185         return high_speeds != 0;
 186 }
 187
 188 inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
 189                       unsigned int us, unsigned int cnt,
 190                       unsigned int size, unsigned int iqe_size)
 191 {
 192         q->adapter = adap;
 193         cxgb4_set_rspq_intr_params(q, us, cnt);
 194         q->iqe_len = iqe_size;
 195         q->size = size;
 196 }
 197
 198 int cfg_queue_count(struct rte_eth_dev *eth_dev)
 199 {
 200         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 201         struct adapter *adap = pi->adapter;
 202         struct sge *s = &adap->sge;
 203         unsigned int max_queues = s->max_ethqsets / adap->params.nports;
 204
 205         if ((eth_dev->data->nb_rx_queues < 1) ||
 206             (eth_dev->data->nb_tx_queues < 1))
 207                 return -EINVAL;
 208
 209         if ((eth_dev->data->nb_rx_queues > max_queues) ||
 210             (eth_dev->data->nb_tx_queues > max_queues))
 211                 return -EINVAL;
 212
 213         if (eth_dev->data->nb_rx_queues > pi->rss_size)
 214                 return -EINVAL;
 215
 216         /* We must configure RSS, since config has changed*/
 217         pi->flags &= ~PORT_RSS_DONE;
 218
 219         pi->n_rx_qsets = eth_dev->data->nb_rx_queues;
 220         pi->n_tx_qsets = eth_dev->data->nb_tx_queues;
 221
 222         return 0;
 223 }
 224
 225 void cfg_queues(struct rte_eth_dev *eth_dev)
 226 {
 227         struct rte_config *config = rte_eal_get_configuration();
 228         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 229         struct adapter *adap = pi->adapter;
 230         struct sge *s = &adap->sge;
 231         unsigned int i, nb_ports = 0, qidx = 0;
 232         unsigned int q_per_port = 0;
 233
 234         if (!(adap->flags & CFG_QUEUES)) {
 235                 for_each_port(adap, i) {
 236                         struct port_info *tpi = adap2pinfo(adap, i);
 237
 238                         nb_ports += (is_x_10g_port(&tpi->link_cfg)) ||
 239                                      is_x_1g_port(&tpi->link_cfg) ? 1 : 0;
 240                 }
 241
 242                 /*
 243                  * We default up to # of cores queues per 1G/10G port.
 244                  */
 245                 if (nb_ports)
 246                         q_per_port = (MAX_ETH_QSETS -
 247                                      (adap->params.nports - nb_ports)) /
 248                                      nb_ports;
 249
 250                 if (q_per_port > config->lcore_count)
 251                         q_per_port = config->lcore_count;
 252
 253                 for_each_port(adap, i) {
 254                         struct port_info *pi = adap2pinfo(adap, i);
 255
 256                         pi->first_qset = qidx;
 257
 258                         /* Initially n_rx_qsets == n_tx_qsets */
 259                         pi->n_rx_qsets = (is_x_10g_port(&pi->link_cfg) ||
 260                                           is_x_1g_port(&pi->link_cfg)) ?
 261                                           q_per_port : 1;
 262                         pi->n_tx_qsets = pi->n_rx_qsets;
 263
 264                         if (pi->n_rx_qsets > pi->rss_size)
 265                                 pi->n_rx_qsets = pi->rss_size;
 266
 267                         qidx += pi->n_rx_qsets;
 268                 }
 269
 270                 s->max_ethqsets = qidx;
 271
 272                 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
 273                         struct sge_eth_rxq *r = &s->ethrxq[i];
 274
 275                         init_rspq(adap, &r->rspq, 5, 32, 1024, 64);
 276                         r->usembufs = 1;
 277                         r->fl.size = (r->usembufs ? 1024 : 72);
 278                 }
 279
 280                 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
 281                         s->ethtxq[i].q.size = 1024;
 282
 283                 init_rspq(adap, &adap->sge.fw_evtq, 0, 0, 1024, 64);
 284                 adap->flags |= CFG_QUEUES;
 285         }
 286 }
 287
 288 void cxgbe_stats_get(struct port_info *pi, struct port_stats *stats)
 289 {
 290         t4_get_port_stats_offset(pi->adapter, pi->tx_chan, stats,
 291                                  &pi->stats_base);
 292 }
 293
 294 void cxgbe_stats_reset(struct port_info *pi)
 295 {
 296         t4_clr_port_stats(pi->adapter, pi->tx_chan);
 297 }
 298
 299 static void setup_memwin(struct adapter *adap)
 300 {
 301         u32 mem_win0_base;
 302
 303         /* For T5, only relative offset inside the PCIe BAR is passed */
 304         mem_win0_base = MEMWIN0_BASE;
 305
 306         /*
 307          * Set up memory window for accessing adapter memory ranges.  (Read
 308          * back MA register to ensure that changes propagate before we attempt
 309          * to use the new values.)
 310          */
 311         t4_write_reg(adap,
 312                      PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
 313                                          MEMWIN_NIC),
 314                      mem_win0_base | V_BIR(0) |
 315                      V_WINDOW(ilog2(MEMWIN0_APERTURE) - X_WINDOW_SHIFT));
 316         t4_read_reg(adap,
 317                     PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
 318                                         MEMWIN_NIC));
 319 }
 320
 321 int init_rss(struct adapter *adap)
 322 {
 323         unsigned int i;
 324
 325         if (is_pf4(adap)) {
 326                 int err;
 327
 328                 err = t4_init_rss_mode(adap, adap->mbox);
 329                 if (err)
 330                         return err;
 331         }
 332
 333         for_each_port(adap, i) {
 334                 struct port_info *pi = adap2pinfo(adap, i);
 335
 336                 pi->rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
 337                 if (!pi->rss)
 338                         return -ENOMEM;
 339
 340                 pi->rss_hf = CXGBE_RSS_HF_ALL;
 341         }
 342         return 0;
 343 }
 344
 345 /**
 346  * Dump basic information about the adapter.
 347  */
 348 void print_adapter_info(struct adapter *adap)
 349 {
 350         /**
 351          * Hardware/Firmware/etc. Version/Revision IDs.
 352          */
 353         t4_dump_version_info(adap);
 354 }
 355
 356 void print_port_info(struct adapter *adap)
 357 {
 358         int i;
 359         char buf[80];
 360         struct rte_pci_addr *loc = &adap->pdev->addr;
 361
 362         for_each_port(adap, i) {
 363                 const struct port_info *pi = adap2pinfo(adap, i);
 364                 char *bufp = buf;
 365
 366                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M)
 367                         bufp += sprintf(bufp, "100M/");
 368                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G)
 369                         bufp += sprintf(bufp, "1G/");
 370                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G)
 371                         bufp += sprintf(bufp, "10G/");
 372                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G)
 373                         bufp += sprintf(bufp, "25G/");
 374                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G)
 375                         bufp += sprintf(bufp, "40G/");
 376                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G)
 377                         bufp += sprintf(bufp, "50G/");
 378                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G)
 379                         bufp += sprintf(bufp, "100G/");
 380                 if (bufp != buf)
 381                         --bufp;
 382                 sprintf(bufp, "BASE-%s",
 383                         t4_get_port_type_description(
 384                                         (enum fw_port_type)pi->port_type));
 385
 386                 dev_info(adap,
 387                          " " PCI_PRI_FMT " Chelsio rev %d %s %s\n",
 388                          loc->domain, loc->bus, loc->devid, loc->function,
 389                          CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
 390                          (adap->flags & USING_MSIX) ? " MSI-X" :
 391                          (adap->flags & USING_MSI) ? " MSI" : "");
 392         }
 393 }
 394
 395 static int
 396 check_devargs_handler(__rte_unused const char *key, const char *value,
 397                       __rte_unused void *opaque)
 398 {
 399         if (strcmp(value, "1"))
 400                 return -1;
 401
 402         return 0;
 403 }
 404
 405 int cxgbe_get_devargs(struct rte_devargs *devargs, const char *key)
 406 {
 407         struct rte_kvargs *kvlist;
 408
 409         if (!devargs)
 410                 return 0;
 411
 412         kvlist = rte_kvargs_parse(devargs->args, NULL);
 413         if (!kvlist)
 414                 return 0;
 415
 416         if (!rte_kvargs_count(kvlist, key)) {
 417                 rte_kvargs_free(kvlist);
 418                 return 0;
 419         }
 420
 421         if (rte_kvargs_process(kvlist, key,
 422                                check_devargs_handler, NULL) < 0) {
 423                 rte_kvargs_free(kvlist);
 424                 return 0;
 425         }
 426         rte_kvargs_free(kvlist);
 427
 428         return 1;
 429 }
 430
 431 static void configure_vlan_types(struct adapter *adapter)
 432 {
 433         struct rte_pci_device *pdev = adapter->pdev;
 434         int i;
 435
 436         for_each_port(adapter, i) {
 437                 /* OVLAN Type 0x88a8 */
 438                 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN0),
 439                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 440                                  V_OVLAN_ETYPE(M_OVLAN_ETYPE),
 441                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 442                                  V_OVLAN_ETYPE(0x88a8));
 443                 /* OVLAN Type 0x9100 */
 444                 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN1),
 445                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 446                                  V_OVLAN_ETYPE(M_OVLAN_ETYPE),
 447                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 448                                  V_OVLAN_ETYPE(0x9100));
 449                 /* OVLAN Type 0x8100 */
 450                 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN2),
 451                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 452                                  V_OVLAN_ETYPE(M_OVLAN_ETYPE),
 453                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 454                                  V_OVLAN_ETYPE(0x8100));
 455
 456                 /* IVLAN 0X8100 */
 457                 t4_set_reg_field(adapter, MPS_PORT_RX_IVLAN(i),
 458                                  V_IVLAN_ETYPE(M_IVLAN_ETYPE),
 459                                  V_IVLAN_ETYPE(0x8100));
 460
 461                 t4_set_reg_field(adapter, MPS_PORT_RX_CTL(i),
 462                                  F_OVLAN_EN0 | F_OVLAN_EN1 |
 463                                  F_OVLAN_EN2 | F_IVLAN_EN,
 464                                  F_OVLAN_EN0 | F_OVLAN_EN1 |
 465                                  F_OVLAN_EN2 | F_IVLAN_EN);
 466         }
 467
 468         if (cxgbe_get_devargs(pdev->device.devargs, CXGBE_DEVARG_KEEP_OVLAN))
 469                 t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG,
 470                                        V_RM_OVLAN(1), V_RM_OVLAN(0));
 471 }
 472
 473 static void configure_pcie_ext_tag(struct adapter *adapter)
 474 {
 475         u16 v;
 476         int pos = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
 477
 478         if (!pos)
 479                 return;
 480
 481         if (pos > 0) {
 482                 t4_os_pci_read_cfg2(adapter, pos + PCI_EXP_DEVCTL, &v);
 483                 v |= PCI_EXP_DEVCTL_EXT_TAG;
 484                 t4_os_pci_write_cfg2(adapter, pos + PCI_EXP_DEVCTL, v);
 485                 if (is_t6(adapter->params.chip)) {
 486                         t4_set_reg_field(adapter, A_PCIE_CFG2,
 487                                          V_T6_TOTMAXTAG(M_T6_TOTMAXTAG),
 488                                          V_T6_TOTMAXTAG(7));
 489                         t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
 490                                          V_T6_MINTAG(M_T6_MINTAG),
 491                                          V_T6_MINTAG(8));
 492                 } else {
 493                         t4_set_reg_field(adapter, A_PCIE_CFG2,
 494                                          V_TOTMAXTAG(M_TOTMAXTAG),
 495                                          V_TOTMAXTAG(3));
 496                         t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
 497                                          V_MINTAG(M_MINTAG),
 498                                          V_MINTAG(8));
 499                 }
 500         }
 501 }
 502
 503 /*
 504  * Tweak configuration based on system architecture, etc.  Most of these have
 505  * defaults assigned to them by Firmware Configuration Files (if we're using
 506  * them) but need to be explicitly set if we're using hard-coded
 507  * initialization. So these are essentially common tweaks/settings for
 508  * Configuration Files and hard-coded initialization ...
 509  */
 510 static int adap_init0_tweaks(struct adapter *adapter)
 511 {
 512         u8 rx_dma_offset;
 513
 514         /*
 515          * Fix up various Host-Dependent Parameters like Page Size, Cache
 516          * Line Size, etc.  The firmware default is for a 4KB Page Size and
 517          * 64B Cache Line Size ...
 518          */
 519         t4_fixup_host_params_compat(adapter, CXGBE_PAGE_SIZE, L1_CACHE_BYTES,
 520                                     T5_LAST_REV);
 521
 522         /*
 523          * Keep the chip default offset to deliver Ingress packets into our
 524          * DMA buffers to zero
 525          */
 526         rx_dma_offset = 0;
 527         t4_set_reg_field(adapter, A_SGE_CONTROL, V_PKTSHIFT(M_PKTSHIFT),
 528                          V_PKTSHIFT(rx_dma_offset));
 529
 530         t4_set_reg_field(adapter, A_SGE_FLM_CFG,
 531                          V_CREDITCNT(M_CREDITCNT) | M_CREDITCNTPACKING,
 532                          V_CREDITCNT(3) | V_CREDITCNTPACKING(1));
 533
 534         t4_set_reg_field(adapter, A_SGE_INGRESS_RX_THRESHOLD,
 535                          V_THRESHOLD_3(M_THRESHOLD_3), V_THRESHOLD_3(32U));
 536
 537         t4_set_reg_field(adapter, A_SGE_CONTROL2, V_IDMAARBROUNDROBIN(1U),
 538                          V_IDMAARBROUNDROBIN(1U));
 539
 540         /*
 541          * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
 542          * adds the pseudo header itself.
 543          */
 544         t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG,
 545                                F_CSUM_HAS_PSEUDO_HDR, 0);
 546
 547         return 0;
 548 }
 549
 550 /*
 551  * Attempt to initialize the adapter via a Firmware Configuration File.
 552  */
 553 static int adap_init0_config(struct adapter *adapter, int reset)
 554 {
 555         struct fw_caps_config_cmd caps_cmd;
 556         unsigned long mtype = 0, maddr = 0;
 557         u32 finiver, finicsum, cfcsum;
 558         int ret;
 559         int config_issued = 0;
 560         int cfg_addr;
 561         char config_name[20];
 562
 563         /*
 564          * Reset device if necessary.
 565          */
 566         if (reset) {
 567                 ret = t4_fw_reset(adapter, adapter->mbox,
 568                                   F_PIORSTMODE | F_PIORST);
 569                 if (ret < 0) {
 570                         dev_warn(adapter, "Firmware reset failed, error %d\n",
 571                                  -ret);
 572                         goto bye;
 573                 }
 574         }
 575
 576         cfg_addr = t4_flash_cfg_addr(adapter);
 577         if (cfg_addr < 0) {
 578                 ret = cfg_addr;
 579                 dev_warn(adapter, "Finding address for firmware config file in flash failed, error %d\n",
 580                          -ret);
 581                 goto bye;
 582         }
 583
 584         strcpy(config_name, "On Flash");
 585         mtype = FW_MEMTYPE_CF_FLASH;
 586         maddr = cfg_addr;
 587
 588         /*
 589          * Issue a Capability Configuration command to the firmware to get it
 590          * to parse the Configuration File.  We don't use t4_fw_config_file()
 591          * because we want the ability to modify various features after we've
 592          * processed the configuration file ...
 593          */
 594         memset(&caps_cmd, 0, sizeof(caps_cmd));
 595         caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
 596                                            F_FW_CMD_REQUEST | F_FW_CMD_READ);
 597         caps_cmd.cfvalid_to_len16 =
 598                 cpu_to_be32(F_FW_CAPS_CONFIG_CMD_CFVALID |
 599                             V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
 600                             V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
 601                             FW_LEN16(caps_cmd));
 602         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
 603                          &caps_cmd);
 604         /*
 605          * If the CAPS_CONFIG failed with an ENOENT (for a Firmware
 606          * Configuration File in FLASH), our last gasp effort is to use the
 607          * Firmware Configuration File which is embedded in the firmware.  A
 608          * very few early versions of the firmware didn't have one embedded
 609          * but we can ignore those.
 610          */
 611         if (ret == -ENOENT) {
 612                 dev_info(adapter, "%s: Going for embedded config in firmware..\n",
 613                          __func__);
 614
 615                 memset(&caps_cmd, 0, sizeof(caps_cmd));
 616                 caps_cmd.op_to_write =
 617                         cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
 618                                     F_FW_CMD_REQUEST | F_FW_CMD_READ);
 619                 caps_cmd.cfvalid_to_len16 = cpu_to_be32(FW_LEN16(caps_cmd));
 620                 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
 621                                  sizeof(caps_cmd), &caps_cmd);
 622                 strcpy(config_name, "Firmware Default");
 623         }
 624
 625         config_issued = 1;
 626         if (ret < 0)
 627                 goto bye;
 628
 629         finiver = be32_to_cpu(caps_cmd.finiver);
 630         finicsum = be32_to_cpu(caps_cmd.finicsum);
 631         cfcsum = be32_to_cpu(caps_cmd.cfcsum);
 632         if (finicsum != cfcsum)
 633                 dev_warn(adapter, "Configuration File checksum mismatch: [fini] csum=%#x, computed csum=%#x\n",
 634                          finicsum, cfcsum);
 635
 636         /*
 637          * If we're a pure NIC driver then disable all offloading facilities.
 638          * This will allow the firmware to optimize aspects of the hardware
 639          * configuration which will result in improved performance.
 640          */
 641         caps_cmd.niccaps &= cpu_to_be16(~(FW_CAPS_CONFIG_NIC_HASHFILTER |
 642                                           FW_CAPS_CONFIG_NIC_ETHOFLD));
 643         caps_cmd.toecaps = 0;
 644         caps_cmd.iscsicaps = 0;
 645         caps_cmd.rdmacaps = 0;
 646         caps_cmd.fcoecaps = 0;
 647
 648         /*
 649          * And now tell the firmware to use the configuration we just loaded.
 650          */
 651         caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
 652                                            F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
 653         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
 654         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
 655                          NULL);
 656         if (ret < 0) {
 657                 dev_warn(adapter, "Unable to finalize Firmware Capabilities %d\n",
 658                          -ret);
 659                 goto bye;
 660         }
 661
 662         /*
 663          * Tweak configuration based on system architecture, etc.
 664          */
 665         ret = adap_init0_tweaks(adapter);
 666         if (ret < 0) {
 667                 dev_warn(adapter, "Unable to do init0-tweaks %d\n", -ret);
 668                 goto bye;
 669         }
 670
 671         /*
 672          * And finally tell the firmware to initialize itself using the
 673          * parameters from the Configuration File.
 674          */
 675         ret = t4_fw_initialize(adapter, adapter->mbox);
 676         if (ret < 0) {
 677                 dev_warn(adapter, "Initializing Firmware failed, error %d\n",
 678                          -ret);
 679                 goto bye;
 680         }
 681
 682         /*
 683          * Return successfully and note that we're operating with parameters
 684          * not supplied by the driver, rather than from hard-wired
 685          * initialization constants buried in the driver.
 686          */
 687         dev_info(adapter,
 688                  "Successfully configured using Firmware Configuration File \"%s\", version %#x, computed checksum %#x\n",
 689                  config_name, finiver, cfcsum);
 690
 691         return 0;
 692
 693         /*
 694          * Something bad happened.  Return the error ...  (If the "error"
 695          * is that there's no Configuration File on the adapter we don't
 696          * want to issue a warning since this is fairly common.)
 697          */
 698 bye:
 699         if (config_issued && ret != -ENOENT)
 700                 dev_warn(adapter, "\"%s\" configuration file error %d\n",
 701                          config_name, -ret);
 702
 703         dev_debug(adapter, "%s: returning ret = %d ..\n", __func__, ret);
 704         return ret;
 705 }
 706
 707 static int adap_init0(struct adapter *adap)
 708 {
 709         int ret = 0;
 710         u32 v, port_vec;
 711         enum dev_state state;
 712         u32 params[7], val[7];
 713         int reset = 1;
 714         int mbox = adap->mbox;
 715
 716         /*
 717          * Contact FW, advertising Master capability.
 718          */
 719         ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state);
 720         if (ret < 0) {
 721                 dev_err(adap, "%s: could not connect to FW, error %d\n",
 722                         __func__, -ret);
 723                 goto bye;
 724         }
 725
 726         CXGBE_DEBUG_MBOX(adap, "%s: adap->mbox = %d; ret = %d\n", __func__,
 727                          adap->mbox, ret);
 728
 729         if (ret == mbox)
 730                 adap->flags |= MASTER_PF;
 731
 732         if (state == DEV_STATE_INIT) {
 733                 /*
 734                  * Force halt and reset FW because a previous instance may have
 735                  * exited abnormally without properly shutting down
 736                  */
 737                 ret = t4_fw_halt(adap, adap->mbox, reset);
 738                 if (ret < 0) {
 739                         dev_err(adap, "Failed to halt. Exit.\n");
 740                         goto bye;
 741                 }
 742
 743                 ret = t4_fw_restart(adap, adap->mbox, reset);
 744                 if (ret < 0) {
 745                         dev_err(adap, "Failed to restart. Exit.\n");
 746                         goto bye;
 747                 }
 748                 state = (enum dev_state)((unsigned)state & ~DEV_STATE_INIT);
 749         }
 750
 751         t4_get_version_info(adap);
 752
 753         ret = t4_get_core_clock(adap, &adap->params.vpd);
 754         if (ret < 0) {
 755                 dev_err(adap, "%s: could not get core clock, error %d\n",
 756                         __func__, -ret);
 757                 goto bye;
 758         }
 759
 760         /*
 761          * If the firmware is initialized already (and we're not forcing a
 762          * master initialization), note that we're living with existing
 763          * adapter parameters.  Otherwise, it's time to try initializing the
 764          * adapter ...
 765          */
 766         if (state == DEV_STATE_INIT) {
 767                 dev_info(adap, "Coming up as %s: Adapter already initialized\n",
 768                          adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
 769         } else {
 770                 dev_info(adap, "Coming up as MASTER: Initializing adapter\n");
 771
 772                 ret = adap_init0_config(adap, reset);
 773                 if (ret == -ENOENT) {
 774                         dev_err(adap,
 775                                 "No Configuration File present on adapter. Using hard-wired configuration parameters.\n");
 776                         goto bye;
 777                 }
 778         }
 779         if (ret < 0) {
 780                 dev_err(adap, "could not initialize adapter, error %d\n", -ret);
 781                 goto bye;
 782         }
 783
 784         /* Find out what ports are available to us. */
 785         v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
 786             V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC);
 787         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
 788         if (ret < 0) {
 789                 dev_err(adap, "%s: failure in t4_query_params; error = %d\n",
 790                         __func__, ret);
 791                 goto bye;
 792         }
 793
 794         adap->params.nports = hweight32(port_vec);
 795         adap->params.portvec = port_vec;
 796
 797         dev_debug(adap, "%s: adap->params.nports = %u\n", __func__,
 798                   adap->params.nports);
 799
 800         /*
 801          * Give the SGE code a chance to pull in anything that it needs ...
 802          * Note that this must be called after we retrieve our VPD parameters
 803          * in order to know how to convert core ticks to seconds, etc.
 804          */
 805         ret = t4_sge_init(adap);
 806         if (ret < 0) {
 807                 dev_err(adap, "t4_sge_init failed with error %d\n",
 808                         -ret);
 809                 goto bye;
 810         }
 811
 812         /*
 813          * Grab some of our basic fundamental operating parameters.
 814          */
 815 #define FW_PARAM_DEV(param) \
 816         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
 817          V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
 818
 819 #define FW_PARAM_PFVF(param) \
 820         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
 821          V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) |  \
 822          V_FW_PARAMS_PARAM_Y(0) | \
 823          V_FW_PARAMS_PARAM_Z(0))
 824
 825         /* If we're running on newer firmware, let it know that we're
 826          * prepared to deal with encapsulated CPL messages.  Older
 827          * firmware won't understand this and we'll just get
 828          * unencapsulated messages ...
 829          */
 830         params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
 831         val[0] = 1;
 832         (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
 833
 834         /*
 835          * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
 836          * capability.  Earlier versions of the firmware didn't have the
 837          * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
 838          * permission to use ULPTX MEMWRITE DSGL.
 839          */
 840         if (is_t4(adap->params.chip)) {
 841                 adap->params.ulptx_memwrite_dsgl = false;
 842         } else {
 843                 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
 844                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
 845                                       1, params, val);
 846                 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
 847         }
 848
 849         /*
 850          * The MTU/MSS Table is initialized by now, so load their values.  If
 851          * we're initializing the adapter, then we'll make any modifications
 852          * we want to the MTU/MSS Table and also initialize the congestion
 853          * parameters.
 854          */
 855         t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
 856         if (state != DEV_STATE_INIT) {
 857                 int i;
 858
 859                 /*
 860                  * The default MTU Table contains values 1492 and 1500.
 861                  * However, for TCP, it's better to have two values which are
 862                  * a multiple of 8 +/- 4 bytes apart near this popular MTU.
 863                  * This allows us to have a TCP Data Payload which is a
 864                  * multiple of 8 regardless of what combination of TCP Options
 865                  * are in use (always a multiple of 4 bytes) which is
 866                  * important for performance reasons.  For instance, if no
 867                  * options are in use, then we have a 20-byte IP header and a
 868                  * 20-byte TCP header.  In this case, a 1500-byte MSS would
 869                  * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
 870                  * which is not a multiple of 8.  So using an MSS of 1488 in
 871                  * this case results in a TCP Data Payload of 1448 bytes which
 872                  * is a multiple of 8.  On the other hand, if 12-byte TCP Time
 873                  * Stamps have been negotiated, then an MTU of 1500 bytes
 874                  * results in a TCP Data Payload of 1448 bytes which, as
 875                  * above, is a multiple of 8 bytes ...
 876                  */
 877                 for (i = 0; i < NMTUS; i++)
 878                         if (adap->params.mtus[i] == 1492) {
 879                                 adap->params.mtus[i] = 1488;
 880                                 break;
 881                         }
 882
 883                 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
 884                              adap->params.b_wnd);
 885         }
 886         t4_init_sge_params(adap);
 887         t4_init_tp_params(adap);
 888         configure_pcie_ext_tag(adap);
 889         configure_vlan_types(adap);
 890
 891         adap->params.drv_memwin = MEMWIN_NIC;
 892         adap->flags |= FW_OK;
 893         dev_debug(adap, "%s: returning zero..\n", __func__);
 894         return 0;
 895
 896         /*
 897          * Something bad happened.  If a command timed out or failed with EIO
 898          * FW does not operate within its spec or something catastrophic
 899          * happened to HW/FW, stop issuing commands.
 900          */
 901 bye:
 902         if (ret != -ETIMEDOUT && ret != -EIO)
 903                 t4_fw_bye(adap, adap->mbox);
 904         return ret;
 905 }
 906
 907 /**
 908  * t4_os_portmod_changed - handle port module changes
 909  * @adap: the adapter associated with the module change
 910  * @port_id: the port index whose module status has changed
 911  *
 912  * This is the OS-dependent handler for port module changes.  It is
 913  * invoked when a port module is removed or inserted for any OS-specific
 914  * processing.
 915  */
 916 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
 917 {
 918         static const char * const mod_str[] = {
 919                 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
 920         };
 921
 922         const struct port_info *pi = adap2pinfo(adap, port_id);
 923
 924         if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
 925                 dev_info(adap, "Port%d: port module unplugged\n", pi->port_id);
 926         else if (pi->mod_type < ARRAY_SIZE(mod_str))
 927                 dev_info(adap, "Port%d: %s port module inserted\n", pi->port_id,
 928                          mod_str[pi->mod_type]);
 929         else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
 930                 dev_info(adap, "Port%d: unsupported port module inserted\n",
 931                          pi->port_id);
 932         else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
 933                 dev_info(adap, "Port%d: unknown port module inserted\n",
 934                          pi->port_id);
 935         else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
 936                 dev_info(adap, "Port%d: transceiver module error\n",
 937                          pi->port_id);
 938         else
 939                 dev_info(adap, "Port%d: unknown module type %d inserted\n",
 940                          pi->port_id, pi->mod_type);
 941 }
 942
 943 inline bool force_linkup(struct adapter *adap)
 944 {
 945         struct rte_pci_device *pdev = adap->pdev;
 946
 947         if (is_pf4(adap))
 948                 return false;   /* force_linkup not required for pf driver*/
 949         if (!cxgbe_get_devargs(pdev->device.devargs,
 950                                CXGBE_DEVARG_FORCE_LINK_UP))
 951                 return false;
 952         return true;
 953 }
 954
 955 /**
 956  * link_start - enable a port
 957  * @dev: the port to enable
 958  *
 959  * Performs the MAC and PHY actions needed to enable a port.
 960  */
 961 int link_start(struct port_info *pi)
 962 {
 963         struct adapter *adapter = pi->adapter;
 964         int ret;
 965         unsigned int mtu;
 966
 967         mtu = pi->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 968               (ETHER_HDR_LEN + ETHER_CRC_LEN);
 969
 970         /*
 971          * We do not set address filters and promiscuity here, the stack does
 972          * that step explicitly.
 973          */
 974         ret = t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, -1, -1,
 975                             -1, 1, true);
 976         if (ret == 0) {
 977                 ret = t4_change_mac(adapter, adapter->mbox, pi->viid,
 978                                     pi->xact_addr_filt,
 979                                     (u8 *)&pi->eth_dev->data->mac_addrs[0],
 980                                     true, true);
 981                 if (ret >= 0) {
 982                         pi->xact_addr_filt = ret;
 983                         ret = 0;
 984                 }
 985         }
 986         if (ret == 0 && is_pf4(adapter))
 987                 ret = t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
 988                                     &pi->link_cfg);
 989         if (ret == 0) {
 990                 /*
 991                  * Enabling a Virtual Interface can result in an interrupt
 992                  * during the processing of the VI Enable command and, in some
 993                  * paths, result in an attempt to issue another command in the
 994                  * interrupt context.  Thus, we disable interrupts during the
 995                  * course of the VI Enable command ...
 996                  */
 997                 ret = t4_enable_vi_params(adapter, adapter->mbox, pi->viid,
 998                                           true, true, false);
 999         }
1000
1001         if (ret == 0 && force_linkup(adapter))
1002                 pi->eth_dev->data->dev_link.link_status = ETH_LINK_UP;
1003         return ret;
1004 }
1005
1006 /**
1007  * cxgbe_write_rss_conf - flash the RSS configuration for a given port
1008  * @pi: the port
1009  * @rss_hf: Hash configuration to apply
1010  */
1011 int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t rss_hf)
1012 {
1013         struct adapter *adapter = pi->adapter;
1014         const struct sge_eth_rxq *rxq;
1015         u64 flags = 0;
1016         u16 rss;
1017         int err;
1018
1019         /*  Should never be called before setting up sge eth rx queues */
1020         if (!(adapter->flags & FULL_INIT_DONE)) {
1021                 dev_err(adap, "%s No RXQs available on port %d\n",
1022                         __func__, pi->port_id);
1023                 return -EINVAL;
1024         }
1025
1026         /* Don't allow unsupported hash functions */
1027         if (rss_hf & ~CXGBE_RSS_HF_ALL)
1028                 return -EINVAL;
1029
1030         if (rss_hf & ETH_RSS_IPV4)
1031                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
1032
1033         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1034                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
1035
1036         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1037                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
1038                          F_FW_RSS_VI_CONFIG_CMD_UDPEN;
1039
1040         if (rss_hf & ETH_RSS_IPV6)
1041                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
1042
1043         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1044                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
1045
1046         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1047                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
1048                          F_FW_RSS_VI_CONFIG_CMD_UDPEN;
1049
1050         rxq = &adapter->sge.ethrxq[pi->first_qset];
1051         rss = rxq[0].rspq.abs_id;
1052
1053         /* If Tunnel All Lookup isn't specified in the global RSS
1054          * Configuration, then we need to specify a default Ingress
1055          * Queue for any ingress packets which aren't hashed.  We'll
1056          * use our first ingress queue ...
1057          */
1058         err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
1059                                flags, rss);
1060         return err;
1061 }
1062
1063 /**
1064  * cxgbe_write_rss - write the RSS table for a given port
1065  * @pi: the port
1066  * @queues: array of queue indices for RSS
1067  *
1068  * Sets up the portion of the HW RSS table for the port's VI to distribute
1069  * packets to the Rx queues in @queues.
1070  */
1071 int cxgbe_write_rss(const struct port_info *pi, const u16 *queues)
1072 {
1073         u16 *rss;
1074         int i, err;
1075         struct adapter *adapter = pi->adapter;
1076         const struct sge_eth_rxq *rxq;
1077
1078         /*  Should never be called before setting up sge eth rx queues */
1079         BUG_ON(!(adapter->flags & FULL_INIT_DONE));
1080
1081         rxq = &adapter->sge.ethrxq[pi->first_qset];
1082         rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
1083         if (!rss)
1084                 return -ENOMEM;
1085
1086         /* map the queue indices to queue ids */
1087         for (i = 0; i < pi->rss_size; i++, queues++)
1088                 rss[i] = rxq[*queues].rspq.abs_id;
1089
1090         err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
1091                                   pi->rss_size, rss, pi->rss_size);
1092         rte_free(rss);
1093         return err;
1094 }
1095
1096 /**
1097  * setup_rss - configure RSS
1098  * @adapter: the adapter
1099  *
1100  * Sets up RSS to distribute packets to multiple receive queues.  We
1101  * configure the RSS CPU lookup table to distribute to the number of HW
1102  * receive queues, and the response queue lookup table to narrow that
1103  * down to the response queues actually configured for each port.
1104  * We always configure the RSS mapping for all ports since the mapping
1105  * table has plenty of entries.
1106  */
1107 int setup_rss(struct port_info *pi)
1108 {
1109         int j, err;
1110         struct adapter *adapter = pi->adapter;
1111
1112         dev_debug(adapter, "%s:  pi->rss_size = %u; pi->n_rx_qsets = %u\n",
1113                   __func__, pi->rss_size, pi->n_rx_qsets);
1114
1115         if (!(pi->flags & PORT_RSS_DONE)) {
1116                 if (adapter->flags & FULL_INIT_DONE) {
1117                         /* Fill default values with equal distribution */
1118                         for (j = 0; j < pi->rss_size; j++)
1119                                 pi->rss[j] = j % pi->n_rx_qsets;
1120
1121                         err = cxgbe_write_rss(pi, pi->rss);
1122                         if (err)
1123                                 return err;
1124
1125                         err = cxgbe_write_rss_conf(pi, pi->rss_hf);
1126                         if (err)
1127                                 return err;
1128                         pi->flags |= PORT_RSS_DONE;
1129                 }
1130         }
1131         return 0;
1132 }
1133
1134 /*
1135  * Enable NAPI scheduling and interrupt generation for all Rx queues.
1136  */
1137 static void enable_rx(struct adapter *adap, struct sge_rspq *q)
1138 {
1139         /* 0-increment GTS to start the timer and enable interrupts */
1140         t4_write_reg(adap, is_pf4(adap) ? MYPF_REG(A_SGE_PF_GTS) :
1141                                           T4VF_SGE_BASE_ADDR + A_SGE_VF_GTS,
1142                      V_SEINTARM(q->intr_params) |
1143                      V_INGRESSQID(q->cntxt_id));
1144 }
1145
1146 void cxgbe_enable_rx_queues(struct port_info *pi)
1147 {
1148         struct adapter *adap = pi->adapter;
1149         struct sge *s = &adap->sge;
1150         unsigned int i;
1151
1152         for (i = 0; i < pi->n_rx_qsets; i++)
1153                 enable_rx(adap, &s->ethrxq[pi->first_qset + i].rspq);
1154 }
1155
1156 /**
1157  * fw_caps_to_speed_caps - translate Firmware Port Caps to Speed Caps.
1158  * @port_type: Firmware Port Type
1159  * @fw_caps: Firmware Port Capabilities
1160  * @speed_caps: Device Info Speed Capabilities
1161  *
1162  * Translate a Firmware Port Capabilities specification to Device Info
1163  * Speed Capabilities.
1164  */
1165 static void fw_caps_to_speed_caps(enum fw_port_type port_type,
1166                                   unsigned int fw_caps,
1167                                   u32 *speed_caps)
1168 {
1169 #define SET_SPEED(__speed_name) \
1170         do { \
1171                 *speed_caps |= ETH_LINK_ ## __speed_name; \
1172         } while (0)
1173
1174 #define FW_CAPS_TO_SPEED(__fw_name) \
1175         do { \
1176                 if (fw_caps & FW_PORT_CAP32_ ## __fw_name) \
1177                         SET_SPEED(__fw_name); \
1178         } while (0)
1179
1180         switch (port_type) {
1181         case FW_PORT_TYPE_BT_SGMII:
1182         case FW_PORT_TYPE_BT_XFI:
1183         case FW_PORT_TYPE_BT_XAUI:
1184                 FW_CAPS_TO_SPEED(SPEED_100M);
1185                 FW_CAPS_TO_SPEED(SPEED_1G);
1186                 FW_CAPS_TO_SPEED(SPEED_10G);
1187                 break;
1188
1189         case FW_PORT_TYPE_KX4:
1190         case FW_PORT_TYPE_KX:
1191         case FW_PORT_TYPE_FIBER_XFI:
1192         case FW_PORT_TYPE_FIBER_XAUI:
1193         case FW_PORT_TYPE_SFP:
1194         case FW_PORT_TYPE_QSFP_10G:
1195         case FW_PORT_TYPE_QSA:
1196                 FW_CAPS_TO_SPEED(SPEED_1G);
1197                 FW_CAPS_TO_SPEED(SPEED_10G);
1198                 break;
1199
1200         case FW_PORT_TYPE_KR:
1201                 SET_SPEED(SPEED_10G);
1202                 break;
1203
1204         case FW_PORT_TYPE_BP_AP:
1205         case FW_PORT_TYPE_BP4_AP:
1206                 SET_SPEED(SPEED_1G);
1207                 SET_SPEED(SPEED_10G);
1208                 break;
1209
1210         case FW_PORT_TYPE_BP40_BA:
1211         case FW_PORT_TYPE_QSFP:
1212                 SET_SPEED(SPEED_40G);
1213                 break;
1214
1215         case FW_PORT_TYPE_CR_QSFP:
1216         case FW_PORT_TYPE_SFP28:
1217         case FW_PORT_TYPE_KR_SFP28:
1218                 FW_CAPS_TO_SPEED(SPEED_1G);
1219                 FW_CAPS_TO_SPEED(SPEED_10G);
1220                 FW_CAPS_TO_SPEED(SPEED_25G);
1221                 break;
1222
1223         case FW_PORT_TYPE_CR2_QSFP:
1224                 SET_SPEED(SPEED_50G);
1225                 break;
1226
1227         case FW_PORT_TYPE_KR4_100G:
1228         case FW_PORT_TYPE_CR4_QSFP:
1229                 FW_CAPS_TO_SPEED(SPEED_25G);
1230                 FW_CAPS_TO_SPEED(SPEED_40G);
1231                 FW_CAPS_TO_SPEED(SPEED_50G);
1232                 FW_CAPS_TO_SPEED(SPEED_100G);
1233                 break;
1234
1235         default:
1236                 break;
1237         }
1238
1239 #undef FW_CAPS_TO_SPEED
1240 #undef SET_SPEED
1241 }
1242
1243 /**
1244  * cxgbe_get_speed_caps - Fetch supported speed capabilities
1245  * @pi: Underlying port's info
1246  * @speed_caps: Device Info speed capabilities
1247  *
1248  * Fetch supported speed capabilities of the underlying port.
1249  */
1250 void cxgbe_get_speed_caps(struct port_info *pi, u32 *speed_caps)
1251 {
1252         *speed_caps = 0;
1253
1254         fw_caps_to_speed_caps(pi->port_type, pi->link_cfg.pcaps,
1255                               speed_caps);
1256
1257         if (!(pi->link_cfg.pcaps & FW_PORT_CAP32_ANEG))
1258                 *speed_caps |= ETH_LINK_SPEED_FIXED;
1259 }
1260
1261 /**
1262  * cxgb_up - enable the adapter
1263  * @adap: adapter being enabled
1264  *
1265  * Called when the first port is enabled, this function performs the
1266  * actions necessary to make an adapter operational, such as completing
1267  * the initialization of HW modules, and enabling interrupts.
1268  */
1269 int cxgbe_up(struct adapter *adap)
1270 {
1271         enable_rx(adap, &adap->sge.fw_evtq);
1272         t4_sge_tx_monitor_start(adap);
1273         if (is_pf4(adap))
1274                 t4_intr_enable(adap);
1275         adap->flags |= FULL_INIT_DONE;
1276
1277         /* TODO: deadman watchdog ?? */
1278         return 0;
1279 }
1280
1281 /*
1282  * Close the port
1283  */
1284 int cxgbe_down(struct port_info *pi)
1285 {
1286         struct adapter *adapter = pi->adapter;
1287         int err = 0;
1288
1289         err = t4_enable_vi(adapter, adapter->mbox, pi->viid, false, false);
1290         if (err) {
1291                 dev_err(adapter, "%s: disable_vi failed: %d\n", __func__, err);
1292                 return err;
1293         }
1294
1295         t4_reset_link_config(adapter, pi->pidx);
1296         return 0;
1297 }
1298
1299 /*
1300  * Release resources when all the ports have been stopped.
1301  */
1302 void cxgbe_close(struct adapter *adapter)
1303 {
1304         struct port_info *pi;
1305         int i;
1306
1307         if (adapter->flags & FULL_INIT_DONE) {
1308                 if (is_pf4(adapter))
1309                         t4_intr_disable(adapter);
1310                 t4_sge_tx_monitor_stop(adapter);
1311                 t4_free_sge_resources(adapter);
1312                 for_each_port(adapter, i) {
1313                         pi = adap2pinfo(adapter, i);
1314                         if (pi->viid != 0)
1315                                 t4_free_vi(adapter, adapter->mbox,
1316                                            adapter->pf, 0, pi->viid);
1317                         rte_free(pi->eth_dev->data->mac_addrs);
1318                         /* Skip first port since it'll be freed by DPDK stack */
1319                         if (i) {
1320                                 rte_free(pi->eth_dev->data->dev_private);
1321                                 rte_eth_dev_release_port(pi->eth_dev);
1322                         }
1323                 }
1324                 adapter->flags &= ~FULL_INIT_DONE;
1325         }
1326
1327         if (is_pf4(adapter) && (adapter->flags & FW_OK))
1328                 t4_fw_bye(adapter, adapter->mbox);
1329 }
1330
1331 int cxgbe_probe(struct adapter *adapter)
1332 {
1333         struct port_info *pi;
1334         int chip;
1335         int func, i;
1336         int err = 0;
1337         u32 whoami;
1338
1339         whoami = t4_read_reg(adapter, A_PL_WHOAMI);
1340         chip = t4_get_chip_type(adapter,
1341                         CHELSIO_PCI_ID_VER(adapter->pdev->id.device_id));
1342         if (chip < 0)
1343                 return chip;
1344
1345         func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ?
1346                G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
1347
1348         adapter->mbox = func;
1349         adapter->pf = func;
1350
1351         t4_os_lock_init(&adapter->mbox_lock);
1352         TAILQ_INIT(&adapter->mbox_list);
1353
1354         err = t4_prep_adapter(adapter);
1355         if (err)
1356                 return err;
1357
1358         setup_memwin(adapter);
1359         err = adap_init0(adapter);
1360         if (err) {
1361                 dev_err(adapter, "%s: Adapter initialization failed, error %d\n",
1362                         __func__, err);
1363                 goto out_free;
1364         }
1365
1366         if (!is_t4(adapter->params.chip)) {
1367                 /*
1368                  * The userspace doorbell BAR is split evenly into doorbell
1369                  * regions, each associated with an egress queue.  If this
1370                  * per-queue region is large enough (at least UDBS_SEG_SIZE)
1371                  * then it can be used to submit a tx work request with an
1372                  * implied doorbell.  Enable write combining on the BAR if
1373                  * there is room for such work requests.
1374                  */
1375                 int s_qpp, qpp, num_seg;
1376
1377                 s_qpp = (S_QUEUESPERPAGEPF0 +
1378                         (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) *
1379                         adapter->pf);
1380                 qpp = 1 << ((t4_read_reg(adapter,
1381                                 A_SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp)
1382                                 & M_QUEUESPERPAGEPF0);
1383                 num_seg = CXGBE_PAGE_SIZE / UDBS_SEG_SIZE;
1384                 if (qpp > num_seg)
1385                         dev_warn(adapter, "Incorrect SGE EGRESS QUEUES_PER_PAGE configuration, continuing in debug mode\n");
1386
1387                 adapter->bar2 = (void *)adapter->pdev->mem_resource[2].addr;
1388                 if (!adapter->bar2) {
1389                         dev_err(adapter, "cannot map device bar2 region\n");
1390                         err = -ENOMEM;
1391                         goto out_free;
1392                 }
1393                 t4_write_reg(adapter, A_SGE_STAT_CFG, V_STATSOURCE_T5(7) |
1394                              V_STATMODE(0));
1395         }
1396
1397         for_each_port(adapter, i) {
1398                 const unsigned int numa_node = rte_socket_id();
1399                 char name[RTE_ETH_NAME_MAX_LEN];
1400                 struct rte_eth_dev *eth_dev;
1401
1402                 snprintf(name, sizeof(name), "%s_%d",
1403                          adapter->pdev->device.name, i);
1404
1405                 if (i == 0) {
1406                         /* First port is already allocated by DPDK */
1407                         eth_dev = adapter->eth_dev;
1408                         goto allocate_mac;
1409                 }
1410
1411                 /*
1412                  * now do all data allocation - for eth_dev structure,
1413                  * and internal (private) data for the remaining ports
1414                  */
1415
1416                 /* reserve an ethdev entry */
1417                 eth_dev = rte_eth_dev_allocate(name);
1418                 if (!eth_dev)
1419                         goto out_free;
1420
1421                 eth_dev->data->dev_private =
1422                         rte_zmalloc_socket(name, sizeof(struct port_info),
1423                                            RTE_CACHE_LINE_SIZE, numa_node);
1424                 if (!eth_dev->data->dev_private)
1425                         goto out_free;
1426
1427 allocate_mac:
1428                 pi = (struct port_info *)eth_dev->data->dev_private;
1429                 adapter->port[i] = pi;
1430                 pi->eth_dev = eth_dev;
1431                 pi->adapter = adapter;
1432                 pi->xact_addr_filt = -1;
1433                 pi->port_id = i;
1434                 pi->pidx = i;
1435
1436                 pi->eth_dev->device = &adapter->pdev->device;
1437                 pi->eth_dev->dev_ops = adapter->eth_dev->dev_ops;
1438                 pi->eth_dev->tx_pkt_burst = adapter->eth_dev->tx_pkt_burst;
1439                 pi->eth_dev->rx_pkt_burst = adapter->eth_dev->rx_pkt_burst;
1440
1441                 rte_eth_copy_pci_info(pi->eth_dev, adapter->pdev);
1442
1443                 pi->eth_dev->data->mac_addrs = rte_zmalloc(name,
1444                                                            ETHER_ADDR_LEN, 0);
1445                 if (!pi->eth_dev->data->mac_addrs) {
1446                         dev_err(adapter, "%s: Mem allocation failed for storing mac addr, aborting\n",
1447                                 __func__);
1448                         err = -1;
1449                         goto out_free;
1450                 }
1451
1452                 if (i > 0) {
1453                         /* First port will be notified by upper layer */
1454                         rte_eth_dev_probing_finish(eth_dev);
1455                 }
1456         }
1457
1458         if (adapter->flags & FW_OK) {
1459                 err = t4_port_init(adapter, adapter->mbox, adapter->pf, 0);
1460                 if (err) {
1461                         dev_err(adapter, "%s: t4_port_init failed with err %d\n",
1462                                 __func__, err);
1463                         goto out_free;
1464                 }
1465         }
1466
1467         cfg_queues(adapter->eth_dev);
1468
1469         print_adapter_info(adapter);
1470         print_port_info(adapter);
1471
1472         err = init_rss(adapter);
1473         if (err)
1474                 goto out_free;
1475
1476         return 0;
1477
1478 out_free:
1479         for_each_port(adapter, i) {
1480                 pi = adap2pinfo(adapter, i);
1481                 if (pi->viid != 0)
1482                         t4_free_vi(adapter, adapter->mbox, adapter->pf,
1483                                    0, pi->viid);
1484                 /* Skip first port since it'll be de-allocated by DPDK */
1485                 if (i == 0)
1486                         continue;
1487                 if (pi->eth_dev) {
1488                         if (pi->eth_dev->data->dev_private)
1489                                 rte_free(pi->eth_dev->data->dev_private);
1490                         rte_eth_dev_release_port(pi->eth_dev);
1491                 }
1492         }
1493
1494         if (adapter->flags & FW_OK)
1495                 t4_fw_bye(adapter, adapter->mbox);
1496         return -err;
1497 }