drivers/net/dpaa/dpaa_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2017-2020 NXP
   5  *
   6  */
   7 /* System headers */
   8 #include <stdio.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <limits.h>
  12 #include <sched.h>
  13 #include <signal.h>
  14 #include <pthread.h>
  15 #include <sys/types.h>
  16 #include <sys/syscall.h>
  17
  18 #include <rte_string_fns.h>
  19 #include <rte_byteorder.h>
  20 #include <rte_common.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_log.h>
  23 #include <rte_debug.h>
  24 #include <rte_pci.h>
  25 #include <rte_atomic.h>
  26 #include <rte_branch_prediction.h>
  27 #include <rte_memory.h>
  28 #include <rte_tailq.h>
  29 #include <rte_eal.h>
  30 #include <rte_alarm.h>
  31 #include <rte_ether.h>
  32 #include <rte_ethdev_driver.h>
  33 #include <rte_malloc.h>
  34 #include <rte_ring.h>
  35
  36 #include <rte_dpaa_bus.h>
  37 #include <rte_dpaa_logs.h>
  38 #include <dpaa_mempool.h>
  39
  40 #include <dpaa_ethdev.h>
  41 #include <dpaa_rxtx.h>
  42 #include <rte_pmd_dpaa.h>
  43
  44 #include <fsl_usd.h>
  45 #include <fsl_qman.h>
  46 #include <fsl_bman.h>
  47 #include <fsl_fman.h>
  48
  49 /* Supported Rx offloads */
  50 static uint64_t dev_rx_offloads_sup =
  51                 DEV_RX_OFFLOAD_JUMBO_FRAME |
  52                 DEV_RX_OFFLOAD_SCATTER;
  53
  54 /* Rx offloads which cannot be disabled */
  55 static uint64_t dev_rx_offloads_nodis =
  56                 DEV_RX_OFFLOAD_IPV4_CKSUM |
  57                 DEV_RX_OFFLOAD_UDP_CKSUM |
  58                 DEV_RX_OFFLOAD_TCP_CKSUM |
  59                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
  60                 DEV_RX_OFFLOAD_RSS_HASH;
  61
  62 /* Supported Tx offloads */
  63 static uint64_t dev_tx_offloads_sup =
  64                 DEV_TX_OFFLOAD_MT_LOCKFREE |
  65                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
  66
  67 /* Tx offloads which cannot be disabled */
  68 static uint64_t dev_tx_offloads_nodis =
  69                 DEV_TX_OFFLOAD_IPV4_CKSUM |
  70                 DEV_TX_OFFLOAD_UDP_CKSUM |
  71                 DEV_TX_OFFLOAD_TCP_CKSUM |
  72                 DEV_TX_OFFLOAD_SCTP_CKSUM |
  73                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
  74                 DEV_TX_OFFLOAD_MULTI_SEGS;
  75
  76 /* Keep track of whether QMAN and BMAN have been globally initialized */
  77 static int is_global_init;
  78 static int default_q;   /* use default queue - FMC is not executed*/
  79 /* At present we only allow up to 4 push mode queues as default - as each of
  80  * this queue need dedicated portal and we are short of portals.
  81  */
  82 #define DPAA_MAX_PUSH_MODE_QUEUE       8
  83 #define DPAA_DEFAULT_PUSH_MODE_QUEUE   4
  84
  85 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE;
  86 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/
  87
  88
  89 /* Per RX FQ Taildrop in frame count */
  90 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH;
  91
  92 /* Per TX FQ Taildrop in frame count, disabled by default */
  93 static unsigned int td_tx_threshold;
  94
  95 struct rte_dpaa_xstats_name_off {
  96         char name[RTE_ETH_XSTATS_NAME_SIZE];
  97         uint32_t offset;
  98 };
  99
 100 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = {
 101         {"rx_align_err",
 102                 offsetof(struct dpaa_if_stats, raln)},
 103         {"rx_valid_pause",
 104                 offsetof(struct dpaa_if_stats, rxpf)},
 105         {"rx_fcs_err",
 106                 offsetof(struct dpaa_if_stats, rfcs)},
 107         {"rx_vlan_frame",
 108                 offsetof(struct dpaa_if_stats, rvlan)},
 109         {"rx_frame_err",
 110                 offsetof(struct dpaa_if_stats, rerr)},
 111         {"rx_drop_err",
 112                 offsetof(struct dpaa_if_stats, rdrp)},
 113         {"rx_undersized",
 114                 offsetof(struct dpaa_if_stats, rund)},
 115         {"rx_oversize_err",
 116                 offsetof(struct dpaa_if_stats, rovr)},
 117         {"rx_fragment_pkt",
 118                 offsetof(struct dpaa_if_stats, rfrg)},
 119         {"tx_valid_pause",
 120                 offsetof(struct dpaa_if_stats, txpf)},
 121         {"tx_fcs_err",
 122                 offsetof(struct dpaa_if_stats, terr)},
 123         {"tx_vlan_frame",
 124                 offsetof(struct dpaa_if_stats, tvlan)},
 125         {"rx_undersized",
 126                 offsetof(struct dpaa_if_stats, tund)},
 127 };
 128
 129 static struct rte_dpaa_driver rte_dpaa_pmd;
 130
 131 static int
 132 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info);
 133
 134 static inline void
 135 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts)
 136 {
 137         memset(opts, 0, sizeof(struct qm_mcc_initfq));
 138         opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
 139         opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING |
 140                            QM_FQCTRL_PREFERINCACHE;
 141         opts->fqd.context_a.stashing.exclusive = 0;
 142         if (dpaa_svr_family != SVR_LS1046A_FAMILY)
 143                 opts->fqd.context_a.stashing.annotation_cl =
 144                                                 DPAA_IF_RX_ANNOTATION_STASH;
 145         opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
 146         opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH;
 147 }
 148
 149 static int
 150 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 151 {
 152         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
 153                                 + VLAN_TAG_SIZE;
 154         uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
 155
 156         PMD_INIT_FUNC_TRACE();
 157
 158         if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN)
 159                 return -EINVAL;
 160         /*
 161          * Refuse mtu that requires the support of scattered packets
 162          * when this feature has not been enabled before.
 163          */
 164         if (dev->data->min_rx_buf_size &&
 165                 !dev->data->scattered_rx && frame_size > buffsz) {
 166                 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer");
 167                 return -EINVAL;
 168         }
 169
 170         /* check <seg size> * <max_seg>  >= max_frame */
 171         if (dev->data->min_rx_buf_size && dev->data->scattered_rx &&
 172                 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) {
 173                 DPAA_PMD_ERR("Too big to fit for Max SG list %d",
 174                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 175                 return -EINVAL;
 176         }
 177
 178         if (frame_size > RTE_ETHER_MAX_LEN)
 179                 dev->data->dev_conf.rxmode.offloads |=
 180                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 181         else
 182                 dev->data->dev_conf.rxmode.offloads &=
 183                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 184
 185         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 186
 187         fman_if_set_maxfrm(dev->process_private, frame_size);
 188
 189         return 0;
 190 }
 191
 192 static int
 193 dpaa_eth_dev_configure(struct rte_eth_dev *dev)
 194 {
 195         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 196         uint64_t rx_offloads = eth_conf->rxmode.offloads;
 197         uint64_t tx_offloads = eth_conf->txmode.offloads;
 198
 199         PMD_INIT_FUNC_TRACE();
 200
 201         /* Rx offloads which are enabled by default */
 202         if (dev_rx_offloads_nodis & ~rx_offloads) {
 203                 DPAA_PMD_INFO(
 204                 "Some of rx offloads enabled by default - requested 0x%" PRIx64
 205                 " fixed are 0x%" PRIx64,
 206                 rx_offloads, dev_rx_offloads_nodis);
 207         }
 208
 209         /* Tx offloads which are enabled by default */
 210         if (dev_tx_offloads_nodis & ~tx_offloads) {
 211                 DPAA_PMD_INFO(
 212                 "Some of tx offloads enabled by default - requested 0x%" PRIx64
 213                 " fixed are 0x%" PRIx64,
 214                 tx_offloads, dev_tx_offloads_nodis);
 215         }
 216
 217         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 218                 uint32_t max_len;
 219
 220                 DPAA_PMD_DEBUG("enabling jumbo");
 221
 222                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
 223                     DPAA_MAX_RX_PKT_LEN)
 224                         max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
 225                 else {
 226                         DPAA_PMD_INFO("enabling jumbo override conf max len=%d "
 227                                 "supported is %d",
 228                                 dev->data->dev_conf.rxmode.max_rx_pkt_len,
 229                                 DPAA_MAX_RX_PKT_LEN);
 230                         max_len = DPAA_MAX_RX_PKT_LEN;
 231                 }
 232
 233                 fman_if_set_maxfrm(dev->process_private, max_len);
 234                 dev->data->mtu = max_len
 235                         - RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE;
 236         }
 237
 238         if (rx_offloads & DEV_RX_OFFLOAD_SCATTER) {
 239                 DPAA_PMD_DEBUG("enabling scatter mode");
 240                 fman_if_set_sg(dev->process_private, 1);
 241                 dev->data->scattered_rx = 1;
 242         }
 243
 244         return 0;
 245 }
 246
 247 static const uint32_t *
 248 dpaa_supported_ptypes_get(struct rte_eth_dev *dev)
 249 {
 250         static const uint32_t ptypes[] = {
 251                 RTE_PTYPE_L2_ETHER,
 252                 RTE_PTYPE_L2_ETHER_VLAN,
 253                 RTE_PTYPE_L2_ETHER_ARP,
 254                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 255                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 256                 RTE_PTYPE_L4_ICMP,
 257                 RTE_PTYPE_L4_TCP,
 258                 RTE_PTYPE_L4_UDP,
 259                 RTE_PTYPE_L4_FRAG,
 260                 RTE_PTYPE_L4_TCP,
 261                 RTE_PTYPE_L4_UDP,
 262                 RTE_PTYPE_L4_SCTP
 263         };
 264
 265         PMD_INIT_FUNC_TRACE();
 266
 267         if (dev->rx_pkt_burst == dpaa_eth_queue_rx)
 268                 return ptypes;
 269         return NULL;
 270 }
 271
 272 static int dpaa_eth_dev_start(struct rte_eth_dev *dev)
 273 {
 274         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 275
 276         PMD_INIT_FUNC_TRACE();
 277
 278         /* Change tx callback to the real one */
 279         if (dpaa_intf->cgr_tx)
 280                 dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
 281         else
 282                 dev->tx_pkt_burst = dpaa_eth_queue_tx;
 283
 284         fman_if_enable_rx(dev->process_private);
 285
 286         return 0;
 287 }
 288
 289 static void dpaa_eth_dev_stop(struct rte_eth_dev *dev)
 290 {
 291         struct fman_if *fif = dev->process_private;
 292
 293         PMD_INIT_FUNC_TRACE();
 294
 295         fman_if_disable_rx(fif);
 296         dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
 297 }
 298
 299 static void dpaa_eth_dev_close(struct rte_eth_dev *dev)
 300 {
 301         PMD_INIT_FUNC_TRACE();
 302
 303         dpaa_eth_dev_stop(dev);
 304 }
 305
 306 static int
 307 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused,
 308                      char *fw_version,
 309                      size_t fw_size)
 310 {
 311         int ret;
 312         FILE *svr_file = NULL;
 313         unsigned int svr_ver = 0;
 314
 315         PMD_INIT_FUNC_TRACE();
 316
 317         svr_file = fopen(DPAA_SOC_ID_FILE, "r");
 318         if (!svr_file) {
 319                 DPAA_PMD_ERR("Unable to open SoC device");
 320                 return -ENOTSUP; /* Not supported on this infra */
 321         }
 322         if (fscanf(svr_file, "svr:%x", &svr_ver) > 0)
 323                 dpaa_svr_family = svr_ver & SVR_MASK;
 324         else
 325                 DPAA_PMD_ERR("Unable to read SoC device");
 326
 327         fclose(svr_file);
 328
 329         ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x",
 330                        svr_ver, fman_ip_rev);
 331         ret += 1; /* add the size of '\0' */
 332
 333         if (fw_size < (uint32_t)ret)
 334                 return ret;
 335         else
 336                 return 0;
 337 }
 338
 339 static int dpaa_eth_dev_info(struct rte_eth_dev *dev,
 340                              struct rte_eth_dev_info *dev_info)
 341 {
 342         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 343         struct fman_if *fif = dev->process_private;
 344
 345         DPAA_PMD_DEBUG(": %s", dpaa_intf->name);
 346
 347         dev_info->max_rx_queues = dpaa_intf->nb_rx_queues;
 348         dev_info->max_tx_queues = dpaa_intf->nb_tx_queues;
 349         dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
 350         dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER;
 351         dev_info->max_hash_mac_addrs = 0;
 352         dev_info->max_vfs = 0;
 353         dev_info->max_vmdq_pools = ETH_16_POOLS;
 354         dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL;
 355
 356         if (fif->mac_type == fman_mac_1g) {
 357                 dev_info->speed_capa = ETH_LINK_SPEED_1G;
 358         } else if (fif->mac_type == fman_mac_2_5g) {
 359                 dev_info->speed_capa = ETH_LINK_SPEED_1G
 360                                         | ETH_LINK_SPEED_2_5G;
 361         } else if (fif->mac_type == fman_mac_10g) {
 362                 dev_info->speed_capa = ETH_LINK_SPEED_1G
 363                                         | ETH_LINK_SPEED_2_5G
 364                                         | ETH_LINK_SPEED_10G;
 365         } else {
 366                 DPAA_PMD_ERR("invalid link_speed: %s, %d",
 367                              dpaa_intf->name, fif->mac_type);
 368                 return -EINVAL;
 369         }
 370
 371         dev_info->rx_offload_capa = dev_rx_offloads_sup |
 372                                         dev_rx_offloads_nodis;
 373         dev_info->tx_offload_capa = dev_tx_offloads_sup |
 374                                         dev_tx_offloads_nodis;
 375         dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE;
 376         dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE;
 377         dev_info->default_rxportconf.nb_queues = 1;
 378         dev_info->default_txportconf.nb_queues = 1;
 379         dev_info->default_txportconf.ring_size = CGR_TX_CGR_THRESH;
 380         dev_info->default_rxportconf.ring_size = CGR_RX_PERFQ_THRESH;
 381
 382         return 0;
 383 }
 384
 385 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
 386                                 int wait_to_complete __rte_unused)
 387 {
 388         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 389         struct rte_eth_link *link = &dev->data->dev_link;
 390         struct fman_if *fif = dev->process_private;
 391
 392         PMD_INIT_FUNC_TRACE();
 393
 394         if (fif->mac_type == fman_mac_1g)
 395                 link->link_speed = ETH_SPEED_NUM_1G;
 396         else if (fif->mac_type == fman_mac_2_5g)
 397                 link->link_speed = ETH_SPEED_NUM_2_5G;
 398         else if (fif->mac_type == fman_mac_10g)
 399                 link->link_speed = ETH_SPEED_NUM_10G;
 400         else
 401                 DPAA_PMD_ERR("invalid link_speed: %s, %d",
 402                              dpaa_intf->name, fif->mac_type);
 403
 404         link->link_status = dpaa_intf->valid;
 405         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 406         link->link_autoneg = ETH_LINK_AUTONEG;
 407         return 0;
 408 }
 409
 410 static int dpaa_eth_stats_get(struct rte_eth_dev *dev,
 411                                struct rte_eth_stats *stats)
 412 {
 413         PMD_INIT_FUNC_TRACE();
 414
 415         fman_if_stats_get(dev->process_private, stats);
 416         return 0;
 417 }
 418
 419 static int dpaa_eth_stats_reset(struct rte_eth_dev *dev)
 420 {
 421         PMD_INIT_FUNC_TRACE();
 422
 423         fman_if_stats_reset(dev->process_private);
 424
 425         return 0;
 426 }
 427
 428 static int
 429 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
 430                     unsigned int n)
 431 {
 432         unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings);
 433         uint64_t values[sizeof(struct dpaa_if_stats) / 8];
 434
 435         if (n < num)
 436                 return num;
 437
 438         if (xstats == NULL)
 439                 return 0;
 440
 441         fman_if_stats_get_all(dev->process_private, values,
 442                               sizeof(struct dpaa_if_stats) / 8);
 443
 444         for (i = 0; i < num; i++) {
 445                 xstats[i].id = i;
 446                 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8];
 447         }
 448         return i;
 449 }
 450
 451 static int
 452 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 453                       struct rte_eth_xstat_name *xstats_names,
 454                       unsigned int limit)
 455 {
 456         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 457
 458         if (limit < stat_cnt)
 459                 return stat_cnt;
 460
 461         if (xstats_names != NULL)
 462                 for (i = 0; i < stat_cnt; i++)
 463                         strlcpy(xstats_names[i].name,
 464                                 dpaa_xstats_strings[i].name,
 465                                 sizeof(xstats_names[i].name));
 466
 467         return stat_cnt;
 468 }
 469
 470 static int
 471 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 472                       uint64_t *values, unsigned int n)
 473 {
 474         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 475         uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8];
 476
 477         if (!ids) {
 478                 if (n < stat_cnt)
 479                         return stat_cnt;
 480
 481                 if (!values)
 482                         return 0;
 483
 484                 fman_if_stats_get_all(dev->process_private, values_copy,
 485                                       sizeof(struct dpaa_if_stats) / 8);
 486
 487                 for (i = 0; i < stat_cnt; i++)
 488                         values[i] =
 489                                 values_copy[dpaa_xstats_strings[i].offset / 8];
 490
 491                 return stat_cnt;
 492         }
 493
 494         dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
 495
 496         for (i = 0; i < n; i++) {
 497                 if (ids[i] >= stat_cnt) {
 498                         DPAA_PMD_ERR("id value isn't valid");
 499                         return -1;
 500                 }
 501                 values[i] = values_copy[ids[i]];
 502         }
 503         return n;
 504 }
 505
 506 static int
 507 dpaa_xstats_get_names_by_id(
 508         struct rte_eth_dev *dev,
 509         struct rte_eth_xstat_name *xstats_names,
 510         const uint64_t *ids,
 511         unsigned int limit)
 512 {
 513         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 514         struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
 515
 516         if (!ids)
 517                 return dpaa_xstats_get_names(dev, xstats_names, limit);
 518
 519         dpaa_xstats_get_names(dev, xstats_names_copy, limit);
 520
 521         for (i = 0; i < limit; i++) {
 522                 if (ids[i] >= stat_cnt) {
 523                         DPAA_PMD_ERR("id value isn't valid");
 524                         return -1;
 525                 }
 526                 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
 527         }
 528         return limit;
 529 }
 530
 531 static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev)
 532 {
 533         PMD_INIT_FUNC_TRACE();
 534
 535         fman_if_promiscuous_enable(dev->process_private);
 536
 537         return 0;
 538 }
 539
 540 static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev)
 541 {
 542         PMD_INIT_FUNC_TRACE();
 543
 544         fman_if_promiscuous_disable(dev->process_private);
 545
 546         return 0;
 547 }
 548
 549 static int dpaa_eth_multicast_enable(struct rte_eth_dev *dev)
 550 {
 551         PMD_INIT_FUNC_TRACE();
 552
 553         fman_if_set_mcast_filter_table(dev->process_private);
 554
 555         return 0;
 556 }
 557
 558 static int dpaa_eth_multicast_disable(struct rte_eth_dev *dev)
 559 {
 560         PMD_INIT_FUNC_TRACE();
 561
 562         fman_if_reset_mcast_filter_table(dev->process_private);
 563
 564         return 0;
 565 }
 566
 567 static
 568 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 569                             uint16_t nb_desc,
 570                             unsigned int socket_id __rte_unused,
 571                             const struct rte_eth_rxconf *rx_conf __rte_unused,
 572                             struct rte_mempool *mp)
 573 {
 574         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 575         struct fman_if *fif = dev->process_private;
 576         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx];
 577         struct qm_mcc_initfq opts = {0};
 578         u32 flags = 0;
 579         int ret;
 580         u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
 581
 582         PMD_INIT_FUNC_TRACE();
 583
 584         if (queue_idx >= dev->data->nb_rx_queues) {
 585                 rte_errno = EOVERFLOW;
 586                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
 587                       (void *)dev, queue_idx, dev->data->nb_rx_queues);
 588                 return -rte_errno;
 589         }
 590
 591         DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)",
 592                         queue_idx, rxq->fqid);
 593
 594         /* Max packet can fit in single buffer */
 595         if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= buffsz) {
 596                 ;
 597         } else if (dev->data->dev_conf.rxmode.offloads &
 598                         DEV_RX_OFFLOAD_SCATTER) {
 599                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len >
 600                         buffsz * DPAA_SGT_MAX_ENTRIES) {
 601                         DPAA_PMD_ERR("max RxPkt size %d too big to fit "
 602                                 "MaxSGlist %d",
 603                                 dev->data->dev_conf.rxmode.max_rx_pkt_len,
 604                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 605                         rte_errno = EOVERFLOW;
 606                         return -rte_errno;
 607                 }
 608         } else {
 609                 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is"
 610                      " larger than a single mbuf (%u) and scattered"
 611                      " mode has not been requested",
 612                      dev->data->dev_conf.rxmode.max_rx_pkt_len,
 613                      buffsz - RTE_PKTMBUF_HEADROOM);
 614         }
 615
 616         if (!dpaa_intf->bp_info || dpaa_intf->bp_info->mp != mp) {
 617                 struct fman_if_ic_params icp;
 618                 uint32_t fd_offset;
 619                 uint32_t bp_size;
 620
 621                 if (!mp->pool_data) {
 622                         DPAA_PMD_ERR("Not an offloaded buffer pool!");
 623                         return -1;
 624                 }
 625                 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
 626
 627                 memset(&icp, 0, sizeof(icp));
 628                 /* set ICEOF for to the default value , which is 0*/
 629                 icp.iciof = DEFAULT_ICIOF;
 630                 icp.iceof = DEFAULT_RX_ICEOF;
 631                 icp.icsz = DEFAULT_ICSZ;
 632                 fman_if_set_ic_params(fif, &icp);
 633
 634                 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE;
 635                 fman_if_set_fdoff(fif, fd_offset);
 636
 637                 /* Buffer pool size should be equal to Dataroom Size*/
 638                 bp_size = rte_pktmbuf_data_room_size(mp);
 639                 fman_if_set_bp(fif, mp->size,
 640                                dpaa_intf->bp_info->bpid, bp_size);
 641                 dpaa_intf->valid = 1;
 642                 DPAA_PMD_DEBUG("if:%s fd_offset = %d offset = %d",
 643                                 dpaa_intf->name, fd_offset,
 644                                 fman_if_get_fdoff(fif));
 645         }
 646         DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name,
 647                 fman_if_get_sg_enable(fif),
 648                 dev->data->dev_conf.rxmode.max_rx_pkt_len);
 649         /* checking if push mode only, no error check for now */
 650         if (!rxq->is_static &&
 651             dpaa_push_mode_max_queue > dpaa_push_queue_idx) {
 652                 struct qman_portal *qp;
 653                 int q_fd;
 654
 655                 dpaa_push_queue_idx++;
 656                 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
 657                 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK |
 658                                    QM_FQCTRL_CTXASTASHING |
 659                                    QM_FQCTRL_PREFERINCACHE;
 660                 opts.fqd.context_a.stashing.exclusive = 0;
 661                 /* In muticore scenario stashing becomes a bottleneck on LS1046.
 662                  * So do not enable stashing in this case
 663                  */
 664                 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
 665                         opts.fqd.context_a.stashing.annotation_cl =
 666                                                 DPAA_IF_RX_ANNOTATION_STASH;
 667                 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
 668                 opts.fqd.context_a.stashing.context_cl =
 669                                                 DPAA_IF_RX_CONTEXT_STASH;
 670
 671                 /*Create a channel and associate given queue with the channel*/
 672                 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0);
 673                 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
 674                 opts.fqd.dest.channel = rxq->ch_id;
 675                 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY;
 676                 flags = QMAN_INITFQ_FLAG_SCHED;
 677
 678                 /* Configure tail drop */
 679                 if (dpaa_intf->cgr_rx) {
 680                         opts.we_mask |= QM_INITFQ_WE_CGID;
 681                         opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid;
 682                         opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 683                 }
 684                 ret = qman_init_fq(rxq, flags, &opts);
 685                 if (ret) {
 686                         DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x "
 687                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
 688                         return ret;
 689                 }
 690                 if (dpaa_svr_family == SVR_LS1043A_FAMILY) {
 691                         rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch;
 692                 } else {
 693                         rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb;
 694                         rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare;
 695                 }
 696
 697                 rxq->is_static = true;
 698
 699                 /* Allocate qman specific portals */
 700                 qp = fsl_qman_fq_portal_create(&q_fd);
 701                 if (!qp) {
 702                         DPAA_PMD_ERR("Unable to alloc fq portal");
 703                         return -1;
 704                 }
 705                 rxq->qp = qp;
 706
 707                 /* Set up the device interrupt handler */
 708                 if (!dev->intr_handle) {
 709                         struct rte_dpaa_device *dpaa_dev;
 710                         struct rte_device *rdev = dev->device;
 711
 712                         dpaa_dev = container_of(rdev, struct rte_dpaa_device,
 713                                                 device);
 714                         dev->intr_handle = &dpaa_dev->intr_handle;
 715                         dev->intr_handle->intr_vec = rte_zmalloc(NULL,
 716                                         dpaa_push_mode_max_queue, 0);
 717                         if (!dev->intr_handle->intr_vec) {
 718                                 DPAA_PMD_ERR("intr_vec alloc failed");
 719                                 return -ENOMEM;
 720                         }
 721                         dev->intr_handle->nb_efd = dpaa_push_mode_max_queue;
 722                         dev->intr_handle->max_intr = dpaa_push_mode_max_queue;
 723                 }
 724
 725                 dev->intr_handle->type = RTE_INTR_HANDLE_EXT;
 726                 dev->intr_handle->intr_vec[queue_idx] = queue_idx + 1;
 727                 dev->intr_handle->efds[queue_idx] = q_fd;
 728                 rxq->q_fd = q_fd;
 729         }
 730         rxq->bp_array = rte_dpaa_bpid_info;
 731         dev->data->rx_queues[queue_idx] = rxq;
 732
 733         /* configure the CGR size as per the desc size */
 734         if (dpaa_intf->cgr_rx) {
 735                 struct qm_mcc_initcgr cgr_opts = {0};
 736
 737                 /* Enable tail drop with cgr on this queue */
 738                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0);
 739                 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts);
 740                 if (ret) {
 741                         DPAA_PMD_WARN(
 742                                 "rx taildrop modify fail on fqid %d (ret=%d)",
 743                                 rxq->fqid, ret);
 744                 }
 745         }
 746
 747         return 0;
 748 }
 749
 750 int
 751 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
 752                 int eth_rx_queue_id,
 753                 u16 ch_id,
 754                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
 755 {
 756         int ret;
 757         u32 flags = 0;
 758         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 759         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
 760         struct qm_mcc_initfq opts = {0};
 761
 762         if (dpaa_push_mode_max_queue)
 763                 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n"
 764                               "PUSH mode already enabled for first %d queues.\n"
 765                               "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n",
 766                               dpaa_push_mode_max_queue);
 767
 768         dpaa_poll_queue_default_config(&opts);
 769
 770         switch (queue_conf->ev.sched_type) {
 771         case RTE_SCHED_TYPE_ATOMIC:
 772                 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE;
 773                 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary
 774                  * configuration with HOLD_ACTIVE setting
 775                  */
 776                 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK);
 777                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic;
 778                 break;
 779         case RTE_SCHED_TYPE_ORDERED:
 780                 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n");
 781                 return -1;
 782         default:
 783                 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK;
 784                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel;
 785                 break;
 786         }
 787
 788         opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
 789         opts.fqd.dest.channel = ch_id;
 790         opts.fqd.dest.wq = queue_conf->ev.priority;
 791
 792         if (dpaa_intf->cgr_rx) {
 793                 opts.we_mask |= QM_INITFQ_WE_CGID;
 794                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
 795                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 796         }
 797
 798         flags = QMAN_INITFQ_FLAG_SCHED;
 799
 800         ret = qman_init_fq(rxq, flags, &opts);
 801         if (ret) {
 802                 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x "
 803                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
 804                 return ret;
 805         }
 806
 807         /* copy configuration which needs to be filled during dequeue */
 808         memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event));
 809         dev->data->rx_queues[eth_rx_queue_id] = rxq;
 810
 811         return ret;
 812 }
 813
 814 int
 815 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
 816                 int eth_rx_queue_id)
 817 {
 818         struct qm_mcc_initfq opts;
 819         int ret;
 820         u32 flags = 0;
 821         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 822         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
 823
 824         dpaa_poll_queue_default_config(&opts);
 825
 826         if (dpaa_intf->cgr_rx) {
 827                 opts.we_mask |= QM_INITFQ_WE_CGID;
 828                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
 829                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 830         }
 831
 832         ret = qman_init_fq(rxq, flags, &opts);
 833         if (ret) {
 834                 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d",
 835                              rxq->fqid, ret);
 836         }
 837
 838         rxq->cb.dqrr_dpdk_cb = NULL;
 839         dev->data->rx_queues[eth_rx_queue_id] = NULL;
 840
 841         return 0;
 842 }
 843
 844 static
 845 void dpaa_eth_rx_queue_release(void *rxq __rte_unused)
 846 {
 847         PMD_INIT_FUNC_TRACE();
 848 }
 849
 850 static
 851 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 852                             uint16_t nb_desc __rte_unused,
 853                 unsigned int socket_id __rte_unused,
 854                 const struct rte_eth_txconf *tx_conf __rte_unused)
 855 {
 856         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 857
 858         PMD_INIT_FUNC_TRACE();
 859
 860         if (queue_idx >= dev->data->nb_tx_queues) {
 861                 rte_errno = EOVERFLOW;
 862                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
 863                       (void *)dev, queue_idx, dev->data->nb_tx_queues);
 864                 return -rte_errno;
 865         }
 866
 867         DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)",
 868                         queue_idx, dpaa_intf->tx_queues[queue_idx].fqid);
 869         dev->data->tx_queues[queue_idx] = &dpaa_intf->tx_queues[queue_idx];
 870
 871         return 0;
 872 }
 873
 874 static void dpaa_eth_tx_queue_release(void *txq __rte_unused)
 875 {
 876         PMD_INIT_FUNC_TRACE();
 877 }
 878
 879 static uint32_t
 880 dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 881 {
 882         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 883         struct qman_fq *rxq = &dpaa_intf->rx_queues[rx_queue_id];
 884         u32 frm_cnt = 0;
 885
 886         PMD_INIT_FUNC_TRACE();
 887
 888         if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) {
 889                 DPAA_PMD_DEBUG("RX frame count for q(%d) is %u",
 890                                rx_queue_id, frm_cnt);
 891         }
 892         return frm_cnt;
 893 }
 894
 895 static int dpaa_link_down(struct rte_eth_dev *dev)
 896 {
 897         PMD_INIT_FUNC_TRACE();
 898
 899         dpaa_eth_dev_stop(dev);
 900         return 0;
 901 }
 902
 903 static int dpaa_link_up(struct rte_eth_dev *dev)
 904 {
 905         PMD_INIT_FUNC_TRACE();
 906
 907         dpaa_eth_dev_start(dev);
 908         return 0;
 909 }
 910
 911 static int
 912 dpaa_flow_ctrl_set(struct rte_eth_dev *dev,
 913                    struct rte_eth_fc_conf *fc_conf)
 914 {
 915         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 916         struct rte_eth_fc_conf *net_fc;
 917
 918         PMD_INIT_FUNC_TRACE();
 919
 920         if (!(dpaa_intf->fc_conf)) {
 921                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
 922                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
 923                 if (!dpaa_intf->fc_conf) {
 924                         DPAA_PMD_ERR("unable to save flow control info");
 925                         return -ENOMEM;
 926                 }
 927         }
 928         net_fc = dpaa_intf->fc_conf;
 929
 930         if (fc_conf->high_water < fc_conf->low_water) {
 931                 DPAA_PMD_ERR("Incorrect Flow Control Configuration");
 932                 return -EINVAL;
 933         }
 934
 935         if (fc_conf->mode == RTE_FC_NONE) {
 936                 return 0;
 937         } else if (fc_conf->mode == RTE_FC_TX_PAUSE ||
 938                  fc_conf->mode == RTE_FC_FULL) {
 939                 fman_if_set_fc_threshold(dev->process_private,
 940                                          fc_conf->high_water,
 941                                          fc_conf->low_water,
 942                                          dpaa_intf->bp_info->bpid);
 943                 if (fc_conf->pause_time)
 944                         fman_if_set_fc_quanta(dev->process_private,
 945                                               fc_conf->pause_time);
 946         }
 947
 948         /* Save the information in dpaa device */
 949         net_fc->pause_time = fc_conf->pause_time;
 950         net_fc->high_water = fc_conf->high_water;
 951         net_fc->low_water = fc_conf->low_water;
 952         net_fc->send_xon = fc_conf->send_xon;
 953         net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
 954         net_fc->mode = fc_conf->mode;
 955         net_fc->autoneg = fc_conf->autoneg;
 956
 957         return 0;
 958 }
 959
 960 static int
 961 dpaa_flow_ctrl_get(struct rte_eth_dev *dev,
 962                    struct rte_eth_fc_conf *fc_conf)
 963 {
 964         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 965         struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf;
 966         int ret;
 967
 968         PMD_INIT_FUNC_TRACE();
 969
 970         if (net_fc) {
 971                 fc_conf->pause_time = net_fc->pause_time;
 972                 fc_conf->high_water = net_fc->high_water;
 973                 fc_conf->low_water = net_fc->low_water;
 974                 fc_conf->send_xon = net_fc->send_xon;
 975                 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd;
 976                 fc_conf->mode = net_fc->mode;
 977                 fc_conf->autoneg = net_fc->autoneg;
 978                 return 0;
 979         }
 980         ret = fman_if_get_fc_threshold(dev->process_private);
 981         if (ret) {
 982                 fc_conf->mode = RTE_FC_TX_PAUSE;
 983                 fc_conf->pause_time =
 984                         fman_if_get_fc_quanta(dev->process_private);
 985         } else {
 986                 fc_conf->mode = RTE_FC_NONE;
 987         }
 988
 989         return 0;
 990 }
 991
 992 static int
 993 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev,
 994                              struct rte_ether_addr *addr,
 995                              uint32_t index,
 996                              __rte_unused uint32_t pool)
 997 {
 998         int ret;
 999
1000         PMD_INIT_FUNC_TRACE();
1001
1002         ret = fman_if_add_mac_addr(dev->process_private,
1003                                    addr->addr_bytes, index);
1004
1005         if (ret)
1006                 DPAA_PMD_ERR("Adding the MAC ADDR failed: err = %d", ret);
1007         return 0;
1008 }
1009
1010 static void
1011 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev,
1012                           uint32_t index)
1013 {
1014         PMD_INIT_FUNC_TRACE();
1015
1016         fman_if_clear_mac_addr(dev->process_private, index);
1017 }
1018
1019 static int
1020 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev,
1021                        struct rte_ether_addr *addr)
1022 {
1023         int ret;
1024
1025         PMD_INIT_FUNC_TRACE();
1026
1027         ret = fman_if_add_mac_addr(dev->process_private, addr->addr_bytes, 0);
1028         if (ret)
1029                 DPAA_PMD_ERR("Setting the MAC ADDR failed %d", ret);
1030
1031         return ret;
1032 }
1033
1034 static int dpaa_dev_queue_intr_enable(struct rte_eth_dev *dev,
1035                                       uint16_t queue_id)
1036 {
1037         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1038         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1039
1040         if (!rxq->is_static)
1041                 return -EINVAL;
1042
1043         return qman_fq_portal_irqsource_add(rxq->qp, QM_PIRQ_DQRI);
1044 }
1045
1046 static int dpaa_dev_queue_intr_disable(struct rte_eth_dev *dev,
1047                                        uint16_t queue_id)
1048 {
1049         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1050         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1051         uint32_t temp;
1052         ssize_t temp1;
1053
1054         if (!rxq->is_static)
1055                 return -EINVAL;
1056
1057         qman_fq_portal_irqsource_remove(rxq->qp, ~0);
1058
1059         temp1 = read(rxq->q_fd, &temp, sizeof(temp));
1060         if (temp1 != sizeof(temp))
1061                 DPAA_PMD_ERR("irq read error");
1062
1063         qman_fq_portal_thread_irq(rxq->qp);
1064
1065         return 0;
1066 }
1067
1068 static struct eth_dev_ops dpaa_devops = {
1069         .dev_configure            = dpaa_eth_dev_configure,
1070         .dev_start                = dpaa_eth_dev_start,
1071         .dev_stop                 = dpaa_eth_dev_stop,
1072         .dev_close                = dpaa_eth_dev_close,
1073         .dev_infos_get            = dpaa_eth_dev_info,
1074         .dev_supported_ptypes_get = dpaa_supported_ptypes_get,
1075
1076         .rx_queue_setup           = dpaa_eth_rx_queue_setup,
1077         .tx_queue_setup           = dpaa_eth_tx_queue_setup,
1078         .rx_queue_release         = dpaa_eth_rx_queue_release,
1079         .tx_queue_release         = dpaa_eth_tx_queue_release,
1080         .rx_queue_count           = dpaa_dev_rx_queue_count,
1081
1082         .flow_ctrl_get            = dpaa_flow_ctrl_get,
1083         .flow_ctrl_set            = dpaa_flow_ctrl_set,
1084
1085         .link_update              = dpaa_eth_link_update,
1086         .stats_get                = dpaa_eth_stats_get,
1087         .xstats_get               = dpaa_dev_xstats_get,
1088         .xstats_get_by_id         = dpaa_xstats_get_by_id,
1089         .xstats_get_names_by_id   = dpaa_xstats_get_names_by_id,
1090         .xstats_get_names         = dpaa_xstats_get_names,
1091         .xstats_reset             = dpaa_eth_stats_reset,
1092         .stats_reset              = dpaa_eth_stats_reset,
1093         .promiscuous_enable       = dpaa_eth_promiscuous_enable,
1094         .promiscuous_disable      = dpaa_eth_promiscuous_disable,
1095         .allmulticast_enable      = dpaa_eth_multicast_enable,
1096         .allmulticast_disable     = dpaa_eth_multicast_disable,
1097         .mtu_set                  = dpaa_mtu_set,
1098         .dev_set_link_down        = dpaa_link_down,
1099         .dev_set_link_up          = dpaa_link_up,
1100         .mac_addr_add             = dpaa_dev_add_mac_addr,
1101         .mac_addr_remove          = dpaa_dev_remove_mac_addr,
1102         .mac_addr_set             = dpaa_dev_set_mac_addr,
1103
1104         .fw_version_get           = dpaa_fw_version_get,
1105
1106         .rx_queue_intr_enable     = dpaa_dev_queue_intr_enable,
1107         .rx_queue_intr_disable    = dpaa_dev_queue_intr_disable,
1108 };
1109
1110 static bool
1111 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv)
1112 {
1113         if (strcmp(dev->device->driver->name,
1114                    drv->driver.name))
1115                 return false;
1116
1117         return true;
1118 }
1119
1120 static bool
1121 is_dpaa_supported(struct rte_eth_dev *dev)
1122 {
1123         return is_device_supported(dev, &rte_dpaa_pmd);
1124 }
1125
1126 int
1127 rte_pmd_dpaa_set_tx_loopback(uint8_t port, uint8_t on)
1128 {
1129         struct rte_eth_dev *dev;
1130
1131         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1132
1133         dev = &rte_eth_devices[port];
1134
1135         if (!is_dpaa_supported(dev))
1136                 return -ENOTSUP;
1137
1138         if (on)
1139                 fman_if_loopback_enable(dev->process_private);
1140         else
1141                 fman_if_loopback_disable(dev->process_private);
1142
1143         return 0;
1144 }
1145
1146 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf,
1147                                struct fman_if *fman_intf)
1148 {
1149         struct rte_eth_fc_conf *fc_conf;
1150         int ret;
1151
1152         PMD_INIT_FUNC_TRACE();
1153
1154         if (!(dpaa_intf->fc_conf)) {
1155                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1156                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1157                 if (!dpaa_intf->fc_conf) {
1158                         DPAA_PMD_ERR("unable to save flow control info");
1159                         return -ENOMEM;
1160                 }
1161         }
1162         fc_conf = dpaa_intf->fc_conf;
1163         ret = fman_if_get_fc_threshold(fman_intf);
1164         if (ret) {
1165                 fc_conf->mode = RTE_FC_TX_PAUSE;
1166                 fc_conf->pause_time = fman_if_get_fc_quanta(fman_intf);
1167         } else {
1168                 fc_conf->mode = RTE_FC_NONE;
1169         }
1170
1171         return 0;
1172 }
1173
1174 /* Initialise an Rx FQ */
1175 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx,
1176                               uint32_t fqid)
1177 {
1178         struct qm_mcc_initfq opts = {0};
1179         int ret;
1180         u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE;
1181         struct qm_mcc_initcgr cgr_opts = {
1182                 .we_mask = QM_CGR_WE_CS_THRES |
1183                                 QM_CGR_WE_CSTD_EN |
1184                                 QM_CGR_WE_MODE,
1185                 .cgr = {
1186                         .cstd_en = QM_CGR_EN,
1187                         .mode = QMAN_CGR_MODE_FRAME
1188                 }
1189         };
1190
1191         if (fqid) {
1192                 ret = qman_reserve_fqid(fqid);
1193                 if (ret) {
1194                         DPAA_PMD_ERR("reserve rx fqid 0x%x failed with ret: %d",
1195                                      fqid, ret);
1196                         return -EINVAL;
1197                 }
1198         } else {
1199                 flags |= QMAN_FQ_FLAG_DYNAMIC_FQID;
1200         }
1201         DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid);
1202         ret = qman_create_fq(fqid, flags, fq);
1203         if (ret) {
1204                 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d",
1205                         fqid, ret);
1206                 return ret;
1207         }
1208         fq->is_static = false;
1209
1210         dpaa_poll_queue_default_config(&opts);
1211
1212         if (cgr_rx) {
1213                 /* Enable tail drop with cgr on this queue */
1214                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0);
1215                 cgr_rx->cb = NULL;
1216                 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT,
1217                                       &cgr_opts);
1218                 if (ret) {
1219                         DPAA_PMD_WARN(
1220                                 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1221                                 fq->fqid, ret);
1222                         goto without_cgr;
1223                 }
1224                 opts.we_mask |= QM_INITFQ_WE_CGID;
1225                 opts.fqd.cgid = cgr_rx->cgrid;
1226                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1227         }
1228 without_cgr:
1229         ret = qman_init_fq(fq, 0, &opts);
1230         if (ret)
1231                 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret);
1232         return ret;
1233 }
1234
1235 /* Initialise a Tx FQ */
1236 static int dpaa_tx_queue_init(struct qman_fq *fq,
1237                               struct fman_if *fman_intf,
1238                               struct qman_cgr *cgr_tx)
1239 {
1240         struct qm_mcc_initfq opts = {0};
1241         struct qm_mcc_initcgr cgr_opts = {
1242                 .we_mask = QM_CGR_WE_CS_THRES |
1243                                 QM_CGR_WE_CSTD_EN |
1244                                 QM_CGR_WE_MODE,
1245                 .cgr = {
1246                         .cstd_en = QM_CGR_EN,
1247                         .mode = QMAN_CGR_MODE_FRAME
1248                 }
1249         };
1250         int ret;
1251
1252         ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
1253                              QMAN_FQ_FLAG_TO_DCPORTAL, fq);
1254         if (ret) {
1255                 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret);
1256                 return ret;
1257         }
1258         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL |
1259                        QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA;
1260         opts.fqd.dest.channel = fman_intf->tx_channel_id;
1261         opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY;
1262         opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE;
1263         opts.fqd.context_b = 0;
1264         /* no tx-confirmation */
1265         opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi;
1266         opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo;
1267         DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid);
1268
1269         if (cgr_tx) {
1270                 /* Enable tail drop with cgr on this queue */
1271                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres,
1272                                       td_tx_threshold, 0);
1273                 cgr_tx->cb = NULL;
1274                 ret = qman_create_cgr(cgr_tx, QMAN_CGR_FLAG_USE_INIT,
1275                                       &cgr_opts);
1276                 if (ret) {
1277                         DPAA_PMD_WARN(
1278                                 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1279                                 fq->fqid, ret);
1280                         goto without_cgr;
1281                 }
1282                 opts.we_mask |= QM_INITFQ_WE_CGID;
1283                 opts.fqd.cgid = cgr_tx->cgrid;
1284                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1285                 DPAA_PMD_DEBUG("Tx FQ tail drop enabled, threshold = %d\n",
1286                                 td_tx_threshold);
1287         }
1288 without_cgr:
1289         ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
1290         if (ret)
1291                 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret);
1292         return ret;
1293 }
1294
1295 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1296 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */
1297 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid)
1298 {
1299         struct qm_mcc_initfq opts = {0};
1300         int ret;
1301
1302         PMD_INIT_FUNC_TRACE();
1303
1304         ret = qman_reserve_fqid(fqid);
1305         if (ret) {
1306                 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d",
1307                         fqid, ret);
1308                 return -EINVAL;
1309         }
1310         /* "map" this Rx FQ to one of the interfaces Tx FQID */
1311         DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid);
1312         ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1313         if (ret) {
1314                 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d",
1315                         fqid, ret);
1316                 return ret;
1317         }
1318         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL;
1319         opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY;
1320         ret = qman_init_fq(fq, 0, &opts);
1321         if (ret)
1322                 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d",
1323                             fqid, ret);
1324         return ret;
1325 }
1326 #endif
1327
1328 /* Initialise a network interface */
1329 static int
1330 dpaa_dev_init_secondary(struct rte_eth_dev *eth_dev)
1331 {
1332         struct rte_dpaa_device *dpaa_device;
1333         struct fm_eth_port_cfg *cfg;
1334         struct dpaa_if *dpaa_intf;
1335         struct fman_if *fman_intf;
1336         int dev_id;
1337
1338         PMD_INIT_FUNC_TRACE();
1339
1340         dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1341         dev_id = dpaa_device->id.dev_id;
1342         cfg = dpaa_get_eth_port_cfg(dev_id);
1343         fman_intf = cfg->fman_if;
1344         eth_dev->process_private = fman_intf;
1345
1346         /* Plugging of UCODE burst API not supported in Secondary */
1347         dpaa_intf = eth_dev->data->dev_private;
1348         eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1349         if (dpaa_intf->cgr_tx)
1350                 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
1351         else
1352                 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx;
1353 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1354         qman_set_fq_lookup_table(
1355                 dpaa_intf->rx_queues->qman_fq_lookup_table);
1356 #endif
1357
1358         return 0;
1359 }
1360
1361 /* Initialise a network interface */
1362 static int
1363 dpaa_dev_init(struct rte_eth_dev *eth_dev)
1364 {
1365         int num_rx_fqs, fqid;
1366         int loop, ret = 0;
1367         int dev_id;
1368         struct rte_dpaa_device *dpaa_device;
1369         struct dpaa_if *dpaa_intf;
1370         struct fm_eth_port_cfg *cfg;
1371         struct fman_if *fman_intf;
1372         struct fman_if_bpool *bp, *tmp_bp;
1373         uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES];
1374         uint32_t cgrid_tx[MAX_DPAA_CORES];
1375         char eth_buf[RTE_ETHER_ADDR_FMT_SIZE];
1376
1377         PMD_INIT_FUNC_TRACE();
1378
1379         dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1380         dev_id = dpaa_device->id.dev_id;
1381         dpaa_intf = eth_dev->data->dev_private;
1382         cfg = dpaa_get_eth_port_cfg(dev_id);
1383         fman_intf = cfg->fman_if;
1384
1385         dpaa_intf->name = dpaa_device->name;
1386
1387         /* save fman_if & cfg in the interface struture */
1388         eth_dev->process_private = fman_intf;
1389         dpaa_intf->ifid = dev_id;
1390         dpaa_intf->cfg = cfg;
1391
1392         /* Initialize Rx FQ's */
1393         if (default_q) {
1394                 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1395         } else {
1396                 if (getenv("DPAA_NUM_RX_QUEUES"))
1397                         num_rx_fqs = atoi(getenv("DPAA_NUM_RX_QUEUES"));
1398                 else
1399                         num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1400         }
1401
1402
1403         /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX
1404          * queues.
1405          */
1406         if (num_rx_fqs <= 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) {
1407                 DPAA_PMD_ERR("Invalid number of RX queues\n");
1408                 return -EINVAL;
1409         }
1410
1411         dpaa_intf->rx_queues = rte_zmalloc(NULL,
1412                 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE);
1413         if (!dpaa_intf->rx_queues) {
1414                 DPAA_PMD_ERR("Failed to alloc mem for RX queues\n");
1415                 return -ENOMEM;
1416         }
1417
1418         memset(cgrid, 0, sizeof(cgrid));
1419         memset(cgrid_tx, 0, sizeof(cgrid_tx));
1420
1421         /* if DPAA_TX_TAILDROP_THRESHOLD is set, use that value; if 0, it means
1422          * Tx tail drop is disabled.
1423          */
1424         if (getenv("DPAA_TX_TAILDROP_THRESHOLD")) {
1425                 td_tx_threshold = atoi(getenv("DPAA_TX_TAILDROP_THRESHOLD"));
1426                 DPAA_PMD_DEBUG("Tail drop threshold env configured: %u",
1427                                td_tx_threshold);
1428                 /* if a very large value is being configured */
1429                 if (td_tx_threshold > UINT16_MAX)
1430                         td_tx_threshold = CGR_RX_PERFQ_THRESH;
1431         }
1432
1433         /* If congestion control is enabled globally*/
1434         if (td_threshold) {
1435                 dpaa_intf->cgr_rx = rte_zmalloc(NULL,
1436                         sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE);
1437                 if (!dpaa_intf->cgr_rx) {
1438                         DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n");
1439                         ret = -ENOMEM;
1440                         goto free_rx;
1441                 }
1442
1443                 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0);
1444                 if (ret != num_rx_fqs) {
1445                         DPAA_PMD_WARN("insufficient CGRIDs available");
1446                         ret = -EINVAL;
1447                         goto free_rx;
1448                 }
1449         } else {
1450                 dpaa_intf->cgr_rx = NULL;
1451         }
1452
1453         for (loop = 0; loop < num_rx_fqs; loop++) {
1454                 if (default_q)
1455                         fqid = cfg->rx_def;
1456                 else
1457                         fqid = DPAA_PCD_FQID_START + fman_intf->mac_idx *
1458                                 DPAA_PCD_FQID_MULTIPLIER + loop;
1459
1460                 if (dpaa_intf->cgr_rx)
1461                         dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop];
1462
1463                 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop],
1464                         dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL,
1465                         fqid);
1466                 if (ret)
1467                         goto free_rx;
1468                 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf;
1469         }
1470         dpaa_intf->nb_rx_queues = num_rx_fqs;
1471
1472         /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */
1473         dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) *
1474                 MAX_DPAA_CORES, MAX_CACHELINE);
1475         if (!dpaa_intf->tx_queues) {
1476                 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n");
1477                 ret = -ENOMEM;
1478                 goto free_rx;
1479         }
1480
1481         /* If congestion control is enabled globally*/
1482         if (td_tx_threshold) {
1483                 dpaa_intf->cgr_tx = rte_zmalloc(NULL,
1484                         sizeof(struct qman_cgr) * MAX_DPAA_CORES,
1485                         MAX_CACHELINE);
1486                 if (!dpaa_intf->cgr_tx) {
1487                         DPAA_PMD_ERR("Failed to alloc mem for cgr_tx\n");
1488                         ret = -ENOMEM;
1489                         goto free_rx;
1490                 }
1491
1492                 ret = qman_alloc_cgrid_range(&cgrid_tx[0], MAX_DPAA_CORES,
1493                                              1, 0);
1494                 if (ret != MAX_DPAA_CORES) {
1495                         DPAA_PMD_WARN("insufficient CGRIDs available");
1496                         ret = -EINVAL;
1497                         goto free_rx;
1498                 }
1499         } else {
1500                 dpaa_intf->cgr_tx = NULL;
1501         }
1502
1503
1504         for (loop = 0; loop < MAX_DPAA_CORES; loop++) {
1505                 if (dpaa_intf->cgr_tx)
1506                         dpaa_intf->cgr_tx[loop].cgrid = cgrid_tx[loop];
1507
1508                 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop],
1509                         fman_intf,
1510                         dpaa_intf->cgr_tx ? &dpaa_intf->cgr_tx[loop] : NULL);
1511                 if (ret)
1512                         goto free_tx;
1513                 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
1514         }
1515         dpaa_intf->nb_tx_queues = MAX_DPAA_CORES;
1516
1517 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1518         dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1519                 DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err);
1520         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf;
1521         dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1522                 DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err);
1523         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf;
1524 #endif
1525
1526         DPAA_PMD_DEBUG("All frame queues created");
1527
1528         /* Get the initial configuration for flow control */
1529         dpaa_fc_set_default(dpaa_intf, fman_intf);
1530
1531         /* reset bpool list, initialize bpool dynamically */
1532         list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) {
1533                 list_del(&bp->node);
1534                 rte_free(bp);
1535         }
1536
1537         /* Populate ethdev structure */
1538         eth_dev->dev_ops = &dpaa_devops;
1539         eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1540         eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
1541
1542         /* Allocate memory for storing MAC addresses */
1543         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
1544                 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0);
1545         if (eth_dev->data->mac_addrs == NULL) {
1546                 DPAA_PMD_ERR("Failed to allocate %d bytes needed to "
1547                                                 "store MAC addresses",
1548                                 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER);
1549                 ret = -ENOMEM;
1550                 goto free_tx;
1551         }
1552
1553         /* copy the primary mac address */
1554         rte_ether_addr_copy(&fman_intf->mac_addr, &eth_dev->data->mac_addrs[0]);
1555         rte_ether_format_addr(eth_buf, sizeof(eth_buf), &fman_intf->mac_addr);
1556
1557         DPAA_PMD_INFO("net: dpaa: %s: %s", dpaa_device->name, eth_buf);
1558
1559         /* Disable RX mode */
1560         fman_if_discard_rx_errors(fman_intf);
1561         fman_if_disable_rx(fman_intf);
1562         /* Disable promiscuous mode */
1563         fman_if_promiscuous_disable(fman_intf);
1564         /* Disable multicast */
1565         fman_if_reset_mcast_filter_table(fman_intf);
1566         /* Reset interface statistics */
1567         fman_if_stats_reset(fman_intf);
1568         /* Disable SG by default */
1569         fman_if_set_sg(fman_intf, 0);
1570         fman_if_set_maxfrm(fman_intf, RTE_ETHER_MAX_LEN + VLAN_TAG_SIZE);
1571
1572         return 0;
1573
1574 free_tx:
1575         rte_free(dpaa_intf->tx_queues);
1576         dpaa_intf->tx_queues = NULL;
1577         dpaa_intf->nb_tx_queues = 0;
1578
1579 free_rx:
1580         rte_free(dpaa_intf->cgr_rx);
1581         rte_free(dpaa_intf->cgr_tx);
1582         rte_free(dpaa_intf->rx_queues);
1583         dpaa_intf->rx_queues = NULL;
1584         dpaa_intf->nb_rx_queues = 0;
1585         return ret;
1586 }
1587
1588 static int
1589 dpaa_dev_uninit(struct rte_eth_dev *dev)
1590 {
1591         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1592         int loop;
1593
1594         PMD_INIT_FUNC_TRACE();
1595
1596         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1597                 return -EPERM;
1598
1599         if (!dpaa_intf) {
1600                 DPAA_PMD_WARN("Already closed or not started");
1601                 return -1;
1602         }
1603
1604         dpaa_eth_dev_close(dev);
1605
1606         /* release configuration memory */
1607         if (dpaa_intf->fc_conf)
1608                 rte_free(dpaa_intf->fc_conf);
1609
1610         /* Release RX congestion Groups */
1611         if (dpaa_intf->cgr_rx) {
1612                 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++)
1613                         qman_delete_cgr(&dpaa_intf->cgr_rx[loop]);
1614
1615                 qman_release_cgrid_range(dpaa_intf->cgr_rx[loop].cgrid,
1616                                          dpaa_intf->nb_rx_queues);
1617         }
1618
1619         rte_free(dpaa_intf->cgr_rx);
1620         dpaa_intf->cgr_rx = NULL;
1621
1622         /* Release TX congestion Groups */
1623         if (dpaa_intf->cgr_tx) {
1624                 for (loop = 0; loop < MAX_DPAA_CORES; loop++)
1625                         qman_delete_cgr(&dpaa_intf->cgr_tx[loop]);
1626
1627                 qman_release_cgrid_range(dpaa_intf->cgr_tx[loop].cgrid,
1628                                          MAX_DPAA_CORES);
1629                 rte_free(dpaa_intf->cgr_tx);
1630                 dpaa_intf->cgr_tx = NULL;
1631         }
1632
1633         rte_free(dpaa_intf->rx_queues);
1634         dpaa_intf->rx_queues = NULL;
1635
1636         rte_free(dpaa_intf->tx_queues);
1637         dpaa_intf->tx_queues = NULL;
1638
1639         dev->dev_ops = NULL;
1640         dev->rx_pkt_burst = NULL;
1641         dev->tx_pkt_burst = NULL;
1642
1643         return 0;
1644 }
1645
1646 static int
1647 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv __rte_unused,
1648                struct rte_dpaa_device *dpaa_dev)
1649 {
1650         int diag;
1651         int ret;
1652         struct rte_eth_dev *eth_dev;
1653
1654         PMD_INIT_FUNC_TRACE();
1655
1656         if ((DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) >
1657                 RTE_PKTMBUF_HEADROOM) {
1658                 DPAA_PMD_ERR(
1659                 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA Annotation req(%d)",
1660                 RTE_PKTMBUF_HEADROOM,
1661                 DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE);
1662
1663                 return -1;
1664         }
1665
1666         /* In case of secondary process, the device is already configured
1667          * and no further action is required, except portal initialization
1668          * and verifying secondary attachment to port name.
1669          */
1670         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1671                 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
1672                 if (!eth_dev)
1673                         return -ENOMEM;
1674                 eth_dev->device = &dpaa_dev->device;
1675                 eth_dev->dev_ops = &dpaa_devops;
1676
1677                 ret = dpaa_dev_init_secondary(eth_dev);
1678                 if (ret != 0) {
1679                         RTE_LOG(ERR, PMD, "secondary dev init failed\n");
1680                         return ret;
1681                 }
1682
1683                 rte_eth_dev_probing_finish(eth_dev);
1684                 return 0;
1685         }
1686
1687         if (!is_global_init && (rte_eal_process_type() == RTE_PROC_PRIMARY)) {
1688                 if (access("/tmp/fmc.bin", F_OK) == -1) {
1689                         DPAA_PMD_INFO("* FMC not configured.Enabling default mode");
1690                         default_q = 1;
1691                 }
1692
1693                 /* disabling the default push mode for LS1043 */
1694                 if (dpaa_svr_family == SVR_LS1043A_FAMILY)
1695                         dpaa_push_mode_max_queue = 0;
1696
1697                 /* if push mode queues to be enabled. Currenly we are allowing
1698                  * only one queue per thread.
1699                  */
1700                 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) {
1701                         dpaa_push_mode_max_queue =
1702                                         atoi(getenv("DPAA_PUSH_QUEUES_NUMBER"));
1703                         if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE)
1704                             dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE;
1705                 }
1706
1707                 is_global_init = 1;
1708         }
1709
1710         if (unlikely(!DPAA_PER_LCORE_PORTAL)) {
1711                 ret = rte_dpaa_portal_init((void *)1);
1712                 if (ret) {
1713                         DPAA_PMD_ERR("Unable to initialize portal");
1714                         return ret;
1715                 }
1716         }
1717
1718         eth_dev = rte_eth_dev_allocate(dpaa_dev->name);
1719         if (!eth_dev)
1720                 return -ENOMEM;
1721
1722         eth_dev->data->dev_private =
1723                         rte_zmalloc("ethdev private structure",
1724                                         sizeof(struct dpaa_if),
1725                                         RTE_CACHE_LINE_SIZE);
1726         if (!eth_dev->data->dev_private) {
1727                 DPAA_PMD_ERR("Cannot allocate memzone for port data");
1728                 rte_eth_dev_release_port(eth_dev);
1729                 return -ENOMEM;
1730         }
1731
1732         eth_dev->device = &dpaa_dev->device;
1733         dpaa_dev->eth_dev = eth_dev;
1734
1735         qman_ern_register_cb(dpaa_free_mbuf);
1736
1737         /* Invoke PMD device initialization function */
1738         diag = dpaa_dev_init(eth_dev);
1739         if (diag == 0) {
1740                 rte_eth_dev_probing_finish(eth_dev);
1741                 return 0;
1742         }
1743
1744         rte_eth_dev_release_port(eth_dev);
1745         return diag;
1746 }
1747
1748 static int
1749 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev)
1750 {
1751         struct rte_eth_dev *eth_dev;
1752
1753         PMD_INIT_FUNC_TRACE();
1754
1755         eth_dev = dpaa_dev->eth_dev;
1756         dpaa_dev_uninit(eth_dev);
1757
1758         rte_eth_dev_release_port(eth_dev);
1759
1760         return 0;
1761 }
1762
1763 static struct rte_dpaa_driver rte_dpaa_pmd = {
1764         .drv_type = FSL_DPAA_ETH,
1765         .probe = rte_dpaa_probe,
1766         .remove = rte_dpaa_remove,
1767 };
1768
1769 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd);
1770 RTE_LOG_REGISTER(dpaa_logtype_pmd, pmd.net.dpaa, NOTICE);