drivers/net/dpaa/dpaa_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2017 NXP
   5  *
   6  */
   7 /* System headers */
   8 #include <stdio.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <limits.h>
  12 #include <sched.h>
  13 #include <signal.h>
  14 #include <pthread.h>
  15 #include <sys/types.h>
  16 #include <sys/syscall.h>
  17
  18 #include <rte_byteorder.h>
  19 #include <rte_common.h>
  20 #include <rte_interrupts.h>
  21 #include <rte_log.h>
  22 #include <rte_debug.h>
  23 #include <rte_pci.h>
  24 #include <rte_atomic.h>
  25 #include <rte_branch_prediction.h>
  26 #include <rte_memory.h>
  27 #include <rte_tailq.h>
  28 #include <rte_eal.h>
  29 #include <rte_alarm.h>
  30 #include <rte_ether.h>
  31 #include <rte_ethdev_driver.h>
  32 #include <rte_malloc.h>
  33 #include <rte_ring.h>
  34
  35 #include <rte_dpaa_bus.h>
  36 #include <rte_dpaa_logs.h>
  37 #include <dpaa_mempool.h>
  38
  39 #include <dpaa_ethdev.h>
  40 #include <dpaa_rxtx.h>
  41 #include <rte_pmd_dpaa.h>
  42
  43 #include <fsl_usd.h>
  44 #include <fsl_qman.h>
  45 #include <fsl_bman.h>
  46 #include <fsl_fman.h>
  47
  48 /* Supported Rx offloads */
  49 static uint64_t dev_rx_offloads_sup =
  50                 DEV_RX_OFFLOAD_JUMBO_FRAME;
  51
  52 /* Rx offloads which cannot be disabled */
  53 static uint64_t dev_rx_offloads_nodis =
  54                 DEV_RX_OFFLOAD_IPV4_CKSUM |
  55                 DEV_RX_OFFLOAD_UDP_CKSUM |
  56                 DEV_RX_OFFLOAD_TCP_CKSUM |
  57                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
  58                 DEV_RX_OFFLOAD_CRC_STRIP |
  59                 DEV_RX_OFFLOAD_SCATTER;
  60
  61 /* Supported Tx offloads */
  62 static uint64_t dev_tx_offloads_sup;
  63
  64 /* Tx offloads which cannot be disabled */
  65 static uint64_t dev_tx_offloads_nodis =
  66                 DEV_TX_OFFLOAD_IPV4_CKSUM |
  67                 DEV_TX_OFFLOAD_UDP_CKSUM |
  68                 DEV_TX_OFFLOAD_TCP_CKSUM |
  69                 DEV_TX_OFFLOAD_SCTP_CKSUM |
  70                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
  71                 DEV_TX_OFFLOAD_MULTI_SEGS |
  72                 DEV_TX_OFFLOAD_MT_LOCKFREE |
  73                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
  74
  75 /* Keep track of whether QMAN and BMAN have been globally initialized */
  76 static int is_global_init;
  77 /* At present we only allow up to 4 push mode queues as default - as each of
  78  * this queue need dedicated portal and we are short of portals.
  79  */
  80 #define DPAA_MAX_PUSH_MODE_QUEUE       8
  81 #define DPAA_DEFAULT_PUSH_MODE_QUEUE   4
  82
  83 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE;
  84 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/
  85
  86
  87 /* Per FQ Taildrop in frame count */
  88 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH;
  89
  90 struct rte_dpaa_xstats_name_off {
  91         char name[RTE_ETH_XSTATS_NAME_SIZE];
  92         uint32_t offset;
  93 };
  94
  95 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = {
  96         {"rx_align_err",
  97                 offsetof(struct dpaa_if_stats, raln)},
  98         {"rx_valid_pause",
  99                 offsetof(struct dpaa_if_stats, rxpf)},
 100         {"rx_fcs_err",
 101                 offsetof(struct dpaa_if_stats, rfcs)},
 102         {"rx_vlan_frame",
 103                 offsetof(struct dpaa_if_stats, rvlan)},
 104         {"rx_frame_err",
 105                 offsetof(struct dpaa_if_stats, rerr)},
 106         {"rx_drop_err",
 107                 offsetof(struct dpaa_if_stats, rdrp)},
 108         {"rx_undersized",
 109                 offsetof(struct dpaa_if_stats, rund)},
 110         {"rx_oversize_err",
 111                 offsetof(struct dpaa_if_stats, rovr)},
 112         {"rx_fragment_pkt",
 113                 offsetof(struct dpaa_if_stats, rfrg)},
 114         {"tx_valid_pause",
 115                 offsetof(struct dpaa_if_stats, txpf)},
 116         {"tx_fcs_err",
 117                 offsetof(struct dpaa_if_stats, terr)},
 118         {"tx_vlan_frame",
 119                 offsetof(struct dpaa_if_stats, tvlan)},
 120         {"rx_undersized",
 121                 offsetof(struct dpaa_if_stats, tund)},
 122 };
 123
 124 static struct rte_dpaa_driver rte_dpaa_pmd;
 125
 126 static void
 127 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info);
 128
 129 static inline void
 130 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts)
 131 {
 132         memset(opts, 0, sizeof(struct qm_mcc_initfq));
 133         opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
 134         opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING |
 135                            QM_FQCTRL_PREFERINCACHE;
 136         opts->fqd.context_a.stashing.exclusive = 0;
 137         if (dpaa_svr_family != SVR_LS1046A_FAMILY)
 138                 opts->fqd.context_a.stashing.annotation_cl =
 139                                                 DPAA_IF_RX_ANNOTATION_STASH;
 140         opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
 141         opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH;
 142 }
 143
 144 static int
 145 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 146 {
 147         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 148         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN
 149                                 + VLAN_TAG_SIZE;
 150
 151         PMD_INIT_FUNC_TRACE();
 152
 153         if (mtu < ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN)
 154                 return -EINVAL;
 155         if (frame_size > ETHER_MAX_LEN)
 156                 dev->data->dev_conf.rxmode.offloads &=
 157                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 158         else
 159                 dev->data->dev_conf.rxmode.offloads &=
 160                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 161
 162         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 163
 164         fman_if_set_maxfrm(dpaa_intf->fif, frame_size);
 165
 166         return 0;
 167 }
 168
 169 static int
 170 dpaa_eth_dev_configure(struct rte_eth_dev *dev)
 171 {
 172         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 173         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 174         uint64_t rx_offloads = eth_conf->rxmode.offloads;
 175         uint64_t tx_offloads = eth_conf->txmode.offloads;
 176
 177         PMD_INIT_FUNC_TRACE();
 178
 179         /* Rx offloads validation */
 180         if (~(dev_rx_offloads_sup | dev_rx_offloads_nodis) & rx_offloads) {
 181                 DPAA_PMD_ERR(
 182                 "Rx offloads non supported - requested 0x%" PRIx64
 183                 " supported 0x%" PRIx64,
 184                         rx_offloads,
 185                         dev_rx_offloads_sup | dev_rx_offloads_nodis);
 186                 return -ENOTSUP;
 187         }
 188         if (dev_rx_offloads_nodis & ~rx_offloads) {
 189                 DPAA_PMD_WARN(
 190                 "Rx offloads non configurable - requested 0x%" PRIx64
 191                 " ignored 0x%" PRIx64,
 192                         rx_offloads, dev_rx_offloads_nodis);
 193         }
 194
 195         /* Tx offloads validation */
 196         if (~(dev_tx_offloads_sup | dev_tx_offloads_nodis) & tx_offloads) {
 197                 DPAA_PMD_ERR(
 198                 "Tx offloads non supported - requested 0x%" PRIx64
 199                 " supported 0x%" PRIx64,
 200                         tx_offloads,
 201                         dev_tx_offloads_sup | dev_tx_offloads_nodis);
 202                 return -ENOTSUP;
 203         }
 204         if (dev_tx_offloads_nodis & ~tx_offloads) {
 205                 DPAA_PMD_WARN(
 206                 "Tx offloads non configurable - requested 0x%" PRIx64
 207                 " ignored 0x%" PRIx64,
 208                         tx_offloads, dev_tx_offloads_nodis);
 209         }
 210
 211         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 212                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
 213                     DPAA_MAX_RX_PKT_LEN) {
 214                         fman_if_set_maxfrm(dpaa_intf->fif,
 215                                 dev->data->dev_conf.rxmode.max_rx_pkt_len);
 216                         return 0;
 217                 } else {
 218                         return -1;
 219                 }
 220         }
 221         return 0;
 222 }
 223
 224 static const uint32_t *
 225 dpaa_supported_ptypes_get(struct rte_eth_dev *dev)
 226 {
 227         static const uint32_t ptypes[] = {
 228                 /*todo -= add more types */
 229                 RTE_PTYPE_L2_ETHER,
 230                 RTE_PTYPE_L3_IPV4,
 231                 RTE_PTYPE_L3_IPV4_EXT,
 232                 RTE_PTYPE_L3_IPV6,
 233                 RTE_PTYPE_L3_IPV6_EXT,
 234                 RTE_PTYPE_L4_TCP,
 235                 RTE_PTYPE_L4_UDP,
 236                 RTE_PTYPE_L4_SCTP
 237         };
 238
 239         PMD_INIT_FUNC_TRACE();
 240
 241         if (dev->rx_pkt_burst == dpaa_eth_queue_rx)
 242                 return ptypes;
 243         return NULL;
 244 }
 245
 246 static int dpaa_eth_dev_start(struct rte_eth_dev *dev)
 247 {
 248         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 249
 250         PMD_INIT_FUNC_TRACE();
 251
 252         /* Change tx callback to the real one */
 253         dev->tx_pkt_burst = dpaa_eth_queue_tx;
 254         fman_if_enable_rx(dpaa_intf->fif);
 255
 256         return 0;
 257 }
 258
 259 static void dpaa_eth_dev_stop(struct rte_eth_dev *dev)
 260 {
 261         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 262
 263         PMD_INIT_FUNC_TRACE();
 264
 265         fman_if_disable_rx(dpaa_intf->fif);
 266         dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
 267 }
 268
 269 static void dpaa_eth_dev_close(struct rte_eth_dev *dev)
 270 {
 271         PMD_INIT_FUNC_TRACE();
 272
 273         dpaa_eth_dev_stop(dev);
 274 }
 275
 276 static int
 277 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused,
 278                      char *fw_version,
 279                      size_t fw_size)
 280 {
 281         int ret;
 282         FILE *svr_file = NULL;
 283         unsigned int svr_ver = 0;
 284
 285         PMD_INIT_FUNC_TRACE();
 286
 287         svr_file = fopen(DPAA_SOC_ID_FILE, "r");
 288         if (!svr_file) {
 289                 DPAA_PMD_ERR("Unable to open SoC device");
 290                 return -ENOTSUP; /* Not supported on this infra */
 291         }
 292         if (fscanf(svr_file, "svr:%x", &svr_ver) > 0)
 293                 dpaa_svr_family = svr_ver & SVR_MASK;
 294         else
 295                 DPAA_PMD_ERR("Unable to read SoC device");
 296
 297         fclose(svr_file);
 298
 299         ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x",
 300                        svr_ver, fman_ip_rev);
 301         ret += 1; /* add the size of '\0' */
 302
 303         if (fw_size < (uint32_t)ret)
 304                 return ret;
 305         else
 306                 return 0;
 307 }
 308
 309 static void dpaa_eth_dev_info(struct rte_eth_dev *dev,
 310                               struct rte_eth_dev_info *dev_info)
 311 {
 312         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 313
 314         PMD_INIT_FUNC_TRACE();
 315
 316         dev_info->max_rx_queues = dpaa_intf->nb_rx_queues;
 317         dev_info->max_tx_queues = dpaa_intf->nb_tx_queues;
 318         dev_info->min_rx_bufsize = DPAA_MIN_RX_BUF_SIZE;
 319         dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
 320         dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER;
 321         dev_info->max_hash_mac_addrs = 0;
 322         dev_info->max_vfs = 0;
 323         dev_info->max_vmdq_pools = ETH_16_POOLS;
 324         dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL;
 325         dev_info->speed_capa = (ETH_LINK_SPEED_1G |
 326                                 ETH_LINK_SPEED_10G);
 327         dev_info->rx_offload_capa = dev_rx_offloads_sup |
 328                                         dev_rx_offloads_nodis;
 329         dev_info->tx_offload_capa = dev_tx_offloads_sup |
 330                                         dev_tx_offloads_nodis;
 331 }
 332
 333 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
 334                                 int wait_to_complete __rte_unused)
 335 {
 336         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 337         struct rte_eth_link *link = &dev->data->dev_link;
 338
 339         PMD_INIT_FUNC_TRACE();
 340
 341         if (dpaa_intf->fif->mac_type == fman_mac_1g)
 342                 link->link_speed = ETH_SPEED_NUM_1G;
 343         else if (dpaa_intf->fif->mac_type == fman_mac_10g)
 344                 link->link_speed = ETH_SPEED_NUM_10G;
 345         else
 346                 DPAA_PMD_ERR("invalid link_speed: %s, %d",
 347                              dpaa_intf->name, dpaa_intf->fif->mac_type);
 348
 349         link->link_status = dpaa_intf->valid;
 350         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 351         link->link_autoneg = ETH_LINK_AUTONEG;
 352         return 0;
 353 }
 354
 355 static int dpaa_eth_stats_get(struct rte_eth_dev *dev,
 356                                struct rte_eth_stats *stats)
 357 {
 358         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 359
 360         PMD_INIT_FUNC_TRACE();
 361
 362         fman_if_stats_get(dpaa_intf->fif, stats);
 363         return 0;
 364 }
 365
 366 static void dpaa_eth_stats_reset(struct rte_eth_dev *dev)
 367 {
 368         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 369
 370         PMD_INIT_FUNC_TRACE();
 371
 372         fman_if_stats_reset(dpaa_intf->fif);
 373 }
 374
 375 static int
 376 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
 377                     unsigned int n)
 378 {
 379         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 380         unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings);
 381         uint64_t values[sizeof(struct dpaa_if_stats) / 8];
 382
 383         if (n < num)
 384                 return num;
 385
 386         if (xstats == NULL)
 387                 return 0;
 388
 389         fman_if_stats_get_all(dpaa_intf->fif, values,
 390                               sizeof(struct dpaa_if_stats) / 8);
 391
 392         for (i = 0; i < num; i++) {
 393                 xstats[i].id = i;
 394                 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8];
 395         }
 396         return i;
 397 }
 398
 399 static int
 400 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 401                       struct rte_eth_xstat_name *xstats_names,
 402                       unsigned int limit)
 403 {
 404         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 405
 406         if (limit < stat_cnt)
 407                 return stat_cnt;
 408
 409         if (xstats_names != NULL)
 410                 for (i = 0; i < stat_cnt; i++)
 411                         snprintf(xstats_names[i].name,
 412                                  sizeof(xstats_names[i].name),
 413                                  "%s",
 414                                  dpaa_xstats_strings[i].name);
 415
 416         return stat_cnt;
 417 }
 418
 419 static int
 420 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 421                       uint64_t *values, unsigned int n)
 422 {
 423         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 424         uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8];
 425
 426         if (!ids) {
 427                 struct dpaa_if *dpaa_intf = dev->data->dev_private;
 428
 429                 if (n < stat_cnt)
 430                         return stat_cnt;
 431
 432                 if (!values)
 433                         return 0;
 434
 435                 fman_if_stats_get_all(dpaa_intf->fif, values_copy,
 436                                       sizeof(struct dpaa_if_stats) / 8);
 437
 438                 for (i = 0; i < stat_cnt; i++)
 439                         values[i] =
 440                                 values_copy[dpaa_xstats_strings[i].offset / 8];
 441
 442                 return stat_cnt;
 443         }
 444
 445         dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
 446
 447         for (i = 0; i < n; i++) {
 448                 if (ids[i] >= stat_cnt) {
 449                         DPAA_PMD_ERR("id value isn't valid");
 450                         return -1;
 451                 }
 452                 values[i] = values_copy[ids[i]];
 453         }
 454         return n;
 455 }
 456
 457 static int
 458 dpaa_xstats_get_names_by_id(
 459         struct rte_eth_dev *dev,
 460         struct rte_eth_xstat_name *xstats_names,
 461         const uint64_t *ids,
 462         unsigned int limit)
 463 {
 464         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 465         struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
 466
 467         if (!ids)
 468                 return dpaa_xstats_get_names(dev, xstats_names, limit);
 469
 470         dpaa_xstats_get_names(dev, xstats_names_copy, limit);
 471
 472         for (i = 0; i < limit; i++) {
 473                 if (ids[i] >= stat_cnt) {
 474                         DPAA_PMD_ERR("id value isn't valid");
 475                         return -1;
 476                 }
 477                 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
 478         }
 479         return limit;
 480 }
 481
 482 static void dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev)
 483 {
 484         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 485
 486         PMD_INIT_FUNC_TRACE();
 487
 488         fman_if_promiscuous_enable(dpaa_intf->fif);
 489 }
 490
 491 static void dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev)
 492 {
 493         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 494
 495         PMD_INIT_FUNC_TRACE();
 496
 497         fman_if_promiscuous_disable(dpaa_intf->fif);
 498 }
 499
 500 static void dpaa_eth_multicast_enable(struct rte_eth_dev *dev)
 501 {
 502         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 503
 504         PMD_INIT_FUNC_TRACE();
 505
 506         fman_if_set_mcast_filter_table(dpaa_intf->fif);
 507 }
 508
 509 static void dpaa_eth_multicast_disable(struct rte_eth_dev *dev)
 510 {
 511         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 512
 513         PMD_INIT_FUNC_TRACE();
 514
 515         fman_if_reset_mcast_filter_table(dpaa_intf->fif);
 516 }
 517
 518 static
 519 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 520                             uint16_t nb_desc,
 521                             unsigned int socket_id __rte_unused,
 522                             const struct rte_eth_rxconf *rx_conf __rte_unused,
 523                             struct rte_mempool *mp)
 524 {
 525         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 526         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx];
 527         struct qm_mcc_initfq opts = {0};
 528         u32 flags = 0;
 529         int ret;
 530
 531         PMD_INIT_FUNC_TRACE();
 532
 533         DPAA_PMD_INFO("Rx queue setup for queue index: %d", queue_idx);
 534
 535         if (!dpaa_intf->bp_info || dpaa_intf->bp_info->mp != mp) {
 536                 struct fman_if_ic_params icp;
 537                 uint32_t fd_offset;
 538                 uint32_t bp_size;
 539
 540                 if (!mp->pool_data) {
 541                         DPAA_PMD_ERR("Not an offloaded buffer pool!");
 542                         return -1;
 543                 }
 544                 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
 545
 546                 memset(&icp, 0, sizeof(icp));
 547                 /* set ICEOF for to the default value , which is 0*/
 548                 icp.iciof = DEFAULT_ICIOF;
 549                 icp.iceof = DEFAULT_RX_ICEOF;
 550                 icp.icsz = DEFAULT_ICSZ;
 551                 fman_if_set_ic_params(dpaa_intf->fif, &icp);
 552
 553                 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE;
 554                 fman_if_set_fdoff(dpaa_intf->fif, fd_offset);
 555
 556                 /* Buffer pool size should be equal to Dataroom Size*/
 557                 bp_size = rte_pktmbuf_data_room_size(mp);
 558                 fman_if_set_bp(dpaa_intf->fif, mp->size,
 559                                dpaa_intf->bp_info->bpid, bp_size);
 560                 dpaa_intf->valid = 1;
 561                 DPAA_PMD_INFO("if =%s - fd_offset = %d offset = %d",
 562                             dpaa_intf->name, fd_offset,
 563                         fman_if_get_fdoff(dpaa_intf->fif));
 564         }
 565         /* checking if push mode only, no error check for now */
 566         if (dpaa_push_mode_max_queue > dpaa_push_queue_idx) {
 567                 dpaa_push_queue_idx++;
 568                 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
 569                 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK |
 570                                    QM_FQCTRL_CTXASTASHING |
 571                                    QM_FQCTRL_PREFERINCACHE;
 572                 opts.fqd.context_a.stashing.exclusive = 0;
 573                 /* In muticore scenario stashing becomes a bottleneck on LS1046.
 574                  * So do not enable stashing in this case
 575                  */
 576                 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
 577                         opts.fqd.context_a.stashing.annotation_cl =
 578                                                 DPAA_IF_RX_ANNOTATION_STASH;
 579                 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
 580                 opts.fqd.context_a.stashing.context_cl =
 581                                                 DPAA_IF_RX_CONTEXT_STASH;
 582
 583                 /*Create a channel and associate given queue with the channel*/
 584                 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0);
 585                 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
 586                 opts.fqd.dest.channel = rxq->ch_id;
 587                 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY;
 588                 flags = QMAN_INITFQ_FLAG_SCHED;
 589
 590                 /* Configure tail drop */
 591                 if (dpaa_intf->cgr_rx) {
 592                         opts.we_mask |= QM_INITFQ_WE_CGID;
 593                         opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid;
 594                         opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 595                 }
 596                 ret = qman_init_fq(rxq, flags, &opts);
 597                 if (ret)
 598                         DPAA_PMD_ERR("Channel/Queue association failed. fqid %d"
 599                                      " ret: %d", rxq->fqid, ret);
 600                 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb;
 601                 rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare;
 602                 rxq->is_static = true;
 603         }
 604         dev->data->rx_queues[queue_idx] = rxq;
 605
 606         /* configure the CGR size as per the desc size */
 607         if (dpaa_intf->cgr_rx) {
 608                 struct qm_mcc_initcgr cgr_opts = {0};
 609
 610                 /* Enable tail drop with cgr on this queue */
 611                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0);
 612                 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts);
 613                 if (ret) {
 614                         DPAA_PMD_WARN(
 615                                 "rx taildrop modify fail on fqid %d (ret=%d)",
 616                                 rxq->fqid, ret);
 617                 }
 618         }
 619
 620         return 0;
 621 }
 622
 623 int __rte_experimental
 624 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
 625                 int eth_rx_queue_id,
 626                 u16 ch_id,
 627                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
 628 {
 629         int ret;
 630         u32 flags = 0;
 631         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 632         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
 633         struct qm_mcc_initfq opts = {0};
 634
 635         if (dpaa_push_mode_max_queue)
 636                 DPAA_PMD_WARN("PUSH mode already enabled for first %d queues.\n"
 637                               "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n",
 638                               dpaa_push_mode_max_queue);
 639
 640         dpaa_poll_queue_default_config(&opts);
 641
 642         switch (queue_conf->ev.sched_type) {
 643         case RTE_SCHED_TYPE_ATOMIC:
 644                 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE;
 645                 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary
 646                  * configuration with HOLD_ACTIVE setting
 647                  */
 648                 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK);
 649                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic;
 650                 break;
 651         case RTE_SCHED_TYPE_ORDERED:
 652                 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n");
 653                 return -1;
 654         default:
 655                 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK;
 656                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel;
 657                 break;
 658         }
 659
 660         opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
 661         opts.fqd.dest.channel = ch_id;
 662         opts.fqd.dest.wq = queue_conf->ev.priority;
 663
 664         if (dpaa_intf->cgr_rx) {
 665                 opts.we_mask |= QM_INITFQ_WE_CGID;
 666                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
 667                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 668         }
 669
 670         flags = QMAN_INITFQ_FLAG_SCHED;
 671
 672         ret = qman_init_fq(rxq, flags, &opts);
 673         if (ret) {
 674                 DPAA_PMD_ERR("Channel/Queue association failed. fqid %d ret:%d",
 675                              rxq->fqid, ret);
 676                 return ret;
 677         }
 678
 679         /* copy configuration which needs to be filled during dequeue */
 680         memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event));
 681         dev->data->rx_queues[eth_rx_queue_id] = rxq;
 682
 683         return ret;
 684 }
 685
 686 int __rte_experimental
 687 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
 688                 int eth_rx_queue_id)
 689 {
 690         struct qm_mcc_initfq opts;
 691         int ret;
 692         u32 flags = 0;
 693         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 694         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
 695
 696         dpaa_poll_queue_default_config(&opts);
 697
 698         if (dpaa_intf->cgr_rx) {
 699                 opts.we_mask |= QM_INITFQ_WE_CGID;
 700                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
 701                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 702         }
 703
 704         ret = qman_init_fq(rxq, flags, &opts);
 705         if (ret) {
 706                 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d",
 707                              rxq->fqid, ret);
 708         }
 709
 710         rxq->cb.dqrr_dpdk_cb = NULL;
 711         dev->data->rx_queues[eth_rx_queue_id] = NULL;
 712
 713         return 0;
 714 }
 715
 716 static
 717 void dpaa_eth_rx_queue_release(void *rxq __rte_unused)
 718 {
 719         PMD_INIT_FUNC_TRACE();
 720 }
 721
 722 static
 723 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 724                             uint16_t nb_desc __rte_unused,
 725                 unsigned int socket_id __rte_unused,
 726                 const struct rte_eth_txconf *tx_conf __rte_unused)
 727 {
 728         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 729
 730         PMD_INIT_FUNC_TRACE();
 731
 732         DPAA_PMD_INFO("Tx queue setup for queue index: %d", queue_idx);
 733         dev->data->tx_queues[queue_idx] = &dpaa_intf->tx_queues[queue_idx];
 734         return 0;
 735 }
 736
 737 static void dpaa_eth_tx_queue_release(void *txq __rte_unused)
 738 {
 739         PMD_INIT_FUNC_TRACE();
 740 }
 741
 742 static uint32_t
 743 dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 744 {
 745         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 746         struct qman_fq *rxq = &dpaa_intf->rx_queues[rx_queue_id];
 747         u32 frm_cnt = 0;
 748
 749         PMD_INIT_FUNC_TRACE();
 750
 751         if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) {
 752                 RTE_LOG(DEBUG, PMD, "RX frame count for q(%d) is %u\n",
 753                         rx_queue_id, frm_cnt);
 754         }
 755         return frm_cnt;
 756 }
 757
 758 static int dpaa_link_down(struct rte_eth_dev *dev)
 759 {
 760         PMD_INIT_FUNC_TRACE();
 761
 762         dpaa_eth_dev_stop(dev);
 763         return 0;
 764 }
 765
 766 static int dpaa_link_up(struct rte_eth_dev *dev)
 767 {
 768         PMD_INIT_FUNC_TRACE();
 769
 770         dpaa_eth_dev_start(dev);
 771         return 0;
 772 }
 773
 774 static int
 775 dpaa_flow_ctrl_set(struct rte_eth_dev *dev,
 776                    struct rte_eth_fc_conf *fc_conf)
 777 {
 778         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 779         struct rte_eth_fc_conf *net_fc;
 780
 781         PMD_INIT_FUNC_TRACE();
 782
 783         if (!(dpaa_intf->fc_conf)) {
 784                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
 785                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
 786                 if (!dpaa_intf->fc_conf) {
 787                         DPAA_PMD_ERR("unable to save flow control info");
 788                         return -ENOMEM;
 789                 }
 790         }
 791         net_fc = dpaa_intf->fc_conf;
 792
 793         if (fc_conf->high_water < fc_conf->low_water) {
 794                 DPAA_PMD_ERR("Incorrect Flow Control Configuration");
 795                 return -EINVAL;
 796         }
 797
 798         if (fc_conf->mode == RTE_FC_NONE) {
 799                 return 0;
 800         } else if (fc_conf->mode == RTE_FC_TX_PAUSE ||
 801                  fc_conf->mode == RTE_FC_FULL) {
 802                 fman_if_set_fc_threshold(dpaa_intf->fif, fc_conf->high_water,
 803                                          fc_conf->low_water,
 804                                 dpaa_intf->bp_info->bpid);
 805                 if (fc_conf->pause_time)
 806                         fman_if_set_fc_quanta(dpaa_intf->fif,
 807                                               fc_conf->pause_time);
 808         }
 809
 810         /* Save the information in dpaa device */
 811         net_fc->pause_time = fc_conf->pause_time;
 812         net_fc->high_water = fc_conf->high_water;
 813         net_fc->low_water = fc_conf->low_water;
 814         net_fc->send_xon = fc_conf->send_xon;
 815         net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
 816         net_fc->mode = fc_conf->mode;
 817         net_fc->autoneg = fc_conf->autoneg;
 818
 819         return 0;
 820 }
 821
 822 static int
 823 dpaa_flow_ctrl_get(struct rte_eth_dev *dev,
 824                    struct rte_eth_fc_conf *fc_conf)
 825 {
 826         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 827         struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf;
 828         int ret;
 829
 830         PMD_INIT_FUNC_TRACE();
 831
 832         if (net_fc) {
 833                 fc_conf->pause_time = net_fc->pause_time;
 834                 fc_conf->high_water = net_fc->high_water;
 835                 fc_conf->low_water = net_fc->low_water;
 836                 fc_conf->send_xon = net_fc->send_xon;
 837                 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd;
 838                 fc_conf->mode = net_fc->mode;
 839                 fc_conf->autoneg = net_fc->autoneg;
 840                 return 0;
 841         }
 842         ret = fman_if_get_fc_threshold(dpaa_intf->fif);
 843         if (ret) {
 844                 fc_conf->mode = RTE_FC_TX_PAUSE;
 845                 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif);
 846         } else {
 847                 fc_conf->mode = RTE_FC_NONE;
 848         }
 849
 850         return 0;
 851 }
 852
 853 static int
 854 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev,
 855                              struct ether_addr *addr,
 856                              uint32_t index,
 857                              __rte_unused uint32_t pool)
 858 {
 859         int ret;
 860         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 861
 862         PMD_INIT_FUNC_TRACE();
 863
 864         ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, index);
 865
 866         if (ret)
 867                 RTE_LOG(ERR, PMD, "error: Adding the MAC ADDR failed:"
 868                         " err = %d", ret);
 869         return 0;
 870 }
 871
 872 static void
 873 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev,
 874                           uint32_t index)
 875 {
 876         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 877
 878         PMD_INIT_FUNC_TRACE();
 879
 880         fman_if_clear_mac_addr(dpaa_intf->fif, index);
 881 }
 882
 883 static int
 884 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev,
 885                        struct ether_addr *addr)
 886 {
 887         int ret;
 888         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 889
 890         PMD_INIT_FUNC_TRACE();
 891
 892         ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, 0);
 893         if (ret)
 894                 RTE_LOG(ERR, PMD, "error: Setting the MAC ADDR failed %d", ret);
 895
 896         return ret;
 897 }
 898
 899 static struct eth_dev_ops dpaa_devops = {
 900         .dev_configure            = dpaa_eth_dev_configure,
 901         .dev_start                = dpaa_eth_dev_start,
 902         .dev_stop                 = dpaa_eth_dev_stop,
 903         .dev_close                = dpaa_eth_dev_close,
 904         .dev_infos_get            = dpaa_eth_dev_info,
 905         .dev_supported_ptypes_get = dpaa_supported_ptypes_get,
 906
 907         .rx_queue_setup           = dpaa_eth_rx_queue_setup,
 908         .tx_queue_setup           = dpaa_eth_tx_queue_setup,
 909         .rx_queue_release         = dpaa_eth_rx_queue_release,
 910         .tx_queue_release         = dpaa_eth_tx_queue_release,
 911         .rx_queue_count           = dpaa_dev_rx_queue_count,
 912
 913         .flow_ctrl_get            = dpaa_flow_ctrl_get,
 914         .flow_ctrl_set            = dpaa_flow_ctrl_set,
 915
 916         .link_update              = dpaa_eth_link_update,
 917         .stats_get                = dpaa_eth_stats_get,
 918         .xstats_get               = dpaa_dev_xstats_get,
 919         .xstats_get_by_id         = dpaa_xstats_get_by_id,
 920         .xstats_get_names_by_id   = dpaa_xstats_get_names_by_id,
 921         .xstats_get_names         = dpaa_xstats_get_names,
 922         .xstats_reset             = dpaa_eth_stats_reset,
 923         .stats_reset              = dpaa_eth_stats_reset,
 924         .promiscuous_enable       = dpaa_eth_promiscuous_enable,
 925         .promiscuous_disable      = dpaa_eth_promiscuous_disable,
 926         .allmulticast_enable      = dpaa_eth_multicast_enable,
 927         .allmulticast_disable     = dpaa_eth_multicast_disable,
 928         .mtu_set                  = dpaa_mtu_set,
 929         .dev_set_link_down        = dpaa_link_down,
 930         .dev_set_link_up          = dpaa_link_up,
 931         .mac_addr_add             = dpaa_dev_add_mac_addr,
 932         .mac_addr_remove          = dpaa_dev_remove_mac_addr,
 933         .mac_addr_set             = dpaa_dev_set_mac_addr,
 934
 935         .fw_version_get           = dpaa_fw_version_get,
 936 };
 937
 938 static bool
 939 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv)
 940 {
 941         if (strcmp(dev->device->driver->name,
 942                    drv->driver.name))
 943                 return false;
 944
 945         return true;
 946 }
 947
 948 static bool
 949 is_dpaa_supported(struct rte_eth_dev *dev)
 950 {
 951         return is_device_supported(dev, &rte_dpaa_pmd);
 952 }
 953
 954 int __rte_experimental
 955 rte_pmd_dpaa_set_tx_loopback(uint8_t port, uint8_t on)
 956 {
 957         struct rte_eth_dev *dev;
 958         struct dpaa_if *dpaa_intf;
 959
 960         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
 961
 962         dev = &rte_eth_devices[port];
 963
 964         if (!is_dpaa_supported(dev))
 965                 return -ENOTSUP;
 966
 967         dpaa_intf = dev->data->dev_private;
 968
 969         if (on)
 970                 fman_if_loopback_enable(dpaa_intf->fif);
 971         else
 972                 fman_if_loopback_disable(dpaa_intf->fif);
 973
 974         return 0;
 975 }
 976
 977 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf)
 978 {
 979         struct rte_eth_fc_conf *fc_conf;
 980         int ret;
 981
 982         PMD_INIT_FUNC_TRACE();
 983
 984         if (!(dpaa_intf->fc_conf)) {
 985                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
 986                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
 987                 if (!dpaa_intf->fc_conf) {
 988                         DPAA_PMD_ERR("unable to save flow control info");
 989                         return -ENOMEM;
 990                 }
 991         }
 992         fc_conf = dpaa_intf->fc_conf;
 993         ret = fman_if_get_fc_threshold(dpaa_intf->fif);
 994         if (ret) {
 995                 fc_conf->mode = RTE_FC_TX_PAUSE;
 996                 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif);
 997         } else {
 998                 fc_conf->mode = RTE_FC_NONE;
 999         }
1000
1001         return 0;
1002 }
1003
1004 /* Initialise an Rx FQ */
1005 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx,
1006                               uint32_t fqid)
1007 {
1008         struct qm_mcc_initfq opts = {0};
1009         int ret;
1010         u32 flags = 0;
1011         struct qm_mcc_initcgr cgr_opts = {
1012                 .we_mask = QM_CGR_WE_CS_THRES |
1013                                 QM_CGR_WE_CSTD_EN |
1014                                 QM_CGR_WE_MODE,
1015                 .cgr = {
1016                         .cstd_en = QM_CGR_EN,
1017                         .mode = QMAN_CGR_MODE_FRAME
1018                 }
1019         };
1020
1021         PMD_INIT_FUNC_TRACE();
1022
1023         ret = qman_reserve_fqid(fqid);
1024         if (ret) {
1025                 DPAA_PMD_ERR("reserve rx fqid %d failed with ret: %d",
1026                              fqid, ret);
1027                 return -EINVAL;
1028         }
1029
1030         DPAA_PMD_DEBUG("creating rx fq %p, fqid %d", fq, fqid);
1031         ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1032         if (ret) {
1033                 DPAA_PMD_ERR("create rx fqid %d failed with ret: %d",
1034                         fqid, ret);
1035                 return ret;
1036         }
1037         fq->is_static = false;
1038
1039         dpaa_poll_queue_default_config(&opts);
1040
1041         if (cgr_rx) {
1042                 /* Enable tail drop with cgr on this queue */
1043                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0);
1044                 cgr_rx->cb = NULL;
1045                 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT,
1046                                       &cgr_opts);
1047                 if (ret) {
1048                         DPAA_PMD_WARN(
1049                                 "rx taildrop init fail on rx fqid %d (ret=%d)",
1050                                 fqid, ret);
1051                         goto without_cgr;
1052                 }
1053                 opts.we_mask |= QM_INITFQ_WE_CGID;
1054                 opts.fqd.cgid = cgr_rx->cgrid;
1055                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1056         }
1057 without_cgr:
1058         ret = qman_init_fq(fq, flags, &opts);
1059         if (ret)
1060                 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d", fqid, ret);
1061         return ret;
1062 }
1063
1064 /* Initialise a Tx FQ */
1065 static int dpaa_tx_queue_init(struct qman_fq *fq,
1066                               struct fman_if *fman_intf)
1067 {
1068         struct qm_mcc_initfq opts = {0};
1069         int ret;
1070
1071         PMD_INIT_FUNC_TRACE();
1072
1073         ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
1074                              QMAN_FQ_FLAG_TO_DCPORTAL, fq);
1075         if (ret) {
1076                 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret);
1077                 return ret;
1078         }
1079         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL |
1080                        QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA;
1081         opts.fqd.dest.channel = fman_intf->tx_channel_id;
1082         opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY;
1083         opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE;
1084         opts.fqd.context_b = 0;
1085         /* no tx-confirmation */
1086         opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi;
1087         opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo;
1088         DPAA_PMD_DEBUG("init tx fq %p, fqid %d", fq, fq->fqid);
1089         ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
1090         if (ret)
1091                 DPAA_PMD_ERR("init tx fqid %d failed %d", fq->fqid, ret);
1092         return ret;
1093 }
1094
1095 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1096 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */
1097 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid)
1098 {
1099         struct qm_mcc_initfq opts = {0};
1100         int ret;
1101
1102         PMD_INIT_FUNC_TRACE();
1103
1104         ret = qman_reserve_fqid(fqid);
1105         if (ret) {
1106                 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d",
1107                         fqid, ret);
1108                 return -EINVAL;
1109         }
1110         /* "map" this Rx FQ to one of the interfaces Tx FQID */
1111         DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid);
1112         ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1113         if (ret) {
1114                 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d",
1115                         fqid, ret);
1116                 return ret;
1117         }
1118         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL;
1119         opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY;
1120         ret = qman_init_fq(fq, 0, &opts);
1121         if (ret)
1122                 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d",
1123                             fqid, ret);
1124         return ret;
1125 }
1126 #endif
1127
1128 /* Initialise a network interface */
1129 static int
1130 dpaa_dev_init(struct rte_eth_dev *eth_dev)
1131 {
1132         int num_cores, num_rx_fqs, fqid;
1133         int loop, ret = 0;
1134         int dev_id;
1135         struct rte_dpaa_device *dpaa_device;
1136         struct dpaa_if *dpaa_intf;
1137         struct fm_eth_port_cfg *cfg;
1138         struct fman_if *fman_intf;
1139         struct fman_if_bpool *bp, *tmp_bp;
1140         uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES];
1141
1142         PMD_INIT_FUNC_TRACE();
1143
1144         /* For secondary processes, the primary has done all the work */
1145         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1146                 return 0;
1147
1148         dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1149         dev_id = dpaa_device->id.dev_id;
1150         dpaa_intf = eth_dev->data->dev_private;
1151         cfg = &dpaa_netcfg->port_cfg[dev_id];
1152         fman_intf = cfg->fman_if;
1153
1154         dpaa_intf->name = dpaa_device->name;
1155
1156         /* save fman_if & cfg in the interface struture */
1157         dpaa_intf->fif = fman_intf;
1158         dpaa_intf->ifid = dev_id;
1159         dpaa_intf->cfg = cfg;
1160
1161         /* Initialize Rx FQ's */
1162         if (getenv("DPAA_NUM_RX_QUEUES"))
1163                 num_rx_fqs = atoi(getenv("DPAA_NUM_RX_QUEUES"));
1164         else
1165                 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1166
1167         /* if push mode queues to be enabled. Currenly we are allowing only
1168          * one queue per thread.
1169          */
1170         if (getenv("DPAA_PUSH_QUEUES_NUMBER")) {
1171                 dpaa_push_mode_max_queue =
1172                                 atoi(getenv("DPAA_PUSH_QUEUES_NUMBER"));
1173                 if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE)
1174                         dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE;
1175         }
1176
1177         /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX
1178          * queues.
1179          */
1180         if (num_rx_fqs <= 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) {
1181                 DPAA_PMD_ERR("Invalid number of RX queues\n");
1182                 return -EINVAL;
1183         }
1184
1185         dpaa_intf->rx_queues = rte_zmalloc(NULL,
1186                 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE);
1187         if (!dpaa_intf->rx_queues) {
1188                 DPAA_PMD_ERR("Failed to alloc mem for RX queues\n");
1189                 return -ENOMEM;
1190         }
1191
1192         /* If congestion control is enabled globally*/
1193         if (td_threshold) {
1194                 dpaa_intf->cgr_rx = rte_zmalloc(NULL,
1195                         sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE);
1196                 if (!dpaa_intf->cgr_rx) {
1197                         DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n");
1198                         ret = -ENOMEM;
1199                         goto free_rx;
1200                 }
1201
1202                 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0);
1203                 if (ret != num_rx_fqs) {
1204                         DPAA_PMD_WARN("insufficient CGRIDs available");
1205                         ret = -EINVAL;
1206                         goto free_rx;
1207                 }
1208         } else {
1209                 dpaa_intf->cgr_rx = NULL;
1210         }
1211
1212         for (loop = 0; loop < num_rx_fqs; loop++) {
1213                 fqid = DPAA_PCD_FQID_START + dpaa_intf->ifid *
1214                         DPAA_PCD_FQID_MULTIPLIER + loop;
1215
1216                 if (dpaa_intf->cgr_rx)
1217                         dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop];
1218
1219                 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop],
1220                         dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL,
1221                         fqid);
1222                 if (ret)
1223                         goto free_rx;
1224                 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf;
1225         }
1226         dpaa_intf->nb_rx_queues = num_rx_fqs;
1227
1228         /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */
1229         num_cores = rte_lcore_count();
1230         dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) *
1231                 num_cores, MAX_CACHELINE);
1232         if (!dpaa_intf->tx_queues) {
1233                 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n");
1234                 ret = -ENOMEM;
1235                 goto free_rx;
1236         }
1237
1238         for (loop = 0; loop < num_cores; loop++) {
1239                 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop],
1240                                          fman_intf);
1241                 if (ret)
1242                         goto free_tx;
1243                 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
1244         }
1245         dpaa_intf->nb_tx_queues = num_cores;
1246
1247 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1248         dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1249                 DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err);
1250         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf;
1251         dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1252                 DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err);
1253         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf;
1254 #endif
1255
1256         DPAA_PMD_DEBUG("All frame queues created");
1257
1258         /* Get the initial configuration for flow control */
1259         dpaa_fc_set_default(dpaa_intf);
1260
1261         /* reset bpool list, initialize bpool dynamically */
1262         list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) {
1263                 list_del(&bp->node);
1264                 free(bp);
1265         }
1266
1267         /* Populate ethdev structure */
1268         eth_dev->dev_ops = &dpaa_devops;
1269         eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1270         eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
1271
1272         /* Allocate memory for storing MAC addresses */
1273         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
1274                 ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0);
1275         if (eth_dev->data->mac_addrs == NULL) {
1276                 DPAA_PMD_ERR("Failed to allocate %d bytes needed to "
1277                                                 "store MAC addresses",
1278                                 ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER);
1279                 ret = -ENOMEM;
1280                 goto free_tx;
1281         }
1282
1283         /* copy the primary mac address */
1284         ether_addr_copy(&fman_intf->mac_addr, &eth_dev->data->mac_addrs[0]);
1285
1286         RTE_LOG(INFO, PMD, "net: dpaa: %s: %02x:%02x:%02x:%02x:%02x:%02x\n",
1287                 dpaa_device->name,
1288                 fman_intf->mac_addr.addr_bytes[0],
1289                 fman_intf->mac_addr.addr_bytes[1],
1290                 fman_intf->mac_addr.addr_bytes[2],
1291                 fman_intf->mac_addr.addr_bytes[3],
1292                 fman_intf->mac_addr.addr_bytes[4],
1293                 fman_intf->mac_addr.addr_bytes[5]);
1294
1295         /* Disable RX mode */
1296         fman_if_discard_rx_errors(fman_intf);
1297         fman_if_disable_rx(fman_intf);
1298         /* Disable promiscuous mode */
1299         fman_if_promiscuous_disable(fman_intf);
1300         /* Disable multicast */
1301         fman_if_reset_mcast_filter_table(fman_intf);
1302         /* Reset interface statistics */
1303         fman_if_stats_reset(fman_intf);
1304
1305         return 0;
1306
1307 free_tx:
1308         rte_free(dpaa_intf->tx_queues);
1309         dpaa_intf->tx_queues = NULL;
1310         dpaa_intf->nb_tx_queues = 0;
1311
1312 free_rx:
1313         rte_free(dpaa_intf->cgr_rx);
1314         rte_free(dpaa_intf->rx_queues);
1315         dpaa_intf->rx_queues = NULL;
1316         dpaa_intf->nb_rx_queues = 0;
1317         return ret;
1318 }
1319
1320 static int
1321 dpaa_dev_uninit(struct rte_eth_dev *dev)
1322 {
1323         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1324         int loop;
1325
1326         PMD_INIT_FUNC_TRACE();
1327
1328         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1329                 return -EPERM;
1330
1331         if (!dpaa_intf) {
1332                 DPAA_PMD_WARN("Already closed or not started");
1333                 return -1;
1334         }
1335
1336         dpaa_eth_dev_close(dev);
1337
1338         /* release configuration memory */
1339         if (dpaa_intf->fc_conf)
1340                 rte_free(dpaa_intf->fc_conf);
1341
1342         /* Release RX congestion Groups */
1343         if (dpaa_intf->cgr_rx) {
1344                 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++)
1345                         qman_delete_cgr(&dpaa_intf->cgr_rx[loop]);
1346
1347                 qman_release_cgrid_range(dpaa_intf->cgr_rx[loop].cgrid,
1348                                          dpaa_intf->nb_rx_queues);
1349         }
1350
1351         rte_free(dpaa_intf->cgr_rx);
1352         dpaa_intf->cgr_rx = NULL;
1353
1354         rte_free(dpaa_intf->rx_queues);
1355         dpaa_intf->rx_queues = NULL;
1356
1357         rte_free(dpaa_intf->tx_queues);
1358         dpaa_intf->tx_queues = NULL;
1359
1360         /* free memory for storing MAC addresses */
1361         rte_free(dev->data->mac_addrs);
1362         dev->data->mac_addrs = NULL;
1363
1364         dev->dev_ops = NULL;
1365         dev->rx_pkt_burst = NULL;
1366         dev->tx_pkt_burst = NULL;
1367
1368         return 0;
1369 }
1370
1371 static int
1372 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv,
1373                struct rte_dpaa_device *dpaa_dev)
1374 {
1375         int diag;
1376         int ret;
1377         struct rte_eth_dev *eth_dev;
1378
1379         PMD_INIT_FUNC_TRACE();
1380
1381         /* In case of secondary process, the device is already configured
1382          * and no further action is required, except portal initialization
1383          * and verifying secondary attachment to port name.
1384          */
1385         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1386                 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
1387                 if (!eth_dev)
1388                         return -ENOMEM;
1389                 return 0;
1390         }
1391
1392         if (!is_global_init) {
1393                 /* One time load of Qman/Bman drivers */
1394                 ret = qman_global_init();
1395                 if (ret) {
1396                         DPAA_PMD_ERR("QMAN initialization failed: %d",
1397                                      ret);
1398                         return ret;
1399                 }
1400                 ret = bman_global_init();
1401                 if (ret) {
1402                         DPAA_PMD_ERR("BMAN initialization failed: %d",
1403                                      ret);
1404                         return ret;
1405                 }
1406
1407                 is_global_init = 1;
1408         }
1409
1410         if (unlikely(!RTE_PER_LCORE(dpaa_io))) {
1411                 ret = rte_dpaa_portal_init((void *)1);
1412                 if (ret) {
1413                         DPAA_PMD_ERR("Unable to initialize portal");
1414                         return ret;
1415                 }
1416         }
1417
1418         eth_dev = rte_eth_dev_allocate(dpaa_dev->name);
1419         if (eth_dev == NULL)
1420                 return -ENOMEM;
1421
1422         eth_dev->data->dev_private = rte_zmalloc(
1423                                         "ethdev private structure",
1424                                         sizeof(struct dpaa_if),
1425                                         RTE_CACHE_LINE_SIZE);
1426         if (!eth_dev->data->dev_private) {
1427                 DPAA_PMD_ERR("Cannot allocate memzone for port data");
1428                 rte_eth_dev_release_port(eth_dev);
1429                 return -ENOMEM;
1430         }
1431
1432         eth_dev->device = &dpaa_dev->device;
1433         eth_dev->device->driver = &dpaa_drv->driver;
1434         dpaa_dev->eth_dev = eth_dev;
1435
1436         /* Invoke PMD device initialization function */
1437         diag = dpaa_dev_init(eth_dev);
1438         if (diag == 0)
1439                 return 0;
1440
1441         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
1442                 rte_free(eth_dev->data->dev_private);
1443
1444         rte_eth_dev_release_port(eth_dev);
1445         return diag;
1446 }
1447
1448 static int
1449 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev)
1450 {
1451         struct rte_eth_dev *eth_dev;
1452
1453         PMD_INIT_FUNC_TRACE();
1454
1455         eth_dev = dpaa_dev->eth_dev;
1456         dpaa_dev_uninit(eth_dev);
1457
1458         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
1459                 rte_free(eth_dev->data->dev_private);
1460
1461         rte_eth_dev_release_port(eth_dev);
1462
1463         return 0;
1464 }
1465
1466 static struct rte_dpaa_driver rte_dpaa_pmd = {
1467         .drv_type = FSL_DPAA_ETH,
1468         .probe = rte_dpaa_probe,
1469         .remove = rte_dpaa_remove,
1470 };
1471
1472 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd);