drivers/net/dpaa/dpaa_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2017 NXP
   5  *
   6  */
   7 /* System headers */
   8 #include <stdio.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <limits.h>
  12 #include <sched.h>
  13 #include <signal.h>
  14 #include <pthread.h>
  15 #include <sys/types.h>
  16 #include <sys/syscall.h>
  17
  18 #include <rte_byteorder.h>
  19 #include <rte_common.h>
  20 #include <rte_interrupts.h>
  21 #include <rte_log.h>
  22 #include <rte_debug.h>
  23 #include <rte_pci.h>
  24 #include <rte_atomic.h>
  25 #include <rte_branch_prediction.h>
  26 #include <rte_memory.h>
  27 #include <rte_tailq.h>
  28 #include <rte_eal.h>
  29 #include <rte_alarm.h>
  30 #include <rte_ether.h>
  31 #include <rte_ethdev_driver.h>
  32 #include <rte_malloc.h>
  33 #include <rte_ring.h>
  34
  35 #include <rte_dpaa_bus.h>
  36 #include <rte_dpaa_logs.h>
  37 #include <dpaa_mempool.h>
  38
  39 #include <dpaa_ethdev.h>
  40 #include <dpaa_rxtx.h>
  41 #include <rte_pmd_dpaa.h>
  42
  43 #include <fsl_usd.h>
  44 #include <fsl_qman.h>
  45 #include <fsl_bman.h>
  46 #include <fsl_fman.h>
  47
  48 /* Supported Rx offloads */
  49 static uint64_t dev_rx_offloads_sup =
  50                 DEV_RX_OFFLOAD_JUMBO_FRAME |
  51                 DEV_RX_OFFLOAD_SCATTER;
  52
  53 /* Rx offloads which cannot be disabled */
  54 static uint64_t dev_rx_offloads_nodis =
  55                 DEV_RX_OFFLOAD_IPV4_CKSUM |
  56                 DEV_RX_OFFLOAD_UDP_CKSUM |
  57                 DEV_RX_OFFLOAD_TCP_CKSUM |
  58                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
  59
  60 /* Supported Tx offloads */
  61 static uint64_t dev_tx_offloads_sup;
  62
  63 /* Tx offloads which cannot be disabled */
  64 static uint64_t dev_tx_offloads_nodis =
  65                 DEV_TX_OFFLOAD_IPV4_CKSUM |
  66                 DEV_TX_OFFLOAD_UDP_CKSUM |
  67                 DEV_TX_OFFLOAD_TCP_CKSUM |
  68                 DEV_TX_OFFLOAD_SCTP_CKSUM |
  69                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
  70                 DEV_TX_OFFLOAD_MULTI_SEGS |
  71                 DEV_TX_OFFLOAD_MT_LOCKFREE |
  72                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
  73
  74 /* Keep track of whether QMAN and BMAN have been globally initialized */
  75 static int is_global_init;
  76 static int default_q;   /* use default queue - FMC is not executed*/
  77 /* At present we only allow up to 4 push mode queues as default - as each of
  78  * this queue need dedicated portal and we are short of portals.
  79  */
  80 #define DPAA_MAX_PUSH_MODE_QUEUE       8
  81 #define DPAA_DEFAULT_PUSH_MODE_QUEUE   4
  82
  83 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE;
  84 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/
  85
  86
  87 /* Per FQ Taildrop in frame count */
  88 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH;
  89
  90 struct rte_dpaa_xstats_name_off {
  91         char name[RTE_ETH_XSTATS_NAME_SIZE];
  92         uint32_t offset;
  93 };
  94
  95 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = {
  96         {"rx_align_err",
  97                 offsetof(struct dpaa_if_stats, raln)},
  98         {"rx_valid_pause",
  99                 offsetof(struct dpaa_if_stats, rxpf)},
 100         {"rx_fcs_err",
 101                 offsetof(struct dpaa_if_stats, rfcs)},
 102         {"rx_vlan_frame",
 103                 offsetof(struct dpaa_if_stats, rvlan)},
 104         {"rx_frame_err",
 105                 offsetof(struct dpaa_if_stats, rerr)},
 106         {"rx_drop_err",
 107                 offsetof(struct dpaa_if_stats, rdrp)},
 108         {"rx_undersized",
 109                 offsetof(struct dpaa_if_stats, rund)},
 110         {"rx_oversize_err",
 111                 offsetof(struct dpaa_if_stats, rovr)},
 112         {"rx_fragment_pkt",
 113                 offsetof(struct dpaa_if_stats, rfrg)},
 114         {"tx_valid_pause",
 115                 offsetof(struct dpaa_if_stats, txpf)},
 116         {"tx_fcs_err",
 117                 offsetof(struct dpaa_if_stats, terr)},
 118         {"tx_vlan_frame",
 119                 offsetof(struct dpaa_if_stats, tvlan)},
 120         {"rx_undersized",
 121                 offsetof(struct dpaa_if_stats, tund)},
 122 };
 123
 124 static struct rte_dpaa_driver rte_dpaa_pmd;
 125
 126 static void
 127 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info);
 128
 129 static inline void
 130 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts)
 131 {
 132         memset(opts, 0, sizeof(struct qm_mcc_initfq));
 133         opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
 134         opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING |
 135                            QM_FQCTRL_PREFERINCACHE;
 136         opts->fqd.context_a.stashing.exclusive = 0;
 137         if (dpaa_svr_family != SVR_LS1046A_FAMILY)
 138                 opts->fqd.context_a.stashing.annotation_cl =
 139                                                 DPAA_IF_RX_ANNOTATION_STASH;
 140         opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
 141         opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH;
 142 }
 143
 144 static int
 145 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 146 {
 147         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 148         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN
 149                                 + VLAN_TAG_SIZE;
 150         uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
 151
 152         PMD_INIT_FUNC_TRACE();
 153
 154         if (mtu < ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN)
 155                 return -EINVAL;
 156         /*
 157          * Refuse mtu that requires the support of scattered packets
 158          * when this feature has not been enabled before.
 159          */
 160         if (dev->data->min_rx_buf_size &&
 161                 !dev->data->scattered_rx && frame_size > buffsz) {
 162                 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer");
 163                 return -EINVAL;
 164         }
 165
 166         /* check <seg size> * <max_seg>  >= max_frame */
 167         if (dev->data->min_rx_buf_size && dev->data->scattered_rx &&
 168                 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) {
 169                 DPAA_PMD_ERR("Too big to fit for Max SG list %d",
 170                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 171                 return -EINVAL;
 172         }
 173
 174         if (frame_size > ETHER_MAX_LEN)
 175                 dev->data->dev_conf.rxmode.offloads &=
 176                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 177         else
 178                 dev->data->dev_conf.rxmode.offloads &=
 179                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 180
 181         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 182
 183         fman_if_set_maxfrm(dpaa_intf->fif, frame_size);
 184
 185         return 0;
 186 }
 187
 188 static int
 189 dpaa_eth_dev_configure(struct rte_eth_dev *dev)
 190 {
 191         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 192         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 193         uint64_t rx_offloads = eth_conf->rxmode.offloads;
 194         uint64_t tx_offloads = eth_conf->txmode.offloads;
 195
 196         PMD_INIT_FUNC_TRACE();
 197
 198         /* Rx offloads validation */
 199         if (dev_rx_offloads_nodis & ~rx_offloads) {
 200                 DPAA_PMD_WARN(
 201                 "Rx offloads non configurable - requested 0x%" PRIx64
 202                 " ignored 0x%" PRIx64,
 203                         rx_offloads, dev_rx_offloads_nodis);
 204         }
 205
 206         /* Tx offloads validation */
 207         if (dev_tx_offloads_nodis & ~tx_offloads) {
 208                 DPAA_PMD_WARN(
 209                 "Tx offloads non configurable - requested 0x%" PRIx64
 210                 " ignored 0x%" PRIx64,
 211                         tx_offloads, dev_tx_offloads_nodis);
 212         }
 213
 214         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 215                 uint32_t max_len;
 216
 217                 DPAA_PMD_DEBUG("enabling jumbo");
 218
 219                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
 220                     DPAA_MAX_RX_PKT_LEN)
 221                         max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
 222                 else {
 223                         DPAA_PMD_INFO("enabling jumbo override conf max len=%d "
 224                                 "supported is %d",
 225                                 dev->data->dev_conf.rxmode.max_rx_pkt_len,
 226                                 DPAA_MAX_RX_PKT_LEN);
 227                         max_len = DPAA_MAX_RX_PKT_LEN;
 228                 }
 229
 230                 fman_if_set_maxfrm(dpaa_intf->fif, max_len);
 231                 dev->data->mtu = max_len
 232                                 - ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE;
 233         }
 234
 235         if (rx_offloads & DEV_RX_OFFLOAD_SCATTER) {
 236                 DPAA_PMD_DEBUG("enabling scatter mode");
 237                 fman_if_set_sg(dpaa_intf->fif, 1);
 238                 dev->data->scattered_rx = 1;
 239         }
 240
 241         return 0;
 242 }
 243
 244 static const uint32_t *
 245 dpaa_supported_ptypes_get(struct rte_eth_dev *dev)
 246 {
 247         static const uint32_t ptypes[] = {
 248                 /*todo -= add more types */
 249                 RTE_PTYPE_L2_ETHER,
 250                 RTE_PTYPE_L3_IPV4,
 251                 RTE_PTYPE_L3_IPV4_EXT,
 252                 RTE_PTYPE_L3_IPV6,
 253                 RTE_PTYPE_L3_IPV6_EXT,
 254                 RTE_PTYPE_L4_TCP,
 255                 RTE_PTYPE_L4_UDP,
 256                 RTE_PTYPE_L4_SCTP
 257         };
 258
 259         PMD_INIT_FUNC_TRACE();
 260
 261         if (dev->rx_pkt_burst == dpaa_eth_queue_rx)
 262                 return ptypes;
 263         return NULL;
 264 }
 265
 266 static int dpaa_eth_dev_start(struct rte_eth_dev *dev)
 267 {
 268         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 269
 270         PMD_INIT_FUNC_TRACE();
 271
 272         /* Change tx callback to the real one */
 273         dev->tx_pkt_burst = dpaa_eth_queue_tx;
 274         fman_if_enable_rx(dpaa_intf->fif);
 275
 276         return 0;
 277 }
 278
 279 static void dpaa_eth_dev_stop(struct rte_eth_dev *dev)
 280 {
 281         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 282
 283         PMD_INIT_FUNC_TRACE();
 284
 285         fman_if_disable_rx(dpaa_intf->fif);
 286         dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
 287 }
 288
 289 static void dpaa_eth_dev_close(struct rte_eth_dev *dev)
 290 {
 291         PMD_INIT_FUNC_TRACE();
 292
 293         dpaa_eth_dev_stop(dev);
 294 }
 295
 296 static int
 297 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused,
 298                      char *fw_version,
 299                      size_t fw_size)
 300 {
 301         int ret;
 302         FILE *svr_file = NULL;
 303         unsigned int svr_ver = 0;
 304
 305         PMD_INIT_FUNC_TRACE();
 306
 307         svr_file = fopen(DPAA_SOC_ID_FILE, "r");
 308         if (!svr_file) {
 309                 DPAA_PMD_ERR("Unable to open SoC device");
 310                 return -ENOTSUP; /* Not supported on this infra */
 311         }
 312         if (fscanf(svr_file, "svr:%x", &svr_ver) > 0)
 313                 dpaa_svr_family = svr_ver & SVR_MASK;
 314         else
 315                 DPAA_PMD_ERR("Unable to read SoC device");
 316
 317         fclose(svr_file);
 318
 319         ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x",
 320                        svr_ver, fman_ip_rev);
 321         ret += 1; /* add the size of '\0' */
 322
 323         if (fw_size < (uint32_t)ret)
 324                 return ret;
 325         else
 326                 return 0;
 327 }
 328
 329 static void dpaa_eth_dev_info(struct rte_eth_dev *dev,
 330                               struct rte_eth_dev_info *dev_info)
 331 {
 332         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 333
 334         PMD_INIT_FUNC_TRACE();
 335
 336         dev_info->max_rx_queues = dpaa_intf->nb_rx_queues;
 337         dev_info->max_tx_queues = dpaa_intf->nb_tx_queues;
 338         dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
 339         dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER;
 340         dev_info->max_hash_mac_addrs = 0;
 341         dev_info->max_vfs = 0;
 342         dev_info->max_vmdq_pools = ETH_16_POOLS;
 343         dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL;
 344         dev_info->speed_capa = (ETH_LINK_SPEED_1G |
 345                                 ETH_LINK_SPEED_10G);
 346         dev_info->rx_offload_capa = dev_rx_offloads_sup |
 347                                         dev_rx_offloads_nodis;
 348         dev_info->tx_offload_capa = dev_tx_offloads_sup |
 349                                         dev_tx_offloads_nodis;
 350         dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE;
 351         dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE;
 352 }
 353
 354 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
 355                                 int wait_to_complete __rte_unused)
 356 {
 357         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 358         struct rte_eth_link *link = &dev->data->dev_link;
 359
 360         PMD_INIT_FUNC_TRACE();
 361
 362         if (dpaa_intf->fif->mac_type == fman_mac_1g)
 363                 link->link_speed = ETH_SPEED_NUM_1G;
 364         else if (dpaa_intf->fif->mac_type == fman_mac_10g)
 365                 link->link_speed = ETH_SPEED_NUM_10G;
 366         else
 367                 DPAA_PMD_ERR("invalid link_speed: %s, %d",
 368                              dpaa_intf->name, dpaa_intf->fif->mac_type);
 369
 370         link->link_status = dpaa_intf->valid;
 371         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 372         link->link_autoneg = ETH_LINK_AUTONEG;
 373         return 0;
 374 }
 375
 376 static int dpaa_eth_stats_get(struct rte_eth_dev *dev,
 377                                struct rte_eth_stats *stats)
 378 {
 379         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 380
 381         PMD_INIT_FUNC_TRACE();
 382
 383         fman_if_stats_get(dpaa_intf->fif, stats);
 384         return 0;
 385 }
 386
 387 static void dpaa_eth_stats_reset(struct rte_eth_dev *dev)
 388 {
 389         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 390
 391         PMD_INIT_FUNC_TRACE();
 392
 393         fman_if_stats_reset(dpaa_intf->fif);
 394 }
 395
 396 static int
 397 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
 398                     unsigned int n)
 399 {
 400         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 401         unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings);
 402         uint64_t values[sizeof(struct dpaa_if_stats) / 8];
 403
 404         if (n < num)
 405                 return num;
 406
 407         if (xstats == NULL)
 408                 return 0;
 409
 410         fman_if_stats_get_all(dpaa_intf->fif, values,
 411                               sizeof(struct dpaa_if_stats) / 8);
 412
 413         for (i = 0; i < num; i++) {
 414                 xstats[i].id = i;
 415                 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8];
 416         }
 417         return i;
 418 }
 419
 420 static int
 421 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 422                       struct rte_eth_xstat_name *xstats_names,
 423                       unsigned int limit)
 424 {
 425         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 426
 427         if (limit < stat_cnt)
 428                 return stat_cnt;
 429
 430         if (xstats_names != NULL)
 431                 for (i = 0; i < stat_cnt; i++)
 432                         snprintf(xstats_names[i].name,
 433                                  sizeof(xstats_names[i].name),
 434                                  "%s",
 435                                  dpaa_xstats_strings[i].name);
 436
 437         return stat_cnt;
 438 }
 439
 440 static int
 441 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 442                       uint64_t *values, unsigned int n)
 443 {
 444         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 445         uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8];
 446
 447         if (!ids) {
 448                 struct dpaa_if *dpaa_intf = dev->data->dev_private;
 449
 450                 if (n < stat_cnt)
 451                         return stat_cnt;
 452
 453                 if (!values)
 454                         return 0;
 455
 456                 fman_if_stats_get_all(dpaa_intf->fif, values_copy,
 457                                       sizeof(struct dpaa_if_stats) / 8);
 458
 459                 for (i = 0; i < stat_cnt; i++)
 460                         values[i] =
 461                                 values_copy[dpaa_xstats_strings[i].offset / 8];
 462
 463                 return stat_cnt;
 464         }
 465
 466         dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
 467
 468         for (i = 0; i < n; i++) {
 469                 if (ids[i] >= stat_cnt) {
 470                         DPAA_PMD_ERR("id value isn't valid");
 471                         return -1;
 472                 }
 473                 values[i] = values_copy[ids[i]];
 474         }
 475         return n;
 476 }
 477
 478 static int
 479 dpaa_xstats_get_names_by_id(
 480         struct rte_eth_dev *dev,
 481         struct rte_eth_xstat_name *xstats_names,
 482         const uint64_t *ids,
 483         unsigned int limit)
 484 {
 485         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 486         struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
 487
 488         if (!ids)
 489                 return dpaa_xstats_get_names(dev, xstats_names, limit);
 490
 491         dpaa_xstats_get_names(dev, xstats_names_copy, limit);
 492
 493         for (i = 0; i < limit; i++) {
 494                 if (ids[i] >= stat_cnt) {
 495                         DPAA_PMD_ERR("id value isn't valid");
 496                         return -1;
 497                 }
 498                 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
 499         }
 500         return limit;
 501 }
 502
 503 static void dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev)
 504 {
 505         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 506
 507         PMD_INIT_FUNC_TRACE();
 508
 509         fman_if_promiscuous_enable(dpaa_intf->fif);
 510 }
 511
 512 static void dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev)
 513 {
 514         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 515
 516         PMD_INIT_FUNC_TRACE();
 517
 518         fman_if_promiscuous_disable(dpaa_intf->fif);
 519 }
 520
 521 static void dpaa_eth_multicast_enable(struct rte_eth_dev *dev)
 522 {
 523         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 524
 525         PMD_INIT_FUNC_TRACE();
 526
 527         fman_if_set_mcast_filter_table(dpaa_intf->fif);
 528 }
 529
 530 static void dpaa_eth_multicast_disable(struct rte_eth_dev *dev)
 531 {
 532         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 533
 534         PMD_INIT_FUNC_TRACE();
 535
 536         fman_if_reset_mcast_filter_table(dpaa_intf->fif);
 537 }
 538
 539 static
 540 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 541                             uint16_t nb_desc,
 542                             unsigned int socket_id __rte_unused,
 543                             const struct rte_eth_rxconf *rx_conf __rte_unused,
 544                             struct rte_mempool *mp)
 545 {
 546         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 547         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx];
 548         struct qm_mcc_initfq opts = {0};
 549         u32 flags = 0;
 550         int ret;
 551         u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
 552
 553         PMD_INIT_FUNC_TRACE();
 554
 555         if (queue_idx >= dev->data->nb_rx_queues) {
 556                 rte_errno = EOVERFLOW;
 557                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
 558                       (void *)dev, queue_idx, dev->data->nb_rx_queues);
 559                 return -rte_errno;
 560         }
 561
 562         DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)",
 563                         queue_idx, rxq->fqid);
 564
 565         /* Max packet can fit in single buffer */
 566         if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= buffsz) {
 567                 ;
 568         } else if (dev->data->dev_conf.rxmode.offloads &
 569                         DEV_RX_OFFLOAD_SCATTER) {
 570                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len >
 571                         buffsz * DPAA_SGT_MAX_ENTRIES) {
 572                         DPAA_PMD_ERR("max RxPkt size %d too big to fit "
 573                                 "MaxSGlist %d",
 574                                 dev->data->dev_conf.rxmode.max_rx_pkt_len,
 575                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 576                         rte_errno = EOVERFLOW;
 577                         return -rte_errno;
 578                 }
 579         } else {
 580                 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is"
 581                      " larger than a single mbuf (%u) and scattered"
 582                      " mode has not been requested",
 583                      dev->data->dev_conf.rxmode.max_rx_pkt_len,
 584                      buffsz - RTE_PKTMBUF_HEADROOM);
 585         }
 586
 587         if (!dpaa_intf->bp_info || dpaa_intf->bp_info->mp != mp) {
 588                 struct fman_if_ic_params icp;
 589                 uint32_t fd_offset;
 590                 uint32_t bp_size;
 591
 592                 if (!mp->pool_data) {
 593                         DPAA_PMD_ERR("Not an offloaded buffer pool!");
 594                         return -1;
 595                 }
 596                 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
 597
 598                 memset(&icp, 0, sizeof(icp));
 599                 /* set ICEOF for to the default value , which is 0*/
 600                 icp.iciof = DEFAULT_ICIOF;
 601                 icp.iceof = DEFAULT_RX_ICEOF;
 602                 icp.icsz = DEFAULT_ICSZ;
 603                 fman_if_set_ic_params(dpaa_intf->fif, &icp);
 604
 605                 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE;
 606                 fman_if_set_fdoff(dpaa_intf->fif, fd_offset);
 607
 608                 /* Buffer pool size should be equal to Dataroom Size*/
 609                 bp_size = rte_pktmbuf_data_room_size(mp);
 610                 fman_if_set_bp(dpaa_intf->fif, mp->size,
 611                                dpaa_intf->bp_info->bpid, bp_size);
 612                 dpaa_intf->valid = 1;
 613                 DPAA_PMD_INFO("if =%s - fd_offset = %d offset = %d",
 614                             dpaa_intf->name, fd_offset,
 615                         fman_if_get_fdoff(dpaa_intf->fif));
 616         }
 617         DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name,
 618                 fman_if_get_sg_enable(dpaa_intf->fif),
 619                 dev->data->dev_conf.rxmode.max_rx_pkt_len);
 620         /* checking if push mode only, no error check for now */
 621         if (dpaa_push_mode_max_queue > dpaa_push_queue_idx) {
 622                 dpaa_push_queue_idx++;
 623                 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
 624                 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK |
 625                                    QM_FQCTRL_CTXASTASHING |
 626                                    QM_FQCTRL_PREFERINCACHE;
 627                 opts.fqd.context_a.stashing.exclusive = 0;
 628                 /* In muticore scenario stashing becomes a bottleneck on LS1046.
 629                  * So do not enable stashing in this case
 630                  */
 631                 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
 632                         opts.fqd.context_a.stashing.annotation_cl =
 633                                                 DPAA_IF_RX_ANNOTATION_STASH;
 634                 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
 635                 opts.fqd.context_a.stashing.context_cl =
 636                                                 DPAA_IF_RX_CONTEXT_STASH;
 637
 638                 /*Create a channel and associate given queue with the channel*/
 639                 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0);
 640                 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
 641                 opts.fqd.dest.channel = rxq->ch_id;
 642                 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY;
 643                 flags = QMAN_INITFQ_FLAG_SCHED;
 644
 645                 /* Configure tail drop */
 646                 if (dpaa_intf->cgr_rx) {
 647                         opts.we_mask |= QM_INITFQ_WE_CGID;
 648                         opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid;
 649                         opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 650                 }
 651                 ret = qman_init_fq(rxq, flags, &opts);
 652                 if (ret) {
 653                         DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x "
 654                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
 655                         return ret;
 656                 }
 657                 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb;
 658                 rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare;
 659                 rxq->is_static = true;
 660         }
 661         dev->data->rx_queues[queue_idx] = rxq;
 662
 663         /* configure the CGR size as per the desc size */
 664         if (dpaa_intf->cgr_rx) {
 665                 struct qm_mcc_initcgr cgr_opts = {0};
 666
 667                 /* Enable tail drop with cgr on this queue */
 668                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0);
 669                 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts);
 670                 if (ret) {
 671                         DPAA_PMD_WARN(
 672                                 "rx taildrop modify fail on fqid %d (ret=%d)",
 673                                 rxq->fqid, ret);
 674                 }
 675         }
 676
 677         return 0;
 678 }
 679
 680 int
 681 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
 682                 int eth_rx_queue_id,
 683                 u16 ch_id,
 684                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
 685 {
 686         int ret;
 687         u32 flags = 0;
 688         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 689         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
 690         struct qm_mcc_initfq opts = {0};
 691
 692         if (dpaa_push_mode_max_queue)
 693                 DPAA_PMD_WARN("PUSH mode already enabled for first %d queues.\n"
 694                               "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n",
 695                               dpaa_push_mode_max_queue);
 696
 697         dpaa_poll_queue_default_config(&opts);
 698
 699         switch (queue_conf->ev.sched_type) {
 700         case RTE_SCHED_TYPE_ATOMIC:
 701                 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE;
 702                 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary
 703                  * configuration with HOLD_ACTIVE setting
 704                  */
 705                 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK);
 706                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic;
 707                 break;
 708         case RTE_SCHED_TYPE_ORDERED:
 709                 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n");
 710                 return -1;
 711         default:
 712                 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK;
 713                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel;
 714                 break;
 715         }
 716
 717         opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
 718         opts.fqd.dest.channel = ch_id;
 719         opts.fqd.dest.wq = queue_conf->ev.priority;
 720
 721         if (dpaa_intf->cgr_rx) {
 722                 opts.we_mask |= QM_INITFQ_WE_CGID;
 723                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
 724                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 725         }
 726
 727         flags = QMAN_INITFQ_FLAG_SCHED;
 728
 729         ret = qman_init_fq(rxq, flags, &opts);
 730         if (ret) {
 731                 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x "
 732                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
 733                 return ret;
 734         }
 735
 736         /* copy configuration which needs to be filled during dequeue */
 737         memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event));
 738         dev->data->rx_queues[eth_rx_queue_id] = rxq;
 739
 740         return ret;
 741 }
 742
 743 int
 744 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
 745                 int eth_rx_queue_id)
 746 {
 747         struct qm_mcc_initfq opts;
 748         int ret;
 749         u32 flags = 0;
 750         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 751         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
 752
 753         dpaa_poll_queue_default_config(&opts);
 754
 755         if (dpaa_intf->cgr_rx) {
 756                 opts.we_mask |= QM_INITFQ_WE_CGID;
 757                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
 758                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 759         }
 760
 761         ret = qman_init_fq(rxq, flags, &opts);
 762         if (ret) {
 763                 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d",
 764                              rxq->fqid, ret);
 765         }
 766
 767         rxq->cb.dqrr_dpdk_cb = NULL;
 768         dev->data->rx_queues[eth_rx_queue_id] = NULL;
 769
 770         return 0;
 771 }
 772
 773 static
 774 void dpaa_eth_rx_queue_release(void *rxq __rte_unused)
 775 {
 776         PMD_INIT_FUNC_TRACE();
 777 }
 778
 779 static
 780 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 781                             uint16_t nb_desc __rte_unused,
 782                 unsigned int socket_id __rte_unused,
 783                 const struct rte_eth_txconf *tx_conf __rte_unused)
 784 {
 785         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 786
 787         PMD_INIT_FUNC_TRACE();
 788
 789         if (queue_idx >= dev->data->nb_tx_queues) {
 790                 rte_errno = EOVERFLOW;
 791                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
 792                       (void *)dev, queue_idx, dev->data->nb_tx_queues);
 793                 return -rte_errno;
 794         }
 795
 796         DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)",
 797                         queue_idx, dpaa_intf->tx_queues[queue_idx].fqid);
 798         dev->data->tx_queues[queue_idx] = &dpaa_intf->tx_queues[queue_idx];
 799         return 0;
 800 }
 801
 802 static void dpaa_eth_tx_queue_release(void *txq __rte_unused)
 803 {
 804         PMD_INIT_FUNC_TRACE();
 805 }
 806
 807 static uint32_t
 808 dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 809 {
 810         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 811         struct qman_fq *rxq = &dpaa_intf->rx_queues[rx_queue_id];
 812         u32 frm_cnt = 0;
 813
 814         PMD_INIT_FUNC_TRACE();
 815
 816         if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) {
 817                 RTE_LOG(DEBUG, PMD, "RX frame count for q(%d) is %u\n",
 818                         rx_queue_id, frm_cnt);
 819         }
 820         return frm_cnt;
 821 }
 822
 823 static int dpaa_link_down(struct rte_eth_dev *dev)
 824 {
 825         PMD_INIT_FUNC_TRACE();
 826
 827         dpaa_eth_dev_stop(dev);
 828         return 0;
 829 }
 830
 831 static int dpaa_link_up(struct rte_eth_dev *dev)
 832 {
 833         PMD_INIT_FUNC_TRACE();
 834
 835         dpaa_eth_dev_start(dev);
 836         return 0;
 837 }
 838
 839 static int
 840 dpaa_flow_ctrl_set(struct rte_eth_dev *dev,
 841                    struct rte_eth_fc_conf *fc_conf)
 842 {
 843         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 844         struct rte_eth_fc_conf *net_fc;
 845
 846         PMD_INIT_FUNC_TRACE();
 847
 848         if (!(dpaa_intf->fc_conf)) {
 849                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
 850                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
 851                 if (!dpaa_intf->fc_conf) {
 852                         DPAA_PMD_ERR("unable to save flow control info");
 853                         return -ENOMEM;
 854                 }
 855         }
 856         net_fc = dpaa_intf->fc_conf;
 857
 858         if (fc_conf->high_water < fc_conf->low_water) {
 859                 DPAA_PMD_ERR("Incorrect Flow Control Configuration");
 860                 return -EINVAL;
 861         }
 862
 863         if (fc_conf->mode == RTE_FC_NONE) {
 864                 return 0;
 865         } else if (fc_conf->mode == RTE_FC_TX_PAUSE ||
 866                  fc_conf->mode == RTE_FC_FULL) {
 867                 fman_if_set_fc_threshold(dpaa_intf->fif, fc_conf->high_water,
 868                                          fc_conf->low_water,
 869                                 dpaa_intf->bp_info->bpid);
 870                 if (fc_conf->pause_time)
 871                         fman_if_set_fc_quanta(dpaa_intf->fif,
 872                                               fc_conf->pause_time);
 873         }
 874
 875         /* Save the information in dpaa device */
 876         net_fc->pause_time = fc_conf->pause_time;
 877         net_fc->high_water = fc_conf->high_water;
 878         net_fc->low_water = fc_conf->low_water;
 879         net_fc->send_xon = fc_conf->send_xon;
 880         net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
 881         net_fc->mode = fc_conf->mode;
 882         net_fc->autoneg = fc_conf->autoneg;
 883
 884         return 0;
 885 }
 886
 887 static int
 888 dpaa_flow_ctrl_get(struct rte_eth_dev *dev,
 889                    struct rte_eth_fc_conf *fc_conf)
 890 {
 891         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 892         struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf;
 893         int ret;
 894
 895         PMD_INIT_FUNC_TRACE();
 896
 897         if (net_fc) {
 898                 fc_conf->pause_time = net_fc->pause_time;
 899                 fc_conf->high_water = net_fc->high_water;
 900                 fc_conf->low_water = net_fc->low_water;
 901                 fc_conf->send_xon = net_fc->send_xon;
 902                 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd;
 903                 fc_conf->mode = net_fc->mode;
 904                 fc_conf->autoneg = net_fc->autoneg;
 905                 return 0;
 906         }
 907         ret = fman_if_get_fc_threshold(dpaa_intf->fif);
 908         if (ret) {
 909                 fc_conf->mode = RTE_FC_TX_PAUSE;
 910                 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif);
 911         } else {
 912                 fc_conf->mode = RTE_FC_NONE;
 913         }
 914
 915         return 0;
 916 }
 917
 918 static int
 919 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev,
 920                              struct ether_addr *addr,
 921                              uint32_t index,
 922                              __rte_unused uint32_t pool)
 923 {
 924         int ret;
 925         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 926
 927         PMD_INIT_FUNC_TRACE();
 928
 929         ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, index);
 930
 931         if (ret)
 932                 RTE_LOG(ERR, PMD, "error: Adding the MAC ADDR failed:"
 933                         " err = %d", ret);
 934         return 0;
 935 }
 936
 937 static void
 938 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev,
 939                           uint32_t index)
 940 {
 941         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 942
 943         PMD_INIT_FUNC_TRACE();
 944
 945         fman_if_clear_mac_addr(dpaa_intf->fif, index);
 946 }
 947
 948 static int
 949 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev,
 950                        struct ether_addr *addr)
 951 {
 952         int ret;
 953         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 954
 955         PMD_INIT_FUNC_TRACE();
 956
 957         ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, 0);
 958         if (ret)
 959                 RTE_LOG(ERR, PMD, "error: Setting the MAC ADDR failed %d", ret);
 960
 961         return ret;
 962 }
 963
 964 static struct eth_dev_ops dpaa_devops = {
 965         .dev_configure            = dpaa_eth_dev_configure,
 966         .dev_start                = dpaa_eth_dev_start,
 967         .dev_stop                 = dpaa_eth_dev_stop,
 968         .dev_close                = dpaa_eth_dev_close,
 969         .dev_infos_get            = dpaa_eth_dev_info,
 970         .dev_supported_ptypes_get = dpaa_supported_ptypes_get,
 971
 972         .rx_queue_setup           = dpaa_eth_rx_queue_setup,
 973         .tx_queue_setup           = dpaa_eth_tx_queue_setup,
 974         .rx_queue_release         = dpaa_eth_rx_queue_release,
 975         .tx_queue_release         = dpaa_eth_tx_queue_release,
 976         .rx_queue_count           = dpaa_dev_rx_queue_count,
 977
 978         .flow_ctrl_get            = dpaa_flow_ctrl_get,
 979         .flow_ctrl_set            = dpaa_flow_ctrl_set,
 980
 981         .link_update              = dpaa_eth_link_update,
 982         .stats_get                = dpaa_eth_stats_get,
 983         .xstats_get               = dpaa_dev_xstats_get,
 984         .xstats_get_by_id         = dpaa_xstats_get_by_id,
 985         .xstats_get_names_by_id   = dpaa_xstats_get_names_by_id,
 986         .xstats_get_names         = dpaa_xstats_get_names,
 987         .xstats_reset             = dpaa_eth_stats_reset,
 988         .stats_reset              = dpaa_eth_stats_reset,
 989         .promiscuous_enable       = dpaa_eth_promiscuous_enable,
 990         .promiscuous_disable      = dpaa_eth_promiscuous_disable,
 991         .allmulticast_enable      = dpaa_eth_multicast_enable,
 992         .allmulticast_disable     = dpaa_eth_multicast_disable,
 993         .mtu_set                  = dpaa_mtu_set,
 994         .dev_set_link_down        = dpaa_link_down,
 995         .dev_set_link_up          = dpaa_link_up,
 996         .mac_addr_add             = dpaa_dev_add_mac_addr,
 997         .mac_addr_remove          = dpaa_dev_remove_mac_addr,
 998         .mac_addr_set             = dpaa_dev_set_mac_addr,
 999
1000         .fw_version_get           = dpaa_fw_version_get,
1001 };
1002
1003 static bool
1004 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv)
1005 {
1006         if (strcmp(dev->device->driver->name,
1007                    drv->driver.name))
1008                 return false;
1009
1010         return true;
1011 }
1012
1013 static bool
1014 is_dpaa_supported(struct rte_eth_dev *dev)
1015 {
1016         return is_device_supported(dev, &rte_dpaa_pmd);
1017 }
1018
1019 int
1020 rte_pmd_dpaa_set_tx_loopback(uint8_t port, uint8_t on)
1021 {
1022         struct rte_eth_dev *dev;
1023         struct dpaa_if *dpaa_intf;
1024
1025         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1026
1027         dev = &rte_eth_devices[port];
1028
1029         if (!is_dpaa_supported(dev))
1030                 return -ENOTSUP;
1031
1032         dpaa_intf = dev->data->dev_private;
1033
1034         if (on)
1035                 fman_if_loopback_enable(dpaa_intf->fif);
1036         else
1037                 fman_if_loopback_disable(dpaa_intf->fif);
1038
1039         return 0;
1040 }
1041
1042 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf)
1043 {
1044         struct rte_eth_fc_conf *fc_conf;
1045         int ret;
1046
1047         PMD_INIT_FUNC_TRACE();
1048
1049         if (!(dpaa_intf->fc_conf)) {
1050                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1051                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1052                 if (!dpaa_intf->fc_conf) {
1053                         DPAA_PMD_ERR("unable to save flow control info");
1054                         return -ENOMEM;
1055                 }
1056         }
1057         fc_conf = dpaa_intf->fc_conf;
1058         ret = fman_if_get_fc_threshold(dpaa_intf->fif);
1059         if (ret) {
1060                 fc_conf->mode = RTE_FC_TX_PAUSE;
1061                 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif);
1062         } else {
1063                 fc_conf->mode = RTE_FC_NONE;
1064         }
1065
1066         return 0;
1067 }
1068
1069 /* Initialise an Rx FQ */
1070 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx,
1071                               uint32_t fqid)
1072 {
1073         struct qm_mcc_initfq opts = {0};
1074         int ret;
1075         u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE;
1076         struct qm_mcc_initcgr cgr_opts = {
1077                 .we_mask = QM_CGR_WE_CS_THRES |
1078                                 QM_CGR_WE_CSTD_EN |
1079                                 QM_CGR_WE_MODE,
1080                 .cgr = {
1081                         .cstd_en = QM_CGR_EN,
1082                         .mode = QMAN_CGR_MODE_FRAME
1083                 }
1084         };
1085
1086         PMD_INIT_FUNC_TRACE();
1087
1088         if (fqid) {
1089                 ret = qman_reserve_fqid(fqid);
1090                 if (ret) {
1091                         DPAA_PMD_ERR("reserve rx fqid 0x%x failed with ret: %d",
1092                                      fqid, ret);
1093                         return -EINVAL;
1094                 }
1095         } else {
1096                 flags |= QMAN_FQ_FLAG_DYNAMIC_FQID;
1097         }
1098         DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid);
1099         ret = qman_create_fq(fqid, flags, fq);
1100         if (ret) {
1101                 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d",
1102                         fqid, ret);
1103                 return ret;
1104         }
1105         fq->is_static = false;
1106
1107         dpaa_poll_queue_default_config(&opts);
1108
1109         if (cgr_rx) {
1110                 /* Enable tail drop with cgr on this queue */
1111                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0);
1112                 cgr_rx->cb = NULL;
1113                 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT,
1114                                       &cgr_opts);
1115                 if (ret) {
1116                         DPAA_PMD_WARN(
1117                                 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1118                                 fq->fqid, ret);
1119                         goto without_cgr;
1120                 }
1121                 opts.we_mask |= QM_INITFQ_WE_CGID;
1122                 opts.fqd.cgid = cgr_rx->cgrid;
1123                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1124         }
1125 without_cgr:
1126         ret = qman_init_fq(fq, 0, &opts);
1127         if (ret)
1128                 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret);
1129         return ret;
1130 }
1131
1132 /* Initialise a Tx FQ */
1133 static int dpaa_tx_queue_init(struct qman_fq *fq,
1134                               struct fman_if *fman_intf)
1135 {
1136         struct qm_mcc_initfq opts = {0};
1137         int ret;
1138
1139         PMD_INIT_FUNC_TRACE();
1140
1141         ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
1142                              QMAN_FQ_FLAG_TO_DCPORTAL, fq);
1143         if (ret) {
1144                 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret);
1145                 return ret;
1146         }
1147         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL |
1148                        QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA;
1149         opts.fqd.dest.channel = fman_intf->tx_channel_id;
1150         opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY;
1151         opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE;
1152         opts.fqd.context_b = 0;
1153         /* no tx-confirmation */
1154         opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi;
1155         opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo;
1156         DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid);
1157         ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
1158         if (ret)
1159                 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret);
1160         return ret;
1161 }
1162
1163 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1164 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */
1165 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid)
1166 {
1167         struct qm_mcc_initfq opts = {0};
1168         int ret;
1169
1170         PMD_INIT_FUNC_TRACE();
1171
1172         ret = qman_reserve_fqid(fqid);
1173         if (ret) {
1174                 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d",
1175                         fqid, ret);
1176                 return -EINVAL;
1177         }
1178         /* "map" this Rx FQ to one of the interfaces Tx FQID */
1179         DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid);
1180         ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1181         if (ret) {
1182                 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d",
1183                         fqid, ret);
1184                 return ret;
1185         }
1186         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL;
1187         opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY;
1188         ret = qman_init_fq(fq, 0, &opts);
1189         if (ret)
1190                 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d",
1191                             fqid, ret);
1192         return ret;
1193 }
1194 #endif
1195
1196 /* Initialise a network interface */
1197 static int
1198 dpaa_dev_init(struct rte_eth_dev *eth_dev)
1199 {
1200         int num_cores, num_rx_fqs, fqid;
1201         int loop, ret = 0;
1202         int dev_id;
1203         struct rte_dpaa_device *dpaa_device;
1204         struct dpaa_if *dpaa_intf;
1205         struct fm_eth_port_cfg *cfg;
1206         struct fman_if *fman_intf;
1207         struct fman_if_bpool *bp, *tmp_bp;
1208         uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES];
1209
1210         PMD_INIT_FUNC_TRACE();
1211
1212         /* For secondary processes, the primary has done all the work */
1213         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1214                 return 0;
1215
1216         dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1217         dev_id = dpaa_device->id.dev_id;
1218         dpaa_intf = eth_dev->data->dev_private;
1219         cfg = &dpaa_netcfg->port_cfg[dev_id];
1220         fman_intf = cfg->fman_if;
1221
1222         dpaa_intf->name = dpaa_device->name;
1223
1224         /* save fman_if & cfg in the interface struture */
1225         dpaa_intf->fif = fman_intf;
1226         dpaa_intf->ifid = dev_id;
1227         dpaa_intf->cfg = cfg;
1228
1229         /* Initialize Rx FQ's */
1230         if (default_q) {
1231                 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1232         } else {
1233                 if (getenv("DPAA_NUM_RX_QUEUES"))
1234                         num_rx_fqs = atoi(getenv("DPAA_NUM_RX_QUEUES"));
1235                 else
1236                         num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1237         }
1238
1239
1240         /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX
1241          * queues.
1242          */
1243         if (num_rx_fqs <= 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) {
1244                 DPAA_PMD_ERR("Invalid number of RX queues\n");
1245                 return -EINVAL;
1246         }
1247
1248         dpaa_intf->rx_queues = rte_zmalloc(NULL,
1249                 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE);
1250         if (!dpaa_intf->rx_queues) {
1251                 DPAA_PMD_ERR("Failed to alloc mem for RX queues\n");
1252                 return -ENOMEM;
1253         }
1254
1255         /* If congestion control is enabled globally*/
1256         if (td_threshold) {
1257                 dpaa_intf->cgr_rx = rte_zmalloc(NULL,
1258                         sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE);
1259                 if (!dpaa_intf->cgr_rx) {
1260                         DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n");
1261                         ret = -ENOMEM;
1262                         goto free_rx;
1263                 }
1264
1265                 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0);
1266                 if (ret != num_rx_fqs) {
1267                         DPAA_PMD_WARN("insufficient CGRIDs available");
1268                         ret = -EINVAL;
1269                         goto free_rx;
1270                 }
1271         } else {
1272                 dpaa_intf->cgr_rx = NULL;
1273         }
1274
1275         for (loop = 0; loop < num_rx_fqs; loop++) {
1276                 if (default_q)
1277                         fqid = cfg->rx_def;
1278                 else
1279                         fqid = DPAA_PCD_FQID_START + dpaa_intf->fif->mac_idx *
1280                                 DPAA_PCD_FQID_MULTIPLIER + loop;
1281
1282                 if (dpaa_intf->cgr_rx)
1283                         dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop];
1284
1285                 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop],
1286                         dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL,
1287                         fqid);
1288                 if (ret)
1289                         goto free_rx;
1290                 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf;
1291         }
1292         dpaa_intf->nb_rx_queues = num_rx_fqs;
1293
1294         /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */
1295         num_cores = rte_lcore_count();
1296         dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) *
1297                 num_cores, MAX_CACHELINE);
1298         if (!dpaa_intf->tx_queues) {
1299                 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n");
1300                 ret = -ENOMEM;
1301                 goto free_rx;
1302         }
1303
1304         for (loop = 0; loop < num_cores; loop++) {
1305                 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop],
1306                                          fman_intf);
1307                 if (ret)
1308                         goto free_tx;
1309                 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
1310         }
1311         dpaa_intf->nb_tx_queues = num_cores;
1312
1313 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1314         dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1315                 DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err);
1316         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf;
1317         dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1318                 DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err);
1319         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf;
1320 #endif
1321
1322         DPAA_PMD_DEBUG("All frame queues created");
1323
1324         /* Get the initial configuration for flow control */
1325         dpaa_fc_set_default(dpaa_intf);
1326
1327         /* reset bpool list, initialize bpool dynamically */
1328         list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) {
1329                 list_del(&bp->node);
1330                 free(bp);
1331         }
1332
1333         /* Populate ethdev structure */
1334         eth_dev->dev_ops = &dpaa_devops;
1335         eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1336         eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
1337
1338         /* Allocate memory for storing MAC addresses */
1339         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
1340                 ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0);
1341         if (eth_dev->data->mac_addrs == NULL) {
1342                 DPAA_PMD_ERR("Failed to allocate %d bytes needed to "
1343                                                 "store MAC addresses",
1344                                 ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER);
1345                 ret = -ENOMEM;
1346                 goto free_tx;
1347         }
1348
1349         /* copy the primary mac address */
1350         ether_addr_copy(&fman_intf->mac_addr, &eth_dev->data->mac_addrs[0]);
1351
1352         RTE_LOG(INFO, PMD, "net: dpaa: %s: %02x:%02x:%02x:%02x:%02x:%02x\n",
1353                 dpaa_device->name,
1354                 fman_intf->mac_addr.addr_bytes[0],
1355                 fman_intf->mac_addr.addr_bytes[1],
1356                 fman_intf->mac_addr.addr_bytes[2],
1357                 fman_intf->mac_addr.addr_bytes[3],
1358                 fman_intf->mac_addr.addr_bytes[4],
1359                 fman_intf->mac_addr.addr_bytes[5]);
1360
1361         /* Disable RX mode */
1362         fman_if_discard_rx_errors(fman_intf);
1363         fman_if_disable_rx(fman_intf);
1364         /* Disable promiscuous mode */
1365         fman_if_promiscuous_disable(fman_intf);
1366         /* Disable multicast */
1367         fman_if_reset_mcast_filter_table(fman_intf);
1368         /* Reset interface statistics */
1369         fman_if_stats_reset(fman_intf);
1370         /* Disable SG by default */
1371         fman_if_set_sg(fman_intf, 0);
1372         fman_if_set_maxfrm(fman_intf, ETHER_MAX_LEN + VLAN_TAG_SIZE);
1373
1374         return 0;
1375
1376 free_tx:
1377         rte_free(dpaa_intf->tx_queues);
1378         dpaa_intf->tx_queues = NULL;
1379         dpaa_intf->nb_tx_queues = 0;
1380
1381 free_rx:
1382         rte_free(dpaa_intf->cgr_rx);
1383         rte_free(dpaa_intf->rx_queues);
1384         dpaa_intf->rx_queues = NULL;
1385         dpaa_intf->nb_rx_queues = 0;
1386         return ret;
1387 }
1388
1389 static int
1390 dpaa_dev_uninit(struct rte_eth_dev *dev)
1391 {
1392         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1393         int loop;
1394
1395         PMD_INIT_FUNC_TRACE();
1396
1397         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1398                 return -EPERM;
1399
1400         if (!dpaa_intf) {
1401                 DPAA_PMD_WARN("Already closed or not started");
1402                 return -1;
1403         }
1404
1405         dpaa_eth_dev_close(dev);
1406
1407         /* release configuration memory */
1408         if (dpaa_intf->fc_conf)
1409                 rte_free(dpaa_intf->fc_conf);
1410
1411         /* Release RX congestion Groups */
1412         if (dpaa_intf->cgr_rx) {
1413                 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++)
1414                         qman_delete_cgr(&dpaa_intf->cgr_rx[loop]);
1415
1416                 qman_release_cgrid_range(dpaa_intf->cgr_rx[loop].cgrid,
1417                                          dpaa_intf->nb_rx_queues);
1418         }
1419
1420         rte_free(dpaa_intf->cgr_rx);
1421         dpaa_intf->cgr_rx = NULL;
1422
1423         rte_free(dpaa_intf->rx_queues);
1424         dpaa_intf->rx_queues = NULL;
1425
1426         rte_free(dpaa_intf->tx_queues);
1427         dpaa_intf->tx_queues = NULL;
1428
1429         /* free memory for storing MAC addresses */
1430         rte_free(dev->data->mac_addrs);
1431         dev->data->mac_addrs = NULL;
1432
1433         dev->dev_ops = NULL;
1434         dev->rx_pkt_burst = NULL;
1435         dev->tx_pkt_burst = NULL;
1436
1437         return 0;
1438 }
1439
1440 static int
1441 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv __rte_unused,
1442                struct rte_dpaa_device *dpaa_dev)
1443 {
1444         int diag;
1445         int ret;
1446         struct rte_eth_dev *eth_dev;
1447
1448         PMD_INIT_FUNC_TRACE();
1449
1450         /* In case of secondary process, the device is already configured
1451          * and no further action is required, except portal initialization
1452          * and verifying secondary attachment to port name.
1453          */
1454         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1455                 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
1456                 if (!eth_dev)
1457                         return -ENOMEM;
1458                 eth_dev->device = &dpaa_dev->device;
1459                 eth_dev->dev_ops = &dpaa_devops;
1460                 rte_eth_dev_probing_finish(eth_dev);
1461                 return 0;
1462         }
1463
1464         if (!is_global_init) {
1465                 /* One time load of Qman/Bman drivers */
1466                 ret = qman_global_init();
1467                 if (ret) {
1468                         DPAA_PMD_ERR("QMAN initialization failed: %d",
1469                                      ret);
1470                         return ret;
1471                 }
1472                 ret = bman_global_init();
1473                 if (ret) {
1474                         DPAA_PMD_ERR("BMAN initialization failed: %d",
1475                                      ret);
1476                         return ret;
1477                 }
1478
1479                 if (access("/tmp/fmc.bin", F_OK) == -1) {
1480                         RTE_LOG(INFO, PMD,
1481                                 "* FMC not configured.Enabling default mode\n");
1482                         default_q = 1;
1483                 }
1484
1485                 /* disabling the default push mode for LS1043 */
1486                 if (dpaa_svr_family == SVR_LS1043A_FAMILY)
1487                         dpaa_push_mode_max_queue = 0;
1488
1489                 /* if push mode queues to be enabled. Currenly we are allowing
1490                  * only one queue per thread.
1491                  */
1492                 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) {
1493                         dpaa_push_mode_max_queue =
1494                                         atoi(getenv("DPAA_PUSH_QUEUES_NUMBER"));
1495                         if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE)
1496                             dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE;
1497                 }
1498
1499                 is_global_init = 1;
1500         }
1501
1502         if (unlikely(!RTE_PER_LCORE(dpaa_io))) {
1503                 ret = rte_dpaa_portal_init((void *)1);
1504                 if (ret) {
1505                         DPAA_PMD_ERR("Unable to initialize portal");
1506                         return ret;
1507                 }
1508         }
1509
1510         eth_dev = rte_eth_dev_allocate(dpaa_dev->name);
1511         if (eth_dev == NULL)
1512                 return -ENOMEM;
1513
1514         eth_dev->data->dev_private = rte_zmalloc(
1515                                         "ethdev private structure",
1516                                         sizeof(struct dpaa_if),
1517                                         RTE_CACHE_LINE_SIZE);
1518         if (!eth_dev->data->dev_private) {
1519                 DPAA_PMD_ERR("Cannot allocate memzone for port data");
1520                 rte_eth_dev_release_port(eth_dev);
1521                 return -ENOMEM;
1522         }
1523
1524         eth_dev->device = &dpaa_dev->device;
1525         dpaa_dev->eth_dev = eth_dev;
1526
1527         /* Invoke PMD device initialization function */
1528         diag = dpaa_dev_init(eth_dev);
1529         if (diag == 0) {
1530                 rte_eth_dev_probing_finish(eth_dev);
1531                 return 0;
1532         }
1533
1534         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
1535                 rte_free(eth_dev->data->dev_private);
1536
1537         rte_eth_dev_release_port(eth_dev);
1538         return diag;
1539 }
1540
1541 static int
1542 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev)
1543 {
1544         struct rte_eth_dev *eth_dev;
1545
1546         PMD_INIT_FUNC_TRACE();
1547
1548         eth_dev = dpaa_dev->eth_dev;
1549         dpaa_dev_uninit(eth_dev);
1550
1551         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
1552                 rte_free(eth_dev->data->dev_private);
1553
1554         rte_eth_dev_release_port(eth_dev);
1555
1556         return 0;
1557 }
1558
1559 static struct rte_dpaa_driver rte_dpaa_pmd = {
1560         .drv_type = FSL_DPAA_ETH,
1561         .probe = rte_dpaa_probe,
1562         .remove = rte_dpaa_remove,
1563 };
1564
1565 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd);