drivers/net/dpaa2/dpaa2_ethdev.c

   1 /* * SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2016-2020 NXP
   5  *
   6  */
   7
   8 #include <time.h>
   9 #include <net/if.h>
  10
  11 #include <rte_mbuf.h>
  12 #include <rte_ethdev_driver.h>
  13 #include <rte_malloc.h>
  14 #include <rte_memcpy.h>
  15 #include <rte_string_fns.h>
  16 #include <rte_cycles.h>
  17 #include <rte_kvargs.h>
  18 #include <rte_dev.h>
  19 #include <rte_fslmc.h>
  20 #include <rte_flow_driver.h>
  21
  22 #include "dpaa2_pmd_logs.h"
  23 #include <fslmc_vfio.h>
  24 #include <dpaa2_hw_pvt.h>
  25 #include <dpaa2_hw_mempool.h>
  26 #include <dpaa2_hw_dpio.h>
  27 #include <mc/fsl_dpmng.h>
  28 #include "dpaa2_ethdev.h"
  29 #include "dpaa2_sparser.h"
  30 #include <fsl_qbman_debug.h>
  31
  32 #define DRIVER_LOOPBACK_MODE "drv_loopback"
  33 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch"
  34
  35 /* Supported Rx offloads */
  36 static uint64_t dev_rx_offloads_sup =
  37                 DEV_RX_OFFLOAD_CHECKSUM |
  38                 DEV_RX_OFFLOAD_SCTP_CKSUM |
  39                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
  40                 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
  41                 DEV_RX_OFFLOAD_VLAN_STRIP |
  42                 DEV_RX_OFFLOAD_VLAN_FILTER |
  43                 DEV_RX_OFFLOAD_JUMBO_FRAME |
  44                 DEV_RX_OFFLOAD_TIMESTAMP;
  45
  46 /* Rx offloads which cannot be disabled */
  47 static uint64_t dev_rx_offloads_nodis =
  48                 DEV_RX_OFFLOAD_RSS_HASH |
  49                 DEV_RX_OFFLOAD_SCATTER;
  50
  51 /* Supported Tx offloads */
  52 static uint64_t dev_tx_offloads_sup =
  53                 DEV_TX_OFFLOAD_VLAN_INSERT |
  54                 DEV_TX_OFFLOAD_IPV4_CKSUM |
  55                 DEV_TX_OFFLOAD_UDP_CKSUM |
  56                 DEV_TX_OFFLOAD_TCP_CKSUM |
  57                 DEV_TX_OFFLOAD_SCTP_CKSUM |
  58                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
  59                 DEV_TX_OFFLOAD_MT_LOCKFREE |
  60                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
  61
  62 /* Tx offloads which cannot be disabled */
  63 static uint64_t dev_tx_offloads_nodis =
  64                 DEV_TX_OFFLOAD_MULTI_SEGS;
  65
  66 /* enable timestamp in mbuf */
  67 enum pmd_dpaa2_ts dpaa2_enable_ts;
  68
  69 struct rte_dpaa2_xstats_name_off {
  70         char name[RTE_ETH_XSTATS_NAME_SIZE];
  71         uint8_t page_id; /* dpni statistics page id */
  72         uint8_t stats_id; /* stats id in the given page */
  73 };
  74
  75 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = {
  76         {"ingress_multicast_frames", 0, 2},
  77         {"ingress_multicast_bytes", 0, 3},
  78         {"ingress_broadcast_frames", 0, 4},
  79         {"ingress_broadcast_bytes", 0, 5},
  80         {"egress_multicast_frames", 1, 2},
  81         {"egress_multicast_bytes", 1, 3},
  82         {"egress_broadcast_frames", 1, 4},
  83         {"egress_broadcast_bytes", 1, 5},
  84         {"ingress_filtered_frames", 2, 0},
  85         {"ingress_discarded_frames", 2, 1},
  86         {"ingress_nobuffer_discards", 2, 2},
  87         {"egress_discarded_frames", 2, 3},
  88         {"egress_confirmed_frames", 2, 4},
  89         {"cgr_reject_frames", 4, 0},
  90         {"cgr_reject_bytes", 4, 1},
  91 };
  92
  93 static const enum rte_filter_op dpaa2_supported_filter_ops[] = {
  94         RTE_ETH_FILTER_ADD,
  95         RTE_ETH_FILTER_DELETE,
  96         RTE_ETH_FILTER_UPDATE,
  97         RTE_ETH_FILTER_FLUSH,
  98         RTE_ETH_FILTER_GET
  99 };
 100
 101 static struct rte_dpaa2_driver rte_dpaa2_pmd;
 102 static int dpaa2_dev_uninit(struct rte_eth_dev *eth_dev);
 103 static int dpaa2_dev_link_update(struct rte_eth_dev *dev,
 104                                  int wait_to_complete);
 105 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev);
 106 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev);
 107 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 108
 109 void
 110 rte_pmd_dpaa2_set_timestamp(enum pmd_dpaa2_ts enable)
 111 {
 112         dpaa2_enable_ts = enable;
 113 }
 114
 115 static int
 116 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 117 {
 118         int ret;
 119         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 120         struct fsl_mc_io *dpni = dev->process_private;
 121
 122         PMD_INIT_FUNC_TRACE();
 123
 124         if (dpni == NULL) {
 125                 DPAA2_PMD_ERR("dpni is NULL");
 126                 return -1;
 127         }
 128
 129         if (on)
 130                 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token,
 131                                        vlan_id, 0, 0, 0);
 132         else
 133                 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW,
 134                                           priv->token, vlan_id);
 135
 136         if (ret < 0)
 137                 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d",
 138                               ret, vlan_id, priv->hw_id);
 139
 140         return ret;
 141 }
 142
 143 static int
 144 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 145 {
 146         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 147         struct fsl_mc_io *dpni = dev->process_private;
 148         int ret = 0;
 149
 150         PMD_INIT_FUNC_TRACE();
 151
 152         if (mask & ETH_VLAN_FILTER_MASK) {
 153                 /* VLAN Filter not avaialble */
 154                 if (!priv->max_vlan_filters) {
 155                         DPAA2_PMD_INFO("VLAN filter not available");
 156                         return -ENOTSUP;
 157                 }
 158
 159                 if (dev->data->dev_conf.rxmode.offloads &
 160                         DEV_RX_OFFLOAD_VLAN_FILTER)
 161                         ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
 162                                                       priv->token, true);
 163                 else
 164                         ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
 165                                                       priv->token, false);
 166                 if (ret < 0)
 167                         DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret);
 168         }
 169
 170         return ret;
 171 }
 172
 173 static int
 174 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev,
 175                       enum rte_vlan_type vlan_type __rte_unused,
 176                       uint16_t tpid)
 177 {
 178         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 179         struct fsl_mc_io *dpni = dev->process_private;
 180         int ret = -ENOTSUP;
 181
 182         PMD_INIT_FUNC_TRACE();
 183
 184         /* nothing to be done for standard vlan tpids */
 185         if (tpid == 0x8100 || tpid == 0x88A8)
 186                 return 0;
 187
 188         ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
 189                                    priv->token, tpid);
 190         if (ret < 0)
 191                 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret);
 192         /* if already configured tpids, remove them first */
 193         if (ret == -EBUSY) {
 194                 struct dpni_custom_tpid_cfg tpid_list = {0};
 195
 196                 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW,
 197                                    priv->token, &tpid_list);
 198                 if (ret < 0)
 199                         goto fail;
 200                 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW,
 201                                    priv->token, tpid_list.tpid1);
 202                 if (ret < 0)
 203                         goto fail;
 204                 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
 205                                            priv->token, tpid);
 206         }
 207 fail:
 208         return ret;
 209 }
 210
 211 static int
 212 dpaa2_fw_version_get(struct rte_eth_dev *dev,
 213                      char *fw_version,
 214                      size_t fw_size)
 215 {
 216         int ret;
 217         struct fsl_mc_io *dpni = dev->process_private;
 218         struct mc_soc_version mc_plat_info = {0};
 219         struct mc_version mc_ver_info = {0};
 220
 221         PMD_INIT_FUNC_TRACE();
 222
 223         if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info))
 224                 DPAA2_PMD_WARN("\tmc_get_soc_version failed");
 225
 226         if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info))
 227                 DPAA2_PMD_WARN("\tmc_get_version failed");
 228
 229         ret = snprintf(fw_version, fw_size,
 230                        "%x-%d.%d.%d",
 231                        mc_plat_info.svr,
 232                        mc_ver_info.major,
 233                        mc_ver_info.minor,
 234                        mc_ver_info.revision);
 235
 236         ret += 1; /* add the size of '\0' */
 237         if (fw_size < (uint32_t)ret)
 238                 return ret;
 239         else
 240                 return 0;
 241 }
 242
 243 static int
 244 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 245 {
 246         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 247
 248         PMD_INIT_FUNC_TRACE();
 249
 250         dev_info->if_index = priv->hw_id;
 251
 252         dev_info->max_mac_addrs = priv->max_mac_filters;
 253         dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN;
 254         dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE;
 255         dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues;
 256         dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues;
 257         dev_info->rx_offload_capa = dev_rx_offloads_sup |
 258                                         dev_rx_offloads_nodis;
 259         dev_info->tx_offload_capa = dev_tx_offloads_sup |
 260                                         dev_tx_offloads_nodis;
 261         dev_info->speed_capa = ETH_LINK_SPEED_1G |
 262                         ETH_LINK_SPEED_2_5G |
 263                         ETH_LINK_SPEED_10G;
 264
 265         dev_info->max_hash_mac_addrs = 0;
 266         dev_info->max_vfs = 0;
 267         dev_info->max_vmdq_pools = ETH_16_POOLS;
 268         dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL;
 269
 270         dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size;
 271         /* same is rx size for best perf */
 272         dev_info->default_txportconf.burst_size = dpaa2_dqrr_size;
 273
 274         dev_info->default_rxportconf.nb_queues = 1;
 275         dev_info->default_txportconf.nb_queues = 1;
 276         dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD;
 277         dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC;
 278
 279         if (dpaa2_svr_family == SVR_LX2160A) {
 280                 dev_info->speed_capa |= ETH_LINK_SPEED_25G |
 281                                 ETH_LINK_SPEED_40G |
 282                                 ETH_LINK_SPEED_50G |
 283                                 ETH_LINK_SPEED_100G;
 284         }
 285
 286         return 0;
 287 }
 288
 289 static int
 290 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)
 291 {
 292         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 293         uint16_t dist_idx;
 294         uint32_t vq_id;
 295         uint8_t num_rxqueue_per_tc;
 296         struct dpaa2_queue *mc_q, *mcq;
 297         uint32_t tot_queues;
 298         int i;
 299         struct dpaa2_queue *dpaa2_q;
 300
 301         PMD_INIT_FUNC_TRACE();
 302
 303         num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc);
 304         if (priv->tx_conf_en)
 305                 tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues;
 306         else
 307                 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues;
 308         mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues,
 309                           RTE_CACHE_LINE_SIZE);
 310         if (!mc_q) {
 311                 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues");
 312                 return -1;
 313         }
 314
 315         for (i = 0; i < priv->nb_rx_queues; i++) {
 316                 mc_q->eth_data = dev->data;
 317                 priv->rx_vq[i] = mc_q++;
 318                 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
 319                 dpaa2_q->q_storage = rte_malloc("dq_storage",
 320                                         sizeof(struct queue_storage_info_t),
 321                                         RTE_CACHE_LINE_SIZE);
 322                 if (!dpaa2_q->q_storage)
 323                         goto fail;
 324
 325                 memset(dpaa2_q->q_storage, 0,
 326                        sizeof(struct queue_storage_info_t));
 327                 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
 328                         goto fail;
 329         }
 330
 331         for (i = 0; i < priv->nb_tx_queues; i++) {
 332                 mc_q->eth_data = dev->data;
 333                 mc_q->flow_id = 0xffff;
 334                 priv->tx_vq[i] = mc_q++;
 335                 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
 336                 dpaa2_q->cscn = rte_malloc(NULL,
 337                                            sizeof(struct qbman_result), 16);
 338                 if (!dpaa2_q->cscn)
 339                         goto fail_tx;
 340         }
 341
 342         if (priv->tx_conf_en) {
 343                 /*Setup tx confirmation queues*/
 344                 for (i = 0; i < priv->nb_tx_queues; i++) {
 345                         mc_q->eth_data = dev->data;
 346                         mc_q->tc_index = i;
 347                         mc_q->flow_id = 0;
 348                         priv->tx_conf_vq[i] = mc_q++;
 349                         dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
 350                         dpaa2_q->q_storage =
 351                                 rte_malloc("dq_storage",
 352                                         sizeof(struct queue_storage_info_t),
 353                                         RTE_CACHE_LINE_SIZE);
 354                         if (!dpaa2_q->q_storage)
 355                                 goto fail_tx_conf;
 356
 357                         memset(dpaa2_q->q_storage, 0,
 358                                sizeof(struct queue_storage_info_t));
 359                         if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
 360                                 goto fail_tx_conf;
 361                 }
 362         }
 363
 364         vq_id = 0;
 365         for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) {
 366                 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id];
 367                 mcq->tc_index = dist_idx / num_rxqueue_per_tc;
 368                 mcq->flow_id = dist_idx % num_rxqueue_per_tc;
 369                 vq_id++;
 370         }
 371
 372         return 0;
 373 fail_tx_conf:
 374         i -= 1;
 375         while (i >= 0) {
 376                 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
 377                 rte_free(dpaa2_q->q_storage);
 378                 priv->tx_conf_vq[i--] = NULL;
 379         }
 380         i = priv->nb_tx_queues;
 381 fail_tx:
 382         i -= 1;
 383         while (i >= 0) {
 384                 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
 385                 rte_free(dpaa2_q->cscn);
 386                 priv->tx_vq[i--] = NULL;
 387         }
 388         i = priv->nb_rx_queues;
 389 fail:
 390         i -= 1;
 391         mc_q = priv->rx_vq[0];
 392         while (i >= 0) {
 393                 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
 394                 dpaa2_free_dq_storage(dpaa2_q->q_storage);
 395                 rte_free(dpaa2_q->q_storage);
 396                 priv->rx_vq[i--] = NULL;
 397         }
 398         rte_free(mc_q);
 399         return -1;
 400 }
 401
 402 static void
 403 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev)
 404 {
 405         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 406         struct dpaa2_queue *dpaa2_q;
 407         int i;
 408
 409         PMD_INIT_FUNC_TRACE();
 410
 411         /* Queue allocation base */
 412         if (priv->rx_vq[0]) {
 413                 /* cleaning up queue storage */
 414                 for (i = 0; i < priv->nb_rx_queues; i++) {
 415                         dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
 416                         if (dpaa2_q->q_storage)
 417                                 rte_free(dpaa2_q->q_storage);
 418                 }
 419                 /* cleanup tx queue cscn */
 420                 for (i = 0; i < priv->nb_tx_queues; i++) {
 421                         dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
 422                         rte_free(dpaa2_q->cscn);
 423                 }
 424                 if (priv->tx_conf_en) {
 425                         /* cleanup tx conf queue storage */
 426                         for (i = 0; i < priv->nb_tx_queues; i++) {
 427                                 dpaa2_q = (struct dpaa2_queue *)
 428                                                 priv->tx_conf_vq[i];
 429                                 rte_free(dpaa2_q->q_storage);
 430                         }
 431                 }
 432                 /*free memory for all queues (RX+TX) */
 433                 rte_free(priv->rx_vq[0]);
 434                 priv->rx_vq[0] = NULL;
 435         }
 436 }
 437
 438 static int
 439 dpaa2_eth_dev_configure(struct rte_eth_dev *dev)
 440 {
 441         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 442         struct fsl_mc_io *dpni = dev->process_private;
 443         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 444         uint64_t rx_offloads = eth_conf->rxmode.offloads;
 445         uint64_t tx_offloads = eth_conf->txmode.offloads;
 446         int rx_l3_csum_offload = false;
 447         int rx_l4_csum_offload = false;
 448         int tx_l3_csum_offload = false;
 449         int tx_l4_csum_offload = false;
 450         int ret, tc_index;
 451
 452         PMD_INIT_FUNC_TRACE();
 453
 454         /* Rx offloads which are enabled by default */
 455         if (dev_rx_offloads_nodis & ~rx_offloads) {
 456                 DPAA2_PMD_INFO(
 457                 "Some of rx offloads enabled by default - requested 0x%" PRIx64
 458                 " fixed are 0x%" PRIx64,
 459                 rx_offloads, dev_rx_offloads_nodis);
 460         }
 461
 462         /* Tx offloads which are enabled by default */
 463         if (dev_tx_offloads_nodis & ~tx_offloads) {
 464                 DPAA2_PMD_INFO(
 465                 "Some of tx offloads enabled by default - requested 0x%" PRIx64
 466                 " fixed are 0x%" PRIx64,
 467                 tx_offloads, dev_tx_offloads_nodis);
 468         }
 469
 470         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 471                 if (eth_conf->rxmode.max_rx_pkt_len <= DPAA2_MAX_RX_PKT_LEN) {
 472                         ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW,
 473                                 priv->token, eth_conf->rxmode.max_rx_pkt_len
 474                                 - RTE_ETHER_CRC_LEN);
 475                         if (ret) {
 476                                 DPAA2_PMD_ERR(
 477                                         "Unable to set mtu. check config");
 478                                 return ret;
 479                         }
 480                         dev->data->mtu =
 481                                 dev->data->dev_conf.rxmode.max_rx_pkt_len -
 482                                 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN -
 483                                 VLAN_TAG_SIZE;
 484                 } else {
 485                         return -1;
 486                 }
 487         }
 488
 489         if (eth_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) {
 490                 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
 491                         ret = dpaa2_setup_flow_dist(dev,
 492                                         eth_conf->rx_adv_conf.rss_conf.rss_hf,
 493                                         tc_index);
 494                         if (ret) {
 495                                 DPAA2_PMD_ERR(
 496                                         "Unable to set flow distribution on tc%d."
 497                                         "Check queue config", tc_index);
 498                                 return ret;
 499                         }
 500                 }
 501         }
 502
 503         if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM)
 504                 rx_l3_csum_offload = true;
 505
 506         if ((rx_offloads & DEV_RX_OFFLOAD_UDP_CKSUM) ||
 507                 (rx_offloads & DEV_RX_OFFLOAD_TCP_CKSUM) ||
 508                 (rx_offloads & DEV_RX_OFFLOAD_SCTP_CKSUM))
 509                 rx_l4_csum_offload = true;
 510
 511         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 512                                DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload);
 513         if (ret) {
 514                 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret);
 515                 return ret;
 516         }
 517
 518         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 519                                DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload);
 520         if (ret) {
 521                 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret);
 522                 return ret;
 523         }
 524
 525 #if !defined(RTE_LIBRTE_IEEE1588)
 526         if (rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP)
 527 #endif
 528         dpaa2_enable_ts = true;
 529
 530         if (tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)
 531                 tx_l3_csum_offload = true;
 532
 533         if ((tx_offloads & DEV_TX_OFFLOAD_UDP_CKSUM) ||
 534                 (tx_offloads & DEV_TX_OFFLOAD_TCP_CKSUM) ||
 535                 (tx_offloads & DEV_TX_OFFLOAD_SCTP_CKSUM))
 536                 tx_l4_csum_offload = true;
 537
 538         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 539                                DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload);
 540         if (ret) {
 541                 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret);
 542                 return ret;
 543         }
 544
 545         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 546                                DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload);
 547         if (ret) {
 548                 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret);
 549                 return ret;
 550         }
 551
 552         /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in
 553          * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC]
 554          * to 0 for LS2 in the hardware thus disabling data/annotation
 555          * stashing. For LX2 this is fixed in hardware and thus hash result and
 556          * parse results can be received in FD using this option.
 557          */
 558         if (dpaa2_svr_family == SVR_LX2160A) {
 559                 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 560                                        DPNI_FLCTYPE_HASH, true);
 561                 if (ret) {
 562                         DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret);
 563                         return ret;
 564                 }
 565         }
 566
 567         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 568                 dpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK);
 569
 570         return 0;
 571 }
 572
 573 /* Function to setup RX flow information. It contains traffic class ID,
 574  * flow ID, destination configuration etc.
 575  */
 576 static int
 577 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
 578                          uint16_t rx_queue_id,
 579                          uint16_t nb_rx_desc,
 580                          unsigned int socket_id __rte_unused,
 581                          const struct rte_eth_rxconf *rx_conf __rte_unused,
 582                          struct rte_mempool *mb_pool)
 583 {
 584         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 585         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
 586         struct dpaa2_queue *dpaa2_q;
 587         struct dpni_queue cfg;
 588         uint8_t options = 0;
 589         uint8_t flow_id;
 590         uint32_t bpid;
 591         int i, ret;
 592
 593         PMD_INIT_FUNC_TRACE();
 594
 595         DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p",
 596                         dev, rx_queue_id, mb_pool, rx_conf);
 597
 598         if (!priv->bp_list || priv->bp_list->mp != mb_pool) {
 599                 bpid = mempool_to_bpid(mb_pool);
 600                 ret = dpaa2_attach_bp_list(priv,
 601                                            rte_dpaa2_bpid_info[bpid].bp_list);
 602                 if (ret)
 603                         return ret;
 604         }
 605         dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
 606         dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */
 607         dpaa2_q->bp_array = rte_dpaa2_bpid_info;
 608
 609         /*Get the flow id from given VQ id*/
 610         flow_id = dpaa2_q->flow_id;
 611         memset(&cfg, 0, sizeof(struct dpni_queue));
 612
 613         options = options | DPNI_QUEUE_OPT_USER_CTX;
 614         cfg.user_context = (size_t)(dpaa2_q);
 615
 616         /* check if a private cgr available. */
 617         for (i = 0; i < priv->max_cgs; i++) {
 618                 if (!priv->cgid_in_use[i]) {
 619                         priv->cgid_in_use[i] = 1;
 620                         break;
 621                 }
 622         }
 623
 624         if (i < priv->max_cgs) {
 625                 options |= DPNI_QUEUE_OPT_SET_CGID;
 626                 cfg.cgid = i;
 627                 dpaa2_q->cgid = cfg.cgid;
 628         } else {
 629                 dpaa2_q->cgid = 0xff;
 630         }
 631
 632         /*if ls2088 or rev2 device, enable the stashing */
 633
 634         if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) {
 635                 options |= DPNI_QUEUE_OPT_FLC;
 636                 cfg.flc.stash_control = true;
 637                 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0;
 638                 /* 00 00 00 - last 6 bit represent annotation, context stashing,
 639                  * data stashing setting 01 01 00 (0x14)
 640                  * (in following order ->DS AS CS)
 641                  * to enable 1 line data, 1 line annotation.
 642                  * For LX2, this setting should be 01 00 00 (0x10)
 643                  */
 644                 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A)
 645                         cfg.flc.value |= 0x10;
 646                 else
 647                         cfg.flc.value |= 0x14;
 648         }
 649         ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX,
 650                              dpaa2_q->tc_index, flow_id, options, &cfg);
 651         if (ret) {
 652                 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret);
 653                 return -1;
 654         }
 655
 656         if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) {
 657                 struct dpni_taildrop taildrop;
 658
 659                 taildrop.enable = 1;
 660
 661                 /* Private CGR will use tail drop length as nb_rx_desc.
 662                  * for rest cases we can use standard byte based tail drop.
 663                  * There is no HW restriction, but number of CGRs are limited,
 664                  * hence this restriction is placed.
 665                  */
 666                 if (dpaa2_q->cgid != 0xff) {
 667                         /*enabling per rx queue congestion control */
 668                         taildrop.threshold = nb_rx_desc;
 669                         taildrop.units = DPNI_CONGESTION_UNIT_FRAMES;
 670                         taildrop.oal = 0;
 671                         DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d",
 672                                         rx_queue_id);
 673                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 674                                                 DPNI_CP_CONGESTION_GROUP,
 675                                                 DPNI_QUEUE_RX,
 676                                                 dpaa2_q->tc_index,
 677                                                 dpaa2_q->cgid, &taildrop);
 678                 } else {
 679                         /*enabling per rx queue congestion control */
 680                         taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q;
 681                         taildrop.units = DPNI_CONGESTION_UNIT_BYTES;
 682                         taildrop.oal = CONG_RX_OAL;
 683                         DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d",
 684                                         rx_queue_id);
 685                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 686                                                 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
 687                                                 dpaa2_q->tc_index, flow_id,
 688                                                 &taildrop);
 689                 }
 690                 if (ret) {
 691                         DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
 692                                       ret);
 693                         return -1;
 694                 }
 695         } else { /* Disable tail Drop */
 696                 struct dpni_taildrop taildrop = {0};
 697                 DPAA2_PMD_INFO("Tail drop is disabled on queue");
 698
 699                 taildrop.enable = 0;
 700                 if (dpaa2_q->cgid != 0xff) {
 701                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 702                                         DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX,
 703                                         dpaa2_q->tc_index,
 704                                         dpaa2_q->cgid, &taildrop);
 705                 } else {
 706                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 707                                         DPNI_CP_QUEUE, DPNI_QUEUE_RX,
 708                                         dpaa2_q->tc_index, flow_id, &taildrop);
 709                 }
 710                 if (ret) {
 711                         DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
 712                                       ret);
 713                         return -1;
 714                 }
 715         }
 716
 717         dev->data->rx_queues[rx_queue_id] = dpaa2_q;
 718         return 0;
 719 }
 720
 721 static int
 722 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
 723                          uint16_t tx_queue_id,
 724                          uint16_t nb_tx_desc __rte_unused,
 725                          unsigned int socket_id __rte_unused,
 726                          const struct rte_eth_txconf *tx_conf __rte_unused)
 727 {
 728         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 729         struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)
 730                 priv->tx_vq[tx_queue_id];
 731         struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *)
 732                 priv->tx_conf_vq[tx_queue_id];
 733         struct fsl_mc_io *dpni = dev->process_private;
 734         struct dpni_queue tx_conf_cfg;
 735         struct dpni_queue tx_flow_cfg;
 736         uint8_t options = 0, flow_id;
 737         struct dpni_queue_id qid;
 738         uint32_t tc_id;
 739         int ret;
 740
 741         PMD_INIT_FUNC_TRACE();
 742
 743         /* Return if queue already configured */
 744         if (dpaa2_q->flow_id != 0xffff) {
 745                 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
 746                 return 0;
 747         }
 748
 749         memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue));
 750         memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue));
 751
 752         tc_id = tx_queue_id;
 753         flow_id = 0;
 754
 755         ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX,
 756                         tc_id, flow_id, options, &tx_flow_cfg);
 757         if (ret) {
 758                 DPAA2_PMD_ERR("Error in setting the tx flow: "
 759                         "tc_id=%d, flow=%d err=%d",
 760                         tc_id, flow_id, ret);
 761                         return -1;
 762         }
 763
 764         dpaa2_q->flow_id = flow_id;
 765
 766         if (tx_queue_id == 0) {
 767                 /*Set tx-conf and error configuration*/
 768                 if (priv->tx_conf_en)
 769                         ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
 770                                                             priv->token,
 771                                                             DPNI_CONF_AFFINE);
 772                 else
 773                         ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
 774                                                             priv->token,
 775                                                             DPNI_CONF_DISABLE);
 776                 if (ret) {
 777                         DPAA2_PMD_ERR("Error in set tx conf mode settings: "
 778                                       "err=%d", ret);
 779                         return -1;
 780                 }
 781         }
 782         dpaa2_q->tc_index = tc_id;
 783
 784         ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
 785                              DPNI_QUEUE_TX, dpaa2_q->tc_index,
 786                              dpaa2_q->flow_id, &tx_flow_cfg, &qid);
 787         if (ret) {
 788                 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
 789                 return -1;
 790         }
 791         dpaa2_q->fqid = qid.fqid;
 792
 793         if (!(priv->flags & DPAA2_TX_CGR_OFF)) {
 794                 struct dpni_congestion_notification_cfg cong_notif_cfg = {0};
 795
 796                 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES;
 797                 cong_notif_cfg.threshold_entry = CONG_ENTER_TX_THRESHOLD;
 798                 /* Notify that the queue is not congested when the data in
 799                  * the queue is below this thershold.
 800                  */
 801                 cong_notif_cfg.threshold_exit = CONG_EXIT_TX_THRESHOLD;
 802                 cong_notif_cfg.message_ctx = 0;
 803                 cong_notif_cfg.message_iova =
 804                                 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn);
 805                 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE;
 806                 cong_notif_cfg.notification_mode =
 807                                          DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
 808                                          DPNI_CONG_OPT_WRITE_MEM_ON_EXIT |
 809                                          DPNI_CONG_OPT_COHERENT_WRITE;
 810                 cong_notif_cfg.cg_point = DPNI_CP_QUEUE;
 811
 812                 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW,
 813                                                        priv->token,
 814                                                        DPNI_QUEUE_TX,
 815                                                        tc_id,
 816                                                        &cong_notif_cfg);
 817                 if (ret) {
 818                         DPAA2_PMD_ERR(
 819                            "Error in setting tx congestion notification: "
 820                            "err=%d", ret);
 821                         return -ret;
 822                 }
 823         }
 824         dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf;
 825         dev->data->tx_queues[tx_queue_id] = dpaa2_q;
 826
 827         if (priv->tx_conf_en) {
 828                 dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q;
 829                 options = options | DPNI_QUEUE_OPT_USER_CTX;
 830                 tx_conf_cfg.user_context = (size_t)(dpaa2_q);
 831                 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
 832                              DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
 833                              dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg);
 834                 if (ret) {
 835                         DPAA2_PMD_ERR("Error in setting the tx conf flow: "
 836                               "tc_index=%d, flow=%d err=%d",
 837                               dpaa2_tx_conf_q->tc_index,
 838                               dpaa2_tx_conf_q->flow_id, ret);
 839                         return -1;
 840                 }
 841
 842                 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
 843                              DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
 844                              dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid);
 845                 if (ret) {
 846                         DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
 847                         return -1;
 848                 }
 849                 dpaa2_tx_conf_q->fqid = qid.fqid;
 850         }
 851         return 0;
 852 }
 853
 854 static void
 855 dpaa2_dev_rx_queue_release(void *q __rte_unused)
 856 {
 857         struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)q;
 858         struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private;
 859         struct fsl_mc_io *dpni =
 860                 (struct fsl_mc_io *)priv->eth_dev->process_private;
 861         uint8_t options = 0;
 862         int ret;
 863         struct dpni_queue cfg;
 864
 865         memset(&cfg, 0, sizeof(struct dpni_queue));
 866         PMD_INIT_FUNC_TRACE();
 867         if (dpaa2_q->cgid != 0xff) {
 868                 options = DPNI_QUEUE_OPT_CLEAR_CGID;
 869                 cfg.cgid = dpaa2_q->cgid;
 870
 871                 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
 872                                      DPNI_QUEUE_RX,
 873                                      dpaa2_q->tc_index, dpaa2_q->flow_id,
 874                                      options, &cfg);
 875                 if (ret)
 876                         DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d",
 877                                         dpaa2_q->fqid, ret);
 878                 priv->cgid_in_use[dpaa2_q->cgid] = 0;
 879                 dpaa2_q->cgid = 0xff;
 880         }
 881 }
 882
 883 static void
 884 dpaa2_dev_tx_queue_release(void *q __rte_unused)
 885 {
 886         PMD_INIT_FUNC_TRACE();
 887 }
 888
 889 static uint32_t
 890 dpaa2_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 891 {
 892         int32_t ret;
 893         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 894         struct dpaa2_queue *dpaa2_q;
 895         struct qbman_swp *swp;
 896         struct qbman_fq_query_np_rslt state;
 897         uint32_t frame_cnt = 0;
 898
 899         if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
 900                 ret = dpaa2_affine_qbman_swp();
 901                 if (ret) {
 902                         DPAA2_PMD_ERR(
 903                                 "Failed to allocate IO portal, tid: %d\n",
 904                                 rte_gettid());
 905                         return -EINVAL;
 906                 }
 907         }
 908         swp = DPAA2_PER_LCORE_PORTAL;
 909
 910         dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
 911
 912         if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) {
 913                 frame_cnt = qbman_fq_state_frame_count(&state);
 914                 DPAA2_PMD_DP_DEBUG("RX frame count for q(%d) is %u",
 915                                 rx_queue_id, frame_cnt);
 916         }
 917         return frame_cnt;
 918 }
 919
 920 static const uint32_t *
 921 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev)
 922 {
 923         static const uint32_t ptypes[] = {
 924                 /*todo -= add more types */
 925                 RTE_PTYPE_L2_ETHER,
 926                 RTE_PTYPE_L3_IPV4,
 927                 RTE_PTYPE_L3_IPV4_EXT,
 928                 RTE_PTYPE_L3_IPV6,
 929                 RTE_PTYPE_L3_IPV6_EXT,
 930                 RTE_PTYPE_L4_TCP,
 931                 RTE_PTYPE_L4_UDP,
 932                 RTE_PTYPE_L4_SCTP,
 933                 RTE_PTYPE_L4_ICMP,
 934                 RTE_PTYPE_UNKNOWN
 935         };
 936
 937         if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx ||
 938                 dev->rx_pkt_burst == dpaa2_dev_rx ||
 939                 dev->rx_pkt_burst == dpaa2_dev_loopback_rx)
 940                 return ptypes;
 941         return NULL;
 942 }
 943
 944 /**
 945  * Dpaa2 link Interrupt handler
 946  *
 947  * @param param
 948  *  The address of parameter (struct rte_eth_dev *) regsitered before.
 949  *
 950  * @return
 951  *  void
 952  */
 953 static void
 954 dpaa2_interrupt_handler(void *param)
 955 {
 956         struct rte_eth_dev *dev = param;
 957         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 958         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
 959         int ret;
 960         int irq_index = DPNI_IRQ_INDEX;
 961         unsigned int status = 0, clear = 0;
 962
 963         PMD_INIT_FUNC_TRACE();
 964
 965         if (dpni == NULL) {
 966                 DPAA2_PMD_ERR("dpni is NULL");
 967                 return;
 968         }
 969
 970         ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token,
 971                                   irq_index, &status);
 972         if (unlikely(ret)) {
 973                 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret);
 974                 clear = 0xffffffff;
 975                 goto out;
 976         }
 977
 978         if (status & DPNI_IRQ_EVENT_LINK_CHANGED) {
 979                 clear = DPNI_IRQ_EVENT_LINK_CHANGED;
 980                 dpaa2_dev_link_update(dev, 0);
 981                 /* calling all the apps registered for link status event */
 982                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
 983                                               NULL);
 984         }
 985 out:
 986         ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token,
 987                                     irq_index, clear);
 988         if (unlikely(ret))
 989                 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret);
 990 }
 991
 992 static int
 993 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable)
 994 {
 995         int err = 0;
 996         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 997         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
 998         int irq_index = DPNI_IRQ_INDEX;
 999         unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED;
1000
1001         PMD_INIT_FUNC_TRACE();
1002
1003         err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token,
1004                                 irq_index, mask);
1005         if (err < 0) {
1006                 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err,
1007                               strerror(-err));
1008                 return err;
1009         }
1010
1011         err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token,
1012                                   irq_index, enable);
1013         if (err < 0)
1014                 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err,
1015                               strerror(-err));
1016
1017         return err;
1018 }
1019
1020 static int
1021 dpaa2_dev_start(struct rte_eth_dev *dev)
1022 {
1023         struct rte_device *rdev = dev->device;
1024         struct rte_dpaa2_device *dpaa2_dev;
1025         struct rte_eth_dev_data *data = dev->data;
1026         struct dpaa2_dev_priv *priv = data->dev_private;
1027         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1028         struct dpni_queue cfg;
1029         struct dpni_error_cfg   err_cfg;
1030         uint16_t qdid;
1031         struct dpni_queue_id qid;
1032         struct dpaa2_queue *dpaa2_q;
1033         int ret, i;
1034         struct rte_intr_handle *intr_handle;
1035
1036         dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);
1037         intr_handle = &dpaa2_dev->intr_handle;
1038
1039         PMD_INIT_FUNC_TRACE();
1040
1041         ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1042         if (ret) {
1043                 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d",
1044                               priv->hw_id, ret);
1045                 return ret;
1046         }
1047
1048         /* Power up the phy. Needed to make the link go UP */
1049         dpaa2_dev_set_link_up(dev);
1050
1051         ret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token,
1052                             DPNI_QUEUE_TX, &qdid);
1053         if (ret) {
1054                 DPAA2_PMD_ERR("Error in getting qdid: err=%d", ret);
1055                 return ret;
1056         }
1057         priv->qdid = qdid;
1058
1059         for (i = 0; i < data->nb_rx_queues; i++) {
1060                 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i];
1061                 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1062                                      DPNI_QUEUE_RX, dpaa2_q->tc_index,
1063                                        dpaa2_q->flow_id, &cfg, &qid);
1064                 if (ret) {
1065                         DPAA2_PMD_ERR("Error in getting flow information: "
1066                                       "err=%d", ret);
1067                         return ret;
1068                 }
1069                 dpaa2_q->fqid = qid.fqid;
1070         }
1071
1072         /*checksum errors, send them to normal path and set it in annotation */
1073         err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE;
1074         err_cfg.errors |= DPNI_ERROR_PHE;
1075
1076         err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE;
1077         err_cfg.set_frame_annotation = true;
1078
1079         ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW,
1080                                        priv->token, &err_cfg);
1081         if (ret) {
1082                 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d",
1083                               ret);
1084                 return ret;
1085         }
1086
1087         /* if the interrupts were configured on this devices*/
1088         if (intr_handle && (intr_handle->fd) &&
1089             (dev->data->dev_conf.intr_conf.lsc != 0)) {
1090                 /* Registering LSC interrupt handler */
1091                 rte_intr_callback_register(intr_handle,
1092                                            dpaa2_interrupt_handler,
1093                                            (void *)dev);
1094
1095                 /* enable vfio intr/eventfd mapping
1096                  * Interrupt index 0 is required, so we can not use
1097                  * rte_intr_enable.
1098                  */
1099                 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX);
1100
1101                 /* enable dpni_irqs */
1102                 dpaa2_eth_setup_irqs(dev, 1);
1103         }
1104
1105         /* Change the tx burst function if ordered queues are used */
1106         if (priv->en_ordered)
1107                 dev->tx_pkt_burst = dpaa2_dev_tx_ordered;
1108
1109         return 0;
1110 }
1111
1112 /**
1113  *  This routine disables all traffic on the adapter by issuing a
1114  *  global reset on the MAC.
1115  */
1116 static void
1117 dpaa2_dev_stop(struct rte_eth_dev *dev)
1118 {
1119         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1120         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1121         int ret;
1122         struct rte_eth_link link;
1123         struct rte_intr_handle *intr_handle = dev->intr_handle;
1124
1125         PMD_INIT_FUNC_TRACE();
1126
1127         /* reset interrupt callback  */
1128         if (intr_handle && (intr_handle->fd) &&
1129             (dev->data->dev_conf.intr_conf.lsc != 0)) {
1130                 /*disable dpni irqs */
1131                 dpaa2_eth_setup_irqs(dev, 0);
1132
1133                 /* disable vfio intr before callback unregister */
1134                 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX);
1135
1136                 /* Unregistering LSC interrupt handler */
1137                 rte_intr_callback_unregister(intr_handle,
1138                                              dpaa2_interrupt_handler,
1139                                              (void *)dev);
1140         }
1141
1142         dpaa2_dev_set_link_down(dev);
1143
1144         ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token);
1145         if (ret) {
1146                 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev",
1147                               ret, priv->hw_id);
1148                 return;
1149         }
1150
1151         /* clear the recorded link status */
1152         memset(&link, 0, sizeof(link));
1153         rte_eth_linkstatus_set(dev, &link);
1154 }
1155
1156 static void
1157 dpaa2_dev_close(struct rte_eth_dev *dev)
1158 {
1159         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1160         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1161         int ret;
1162         struct rte_eth_link link;
1163
1164         PMD_INIT_FUNC_TRACE();
1165
1166         dpaa2_flow_clean(dev);
1167
1168         /* Clean the device first */
1169         ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token);
1170         if (ret) {
1171                 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret);
1172                 return;
1173         }
1174
1175         memset(&link, 0, sizeof(link));
1176         rte_eth_linkstatus_set(dev, &link);
1177 }
1178
1179 static int
1180 dpaa2_dev_promiscuous_enable(
1181                 struct rte_eth_dev *dev)
1182 {
1183         int ret;
1184         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1185         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1186
1187         PMD_INIT_FUNC_TRACE();
1188
1189         if (dpni == NULL) {
1190                 DPAA2_PMD_ERR("dpni is NULL");
1191                 return -ENODEV;
1192         }
1193
1194         ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1195         if (ret < 0)
1196                 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret);
1197
1198         ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1199         if (ret < 0)
1200                 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret);
1201
1202         return ret;
1203 }
1204
1205 static int
1206 dpaa2_dev_promiscuous_disable(
1207                 struct rte_eth_dev *dev)
1208 {
1209         int ret;
1210         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1211         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1212
1213         PMD_INIT_FUNC_TRACE();
1214
1215         if (dpni == NULL) {
1216                 DPAA2_PMD_ERR("dpni is NULL");
1217                 return -ENODEV;
1218         }
1219
1220         ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1221         if (ret < 0)
1222                 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret);
1223
1224         if (dev->data->all_multicast == 0) {
1225                 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW,
1226                                                  priv->token, false);
1227                 if (ret < 0)
1228                         DPAA2_PMD_ERR("Unable to disable M promisc mode %d",
1229                                       ret);
1230         }
1231
1232         return ret;
1233 }
1234
1235 static int
1236 dpaa2_dev_allmulticast_enable(
1237                 struct rte_eth_dev *dev)
1238 {
1239         int ret;
1240         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1241         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1242
1243         PMD_INIT_FUNC_TRACE();
1244
1245         if (dpni == NULL) {
1246                 DPAA2_PMD_ERR("dpni is NULL");
1247                 return -ENODEV;
1248         }
1249
1250         ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1251         if (ret < 0)
1252                 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret);
1253
1254         return ret;
1255 }
1256
1257 static int
1258 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev)
1259 {
1260         int ret;
1261         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1262         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1263
1264         PMD_INIT_FUNC_TRACE();
1265
1266         if (dpni == NULL) {
1267                 DPAA2_PMD_ERR("dpni is NULL");
1268                 return -ENODEV;
1269         }
1270
1271         /* must remain on for all promiscuous */
1272         if (dev->data->promiscuous == 1)
1273                 return 0;
1274
1275         ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1276         if (ret < 0)
1277                 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret);
1278
1279         return ret;
1280 }
1281
1282 static int
1283 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1284 {
1285         int ret;
1286         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1287         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1288         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
1289                                 + VLAN_TAG_SIZE;
1290
1291         PMD_INIT_FUNC_TRACE();
1292
1293         if (dpni == NULL) {
1294                 DPAA2_PMD_ERR("dpni is NULL");
1295                 return -EINVAL;
1296         }
1297
1298         /* check that mtu is within the allowed range */
1299         if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA2_MAX_RX_PKT_LEN)
1300                 return -EINVAL;
1301
1302         if (frame_size > RTE_ETHER_MAX_LEN)
1303                 dev->data->dev_conf.rxmode.offloads |=
1304                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
1305         else
1306                 dev->data->dev_conf.rxmode.offloads &=
1307                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1308
1309         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1310
1311         /* Set the Max Rx frame length as 'mtu' +
1312          * Maximum Ethernet header length
1313          */
1314         ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
1315                                         frame_size - RTE_ETHER_CRC_LEN);
1316         if (ret) {
1317                 DPAA2_PMD_ERR("Setting the max frame length failed");
1318                 return -1;
1319         }
1320         DPAA2_PMD_INFO("MTU configured for the device: %d", mtu);
1321         return 0;
1322 }
1323
1324 static int
1325 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev,
1326                        struct rte_ether_addr *addr,
1327                        __rte_unused uint32_t index,
1328                        __rte_unused uint32_t pool)
1329 {
1330         int ret;
1331         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1332         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1333
1334         PMD_INIT_FUNC_TRACE();
1335
1336         if (dpni == NULL) {
1337                 DPAA2_PMD_ERR("dpni is NULL");
1338                 return -1;
1339         }
1340
1341         ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, priv->token,
1342                                 addr->addr_bytes, 0, 0, 0);
1343         if (ret)
1344                 DPAA2_PMD_ERR(
1345                         "error: Adding the MAC ADDR failed: err = %d", ret);
1346         return 0;
1347 }
1348
1349 static void
1350 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev,
1351                           uint32_t index)
1352 {
1353         int ret;
1354         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1355         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1356         struct rte_eth_dev_data *data = dev->data;
1357         struct rte_ether_addr *macaddr;
1358
1359         PMD_INIT_FUNC_TRACE();
1360
1361         macaddr = &data->mac_addrs[index];
1362
1363         if (dpni == NULL) {
1364                 DPAA2_PMD_ERR("dpni is NULL");
1365                 return;
1366         }
1367
1368         ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW,
1369                                    priv->token, macaddr->addr_bytes);
1370         if (ret)
1371                 DPAA2_PMD_ERR(
1372                         "error: Removing the MAC ADDR failed: err = %d", ret);
1373 }
1374
1375 static int
1376 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev,
1377                        struct rte_ether_addr *addr)
1378 {
1379         int ret;
1380         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1381         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1382
1383         PMD_INIT_FUNC_TRACE();
1384
1385         if (dpni == NULL) {
1386                 DPAA2_PMD_ERR("dpni is NULL");
1387                 return -EINVAL;
1388         }
1389
1390         ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW,
1391                                         priv->token, addr->addr_bytes);
1392
1393         if (ret)
1394                 DPAA2_PMD_ERR(
1395                         "error: Setting the MAC ADDR failed %d", ret);
1396
1397         return ret;
1398 }
1399
1400 static
1401 int dpaa2_dev_stats_get(struct rte_eth_dev *dev,
1402                          struct rte_eth_stats *stats)
1403 {
1404         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1405         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1406         int32_t  retcode;
1407         uint8_t page0 = 0, page1 = 1, page2 = 2;
1408         union dpni_statistics value;
1409         int i;
1410         struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq;
1411
1412         memset(&value, 0, sizeof(union dpni_statistics));
1413
1414         PMD_INIT_FUNC_TRACE();
1415
1416         if (!dpni) {
1417                 DPAA2_PMD_ERR("dpni is NULL");
1418                 return -EINVAL;
1419         }
1420
1421         if (!stats) {
1422                 DPAA2_PMD_ERR("stats is NULL");
1423                 return -EINVAL;
1424         }
1425
1426         /*Get Counters from page_0*/
1427         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1428                                       page0, 0, &value);
1429         if (retcode)
1430                 goto err;
1431
1432         stats->ipackets = value.page_0.ingress_all_frames;
1433         stats->ibytes = value.page_0.ingress_all_bytes;
1434
1435         /*Get Counters from page_1*/
1436         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1437                                       page1, 0, &value);
1438         if (retcode)
1439                 goto err;
1440
1441         stats->opackets = value.page_1.egress_all_frames;
1442         stats->obytes = value.page_1.egress_all_bytes;
1443
1444         /*Get Counters from page_2*/
1445         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1446                                       page2, 0, &value);
1447         if (retcode)
1448                 goto err;
1449
1450         /* Ingress drop frame count due to configured rules */
1451         stats->ierrors = value.page_2.ingress_filtered_frames;
1452         /* Ingress drop frame count due to error */
1453         stats->ierrors += value.page_2.ingress_discarded_frames;
1454
1455         stats->oerrors = value.page_2.egress_discarded_frames;
1456         stats->imissed = value.page_2.ingress_nobuffer_discards;
1457
1458         /* Fill in per queue stats */
1459         for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1460                 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) {
1461                 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i];
1462                 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i];
1463                 if (dpaa2_rxq)
1464                         stats->q_ipackets[i] = dpaa2_rxq->rx_pkts;
1465                 if (dpaa2_txq)
1466                         stats->q_opackets[i] = dpaa2_txq->tx_pkts;
1467
1468                 /* Byte counting is not implemented */
1469                 stats->q_ibytes[i]   = 0;
1470                 stats->q_obytes[i]   = 0;
1471         }
1472
1473         return 0;
1474
1475 err:
1476         DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1477         return retcode;
1478 };
1479
1480 static int
1481 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1482                      unsigned int n)
1483 {
1484         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1485         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1486         int32_t  retcode;
1487         union dpni_statistics value[5] = {};
1488         unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings);
1489
1490         if (n < num)
1491                 return num;
1492
1493         if (xstats == NULL)
1494                 return 0;
1495
1496         /* Get Counters from page_0*/
1497         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1498                                       0, 0, &value[0]);
1499         if (retcode)
1500                 goto err;
1501
1502         /* Get Counters from page_1*/
1503         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1504                                       1, 0, &value[1]);
1505         if (retcode)
1506                 goto err;
1507
1508         /* Get Counters from page_2*/
1509         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1510                                       2, 0, &value[2]);
1511         if (retcode)
1512                 goto err;
1513
1514         for (i = 0; i < priv->max_cgs; i++) {
1515                 if (!priv->cgid_in_use[i]) {
1516                         /* Get Counters from page_4*/
1517                         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW,
1518                                                       priv->token,
1519                                                       4, 0, &value[4]);
1520                         if (retcode)
1521                                 goto err;
1522                         break;
1523                 }
1524         }
1525
1526         for (i = 0; i < num; i++) {
1527                 xstats[i].id = i;
1528                 xstats[i].value = value[dpaa2_xstats_strings[i].page_id].
1529                         raw.counter[dpaa2_xstats_strings[i].stats_id];
1530         }
1531         return i;
1532 err:
1533         DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode);
1534         return retcode;
1535 }
1536
1537 static int
1538 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1539                        struct rte_eth_xstat_name *xstats_names,
1540                        unsigned int limit)
1541 {
1542         unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1543
1544         if (limit < stat_cnt)
1545                 return stat_cnt;
1546
1547         if (xstats_names != NULL)
1548                 for (i = 0; i < stat_cnt; i++)
1549                         strlcpy(xstats_names[i].name,
1550                                 dpaa2_xstats_strings[i].name,
1551                                 sizeof(xstats_names[i].name));
1552
1553         return stat_cnt;
1554 }
1555
1556 static int
1557 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1558                        uint64_t *values, unsigned int n)
1559 {
1560         unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1561         uint64_t values_copy[stat_cnt];
1562
1563         if (!ids) {
1564                 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1565                 struct fsl_mc_io *dpni =
1566                         (struct fsl_mc_io *)dev->process_private;
1567                 int32_t  retcode;
1568                 union dpni_statistics value[5] = {};
1569
1570                 if (n < stat_cnt)
1571                         return stat_cnt;
1572
1573                 if (!values)
1574                         return 0;
1575
1576                 /* Get Counters from page_0*/
1577                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1578                                               0, 0, &value[0]);
1579                 if (retcode)
1580                         return 0;
1581
1582                 /* Get Counters from page_1*/
1583                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1584                                               1, 0, &value[1]);
1585                 if (retcode)
1586                         return 0;
1587
1588                 /* Get Counters from page_2*/
1589                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1590                                               2, 0, &value[2]);
1591                 if (retcode)
1592                         return 0;
1593
1594                 /* Get Counters from page_4*/
1595                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1596                                               4, 0, &value[4]);
1597                 if (retcode)
1598                         return 0;
1599
1600                 for (i = 0; i < stat_cnt; i++) {
1601                         values[i] = value[dpaa2_xstats_strings[i].page_id].
1602                                 raw.counter[dpaa2_xstats_strings[i].stats_id];
1603                 }
1604                 return stat_cnt;
1605         }
1606
1607         dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
1608
1609         for (i = 0; i < n; i++) {
1610                 if (ids[i] >= stat_cnt) {
1611                         DPAA2_PMD_ERR("xstats id value isn't valid");
1612                         return -1;
1613                 }
1614                 values[i] = values_copy[ids[i]];
1615         }
1616         return n;
1617 }
1618
1619 static int
1620 dpaa2_xstats_get_names_by_id(
1621         struct rte_eth_dev *dev,
1622         struct rte_eth_xstat_name *xstats_names,
1623         const uint64_t *ids,
1624         unsigned int limit)
1625 {
1626         unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1627         struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
1628
1629         if (!ids)
1630                 return dpaa2_xstats_get_names(dev, xstats_names, limit);
1631
1632         dpaa2_xstats_get_names(dev, xstats_names_copy, limit);
1633
1634         for (i = 0; i < limit; i++) {
1635                 if (ids[i] >= stat_cnt) {
1636                         DPAA2_PMD_ERR("xstats id value isn't valid");
1637                         return -1;
1638                 }
1639                 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
1640         }
1641         return limit;
1642 }
1643
1644 static int
1645 dpaa2_dev_stats_reset(struct rte_eth_dev *dev)
1646 {
1647         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1648         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1649         int retcode;
1650         int i;
1651         struct dpaa2_queue *dpaa2_q;
1652
1653         PMD_INIT_FUNC_TRACE();
1654
1655         if (dpni == NULL) {
1656                 DPAA2_PMD_ERR("dpni is NULL");
1657                 return -EINVAL;
1658         }
1659
1660         retcode =  dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token);
1661         if (retcode)
1662                 goto error;
1663
1664         /* Reset the per queue stats in dpaa2_queue structure */
1665         for (i = 0; i < priv->nb_rx_queues; i++) {
1666                 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
1667                 if (dpaa2_q)
1668                         dpaa2_q->rx_pkts = 0;
1669         }
1670
1671         for (i = 0; i < priv->nb_tx_queues; i++) {
1672                 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
1673                 if (dpaa2_q)
1674                         dpaa2_q->tx_pkts = 0;
1675         }
1676
1677         return 0;
1678
1679 error:
1680         DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1681         return retcode;
1682 };
1683
1684 /* return 0 means link status changed, -1 means not changed */
1685 static int
1686 dpaa2_dev_link_update(struct rte_eth_dev *dev,
1687                         int wait_to_complete __rte_unused)
1688 {
1689         int ret;
1690         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1691         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1692         struct rte_eth_link link;
1693         struct dpni_link_state state = {0};
1694
1695         if (dpni == NULL) {
1696                 DPAA2_PMD_ERR("dpni is NULL");
1697                 return 0;
1698         }
1699
1700         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1701         if (ret < 0) {
1702                 DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret);
1703                 return -1;
1704         }
1705
1706         memset(&link, 0, sizeof(struct rte_eth_link));
1707         link.link_status = state.up;
1708         link.link_speed = state.rate;
1709
1710         if (state.options & DPNI_LINK_OPT_HALF_DUPLEX)
1711                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1712         else
1713                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1714
1715         ret = rte_eth_linkstatus_set(dev, &link);
1716         if (ret == -1)
1717                 DPAA2_PMD_DEBUG("No change in status");
1718         else
1719                 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
1720                                link.link_status ? "Up" : "Down");
1721
1722         return ret;
1723 }
1724
1725 /**
1726  * Toggle the DPNI to enable, if not already enabled.
1727  * This is not strictly PHY up/down - it is more of logical toggling.
1728  */
1729 static int
1730 dpaa2_dev_set_link_up(struct rte_eth_dev *dev)
1731 {
1732         int ret = -EINVAL;
1733         struct dpaa2_dev_priv *priv;
1734         struct fsl_mc_io *dpni;
1735         int en = 0;
1736         struct dpni_link_state state = {0};
1737
1738         priv = dev->data->dev_private;
1739         dpni = (struct fsl_mc_io *)dev->process_private;
1740
1741         if (dpni == NULL) {
1742                 DPAA2_PMD_ERR("dpni is NULL");
1743                 return ret;
1744         }
1745
1746         /* Check if DPNI is currently enabled */
1747         ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en);
1748         if (ret) {
1749                 /* Unable to obtain dpni status; Not continuing */
1750                 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1751                 return -EINVAL;
1752         }
1753
1754         /* Enable link if not already enabled */
1755         if (!en) {
1756                 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1757                 if (ret) {
1758                         DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1759                         return -EINVAL;
1760                 }
1761         }
1762         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1763         if (ret < 0) {
1764                 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret);
1765                 return -1;
1766         }
1767
1768         /* changing tx burst function to start enqueues */
1769         dev->tx_pkt_burst = dpaa2_dev_tx;
1770         dev->data->dev_link.link_status = state.up;
1771         dev->data->dev_link.link_speed = state.rate;
1772
1773         if (state.up)
1774                 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id);
1775         else
1776                 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id);
1777         return ret;
1778 }
1779
1780 /**
1781  * Toggle the DPNI to disable, if not already disabled.
1782  * This is not strictly PHY up/down - it is more of logical toggling.
1783  */
1784 static int
1785 dpaa2_dev_set_link_down(struct rte_eth_dev *dev)
1786 {
1787         int ret = -EINVAL;
1788         struct dpaa2_dev_priv *priv;
1789         struct fsl_mc_io *dpni;
1790         int dpni_enabled = 0;
1791         int retries = 10;
1792
1793         PMD_INIT_FUNC_TRACE();
1794
1795         priv = dev->data->dev_private;
1796         dpni = (struct fsl_mc_io *)dev->process_private;
1797
1798         if (dpni == NULL) {
1799                 DPAA2_PMD_ERR("Device has not yet been configured");
1800                 return ret;
1801         }
1802
1803         /*changing  tx burst function to avoid any more enqueues */
1804         dev->tx_pkt_burst = dummy_dev_tx;
1805
1806         /* Loop while dpni_disable() attempts to drain the egress FQs
1807          * and confirm them back to us.
1808          */
1809         do {
1810                 ret = dpni_disable(dpni, 0, priv->token);
1811                 if (ret) {
1812                         DPAA2_PMD_ERR("dpni disable failed (%d)", ret);
1813                         return ret;
1814                 }
1815                 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled);
1816                 if (ret) {
1817                         DPAA2_PMD_ERR("dpni enable check failed (%d)", ret);
1818                         return ret;
1819                 }
1820                 if (dpni_enabled)
1821                         /* Allow the MC some slack */
1822                         rte_delay_us(100 * 1000);
1823         } while (dpni_enabled && --retries);
1824
1825         if (!retries) {
1826                 DPAA2_PMD_WARN("Retry count exceeded disabling dpni");
1827                 /* todo- we may have to manually cleanup queues.
1828                  */
1829         } else {
1830                 DPAA2_PMD_INFO("Port %d Link DOWN successful",
1831                                dev->data->port_id);
1832         }
1833
1834         dev->data->dev_link.link_status = 0;
1835
1836         return ret;
1837 }
1838
1839 static int
1840 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1841 {
1842         int ret = -EINVAL;
1843         struct dpaa2_dev_priv *priv;
1844         struct fsl_mc_io *dpni;
1845         struct dpni_link_state state = {0};
1846
1847         PMD_INIT_FUNC_TRACE();
1848
1849         priv = dev->data->dev_private;
1850         dpni = (struct fsl_mc_io *)dev->process_private;
1851
1852         if (dpni == NULL || fc_conf == NULL) {
1853                 DPAA2_PMD_ERR("device not configured");
1854                 return ret;
1855         }
1856
1857         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1858         if (ret) {
1859                 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret);
1860                 return ret;
1861         }
1862
1863         memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf));
1864         if (state.options & DPNI_LINK_OPT_PAUSE) {
1865                 /* DPNI_LINK_OPT_PAUSE set
1866                  *  if ASYM_PAUSE not set,
1867                  *      RX Side flow control (handle received Pause frame)
1868                  *      TX side flow control (send Pause frame)
1869                  *  if ASYM_PAUSE set,
1870                  *      RX Side flow control (handle received Pause frame)
1871                  *      No TX side flow control (send Pause frame disabled)
1872                  */
1873                 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE))
1874                         fc_conf->mode = RTE_FC_FULL;
1875                 else
1876                         fc_conf->mode = RTE_FC_RX_PAUSE;
1877         } else {
1878                 /* DPNI_LINK_OPT_PAUSE not set
1879                  *  if ASYM_PAUSE set,
1880                  *      TX side flow control (send Pause frame)
1881                  *      No RX side flow control (No action on pause frame rx)
1882                  *  if ASYM_PAUSE not set,
1883                  *      Flow control disabled
1884                  */
1885                 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE)
1886                         fc_conf->mode = RTE_FC_TX_PAUSE;
1887                 else
1888                         fc_conf->mode = RTE_FC_NONE;
1889         }
1890
1891         return ret;
1892 }
1893
1894 static int
1895 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1896 {
1897         int ret = -EINVAL;
1898         struct dpaa2_dev_priv *priv;
1899         struct fsl_mc_io *dpni;
1900         struct dpni_link_state state = {0};
1901         struct dpni_link_cfg cfg = {0};
1902
1903         PMD_INIT_FUNC_TRACE();
1904
1905         priv = dev->data->dev_private;
1906         dpni = (struct fsl_mc_io *)dev->process_private;
1907
1908         if (dpni == NULL) {
1909                 DPAA2_PMD_ERR("dpni is NULL");
1910                 return ret;
1911         }
1912
1913         /* It is necessary to obtain the current state before setting fc_conf
1914          * as MC would return error in case rate, autoneg or duplex values are
1915          * different.
1916          */
1917         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1918         if (ret) {
1919                 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret);
1920                 return -1;
1921         }
1922
1923         /* Disable link before setting configuration */
1924         dpaa2_dev_set_link_down(dev);
1925
1926         /* Based on fc_conf, update cfg */
1927         cfg.rate = state.rate;
1928         cfg.options = state.options;
1929
1930         /* update cfg with fc_conf */
1931         switch (fc_conf->mode) {
1932         case RTE_FC_FULL:
1933                 /* Full flow control;
1934                  * OPT_PAUSE set, ASYM_PAUSE not set
1935                  */
1936                 cfg.options |= DPNI_LINK_OPT_PAUSE;
1937                 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
1938                 break;
1939         case RTE_FC_TX_PAUSE:
1940                 /* Enable RX flow control
1941                  * OPT_PAUSE not set;
1942                  * ASYM_PAUSE set;
1943                  */
1944                 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
1945                 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
1946                 break;
1947         case RTE_FC_RX_PAUSE:
1948                 /* Enable TX Flow control
1949                  * OPT_PAUSE set
1950                  * ASYM_PAUSE set
1951                  */
1952                 cfg.options |= DPNI_LINK_OPT_PAUSE;
1953                 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
1954                 break;
1955         case RTE_FC_NONE:
1956                 /* Disable Flow control
1957                  * OPT_PAUSE not set
1958                  * ASYM_PAUSE not set
1959                  */
1960                 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
1961                 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
1962                 break;
1963         default:
1964                 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)",
1965                               fc_conf->mode);
1966                 return -1;
1967         }
1968
1969         ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg);
1970         if (ret)
1971                 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)",
1972                               ret);
1973
1974         /* Enable link */
1975         dpaa2_dev_set_link_up(dev);
1976
1977         return ret;
1978 }
1979
1980 static int
1981 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev,
1982                           struct rte_eth_rss_conf *rss_conf)
1983 {
1984         struct rte_eth_dev_data *data = dev->data;
1985         struct dpaa2_dev_priv *priv = data->dev_private;
1986         struct rte_eth_conf *eth_conf = &data->dev_conf;
1987         int ret, tc_index;
1988
1989         PMD_INIT_FUNC_TRACE();
1990
1991         if (rss_conf->rss_hf) {
1992                 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
1993                         ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf,
1994                                 tc_index);
1995                         if (ret) {
1996                                 DPAA2_PMD_ERR("Unable to set flow dist on tc%d",
1997                                         tc_index);
1998                                 return ret;
1999                         }
2000                 }
2001         } else {
2002                 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2003                         ret = dpaa2_remove_flow_dist(dev, tc_index);
2004                         if (ret) {
2005                                 DPAA2_PMD_ERR(
2006                                         "Unable to remove flow dist on tc%d",
2007                                         tc_index);
2008                                 return ret;
2009                         }
2010                 }
2011         }
2012         eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
2013         return 0;
2014 }
2015
2016 static int
2017 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2018                             struct rte_eth_rss_conf *rss_conf)
2019 {
2020         struct rte_eth_dev_data *data = dev->data;
2021         struct rte_eth_conf *eth_conf = &data->dev_conf;
2022
2023         /* dpaa2 does not support rss_key, so length should be 0*/
2024         rss_conf->rss_key_len = 0;
2025         rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
2026         return 0;
2027 }
2028
2029 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
2030                 int eth_rx_queue_id,
2031                 struct dpaa2_dpcon_dev *dpcon,
2032                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
2033 {
2034         struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2035         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2036         struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2037         uint8_t flow_id = dpaa2_ethq->flow_id;
2038         struct dpni_queue cfg;
2039         uint8_t options, priority;
2040         int ret;
2041
2042         if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL)
2043                 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event;
2044         else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC)
2045                 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event;
2046         else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED)
2047                 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event;
2048         else
2049                 return -EINVAL;
2050
2051         priority = (RTE_EVENT_DEV_PRIORITY_LOWEST / queue_conf->ev.priority) *
2052                    (dpcon->num_priorities - 1);
2053
2054         memset(&cfg, 0, sizeof(struct dpni_queue));
2055         options = DPNI_QUEUE_OPT_DEST;
2056         cfg.destination.type = DPNI_DEST_DPCON;
2057         cfg.destination.id = dpcon->dpcon_id;
2058         cfg.destination.priority = priority;
2059
2060         if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
2061                 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE;
2062                 cfg.destination.hold_active = 1;
2063         }
2064
2065         if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED &&
2066                         !eth_priv->en_ordered) {
2067                 struct opr_cfg ocfg;
2068
2069                 /* Restoration window size = 256 frames */
2070                 ocfg.oprrws = 3;
2071                 /* Restoration window size = 512 frames for LX2 */
2072                 if (dpaa2_svr_family == SVR_LX2160A)
2073                         ocfg.oprrws = 4;
2074                 /* Auto advance NESN window enabled */
2075                 ocfg.oa = 1;
2076                 /* Late arrival window size disabled */
2077                 ocfg.olws = 0;
2078                 /* ORL resource exhaustaion advance NESN disabled */
2079                 ocfg.oeane = 0;
2080                 /* Loose ordering enabled */
2081                 ocfg.oloe = 1;
2082                 eth_priv->en_loose_ordered = 1;
2083                 /* Strict ordering enabled if explicitly set */
2084                 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) {
2085                         ocfg.oloe = 0;
2086                         eth_priv->en_loose_ordered = 0;
2087                 }
2088
2089                 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token,
2090                                    dpaa2_ethq->tc_index, flow_id,
2091                                    OPR_OPT_CREATE, &ocfg);
2092                 if (ret) {
2093                         DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret);
2094                         return ret;
2095                 }
2096
2097                 eth_priv->en_ordered = 1;
2098         }
2099
2100         options |= DPNI_QUEUE_OPT_USER_CTX;
2101         cfg.user_context = (size_t)(dpaa2_ethq);
2102
2103         ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2104                              dpaa2_ethq->tc_index, flow_id, options, &cfg);
2105         if (ret) {
2106                 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2107                 return ret;
2108         }
2109
2110         memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event));
2111
2112         return 0;
2113 }
2114
2115 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
2116                 int eth_rx_queue_id)
2117 {
2118         struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2119         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2120         struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2121         uint8_t flow_id = dpaa2_ethq->flow_id;
2122         struct dpni_queue cfg;
2123         uint8_t options;
2124         int ret;
2125
2126         memset(&cfg, 0, sizeof(struct dpni_queue));
2127         options = DPNI_QUEUE_OPT_DEST;
2128         cfg.destination.type = DPNI_DEST_NONE;
2129
2130         ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2131                              dpaa2_ethq->tc_index, flow_id, options, &cfg);
2132         if (ret)
2133                 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2134
2135         return ret;
2136 }
2137
2138 static inline int
2139 dpaa2_dev_verify_filter_ops(enum rte_filter_op filter_op)
2140 {
2141         unsigned int i;
2142
2143         for (i = 0; i < RTE_DIM(dpaa2_supported_filter_ops); i++) {
2144                 if (dpaa2_supported_filter_ops[i] == filter_op)
2145                         return 0;
2146         }
2147         return -ENOTSUP;
2148 }
2149
2150 static int
2151 dpaa2_dev_flow_ctrl(struct rte_eth_dev *dev,
2152                     enum rte_filter_type filter_type,
2153                                  enum rte_filter_op filter_op,
2154                                  void *arg)
2155 {
2156         int ret = 0;
2157
2158         if (!dev)
2159                 return -ENODEV;
2160
2161         switch (filter_type) {
2162         case RTE_ETH_FILTER_GENERIC:
2163                 if (dpaa2_dev_verify_filter_ops(filter_op) < 0) {
2164                         ret = -ENOTSUP;
2165                         break;
2166                 }
2167                 *(const void **)arg = &dpaa2_flow_ops;
2168                 dpaa2_filter_type |= filter_type;
2169                 break;
2170         default:
2171                 RTE_LOG(ERR, PMD, "Filter type (%d) not supported",
2172                         filter_type);
2173                 ret = -ENOTSUP;
2174                 break;
2175         }
2176         return ret;
2177 }
2178
2179 static struct eth_dev_ops dpaa2_ethdev_ops = {
2180         .dev_configure    = dpaa2_eth_dev_configure,
2181         .dev_start            = dpaa2_dev_start,
2182         .dev_stop             = dpaa2_dev_stop,
2183         .dev_close            = dpaa2_dev_close,
2184         .promiscuous_enable   = dpaa2_dev_promiscuous_enable,
2185         .promiscuous_disable  = dpaa2_dev_promiscuous_disable,
2186         .allmulticast_enable  = dpaa2_dev_allmulticast_enable,
2187         .allmulticast_disable = dpaa2_dev_allmulticast_disable,
2188         .dev_set_link_up      = dpaa2_dev_set_link_up,
2189         .dev_set_link_down    = dpaa2_dev_set_link_down,
2190         .link_update       = dpaa2_dev_link_update,
2191         .stats_get             = dpaa2_dev_stats_get,
2192         .xstats_get            = dpaa2_dev_xstats_get,
2193         .xstats_get_by_id     = dpaa2_xstats_get_by_id,
2194         .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id,
2195         .xstats_get_names      = dpaa2_xstats_get_names,
2196         .stats_reset       = dpaa2_dev_stats_reset,
2197         .xstats_reset         = dpaa2_dev_stats_reset,
2198         .fw_version_get    = dpaa2_fw_version_get,
2199         .dev_infos_get     = dpaa2_dev_info_get,
2200         .dev_supported_ptypes_get = dpaa2_supported_ptypes_get,
2201         .mtu_set           = dpaa2_dev_mtu_set,
2202         .vlan_filter_set      = dpaa2_vlan_filter_set,
2203         .vlan_offload_set     = dpaa2_vlan_offload_set,
2204         .vlan_tpid_set        = dpaa2_vlan_tpid_set,
2205         .rx_queue_setup    = dpaa2_dev_rx_queue_setup,
2206         .rx_queue_release  = dpaa2_dev_rx_queue_release,
2207         .tx_queue_setup    = dpaa2_dev_tx_queue_setup,
2208         .tx_queue_release  = dpaa2_dev_tx_queue_release,
2209         .rx_queue_count       = dpaa2_dev_rx_queue_count,
2210         .flow_ctrl_get        = dpaa2_flow_ctrl_get,
2211         .flow_ctrl_set        = dpaa2_flow_ctrl_set,
2212         .mac_addr_add         = dpaa2_dev_add_mac_addr,
2213         .mac_addr_remove      = dpaa2_dev_remove_mac_addr,
2214         .mac_addr_set         = dpaa2_dev_set_mac_addr,
2215         .rss_hash_update      = dpaa2_dev_rss_hash_update,
2216         .rss_hash_conf_get    = dpaa2_dev_rss_hash_conf_get,
2217         .filter_ctrl          = dpaa2_dev_flow_ctrl,
2218 #if defined(RTE_LIBRTE_IEEE1588)
2219         .timesync_enable      = dpaa2_timesync_enable,
2220         .timesync_disable     = dpaa2_timesync_disable,
2221         .timesync_read_time   = dpaa2_timesync_read_time,
2222         .timesync_write_time  = dpaa2_timesync_write_time,
2223         .timesync_adjust_time = dpaa2_timesync_adjust_time,
2224         .timesync_read_rx_timestamp = dpaa2_timesync_read_rx_timestamp,
2225         .timesync_read_tx_timestamp = dpaa2_timesync_read_tx_timestamp,
2226 #endif
2227 };
2228
2229 /* Populate the mac address from physically available (u-boot/firmware) and/or
2230  * one set by higher layers like MC (restool) etc.
2231  * Returns the table of MAC entries (multiple entries)
2232  */
2233 static int
2234 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv,
2235                   struct rte_ether_addr *mac_entry)
2236 {
2237         int ret;
2238         struct rte_ether_addr phy_mac, prime_mac;
2239
2240         memset(&phy_mac, 0, sizeof(struct rte_ether_addr));
2241         memset(&prime_mac, 0, sizeof(struct rte_ether_addr));
2242
2243         /* Get the physical device MAC address */
2244         ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2245                                      phy_mac.addr_bytes);
2246         if (ret) {
2247                 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret);
2248                 goto cleanup;
2249         }
2250
2251         ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2252                                         prime_mac.addr_bytes);
2253         if (ret) {
2254                 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret);
2255                 goto cleanup;
2256         }
2257
2258         /* Now that both MAC have been obtained, do:
2259          *  if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy
2260          *     and return phy
2261          *  If empty_mac(phy), return prime.
2262          *  if both are empty, create random MAC, set as prime and return
2263          */
2264         if (!rte_is_zero_ether_addr(&phy_mac)) {
2265                 /* If the addresses are not same, overwrite prime */
2266                 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) {
2267                         ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2268                                                         priv->token,
2269                                                         phy_mac.addr_bytes);
2270                         if (ret) {
2271                                 DPAA2_PMD_ERR("Unable to set MAC Address: %d",
2272                                               ret);
2273                                 goto cleanup;
2274                         }
2275                         memcpy(&prime_mac, &phy_mac,
2276                                 sizeof(struct rte_ether_addr));
2277                 }
2278         } else if (rte_is_zero_ether_addr(&prime_mac)) {
2279                 /* In case phys and prime, both are zero, create random MAC */
2280                 rte_eth_random_addr(prime_mac.addr_bytes);
2281                 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2282                                                 priv->token,
2283                                                 prime_mac.addr_bytes);
2284                 if (ret) {
2285                         DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret);
2286                         goto cleanup;
2287                 }
2288         }
2289
2290         /* prime_mac the final MAC address */
2291         memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr));
2292         return 0;
2293
2294 cleanup:
2295         return -1;
2296 }
2297
2298 static int
2299 check_devargs_handler(__rte_unused const char *key, const char *value,
2300                       __rte_unused void *opaque)
2301 {
2302         if (strcmp(value, "1"))
2303                 return -1;
2304
2305         return 0;
2306 }
2307
2308 static int
2309 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key)
2310 {
2311         struct rte_kvargs *kvlist;
2312
2313         if (!devargs)
2314                 return 0;
2315
2316         kvlist = rte_kvargs_parse(devargs->args, NULL);
2317         if (!kvlist)
2318                 return 0;
2319
2320         if (!rte_kvargs_count(kvlist, key)) {
2321                 rte_kvargs_free(kvlist);
2322                 return 0;
2323         }
2324
2325         if (rte_kvargs_process(kvlist, key,
2326                                check_devargs_handler, NULL) < 0) {
2327                 rte_kvargs_free(kvlist);
2328                 return 0;
2329         }
2330         rte_kvargs_free(kvlist);
2331
2332         return 1;
2333 }
2334
2335 static int
2336 dpaa2_dev_init(struct rte_eth_dev *eth_dev)
2337 {
2338         struct rte_device *dev = eth_dev->device;
2339         struct rte_dpaa2_device *dpaa2_dev;
2340         struct fsl_mc_io *dpni_dev;
2341         struct dpni_attr attr;
2342         struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2343         struct dpni_buffer_layout layout;
2344         int ret, hw_id, i;
2345
2346         PMD_INIT_FUNC_TRACE();
2347
2348         dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0);
2349         if (!dpni_dev) {
2350                 DPAA2_PMD_ERR("Memory allocation failed for dpni device");
2351                 return -1;
2352         }
2353         dpni_dev->regs = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX);
2354         eth_dev->process_private = (void *)dpni_dev;
2355
2356         /* For secondary processes, the primary has done all the work */
2357         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2358                 /* In case of secondary, only burst and ops API need to be
2359                  * plugged.
2360                  */
2361                 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2362                 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE))
2363                         eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2364                 else if (dpaa2_get_devargs(dev->devargs,
2365                                         DRIVER_NO_PREFETCH_MODE))
2366                         eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2367                 else
2368                         eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2369                 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2370                 return 0;
2371         }
2372
2373         dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device);
2374
2375         hw_id = dpaa2_dev->object_id;
2376         ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token);
2377         if (ret) {
2378                 DPAA2_PMD_ERR(
2379                              "Failure in opening dpni@%d with err code %d",
2380                              hw_id, ret);
2381                 rte_free(dpni_dev);
2382                 return -1;
2383         }
2384
2385         /* Clean the device first */
2386         ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token);
2387         if (ret) {
2388                 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d",
2389                               hw_id, ret);
2390                 goto init_err;
2391         }
2392
2393         ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr);
2394         if (ret) {
2395                 DPAA2_PMD_ERR(
2396                              "Failure in get dpni@%d attribute, err code %d",
2397                              hw_id, ret);
2398                 goto init_err;
2399         }
2400
2401         priv->num_rx_tc = attr.num_rx_tcs;
2402         priv->qos_entries = attr.qos_entries;
2403         priv->fs_entries = attr.fs_entries;
2404         priv->dist_queues = attr.num_queues;
2405
2406         /* only if the custom CG is enabled */
2407         if (attr.options & DPNI_OPT_CUSTOM_CG)
2408                 priv->max_cgs = attr.num_cgs;
2409         else
2410                 priv->max_cgs = 0;
2411
2412         for (i = 0; i < priv->max_cgs; i++)
2413                 priv->cgid_in_use[i] = 0;
2414
2415         for (i = 0; i < attr.num_rx_tcs; i++)
2416                 priv->nb_rx_queues += attr.num_queues;
2417
2418         /* Using number of TX queues as number of TX TCs */
2419         priv->nb_tx_queues = attr.num_tx_tcs;
2420
2421         DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d",
2422                         priv->num_rx_tc, priv->nb_rx_queues,
2423                         priv->nb_tx_queues, priv->max_cgs);
2424
2425         priv->hw = dpni_dev;
2426         priv->hw_id = hw_id;
2427         priv->options = attr.options;
2428         priv->max_mac_filters = attr.mac_filter_entries;
2429         priv->max_vlan_filters = attr.vlan_filter_entries;
2430         priv->flags = 0;
2431 #if defined(RTE_LIBRTE_IEEE1588)
2432         priv->tx_conf_en = 1;
2433 #else
2434         priv->tx_conf_en = 0;
2435 #endif
2436
2437         /* Allocate memory for hardware structure for queues */
2438         ret = dpaa2_alloc_rx_tx_queues(eth_dev);
2439         if (ret) {
2440                 DPAA2_PMD_ERR("Queue allocation Failed");
2441                 goto init_err;
2442         }
2443
2444         /* Allocate memory for storing MAC addresses.
2445          * Table of mac_filter_entries size is allocated so that RTE ether lib
2446          * can add MAC entries when rte_eth_dev_mac_addr_add is called.
2447          */
2448         eth_dev->data->mac_addrs = rte_zmalloc("dpni",
2449                 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0);
2450         if (eth_dev->data->mac_addrs == NULL) {
2451                 DPAA2_PMD_ERR(
2452                    "Failed to allocate %d bytes needed to store MAC addresses",
2453                    RTE_ETHER_ADDR_LEN * attr.mac_filter_entries);
2454                 ret = -ENOMEM;
2455                 goto init_err;
2456         }
2457
2458         ret = populate_mac_addr(dpni_dev, priv, &eth_dev->data->mac_addrs[0]);
2459         if (ret) {
2460                 DPAA2_PMD_ERR("Unable to fetch MAC Address for device");
2461                 rte_free(eth_dev->data->mac_addrs);
2462                 eth_dev->data->mac_addrs = NULL;
2463                 goto init_err;
2464         }
2465
2466         /* ... tx buffer layout ... */
2467         memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2468         if (priv->tx_conf_en) {
2469                 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2470                                  DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2471                 layout.pass_timestamp = true;
2472         } else {
2473                 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2474         }
2475         layout.pass_frame_status = 1;
2476         ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2477                                      DPNI_QUEUE_TX, &layout);
2478         if (ret) {
2479                 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret);
2480                 goto init_err;
2481         }
2482
2483         /* ... tx-conf and error buffer layout ... */
2484         memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2485         if (priv->tx_conf_en) {
2486                 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2487                                  DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2488                 layout.pass_timestamp = true;
2489         } else {
2490                 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2491         }
2492         layout.pass_frame_status = 1;
2493         ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2494                                      DPNI_QUEUE_TX_CONFIRM, &layout);
2495         if (ret) {
2496                 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout",
2497                              ret);
2498                 goto init_err;
2499         }
2500
2501         eth_dev->dev_ops = &dpaa2_ethdev_ops;
2502
2503         if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) {
2504                 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2505                 DPAA2_PMD_INFO("Loopback mode");
2506         } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) {
2507                 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2508                 DPAA2_PMD_INFO("No Prefetch mode");
2509         } else {
2510                 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2511         }
2512         eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2513
2514         /*Init fields w.r.t. classficaition*/
2515         memset(&priv->extract.qos_key_extract, 0,
2516                 sizeof(struct dpaa2_key_extract));
2517         priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64);
2518         if (!priv->extract.qos_extract_param) {
2519                 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow "
2520                             " classificaiton ", ret);
2521                 goto init_err;
2522         }
2523         priv->extract.qos_key_extract.key_info.ipv4_src_offset =
2524                 IP_ADDRESS_OFFSET_INVALID;
2525         priv->extract.qos_key_extract.key_info.ipv4_dst_offset =
2526                 IP_ADDRESS_OFFSET_INVALID;
2527         priv->extract.qos_key_extract.key_info.ipv6_src_offset =
2528                 IP_ADDRESS_OFFSET_INVALID;
2529         priv->extract.qos_key_extract.key_info.ipv6_dst_offset =
2530                 IP_ADDRESS_OFFSET_INVALID;
2531
2532         for (i = 0; i < MAX_TCS; i++) {
2533                 memset(&priv->extract.tc_key_extract[i], 0,
2534                         sizeof(struct dpaa2_key_extract));
2535                 priv->extract.tc_extract_param[i] =
2536                         (size_t)rte_malloc(NULL, 256, 64);
2537                 if (!priv->extract.tc_extract_param[i]) {
2538                         DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classificaiton",
2539                                      ret);
2540                         goto init_err;
2541                 }
2542                 priv->extract.tc_key_extract[i].key_info.ipv4_src_offset =
2543                         IP_ADDRESS_OFFSET_INVALID;
2544                 priv->extract.tc_key_extract[i].key_info.ipv4_dst_offset =
2545                         IP_ADDRESS_OFFSET_INVALID;
2546                 priv->extract.tc_key_extract[i].key_info.ipv6_src_offset =
2547                         IP_ADDRESS_OFFSET_INVALID;
2548                 priv->extract.tc_key_extract[i].key_info.ipv6_dst_offset =
2549                         IP_ADDRESS_OFFSET_INVALID;
2550         }
2551
2552         ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token,
2553                                         RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN
2554                                         + VLAN_TAG_SIZE);
2555         if (ret) {
2556                 DPAA2_PMD_ERR("Unable to set mtu. check config");
2557                 goto init_err;
2558         }
2559
2560         /*TODO To enable soft parser support DPAA2 driver needs to integrate
2561          * with external entity to receive byte code for software sequence
2562          * and same will be offload to the H/W using MC interface.
2563          * Currently it is assumed that DPAA2 driver has byte code by some
2564          * mean and same if offloaded to H/W.
2565          */
2566         if (getenv("DPAA2_ENABLE_SOFT_PARSER")) {
2567                 WRIOP_SS_INITIALIZER(priv);
2568                 ret = dpaa2_eth_load_wriop_soft_parser(priv, DPNI_SS_INGRESS);
2569                 if (ret < 0) {
2570                         DPAA2_PMD_ERR(" Error(%d) in loading softparser\n",
2571                                       ret);
2572                         return ret;
2573                 }
2574
2575                 ret = dpaa2_eth_enable_wriop_soft_parser(priv,
2576                                                          DPNI_SS_INGRESS);
2577                 if (ret < 0) {
2578                         DPAA2_PMD_ERR(" Error(%d) in enabling softparser\n",
2579                                       ret);
2580                         return ret;
2581                 }
2582         }
2583         RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name);
2584         return 0;
2585 init_err:
2586         dpaa2_dev_uninit(eth_dev);
2587         return ret;
2588 }
2589
2590 static int
2591 dpaa2_dev_uninit(struct rte_eth_dev *eth_dev)
2592 {
2593         struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2594         struct fsl_mc_io *dpni = (struct fsl_mc_io *)eth_dev->process_private;
2595         int i, ret;
2596
2597         PMD_INIT_FUNC_TRACE();
2598
2599         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2600                 return 0;
2601
2602         if (!dpni) {
2603                 DPAA2_PMD_WARN("Already closed or not started");
2604                 return -1;
2605         }
2606
2607         dpaa2_dev_close(eth_dev);
2608
2609         dpaa2_free_rx_tx_queues(eth_dev);
2610
2611         /* Close the device at underlying layer*/
2612         ret = dpni_close(dpni, CMD_PRI_LOW, priv->token);
2613         if (ret) {
2614                 DPAA2_PMD_ERR(
2615                              "Failure closing dpni device with err code %d",
2616                              ret);
2617         }
2618
2619         /* Free the allocated memory for ethernet private data and dpni*/
2620         priv->hw = NULL;
2621         eth_dev->process_private = NULL;
2622         rte_free(dpni);
2623
2624         for (i = 0; i < MAX_TCS; i++)
2625                 rte_free((void *)(size_t)priv->extract.tc_extract_param[i]);
2626
2627         if (priv->extract.qos_extract_param)
2628                 rte_free((void *)(size_t)priv->extract.qos_extract_param);
2629
2630         eth_dev->dev_ops = NULL;
2631         eth_dev->rx_pkt_burst = NULL;
2632         eth_dev->tx_pkt_burst = NULL;
2633
2634         DPAA2_PMD_INFO("%s: netdev deleted", eth_dev->data->name);
2635         return 0;
2636 }
2637
2638 static int
2639 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv,
2640                 struct rte_dpaa2_device *dpaa2_dev)
2641 {
2642         struct rte_eth_dev *eth_dev;
2643         struct dpaa2_dev_priv *dev_priv;
2644         int diag;
2645
2646         if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) >
2647                 RTE_PKTMBUF_HEADROOM) {
2648                 DPAA2_PMD_ERR(
2649                 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)",
2650                 RTE_PKTMBUF_HEADROOM,
2651                 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE);
2652
2653                 return -1;
2654         }
2655
2656         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2657                 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name);
2658                 if (!eth_dev)
2659                         return -ENODEV;
2660                 dev_priv = rte_zmalloc("ethdev private structure",
2661                                        sizeof(struct dpaa2_dev_priv),
2662                                        RTE_CACHE_LINE_SIZE);
2663                 if (dev_priv == NULL) {
2664                         DPAA2_PMD_CRIT(
2665                                 "Unable to allocate memory for private data");
2666                         rte_eth_dev_release_port(eth_dev);
2667                         return -ENOMEM;
2668                 }
2669                 eth_dev->data->dev_private = (void *)dev_priv;
2670                 /* Store a pointer to eth_dev in dev_private */
2671                 dev_priv->eth_dev = eth_dev;
2672                 dev_priv->tx_conf_en = 0;
2673         } else {
2674                 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name);
2675                 if (!eth_dev) {
2676                         DPAA2_PMD_DEBUG("returning enodev");
2677                         return -ENODEV;
2678                 }
2679         }
2680
2681         eth_dev->device = &dpaa2_dev->device;
2682
2683         dpaa2_dev->eth_dev = eth_dev;
2684         eth_dev->data->rx_mbuf_alloc_failed = 0;
2685
2686         if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC)
2687                 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2688
2689         /* Invoke PMD device initialization function */
2690         diag = dpaa2_dev_init(eth_dev);
2691         if (diag == 0) {
2692                 rte_eth_dev_probing_finish(eth_dev);
2693                 return 0;
2694         }
2695
2696         rte_eth_dev_release_port(eth_dev);
2697         return diag;
2698 }
2699
2700 static int
2701 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev)
2702 {
2703         struct rte_eth_dev *eth_dev;
2704
2705         eth_dev = dpaa2_dev->eth_dev;
2706         dpaa2_dev_uninit(eth_dev);
2707
2708         rte_eth_dev_release_port(eth_dev);
2709
2710         return 0;
2711 }
2712
2713 static struct rte_dpaa2_driver rte_dpaa2_pmd = {
2714         .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA,
2715         .drv_type = DPAA2_ETH,
2716         .probe = rte_dpaa2_probe,
2717         .remove = rte_dpaa2_remove,
2718 };
2719
2720 RTE_PMD_REGISTER_DPAA2(net_dpaa2, rte_dpaa2_pmd);
2721 RTE_PMD_REGISTER_PARAM_STRING(net_dpaa2,
2722                 DRIVER_LOOPBACK_MODE "=<int> "
2723                 DRIVER_NO_PREFETCH_MODE "=<int>");
2724 RTE_LOG_REGISTER(dpaa2_logtype_pmd, pmd.net.dpaa2, NOTICE);