drivers/net/dpaa2/dpaa2_ethdev.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright (c) 2015-2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2016-2021 NXP
   5  *
   6  */
   7
   8 #ifndef _DPAA2_ETHDEV_H
   9 #define _DPAA2_ETHDEV_H
  10
  11 #include <rte_event_eth_rx_adapter.h>
  12 #include <rte_pmd_dpaa2.h>
  13
  14 #include <dpaa2_hw_pvt.h>
  15 #include "dpaa2_tm.h"
  16
  17 #include <mc/fsl_dpni.h>
  18 #include <mc/fsl_mc_sys.h>
  19
  20 #define DPAA2_MIN_RX_BUF_SIZE 512
  21 #define DPAA2_MAX_RX_PKT_LEN  10240 /*WRIOP support*/
  22
  23 #define MAX_TCS                 DPNI_MAX_TC
  24 #define MAX_RX_QUEUES           128
  25 #define MAX_TX_QUEUES           16
  26 #define MAX_DPNI                8
  27
  28 #define DPAA2_RX_DEFAULT_NBDESC 512
  29
  30 #define DPAA2_ETH_MAX_LEN (RTE_ETHER_MTU + \
  31                            RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + \
  32                            VLAN_TAG_SIZE)
  33
  34 /*default tc to be used for ,congestion, distribution etc configuration. */
  35 #define DPAA2_DEF_TC            0
  36
  37 /* Threshold for a Tx queue to *Enter* Congestion state.
  38  */
  39 #define CONG_ENTER_TX_THRESHOLD   512
  40
  41 /* Threshold for a queue to *Exit* Congestion state.
  42  */
  43 #define CONG_EXIT_TX_THRESHOLD    480
  44
  45 #define CONG_RETRY_COUNT 18000
  46
  47 /* RX queue tail drop threshold
  48  * currently considering 64 KB packets
  49  */
  50 #define CONG_THRESHOLD_RX_BYTES_Q  (64 * 1024)
  51 #define CONG_RX_OAL     128
  52
  53 /* Size of the input SMMU mapped memory required by MC */
  54 #define DIST_PARAM_IOVA_SIZE 256
  55
  56 /* Enable TX Congestion control support
  57  * default is disable
  58  */
  59 #define DPAA2_TX_CGR_OFF        0x01
  60
  61 /* Disable RX tail drop, default is enable */
  62 #define DPAA2_RX_TAILDROP_OFF   0x04
  63 /* Tx confirmation enabled */
  64 #define DPAA2_TX_CONF_ENABLE    0x08
  65
  66 #define DPAA2_RSS_OFFLOAD_ALL ( \
  67         ETH_RSS_L2_PAYLOAD | \
  68         ETH_RSS_IP | \
  69         ETH_RSS_UDP | \
  70         ETH_RSS_TCP | \
  71         ETH_RSS_SCTP | \
  72         ETH_RSS_MPLS)
  73
  74 /* LX2 FRC Parsed values (Little Endian) */
  75 #define DPAA2_PKT_TYPE_ETHER            0x0060
  76 #define DPAA2_PKT_TYPE_IPV4             0x0000
  77 #define DPAA2_PKT_TYPE_IPV6             0x0020
  78 #define DPAA2_PKT_TYPE_IPV4_EXT \
  79                         (0x0001 | DPAA2_PKT_TYPE_IPV4)
  80 #define DPAA2_PKT_TYPE_IPV6_EXT \
  81                         (0x0001 | DPAA2_PKT_TYPE_IPV6)
  82 #define DPAA2_PKT_TYPE_IPV4_TCP \
  83                         (0x000e | DPAA2_PKT_TYPE_IPV4)
  84 #define DPAA2_PKT_TYPE_IPV6_TCP \
  85                         (0x000e | DPAA2_PKT_TYPE_IPV6)
  86 #define DPAA2_PKT_TYPE_IPV4_UDP \
  87                         (0x0010 | DPAA2_PKT_TYPE_IPV4)
  88 #define DPAA2_PKT_TYPE_IPV6_UDP \
  89                         (0x0010 | DPAA2_PKT_TYPE_IPV6)
  90 #define DPAA2_PKT_TYPE_IPV4_SCTP        \
  91                         (0x000f | DPAA2_PKT_TYPE_IPV4)
  92 #define DPAA2_PKT_TYPE_IPV6_SCTP        \
  93                         (0x000f | DPAA2_PKT_TYPE_IPV6)
  94 #define DPAA2_PKT_TYPE_IPV4_ICMP \
  95                         (0x0003 | DPAA2_PKT_TYPE_IPV4_EXT)
  96 #define DPAA2_PKT_TYPE_IPV6_ICMP \
  97                         (0x0003 | DPAA2_PKT_TYPE_IPV6_EXT)
  98 #define DPAA2_PKT_TYPE_VLAN_1           0x0160
  99 #define DPAA2_PKT_TYPE_VLAN_2           0x0260
 100
 101 /* enable timestamp in mbuf*/
 102 extern bool dpaa2_enable_ts[];
 103 extern uint64_t dpaa2_timestamp_rx_dynflag;
 104 extern int dpaa2_timestamp_dynfield_offset;
 105
 106 #define DPAA2_QOS_TABLE_RECONFIGURE     1
 107 #define DPAA2_FS_TABLE_RECONFIGURE      2
 108
 109 #define DPAA2_QOS_TABLE_IPADDR_EXTRACT 4
 110 #define DPAA2_FS_TABLE_IPADDR_EXTRACT 8
 111
 112 #define DPAA2_FLOW_MAX_KEY_SIZE         16
 113
 114 /*Externaly defined*/
 115 extern const struct rte_flow_ops dpaa2_flow_ops;
 116
 117 extern const struct rte_tm_ops dpaa2_tm_ops;
 118
 119 extern bool dpaa2_enable_err_queue;
 120
 121 #define IP_ADDRESS_OFFSET_INVALID (-1)
 122
 123 struct dpaa2_key_info {
 124         uint8_t key_offset[DPKG_MAX_NUM_OF_EXTRACTS];
 125         uint8_t key_size[DPKG_MAX_NUM_OF_EXTRACTS];
 126         /* Special for IP address. */
 127         int ipv4_src_offset;
 128         int ipv4_dst_offset;
 129         int ipv6_src_offset;
 130         int ipv6_dst_offset;
 131         uint8_t key_total_size;
 132 };
 133
 134 struct dpaa2_key_extract {
 135         struct dpkg_profile_cfg dpkg;
 136         struct dpaa2_key_info key_info;
 137 };
 138
 139 struct extract_s {
 140         struct dpaa2_key_extract qos_key_extract;
 141         struct dpaa2_key_extract tc_key_extract[MAX_TCS];
 142         uint64_t qos_extract_param;
 143         uint64_t tc_extract_param[MAX_TCS];
 144 };
 145
 146 struct dpaa2_dev_priv {
 147         void *hw;
 148         int32_t hw_id;
 149         int32_t qdid;
 150         uint16_t token;
 151         uint8_t nb_tx_queues;
 152         uint8_t nb_rx_queues;
 153         uint32_t options;
 154         void *rx_vq[MAX_RX_QUEUES];
 155         void *tx_vq[MAX_TX_QUEUES];
 156         struct dpaa2_bp_list *bp_list; /**<Attached buffer pool list */
 157         void *tx_conf_vq[MAX_TX_QUEUES];
 158         void *rx_err_vq;
 159         uint8_t flags; /*dpaa2 config flags */
 160         uint8_t max_mac_filters;
 161         uint8_t max_vlan_filters;
 162         uint8_t num_rx_tc;
 163         uint16_t qos_entries;
 164         uint16_t fs_entries;
 165         uint8_t dist_queues;
 166         uint8_t en_ordered;
 167         uint8_t en_loose_ordered;
 168         uint8_t max_cgs;
 169         uint8_t cgid_in_use[MAX_RX_QUEUES];
 170
 171         struct extract_s extract;
 172
 173         uint16_t ss_offset;
 174         uint64_t ss_iova;
 175         uint64_t ss_param_iova;
 176         /*stores timestamp of last received packet on dev*/
 177         uint64_t rx_timestamp;
 178         /*stores timestamp of last received tx confirmation packet on dev*/
 179         uint64_t tx_timestamp;
 180         /* stores pointer to next tx_conf queue that should be processed,
 181          * it corresponds to last packet transmitted
 182          */
 183         struct dpaa2_queue *next_tx_conf_queue;
 184
 185         struct rte_eth_dev *eth_dev; /**< Pointer back to holding ethdev */
 186
 187         LIST_HEAD(, rte_flow) flows; /**< Configured flow rule handles. */
 188         LIST_HEAD(nodes, dpaa2_tm_node) nodes;
 189         LIST_HEAD(shaper_profiles, dpaa2_tm_shaper_profile) shaper_profiles;
 190 };
 191
 192 int dpaa2_distset_to_dpkg_profile_cfg(uint64_t req_dist_set,
 193                                       struct dpkg_profile_cfg *kg_cfg);
 194
 195 int dpaa2_setup_flow_dist(struct rte_eth_dev *eth_dev,
 196                 uint64_t req_dist_set, int tc_index);
 197
 198 int dpaa2_remove_flow_dist(struct rte_eth_dev *eth_dev,
 199                            uint8_t tc_index);
 200
 201 int dpaa2_attach_bp_list(struct dpaa2_dev_priv *priv, void *blist);
 202
 203 __rte_internal
 204 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
 205                 int eth_rx_queue_id,
 206                 struct dpaa2_dpcon_dev *dpcon,
 207                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf);
 208
 209 __rte_internal
 210 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
 211                 int eth_rx_queue_id);
 212
 213 uint16_t dpaa2_dev_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
 214
 215 uint16_t dpaa2_dev_loopback_rx(void *queue, struct rte_mbuf **bufs,
 216                                 uint16_t nb_pkts);
 217
 218 uint16_t dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs,
 219                                uint16_t nb_pkts);
 220 void dpaa2_dev_process_parallel_event(struct qbman_swp *swp,
 221                                       const struct qbman_fd *fd,
 222                                       const struct qbman_result *dq,
 223                                       struct dpaa2_queue *rxq,
 224                                       struct rte_event *ev);
 225 void dpaa2_dev_process_atomic_event(struct qbman_swp *swp,
 226                                     const struct qbman_fd *fd,
 227                                     const struct qbman_result *dq,
 228                                     struct dpaa2_queue *rxq,
 229                                     struct rte_event *ev);
 230 void dpaa2_dev_process_ordered_event(struct qbman_swp *swp,
 231                                      const struct qbman_fd *fd,
 232                                      const struct qbman_result *dq,
 233                                      struct dpaa2_queue *rxq,
 234                                      struct rte_event *ev);
 235 uint16_t dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
 236 uint16_t dpaa2_dev_tx_ordered(void *queue, struct rte_mbuf **bufs,
 237                               uint16_t nb_pkts);
 238 uint16_t dummy_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
 239 void dpaa2_dev_free_eqresp_buf(uint16_t eqresp_ci);
 240 void dpaa2_flow_clean(struct rte_eth_dev *dev);
 241 uint16_t dpaa2_dev_tx_conf(void *queue)  __rte_unused;
 242
 243 int dpaa2_timesync_enable(struct rte_eth_dev *dev);
 244 int dpaa2_timesync_disable(struct rte_eth_dev *dev);
 245 int dpaa2_timesync_read_time(struct rte_eth_dev *dev,
 246                                         struct timespec *timestamp);
 247 int dpaa2_timesync_write_time(struct rte_eth_dev *dev,
 248                                         const struct timespec *timestamp);
 249 int dpaa2_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 250 int dpaa2_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 251                                                 struct timespec *timestamp,
 252                                                 uint32_t flags __rte_unused);
 253 int dpaa2_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 254                                           struct timespec *timestamp);
 255 #endif /* _DPAA2_ETHDEV_H */