drivers/net/dpaa2/dpaa2_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
   5  *   Copyright (c) 2016 NXP. All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Freescale Semiconductor, Inc nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <time.h>
  35 #include <net/if.h>
  36
  37 #include <rte_mbuf.h>
  38 #include <rte_ethdev.h>
  39 #include <rte_malloc.h>
  40 #include <rte_memcpy.h>
  41 #include <rte_string_fns.h>
  42 #include <rte_dev.h>
  43 #include <rte_ethdev.h>
  44
  45 #include <fslmc_logs.h>
  46 #include <fslmc_vfio.h>
  47 #include <dpaa2_hw_pvt.h>
  48 #include <dpaa2_hw_dpio.h>
  49 #include <dpaa2_hw_mempool.h>
  50
  51 #include "dpaa2_ethdev.h"
  52 #include "base/dpaa2_hw_dpni_annot.h"
  53
  54 static inline uint32_t __attribute__((hot))
  55 dpaa2_dev_rx_parse(uint64_t hw_annot_addr)
  56 {
  57         uint32_t pkt_type = RTE_PTYPE_UNKNOWN;
  58         struct dpaa2_annot_hdr *annotation =
  59                         (struct dpaa2_annot_hdr *)hw_annot_addr;
  60
  61         PMD_RX_LOG(DEBUG, "annotation = 0x%lx   ", annotation->word4);
  62
  63         if (BIT_ISSET_AT_POS(annotation->word3, L2_ARP_PRESENT)) {
  64                 pkt_type = RTE_PTYPE_L2_ETHER_ARP;
  65                 goto parse_done;
  66         } else if (BIT_ISSET_AT_POS(annotation->word3, L2_ETH_MAC_PRESENT)) {
  67                 pkt_type = RTE_PTYPE_L2_ETHER;
  68         } else {
  69                 goto parse_done;
  70         }
  71
  72         if (BIT_ISSET_AT_POS(annotation->word4, L3_IPV4_1_PRESENT |
  73                              L3_IPV4_N_PRESENT)) {
  74                 pkt_type |= RTE_PTYPE_L3_IPV4;
  75                 if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_1_OPT_PRESENT |
  76                         L3_IP_N_OPT_PRESENT))
  77                         pkt_type |= RTE_PTYPE_L3_IPV4_EXT;
  78
  79         } else if (BIT_ISSET_AT_POS(annotation->word4, L3_IPV6_1_PRESENT |
  80                   L3_IPV6_N_PRESENT)) {
  81                 pkt_type |= RTE_PTYPE_L3_IPV6;
  82                 if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_1_OPT_PRESENT |
  83                     L3_IP_N_OPT_PRESENT))
  84                         pkt_type |= RTE_PTYPE_L3_IPV6_EXT;
  85         } else {
  86                 goto parse_done;
  87         }
  88
  89         if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_1_FIRST_FRAGMENT |
  90             L3_IP_1_MORE_FRAGMENT |
  91             L3_IP_N_FIRST_FRAGMENT |
  92             L3_IP_N_MORE_FRAGMENT)) {
  93                 pkt_type |= RTE_PTYPE_L4_FRAG;
  94                 goto parse_done;
  95         } else {
  96                 pkt_type |= RTE_PTYPE_L4_NONFRAG;
  97         }
  98
  99         if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_UDP_PRESENT))
 100                 pkt_type |= RTE_PTYPE_L4_UDP;
 101
 102         else if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_TCP_PRESENT))
 103                 pkt_type |= RTE_PTYPE_L4_TCP;
 104
 105         else if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_SCTP_PRESENT))
 106                 pkt_type |= RTE_PTYPE_L4_SCTP;
 107
 108         else if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_ICMP_PRESENT))
 109                 pkt_type |= RTE_PTYPE_L4_ICMP;
 110
 111         else if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_UNKNOWN_PROTOCOL))
 112                 pkt_type |= RTE_PTYPE_UNKNOWN;
 113
 114 parse_done:
 115         return pkt_type;
 116 }
 117
 118 static inline void __attribute__((hot))
 119 dpaa2_dev_rx_offload(uint64_t hw_annot_addr, struct rte_mbuf *mbuf)
 120 {
 121         struct dpaa2_annot_hdr *annotation =
 122                 (struct dpaa2_annot_hdr *)hw_annot_addr;
 123
 124         if (BIT_ISSET_AT_POS(annotation->word3,
 125                              L2_VLAN_1_PRESENT | L2_VLAN_N_PRESENT))
 126                 mbuf->ol_flags |= PKT_RX_VLAN_PKT;
 127
 128         if (BIT_ISSET_AT_POS(annotation->word8, DPAA2_ETH_FAS_L3CE))
 129                 mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
 130
 131         if (BIT_ISSET_AT_POS(annotation->word8, DPAA2_ETH_FAS_L4CE))
 132                 mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
 133 }
 134
 135 static inline struct rte_mbuf *__attribute__((hot))
 136 eth_fd_to_mbuf(const struct qbman_fd *fd)
 137 {
 138         struct rte_mbuf *mbuf = DPAA2_INLINE_MBUF_FROM_BUF(
 139                         DPAA2_GET_FD_ADDR(fd),
 140                      rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size);
 141
 142         /* need to repopulated some of the fields,
 143          * as they may have changed in last transmission
 144          */
 145         mbuf->nb_segs = 1;
 146         mbuf->ol_flags = 0;
 147         mbuf->data_off = DPAA2_GET_FD_OFFSET(fd);
 148         mbuf->data_len = DPAA2_GET_FD_LEN(fd);
 149         mbuf->pkt_len = mbuf->data_len;
 150
 151         /* Parse the packet */
 152         /* parse results are after the private - sw annotation area */
 153         mbuf->packet_type = dpaa2_dev_rx_parse(
 154                         (uint64_t)(DPAA2_GET_FD_ADDR(fd))
 155                          + DPAA2_FD_PTA_SIZE);
 156
 157         dpaa2_dev_rx_offload((uint64_t)(DPAA2_GET_FD_ADDR(fd)) +
 158                              DPAA2_FD_PTA_SIZE, mbuf);
 159
 160         mbuf->next = NULL;
 161         rte_mbuf_refcnt_set(mbuf, 1);
 162
 163         PMD_RX_LOG(DEBUG, "to mbuf - mbuf =%p, mbuf->buf_addr =%p, off = %d,"
 164                 "fd_off=%d fd =%lx, meta = %d  bpid =%d, len=%d\n",
 165                 mbuf, mbuf->buf_addr, mbuf->data_off,
 166                 DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_ADDR(fd),
 167                 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,
 168                 DPAA2_GET_FD_BPID(fd), DPAA2_GET_FD_LEN(fd));
 169
 170         return mbuf;
 171 }
 172
 173 static void __attribute__ ((noinline)) __attribute__((hot))
 174 eth_mbuf_to_fd(struct rte_mbuf *mbuf,
 175                struct qbman_fd *fd, uint16_t bpid)
 176 {
 177         /*Resetting the buffer pool id and offset field*/
 178         fd->simple.bpid_offset = 0;
 179
 180         DPAA2_SET_FD_ADDR(fd, (mbuf->buf_addr));
 181         DPAA2_SET_FD_LEN(fd, mbuf->data_len);
 182         DPAA2_SET_FD_BPID(fd, bpid);
 183         DPAA2_SET_FD_OFFSET(fd, mbuf->data_off);
 184         DPAA2_SET_FD_ASAL(fd, DPAA2_ASAL_VAL);
 185
 186         PMD_TX_LOG(DEBUG, "mbuf =%p, mbuf->buf_addr =%p, off = %d,"
 187                 "fd_off=%d fd =%lx, meta = %d  bpid =%d, len=%d\n",
 188                 mbuf, mbuf->buf_addr, mbuf->data_off,
 189                 DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_ADDR(fd),
 190                 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,
 191                 DPAA2_GET_FD_BPID(fd), DPAA2_GET_FD_LEN(fd));
 192 }
 193
 194 uint16_t
 195 dpaa2_dev_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
 196 {
 197         /* Function is responsible to receive frames for a given device and VQ*/
 198         struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)queue;
 199         struct qbman_result *dq_storage;
 200         uint32_t fqid = dpaa2_q->fqid;
 201         int ret, num_rx = 0;
 202         uint8_t is_last = 0, status;
 203         struct qbman_swp *swp;
 204         const struct qbman_fd *fd;
 205         struct qbman_pull_desc pulldesc;
 206         struct rte_eth_dev *dev = dpaa2_q->dev;
 207
 208         if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
 209                 ret = dpaa2_affine_qbman_swp();
 210                 if (ret) {
 211                         RTE_LOG(ERR, PMD, "Failure in affining portal\n");
 212                         return 0;
 213                 }
 214         }
 215         swp = DPAA2_PER_LCORE_PORTAL;
 216         dq_storage = dpaa2_q->q_storage->dq_storage[0];
 217
 218         qbman_pull_desc_clear(&pulldesc);
 219         qbman_pull_desc_set_numframes(&pulldesc,
 220                                       (nb_pkts > DPAA2_DQRR_RING_SIZE) ?
 221                                        DPAA2_DQRR_RING_SIZE : nb_pkts);
 222         qbman_pull_desc_set_fq(&pulldesc, fqid);
 223         /* todo optimization - we can have dq_storage_phys available*/
 224         qbman_pull_desc_set_storage(&pulldesc, dq_storage,
 225                         (dma_addr_t)(dq_storage), 1);
 226
 227         /*Issue a volatile dequeue command. */
 228         while (1) {
 229                 if (qbman_swp_pull(swp, &pulldesc)) {
 230                         PMD_RX_LOG(ERR, "VDQ command is not issued."
 231                                    "QBMAN is busy\n");
 232                         /* Portal was busy, try again */
 233                         continue;
 234                 }
 235                 break;
 236         };
 237
 238         /* Receive the packets till Last Dequeue entry is found with
 239          * respect to the above issues PULL command.
 240          */
 241         while (!is_last) {
 242                 struct rte_mbuf *mbuf;
 243                 /*Check if the previous issued command is completed.
 244                  * Also seems like the SWP is shared between the
 245                  * Ethernet Driver and the SEC driver.
 246                  */
 247                 while (!qbman_check_command_complete(swp, dq_storage))
 248                         ;
 249                 /* Loop until the dq_storage is updated with
 250                  * new token by QBMAN
 251                  */
 252                 while (!qbman_result_has_new_result(swp, dq_storage))
 253                         ;
 254                 /* Check whether Last Pull command is Expired and
 255                  * setting Condition for Loop termination
 256                  */
 257                 if (qbman_result_DQ_is_pull_complete(dq_storage)) {
 258                         is_last = 1;
 259                         /* Check for valid frame. */
 260                         status = (uint8_t)qbman_result_DQ_flags(dq_storage);
 261                         if (unlikely((status & QBMAN_DQ_STAT_VALIDFRAME) == 0))
 262                                 continue;
 263                 }
 264
 265                 fd = qbman_result_DQ_fd(dq_storage);
 266                 mbuf = (struct rte_mbuf *)(DPAA2_GET_FD_ADDR(fd)
 267                    - rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size);
 268                 /* Prefeth mbuf */
 269                 rte_prefetch0(mbuf);
 270                 /* Prefetch Annotation address for the parse results */
 271                 rte_prefetch0((void *)((uint64_t)DPAA2_GET_FD_ADDR(fd)
 272                                                 + DPAA2_FD_PTA_SIZE + 16));
 273
 274                 bufs[num_rx] = eth_fd_to_mbuf(fd);
 275                 bufs[num_rx]->port = dev->data->port_id;
 276
 277                 num_rx++;
 278                 dq_storage++;
 279         } /* End of Packet Rx loop */
 280
 281         dpaa2_q->rx_pkts += num_rx;
 282
 283         /*Return the total number of packets received to DPAA2 app*/
 284         return num_rx;
 285 }
 286
 287 /*
 288  * Callback to handle sending packets through WRIOP based interface
 289  */
 290 uint16_t
 291 dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
 292 {
 293         /* Function to transmit the frames to given device and VQ*/
 294         uint32_t loop;
 295         int32_t ret;
 296         struct qbman_fd fd_arr[MAX_TX_RING_SLOTS];
 297         uint32_t frames_to_send;
 298         struct rte_mempool *mp;
 299         struct qbman_eq_desc eqdesc;
 300         struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)queue;
 301         struct qbman_swp *swp;
 302         uint16_t num_tx = 0;
 303         uint16_t bpid;
 304         struct rte_eth_dev *dev = dpaa2_q->dev;
 305         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 306
 307         if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
 308                 ret = dpaa2_affine_qbman_swp();
 309                 if (ret) {
 310                         RTE_LOG(ERR, PMD, "Failure in affining portal\n");
 311                         return 0;
 312                 }
 313         }
 314         swp = DPAA2_PER_LCORE_PORTAL;
 315
 316         PMD_TX_LOG(DEBUG, "===> dev =%p, fqid =%d", dev, dpaa2_q->fqid);
 317
 318         /*Prepare enqueue descriptor*/
 319         qbman_eq_desc_clear(&eqdesc);
 320         qbman_eq_desc_set_no_orp(&eqdesc, DPAA2_EQ_RESP_ERR_FQ);
 321         qbman_eq_desc_set_response(&eqdesc, 0, 0);
 322         qbman_eq_desc_set_qd(&eqdesc, priv->qdid,
 323                              dpaa2_q->flow_id, dpaa2_q->tc_index);
 324
 325         /*Clear the unused FD fields before sending*/
 326         while (nb_pkts) {
 327                 frames_to_send = (nb_pkts >> 3) ? MAX_TX_RING_SLOTS : nb_pkts;
 328
 329                 for (loop = 0; loop < frames_to_send; loop++) {
 330                         fd_arr[loop].simple.frc = 0;
 331                         DPAA2_RESET_FD_CTRL((&fd_arr[loop]));
 332                         DPAA2_SET_FD_FLC((&fd_arr[loop]), NULL);
 333                         mp = (*bufs)->pool;
 334                         bpid = mempool_to_bpid(mp);
 335                         eth_mbuf_to_fd(*bufs, &fd_arr[loop], bpid);
 336                         bufs++;
 337                 }
 338                 loop = 0;
 339                 while (loop < frames_to_send) {
 340                         loop += qbman_swp_send_multiple(swp, &eqdesc,
 341                                         &fd_arr[loop], frames_to_send - loop);
 342                 }
 343
 344                 num_tx += frames_to_send;
 345                 dpaa2_q->tx_pkts += frames_to_send;
 346                 nb_pkts -= frames_to_send;
 347         }
 348         return num_tx;
 349 }