drivers/net/dpaa2/dpaa2_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2016 NXP
   5  *
   6  */
   7
   8 #include <time.h>
   9 #include <net/if.h>
  10
  11 #include <rte_mbuf.h>
  12 #include <rte_ethdev.h>
  13 #include <rte_malloc.h>
  14 #include <rte_memcpy.h>
  15 #include <rte_string_fns.h>
  16 #include <rte_dev.h>
  17
  18 #include <rte_fslmc.h>
  19 #include <fslmc_logs.h>
  20 #include <fslmc_vfio.h>
  21 #include <dpaa2_hw_pvt.h>
  22 #include <dpaa2_hw_dpio.h>
  23 #include <dpaa2_hw_mempool.h>
  24 #include <dpaa2_eventdev.h>
  25
  26 #include "dpaa2_ethdev.h"
  27 #include "base/dpaa2_hw_dpni_annot.h"
  28
  29 #define DPAA2_MBUF_TO_CONTIG_FD(_mbuf, _fd, _bpid)  do { \
  30         DPAA2_SET_FD_ADDR(_fd, DPAA2_MBUF_VADDR_TO_IOVA(_mbuf)); \
  31         DPAA2_SET_FD_LEN(_fd, _mbuf->data_len); \
  32         DPAA2_SET_ONLY_FD_BPID(_fd, _bpid); \
  33         DPAA2_SET_FD_OFFSET(_fd, _mbuf->data_off); \
  34         DPAA2_SET_FD_ASAL(_fd, DPAA2_ASAL_VAL); \
  35 } while (0)
  36
  37 static inline void __attribute__((hot))
  38 dpaa2_dev_rx_parse_frc(struct rte_mbuf *m, uint16_t frc)
  39 {
  40         PMD_RX_LOG(DEBUG, "frc = 0x%x   ", frc);
  41
  42         m->packet_type = RTE_PTYPE_UNKNOWN;
  43         switch (frc) {
  44         case DPAA2_PKT_TYPE_ETHER:
  45                 m->packet_type = RTE_PTYPE_L2_ETHER;
  46                 break;
  47         case DPAA2_PKT_TYPE_IPV4:
  48                 m->packet_type = RTE_PTYPE_L2_ETHER |
  49                         RTE_PTYPE_L3_IPV4;
  50                 break;
  51         case DPAA2_PKT_TYPE_IPV6:
  52                 m->packet_type = RTE_PTYPE_L2_ETHER |
  53                         RTE_PTYPE_L3_IPV6;
  54                 break;
  55         case DPAA2_PKT_TYPE_IPV4_EXT:
  56                 m->packet_type = RTE_PTYPE_L2_ETHER |
  57                         RTE_PTYPE_L3_IPV4_EXT;
  58                 break;
  59         case DPAA2_PKT_TYPE_IPV6_EXT:
  60                 m->packet_type = RTE_PTYPE_L2_ETHER |
  61                         RTE_PTYPE_L3_IPV6_EXT;
  62                 break;
  63         case DPAA2_PKT_TYPE_IPV4_TCP:
  64                 m->packet_type = RTE_PTYPE_L2_ETHER |
  65                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP;
  66                 break;
  67         case DPAA2_PKT_TYPE_IPV6_TCP:
  68                 m->packet_type = RTE_PTYPE_L2_ETHER |
  69                         RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP;
  70                 break;
  71         case DPAA2_PKT_TYPE_IPV4_UDP:
  72                 m->packet_type = RTE_PTYPE_L2_ETHER |
  73                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP;
  74                 break;
  75         case DPAA2_PKT_TYPE_IPV6_UDP:
  76                 m->packet_type = RTE_PTYPE_L2_ETHER |
  77                         RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP;
  78                 break;
  79         case DPAA2_PKT_TYPE_IPV4_SCTP:
  80                 m->packet_type = RTE_PTYPE_L2_ETHER |
  81                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_SCTP;
  82                 break;
  83         case DPAA2_PKT_TYPE_IPV6_SCTP:
  84                 m->packet_type = RTE_PTYPE_L2_ETHER |
  85                         RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_SCTP;
  86                 break;
  87         case DPAA2_PKT_TYPE_IPV4_ICMP:
  88                 m->packet_type = RTE_PTYPE_L2_ETHER |
  89                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_ICMP;
  90                 break;
  91         case DPAA2_PKT_TYPE_IPV6_ICMP:
  92                 m->packet_type = RTE_PTYPE_L2_ETHER |
  93                         RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_ICMP;
  94                 break;
  95         case DPAA2_PKT_TYPE_VLAN_1:
  96         case DPAA2_PKT_TYPE_VLAN_2:
  97                 m->ol_flags |= PKT_RX_VLAN;
  98                 break;
  99         /* More switch cases can be added */
 100         /* TODO: Add handling for checksum error check from FRC */
 101         default:
 102                 m->packet_type = RTE_PTYPE_UNKNOWN;
 103         }
 104 }
 105
 106 static inline uint32_t __attribute__((hot))
 107 dpaa2_dev_rx_parse_slow(uint64_t hw_annot_addr)
 108 {
 109         uint32_t pkt_type = RTE_PTYPE_UNKNOWN;
 110         struct dpaa2_annot_hdr *annotation =
 111                         (struct dpaa2_annot_hdr *)hw_annot_addr;
 112
 113         PMD_RX_LOG(DEBUG, "annotation = 0x%lx   ", annotation->word4);
 114         if (BIT_ISSET_AT_POS(annotation->word3, L2_ARP_PRESENT)) {
 115                 pkt_type = RTE_PTYPE_L2_ETHER_ARP;
 116                 goto parse_done;
 117         } else if (BIT_ISSET_AT_POS(annotation->word3, L2_ETH_MAC_PRESENT)) {
 118                 pkt_type = RTE_PTYPE_L2_ETHER;
 119         } else {
 120                 goto parse_done;
 121         }
 122
 123         if (BIT_ISSET_AT_POS(annotation->word4, L3_IPV4_1_PRESENT |
 124                              L3_IPV4_N_PRESENT)) {
 125                 pkt_type |= RTE_PTYPE_L3_IPV4;
 126                 if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_1_OPT_PRESENT |
 127                         L3_IP_N_OPT_PRESENT))
 128                         pkt_type |= RTE_PTYPE_L3_IPV4_EXT;
 129
 130         } else if (BIT_ISSET_AT_POS(annotation->word4, L3_IPV6_1_PRESENT |
 131                   L3_IPV6_N_PRESENT)) {
 132                 pkt_type |= RTE_PTYPE_L3_IPV6;
 133                 if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_1_OPT_PRESENT |
 134                     L3_IP_N_OPT_PRESENT))
 135                         pkt_type |= RTE_PTYPE_L3_IPV6_EXT;
 136         } else {
 137                 goto parse_done;
 138         }
 139
 140         if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_1_FIRST_FRAGMENT |
 141             L3_IP_1_MORE_FRAGMENT |
 142             L3_IP_N_FIRST_FRAGMENT |
 143             L3_IP_N_MORE_FRAGMENT)) {
 144                 pkt_type |= RTE_PTYPE_L4_FRAG;
 145                 goto parse_done;
 146         } else {
 147                 pkt_type |= RTE_PTYPE_L4_NONFRAG;
 148         }
 149
 150         if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_UDP_PRESENT))
 151                 pkt_type |= RTE_PTYPE_L4_UDP;
 152
 153         else if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_TCP_PRESENT))
 154                 pkt_type |= RTE_PTYPE_L4_TCP;
 155
 156         else if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_SCTP_PRESENT))
 157                 pkt_type |= RTE_PTYPE_L4_SCTP;
 158
 159         else if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_ICMP_PRESENT))
 160                 pkt_type |= RTE_PTYPE_L4_ICMP;
 161
 162         else if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_UNKNOWN_PROTOCOL))
 163                 pkt_type |= RTE_PTYPE_UNKNOWN;
 164
 165 parse_done:
 166         return pkt_type;
 167 }
 168
 169
 170 static inline uint32_t __attribute__((hot))
 171 dpaa2_dev_rx_parse(uint64_t hw_annot_addr)
 172 {
 173         struct dpaa2_annot_hdr *annotation =
 174                         (struct dpaa2_annot_hdr *)hw_annot_addr;
 175
 176         PMD_RX_LOG(DEBUG, "annotation = 0x%lx   ", annotation->word4);
 177
 178         /* Return some common types from parse processing */
 179         switch (annotation->word4) {
 180         case DPAA2_L3_IPv4:
 181                 return RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4;
 182         case DPAA2_L3_IPv6:
 183                 return  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6;
 184         case DPAA2_L3_IPv4_TCP:
 185                 return  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4 |
 186                                 RTE_PTYPE_L4_TCP;
 187         case DPAA2_L3_IPv4_UDP:
 188                 return  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4 |
 189                                 RTE_PTYPE_L4_UDP;
 190         case DPAA2_L3_IPv6_TCP:
 191                 return  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6 |
 192                                 RTE_PTYPE_L4_TCP;
 193         case DPAA2_L3_IPv6_UDP:
 194                 return  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6 |
 195                                 RTE_PTYPE_L4_UDP;
 196         default:
 197                 PMD_RX_LOG(DEBUG, "Slow parse the parsing results\n");
 198                 break;
 199         }
 200
 201         return dpaa2_dev_rx_parse_slow(hw_annot_addr);
 202 }
 203
 204 static inline void __attribute__((hot))
 205 dpaa2_dev_rx_offload(uint64_t hw_annot_addr, struct rte_mbuf *mbuf)
 206 {
 207         struct dpaa2_annot_hdr *annotation =
 208                 (struct dpaa2_annot_hdr *)hw_annot_addr;
 209
 210         if (BIT_ISSET_AT_POS(annotation->word3,
 211                              L2_VLAN_1_PRESENT | L2_VLAN_N_PRESENT))
 212                 mbuf->ol_flags |= PKT_RX_VLAN;
 213
 214         if (BIT_ISSET_AT_POS(annotation->word8, DPAA2_ETH_FAS_L3CE))
 215                 mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
 216
 217         if (BIT_ISSET_AT_POS(annotation->word8, DPAA2_ETH_FAS_L4CE))
 218                 mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
 219 }
 220
 221 static inline struct rte_mbuf *__attribute__((hot))
 222 eth_sg_fd_to_mbuf(const struct qbman_fd *fd)
 223 {
 224         struct qbman_sge *sgt, *sge;
 225         dma_addr_t sg_addr;
 226         int i = 0;
 227         uint64_t fd_addr;
 228         struct rte_mbuf *first_seg, *next_seg, *cur_seg, *temp;
 229
 230         fd_addr = (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd));
 231
 232         /* Get Scatter gather table address */
 233         sgt = (struct qbman_sge *)(fd_addr + DPAA2_GET_FD_OFFSET(fd));
 234
 235         sge = &sgt[i++];
 236         sg_addr = (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FLE_ADDR(sge));
 237
 238         /* First Scatter gather entry */
 239         first_seg = DPAA2_INLINE_MBUF_FROM_BUF(sg_addr,
 240                 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size);
 241         /* Prepare all the metadata for first segment */
 242         first_seg->buf_addr = (uint8_t *)sg_addr;
 243         first_seg->ol_flags = 0;
 244         first_seg->data_off = DPAA2_GET_FLE_OFFSET(sge);
 245         first_seg->data_len = sge->length  & 0x1FFFF;
 246         first_seg->pkt_len = DPAA2_GET_FD_LEN(fd);
 247         first_seg->nb_segs = 1;
 248         first_seg->next = NULL;
 249         if (dpaa2_svr_family == SVR_LX2160A)
 250                 dpaa2_dev_rx_parse_frc(first_seg,
 251                                 DPAA2_GET_FD_FRC_PARSE_SUM(fd));
 252         else {
 253                 first_seg->packet_type = dpaa2_dev_rx_parse(
 254                          (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
 255                          + DPAA2_FD_PTA_SIZE);
 256                 dpaa2_dev_rx_offload((uint64_t)DPAA2_IOVA_TO_VADDR(
 257                         DPAA2_GET_FD_ADDR(fd)) +
 258                         DPAA2_FD_PTA_SIZE, first_seg);
 259         }
 260         rte_mbuf_refcnt_set(first_seg, 1);
 261         cur_seg = first_seg;
 262         while (!DPAA2_SG_IS_FINAL(sge)) {
 263                 sge = &sgt[i++];
 264                 sg_addr = (uint64_t)DPAA2_IOVA_TO_VADDR(
 265                                 DPAA2_GET_FLE_ADDR(sge));
 266                 next_seg = DPAA2_INLINE_MBUF_FROM_BUF(sg_addr,
 267                         rte_dpaa2_bpid_info[DPAA2_GET_FLE_BPID(sge)].meta_data_size);
 268                 next_seg->buf_addr  = (uint8_t *)sg_addr;
 269                 next_seg->data_off  = DPAA2_GET_FLE_OFFSET(sge);
 270                 next_seg->data_len  = sge->length  & 0x1FFFF;
 271                 first_seg->nb_segs += 1;
 272                 rte_mbuf_refcnt_set(next_seg, 1);
 273                 cur_seg->next = next_seg;
 274                 next_seg->next = NULL;
 275                 cur_seg = next_seg;
 276         }
 277         temp = DPAA2_INLINE_MBUF_FROM_BUF(fd_addr,
 278                 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size);
 279         rte_mbuf_refcnt_set(temp, 1);
 280         rte_pktmbuf_free_seg(temp);
 281
 282         return (void *)first_seg;
 283 }
 284
 285 static inline struct rte_mbuf *__attribute__((hot))
 286 eth_fd_to_mbuf(const struct qbman_fd *fd)
 287 {
 288         struct rte_mbuf *mbuf = DPAA2_INLINE_MBUF_FROM_BUF(
 289                 DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)),
 290                      rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size);
 291
 292         /* need to repopulated some of the fields,
 293          * as they may have changed in last transmission
 294          */
 295         mbuf->nb_segs = 1;
 296         mbuf->ol_flags = 0;
 297         mbuf->data_off = DPAA2_GET_FD_OFFSET(fd);
 298         mbuf->data_len = DPAA2_GET_FD_LEN(fd);
 299         mbuf->pkt_len = mbuf->data_len;
 300         mbuf->next = NULL;
 301         rte_mbuf_refcnt_set(mbuf, 1);
 302
 303         /* Parse the packet */
 304         /* parse results for LX2 are there in FRC field of FD.
 305          * For other DPAA2 platforms , parse results are after
 306          * the private - sw annotation area
 307          */
 308
 309         if (dpaa2_svr_family == SVR_LX2160A)
 310                 dpaa2_dev_rx_parse_frc(mbuf, DPAA2_GET_FD_FRC_PARSE_SUM(fd));
 311         else {
 312                 mbuf->packet_type = dpaa2_dev_rx_parse(
 313                         (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
 314                          + DPAA2_FD_PTA_SIZE);
 315                 dpaa2_dev_rx_offload((uint64_t)DPAA2_IOVA_TO_VADDR(
 316                              DPAA2_GET_FD_ADDR(fd)) +
 317                              DPAA2_FD_PTA_SIZE, mbuf);
 318         }
 319
 320         PMD_RX_LOG(DEBUG, "to mbuf - mbuf =%p, mbuf->buf_addr =%p, off = %d,"
 321                 "fd_off=%d fd =%lx, meta = %d  bpid =%d, len=%d\n",
 322                 mbuf, mbuf->buf_addr, mbuf->data_off,
 323                 DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_ADDR(fd),
 324                 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,
 325                 DPAA2_GET_FD_BPID(fd), DPAA2_GET_FD_LEN(fd));
 326
 327         return mbuf;
 328 }
 329
 330 static int __attribute__ ((noinline)) __attribute__((hot))
 331 eth_mbuf_to_sg_fd(struct rte_mbuf *mbuf,
 332                   struct qbman_fd *fd, uint16_t bpid)
 333 {
 334         struct rte_mbuf *cur_seg = mbuf, *prev_seg, *mi, *temp;
 335         struct qbman_sge *sgt, *sge = NULL;
 336         int i;
 337
 338         /* First Prepare FD to be transmited*/
 339         /* Resetting the buffer pool id and offset field*/
 340         fd->simple.bpid_offset = 0;
 341
 342         if (unlikely(mbuf->ol_flags & PKT_TX_VLAN_PKT)) {
 343                 int ret = rte_vlan_insert(&mbuf);
 344                 if (ret)
 345                         return ret;
 346         }
 347
 348         temp = rte_pktmbuf_alloc(mbuf->pool);
 349         if (temp == NULL) {
 350                 PMD_TX_LOG(ERR, "No memory to allocate S/G table");
 351                 return -ENOMEM;
 352         }
 353
 354         DPAA2_SET_FD_ADDR(fd, DPAA2_MBUF_VADDR_TO_IOVA(temp));
 355         DPAA2_SET_FD_LEN(fd, mbuf->pkt_len);
 356         DPAA2_SET_FD_OFFSET(fd, temp->data_off);
 357         DPAA2_SET_FD_BPID(fd, bpid);
 358         DPAA2_SET_FD_ASAL(fd, DPAA2_ASAL_VAL);
 359         DPAA2_FD_SET_FORMAT(fd, qbman_fd_sg);
 360         /*Set Scatter gather table and Scatter gather entries*/
 361         sgt = (struct qbman_sge *)(
 362                         (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
 363                         + DPAA2_GET_FD_OFFSET(fd));
 364
 365         for (i = 0; i < mbuf->nb_segs; i++) {
 366                 sge = &sgt[i];
 367                 /*Resetting the buffer pool id and offset field*/
 368                 sge->fin_bpid_offset = 0;
 369                 DPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(cur_seg));
 370                 DPAA2_SET_FLE_OFFSET(sge, cur_seg->data_off);
 371                 sge->length = cur_seg->data_len;
 372                 if (RTE_MBUF_DIRECT(cur_seg)) {
 373                         if (rte_mbuf_refcnt_read(cur_seg) > 1) {
 374                                 /* If refcnt > 1, invalid bpid is set to ensure
 375                                  * buffer is not freed by HW
 376                                  */
 377                                 DPAA2_SET_FLE_IVP(sge);
 378                                 rte_mbuf_refcnt_update(cur_seg, -1);
 379                         } else
 380                                 DPAA2_SET_FLE_BPID(sge,
 381                                                 mempool_to_bpid(cur_seg->pool));
 382                         cur_seg = cur_seg->next;
 383                 } else {
 384                         /* Get owner MBUF from indirect buffer */
 385                         mi = rte_mbuf_from_indirect(cur_seg);
 386                         if (rte_mbuf_refcnt_read(mi) > 1) {
 387                                 /* If refcnt > 1, invalid bpid is set to ensure
 388                                  * owner buffer is not freed by HW
 389                                  */
 390                                 DPAA2_SET_FLE_IVP(sge);
 391                         } else {
 392                                 DPAA2_SET_FLE_BPID(sge,
 393                                                    mempool_to_bpid(mi->pool));
 394                                 rte_mbuf_refcnt_update(mi, 1);
 395                         }
 396                         prev_seg = cur_seg;
 397                         cur_seg = cur_seg->next;
 398                         prev_seg->next = NULL;
 399                         rte_pktmbuf_free(prev_seg);
 400                 }
 401         }
 402         DPAA2_SG_SET_FINAL(sge, true);
 403         return 0;
 404 }
 405
 406 static void
 407 eth_mbuf_to_fd(struct rte_mbuf *mbuf,
 408                struct qbman_fd *fd, uint16_t bpid) __attribute__((unused));
 409
 410 static void __attribute__ ((noinline)) __attribute__((hot))
 411 eth_mbuf_to_fd(struct rte_mbuf *mbuf,
 412                struct qbman_fd *fd, uint16_t bpid)
 413 {
 414         if (unlikely(mbuf->ol_flags & PKT_TX_VLAN_PKT)) {
 415                 if (rte_vlan_insert(&mbuf)) {
 416                         rte_pktmbuf_free(mbuf);
 417                         return;
 418                 }
 419         }
 420         /*Resetting the buffer pool id and offset field*/
 421         fd->simple.bpid_offset = 0;
 422
 423         DPAA2_MBUF_TO_CONTIG_FD(mbuf, fd, bpid);
 424
 425         PMD_TX_LOG(DEBUG, "mbuf =%p, mbuf->buf_addr =%p, off = %d,"
 426                 "fd_off=%d fd =%lx, meta = %d  bpid =%d, len=%d\n",
 427                 mbuf, mbuf->buf_addr, mbuf->data_off,
 428                 DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_ADDR(fd),
 429                 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,
 430                 DPAA2_GET_FD_BPID(fd), DPAA2_GET_FD_LEN(fd));
 431         if (RTE_MBUF_DIRECT(mbuf)) {
 432                 if (rte_mbuf_refcnt_read(mbuf) > 1) {
 433                         DPAA2_SET_FD_IVP(fd);
 434                         rte_mbuf_refcnt_update(mbuf, -1);
 435                 }
 436         } else {
 437                 struct rte_mbuf *mi;
 438
 439                 mi = rte_mbuf_from_indirect(mbuf);
 440                 if (rte_mbuf_refcnt_read(mi) > 1)
 441                         DPAA2_SET_FD_IVP(fd);
 442                 else
 443                         rte_mbuf_refcnt_update(mi, 1);
 444                 rte_pktmbuf_free(mbuf);
 445         }
 446 }
 447
 448 static inline int __attribute__((hot))
 449 eth_copy_mbuf_to_fd(struct rte_mbuf *mbuf,
 450                     struct qbman_fd *fd, uint16_t bpid)
 451 {
 452         struct rte_mbuf *m;
 453         void *mb = NULL;
 454
 455         if (unlikely(mbuf->ol_flags & PKT_TX_VLAN_PKT)) {
 456                 int ret = rte_vlan_insert(&mbuf);
 457                 if (ret)
 458                         return ret;
 459         }
 460
 461         if (rte_dpaa2_mbuf_alloc_bulk(
 462                 rte_dpaa2_bpid_info[bpid].bp_list->mp, &mb, 1)) {
 463                 PMD_TX_LOG(WARNING, "Unable to allocated DPAA2 buffer");
 464                 return -1;
 465         }
 466         m = (struct rte_mbuf *)mb;
 467         memcpy((char *)m->buf_addr + mbuf->data_off,
 468                (void *)((char *)mbuf->buf_addr + mbuf->data_off),
 469                 mbuf->pkt_len);
 470
 471         /* Copy required fields */
 472         m->data_off = mbuf->data_off;
 473         m->ol_flags = mbuf->ol_flags;
 474         m->packet_type = mbuf->packet_type;
 475         m->tx_offload = mbuf->tx_offload;
 476
 477         /*Resetting the buffer pool id and offset field*/
 478         fd->simple.bpid_offset = 0;
 479
 480         DPAA2_MBUF_TO_CONTIG_FD(m, fd, bpid);
 481
 482         PMD_TX_LOG(DEBUG, " mbuf %p BMAN buf addr %p",
 483                    (void *)mbuf, mbuf->buf_addr);
 484
 485         PMD_TX_LOG(DEBUG, " fdaddr =%lx bpid =%d meta =%d off =%d, len =%d",
 486                    DPAA2_GET_FD_ADDR(fd),
 487                 DPAA2_GET_FD_BPID(fd),
 488                 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,
 489                 DPAA2_GET_FD_OFFSET(fd),
 490                 DPAA2_GET_FD_LEN(fd));
 491
 492         return 0;
 493 }
 494
 495 uint16_t
 496 dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
 497 {
 498         /* Function receive frames for a given device and VQ*/
 499         struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)queue;
 500         struct qbman_result *dq_storage;
 501         uint32_t fqid = dpaa2_q->fqid;
 502         int ret, num_rx = 0;
 503         uint8_t is_last = 0, status;
 504         struct qbman_swp *swp;
 505         const struct qbman_fd *fd[DPAA2_DQRR_RING_SIZE], *next_fd;
 506         struct qbman_pull_desc pulldesc;
 507         struct queue_storage_info_t *q_storage = dpaa2_q->q_storage;
 508         struct rte_eth_dev *dev = dpaa2_q->dev;
 509
 510         if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
 511                 ret = dpaa2_affine_qbman_swp();
 512                 if (ret) {
 513                         RTE_LOG(ERR, PMD, "Failure in affining portal\n");
 514                         return 0;
 515                 }
 516         }
 517         swp = DPAA2_PER_LCORE_PORTAL;
 518         if (!q_storage->active_dqs) {
 519                 q_storage->toggle = 0;
 520                 dq_storage = q_storage->dq_storage[q_storage->toggle];
 521                 qbman_pull_desc_clear(&pulldesc);
 522                 qbman_pull_desc_set_numframes(&pulldesc,
 523                                               (nb_pkts > DPAA2_DQRR_RING_SIZE) ?
 524                                                DPAA2_DQRR_RING_SIZE : nb_pkts);
 525                 qbman_pull_desc_set_fq(&pulldesc, fqid);
 526                 qbman_pull_desc_set_storage(&pulldesc, dq_storage,
 527                         (dma_addr_t)(DPAA2_VADDR_TO_IOVA(dq_storage)), 1);
 528                 if (check_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index)) {
 529                         while (!qbman_check_command_complete(
 530                                get_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index)))
 531                                 ;
 532                         clear_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index);
 533                 }
 534                 while (1) {
 535                         if (qbman_swp_pull(swp, &pulldesc)) {
 536                                 PMD_RX_LOG(WARNING, "VDQ command is not issued."
 537                                            "QBMAN is busy\n");
 538                                 /* Portal was busy, try again */
 539                                 continue;
 540                         }
 541                         break;
 542                 }
 543                 q_storage->active_dqs = dq_storage;
 544                 q_storage->active_dpio_id = DPAA2_PER_LCORE_DPIO->index;
 545                 set_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index, dq_storage);
 546         }
 547         dq_storage = q_storage->active_dqs;
 548         rte_prefetch0((void *)((uint64_t)(dq_storage + 1)));
 549         /* Check if the previous issued command is completed.
 550          * Also seems like the SWP is shared between the Ethernet Driver
 551          * and the SEC driver.
 552          */
 553         while (!qbman_check_command_complete(dq_storage))
 554                 ;
 555         if (dq_storage == get_swp_active_dqs(q_storage->active_dpio_id))
 556                 clear_swp_active_dqs(q_storage->active_dpio_id);
 557         while (!is_last) {
 558                 /* Loop until the dq_storage is updated with
 559                  * new token by QBMAN
 560                  */
 561                 while (!qbman_check_new_result(dq_storage))
 562                         ;
 563                 rte_prefetch0((void *)((uint64_t)(dq_storage + 2)));
 564                 /* Check whether Last Pull command is Expired and
 565                  * setting Condition for Loop termination
 566                  */
 567                 if (qbman_result_DQ_is_pull_complete(dq_storage)) {
 568                         is_last = 1;
 569                         /* Check for valid frame. */
 570                         status = (uint8_t)qbman_result_DQ_flags(dq_storage);
 571                         if (unlikely((status & QBMAN_DQ_STAT_VALIDFRAME) == 0))
 572                                 continue;
 573                 }
 574                 fd[num_rx] = qbman_result_DQ_fd(dq_storage);
 575
 576                 next_fd = qbman_result_DQ_fd(dq_storage + 1);
 577                 /* Prefetch Annotation address for the parse results */
 578                 rte_prefetch0((void *)((uint64_t)DPAA2_GET_FD_ADDR(next_fd)
 579                                 + DPAA2_FD_PTA_SIZE + 16));
 580
 581                 if (unlikely(DPAA2_FD_GET_FORMAT(fd[num_rx]) == qbman_fd_sg))
 582                         bufs[num_rx] = eth_sg_fd_to_mbuf(fd[num_rx]);
 583                 else
 584                         bufs[num_rx] = eth_fd_to_mbuf(fd[num_rx]);
 585                 bufs[num_rx]->port = dev->data->port_id;
 586
 587                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
 588                         rte_vlan_strip(bufs[num_rx]);
 589
 590                 dq_storage++;
 591                 num_rx++;
 592         }
 593
 594         if (check_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index)) {
 595                 while (!qbman_check_command_complete(
 596                        get_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index)))
 597                         ;
 598                 clear_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index);
 599         }
 600         q_storage->toggle ^= 1;
 601         dq_storage = q_storage->dq_storage[q_storage->toggle];
 602         qbman_pull_desc_clear(&pulldesc);
 603         qbman_pull_desc_set_numframes(&pulldesc, DPAA2_DQRR_RING_SIZE);
 604         qbman_pull_desc_set_fq(&pulldesc, fqid);
 605         qbman_pull_desc_set_storage(&pulldesc, dq_storage,
 606                         (dma_addr_t)(DPAA2_VADDR_TO_IOVA(dq_storage)), 1);
 607         /* Issue a volatile dequeue command. */
 608         while (1) {
 609                 if (qbman_swp_pull(swp, &pulldesc)) {
 610                         PMD_RX_LOG(WARNING, "VDQ command is not issued."
 611                                    "QBMAN is busy\n");
 612                         continue;
 613                 }
 614                 break;
 615         }
 616         q_storage->active_dqs = dq_storage;
 617         q_storage->active_dpio_id = DPAA2_PER_LCORE_DPIO->index;
 618         set_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index, dq_storage);
 619
 620         dpaa2_q->rx_pkts += num_rx;
 621
 622         /* Return the total number of packets received to DPAA2 app */
 623         return num_rx;
 624 }
 625
 626 void __attribute__((hot))
 627 dpaa2_dev_process_parallel_event(struct qbman_swp *swp,
 628                                  const struct qbman_fd *fd,
 629                                  const struct qbman_result *dq,
 630                                  struct dpaa2_queue *rxq,
 631                                  struct rte_event *ev)
 632 {
 633         ev->mbuf = eth_fd_to_mbuf(fd);
 634
 635         ev->flow_id = rxq->ev.flow_id;
 636         ev->sub_event_type = rxq->ev.sub_event_type;
 637         ev->event_type = RTE_EVENT_TYPE_ETHDEV;
 638         ev->op = RTE_EVENT_OP_NEW;
 639         ev->sched_type = rxq->ev.sched_type;
 640         ev->queue_id = rxq->ev.queue_id;
 641         ev->priority = rxq->ev.priority;
 642
 643         qbman_swp_dqrr_consume(swp, dq);
 644 }
 645
 646 void dpaa2_dev_process_atomic_event(struct qbman_swp *swp __attribute__((unused)),
 647                                     const struct qbman_fd *fd,
 648                                     const struct qbman_result *dq,
 649                                     struct dpaa2_queue *rxq,
 650                                     struct rte_event *ev)
 651 {
 652         uint8_t dqrr_index = qbman_get_dqrr_idx(dq);
 653
 654         ev->mbuf = eth_fd_to_mbuf(fd);
 655
 656         ev->flow_id = rxq->ev.flow_id;
 657         ev->sub_event_type = rxq->ev.sub_event_type;
 658         ev->event_type = RTE_EVENT_TYPE_ETHDEV;
 659         ev->op = RTE_EVENT_OP_NEW;
 660         ev->sched_type = rxq->ev.sched_type;
 661         ev->queue_id = rxq->ev.queue_id;
 662         ev->priority = rxq->ev.priority;
 663
 664         ev->mbuf->seqn = dqrr_index + 1;
 665         DPAA2_PER_LCORE_DQRR_SIZE++;
 666         DPAA2_PER_LCORE_DQRR_HELD |= 1 << dqrr_index;
 667         DPAA2_PER_LCORE_DQRR_MBUF(dqrr_index) = ev->mbuf;
 668 }
 669
 670 /*
 671  * Callback to handle sending packets through WRIOP based interface
 672  */
 673 uint16_t
 674 dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
 675 {
 676         /* Function to transmit the frames to given device and VQ*/
 677         uint32_t loop, retry_count;
 678         int32_t ret;
 679         struct qbman_fd fd_arr[MAX_TX_RING_SLOTS];
 680         struct rte_mbuf *mi;
 681         uint32_t frames_to_send;
 682         struct rte_mempool *mp;
 683         struct qbman_eq_desc eqdesc;
 684         struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)queue;
 685         struct qbman_swp *swp;
 686         uint16_t num_tx = 0;
 687         uint16_t bpid;
 688         struct rte_eth_dev *dev = dpaa2_q->dev;
 689         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 690         uint32_t flags[MAX_TX_RING_SLOTS] = {0};
 691
 692         if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
 693                 ret = dpaa2_affine_qbman_swp();
 694                 if (ret) {
 695                         RTE_LOG(ERR, PMD, "Failure in affining portal\n");
 696                         return 0;
 697                 }
 698         }
 699         swp = DPAA2_PER_LCORE_PORTAL;
 700
 701         PMD_TX_LOG(DEBUG, "===> dev =%p, fqid =%d", dev, dpaa2_q->fqid);
 702
 703         /*Prepare enqueue descriptor*/
 704         qbman_eq_desc_clear(&eqdesc);
 705         qbman_eq_desc_set_no_orp(&eqdesc, DPAA2_EQ_RESP_ERR_FQ);
 706         qbman_eq_desc_set_response(&eqdesc, 0, 0);
 707         qbman_eq_desc_set_qd(&eqdesc, priv->qdid,
 708                              dpaa2_q->flow_id, dpaa2_q->tc_index);
 709         /*Clear the unused FD fields before sending*/
 710         while (nb_pkts) {
 711                 /*Check if the queue is congested*/
 712                 retry_count = 0;
 713                 while (qbman_result_SCN_state(dpaa2_q->cscn)) {
 714                         retry_count++;
 715                         /* Retry for some time before giving up */
 716                         if (retry_count > CONG_RETRY_COUNT)
 717                                 goto skip_tx;
 718                 }
 719
 720                 frames_to_send = (nb_pkts >> 3) ? MAX_TX_RING_SLOTS : nb_pkts;
 721
 722                 for (loop = 0; loop < frames_to_send; loop++) {
 723                         if ((*bufs)->seqn) {
 724                                 uint8_t dqrr_index = (*bufs)->seqn - 1;
 725
 726                                 flags[loop] = QBMAN_ENQUEUE_FLAG_DCA |
 727                                                 dqrr_index;
 728                                 DPAA2_PER_LCORE_DQRR_SIZE--;
 729                                 DPAA2_PER_LCORE_DQRR_HELD &= ~(1 << dqrr_index);
 730                                 (*bufs)->seqn = DPAA2_INVALID_MBUF_SEQN;
 731                         }
 732
 733                         fd_arr[loop].simple.frc = 0;
 734                         DPAA2_RESET_FD_CTRL((&fd_arr[loop]));
 735                         DPAA2_SET_FD_FLC((&fd_arr[loop]), NULL);
 736                         if (likely(RTE_MBUF_DIRECT(*bufs))) {
 737                                 mp = (*bufs)->pool;
 738                                 /* Check the basic scenario and set
 739                                  * the FD appropriately here itself.
 740                                  */
 741                                 if (likely(mp && mp->ops_index ==
 742                                     priv->bp_list->dpaa2_ops_index &&
 743                                     (*bufs)->nb_segs == 1 &&
 744                                     rte_mbuf_refcnt_read((*bufs)) == 1)) {
 745                                         if (unlikely((*bufs)->ol_flags
 746                                                 & PKT_TX_VLAN_PKT)) {
 747                                                 ret = rte_vlan_insert(bufs);
 748                                                 if (ret)
 749                                                         goto send_n_return;
 750                                         }
 751                                         DPAA2_MBUF_TO_CONTIG_FD((*bufs),
 752                                         &fd_arr[loop], mempool_to_bpid(mp));
 753                                         bufs++;
 754                                         continue;
 755                                 }
 756                         } else {
 757                                 mi = rte_mbuf_from_indirect(*bufs);
 758                                 mp = mi->pool;
 759                         }
 760                         /* Not a hw_pkt pool allocated frame */
 761                         if (unlikely(!mp || !priv->bp_list)) {
 762                                 PMD_TX_LOG(ERR, "err: no bpool attached");
 763                                 goto send_n_return;
 764                         }
 765
 766                         if (mp->ops_index != priv->bp_list->dpaa2_ops_index) {
 767                                 PMD_TX_LOG(ERR, "non hw offload bufffer ");
 768                                 /* alloc should be from the default buffer pool
 769                                  * attached to this interface
 770                                  */
 771                                 bpid = priv->bp_list->buf_pool.bpid;
 772
 773                                 if (unlikely((*bufs)->nb_segs > 1)) {
 774                                         PMD_TX_LOG(ERR, "S/G support not added"
 775                                                 " for non hw offload buffer");
 776                                         goto send_n_return;
 777                                 }
 778                                 if (eth_copy_mbuf_to_fd(*bufs,
 779                                                         &fd_arr[loop], bpid)) {
 780                                         goto send_n_return;
 781                                 }
 782                                 /* free the original packet */
 783                                 rte_pktmbuf_free(*bufs);
 784                         } else {
 785                                 bpid = mempool_to_bpid(mp);
 786                                 if (unlikely((*bufs)->nb_segs > 1)) {
 787                                         if (eth_mbuf_to_sg_fd(*bufs,
 788                                                         &fd_arr[loop], bpid))
 789                                                 goto send_n_return;
 790                                 } else {
 791                                         eth_mbuf_to_fd(*bufs,
 792                                                        &fd_arr[loop], bpid);
 793                                 }
 794                         }
 795                         bufs++;
 796                 }
 797                 loop = 0;
 798                 while (loop < frames_to_send) {
 799                         loop += qbman_swp_enqueue_multiple(swp, &eqdesc,
 800                                         &fd_arr[loop], &flags[loop],
 801                                         frames_to_send - loop);
 802                 }
 803
 804                 num_tx += frames_to_send;
 805                 nb_pkts -= frames_to_send;
 806         }
 807         dpaa2_q->tx_pkts += num_tx;
 808         return num_tx;
 809
 810 send_n_return:
 811         /* send any already prepared fd */
 812         if (loop) {
 813                 unsigned int i = 0;
 814
 815                 while (i < loop) {
 816                         i += qbman_swp_enqueue_multiple(swp, &eqdesc,
 817                                                         &fd_arr[i],
 818                                                         &flags[loop],
 819                                                         loop - i);
 820                 }
 821                 num_tx += loop;
 822         }
 823 skip_tx:
 824         dpaa2_q->tx_pkts += num_tx;
 825         return num_tx;
 826 }
 827
 828 /**
 829  * Dummy DPDK callback for TX.
 830  *
 831  * This function is used to temporarily replace the real callback during
 832  * unsafe control operations on the queue, or in case of error.
 833  *
 834  * @param dpdk_txq
 835  *   Generic pointer to TX queue structure.
 836  * @param[in] pkts
 837  *   Packets to transmit.
 838  * @param pkts_n
 839  *   Number of packets in array.
 840  *
 841  * @return
 842  *   Number of packets successfully transmitted (<= pkts_n).
 843  */
 844 uint16_t
 845 dummy_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
 846 {
 847         (void)queue;
 848         (void)bufs;
 849         (void)nb_pkts;
 850         return 0;
 851 }