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34 #ifndef _E1000_ETHDEV_H_
35 #define _E1000_ETHDEV_H_
37 /* need update link, bit flag */
38 #define E1000_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
39 #define E1000_FLAG_MAILBOX (uint32_t)(1 << 1)
42 * Defines that were not part of e1000_hw.h as they are not used by the FreeBSD
45 #define E1000_ADVTXD_POPTS_TXSM 0x00000200 /* L4 Checksum offload request */
46 #define E1000_ADVTXD_POPTS_IXSM 0x00000100 /* IP Checksum offload request */
47 #define E1000_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* L4 Packet TYPE of Reserved */
48 #define E1000_RXD_STAT_TMST 0x10000 /* Timestamped Packet indication */
49 #define E1000_RXD_ERR_CKSUM_BIT 29
50 #define E1000_RXD_ERR_CKSUM_MSK 3
51 #define E1000_ADVTXD_MACLEN_SHIFT 9 /* Bit shift for l2_len */
52 #define E1000_CTRL_EXT_EXTEND_VLAN (1<<26) /* EXTENDED VLAN */
53 #define IGB_VFTA_SIZE 128
55 #define IGB_MAX_RX_QUEUE_NUM 8
56 #define IGB_MAX_RX_QUEUE_NUM_82576 16
58 #define E1000_SYN_FILTER_ENABLE 0x00000001 /* syn filter enable field */
59 #define E1000_SYN_FILTER_QUEUE 0x0000000E /* syn filter queue field */
60 #define E1000_SYN_FILTER_QUEUE_SHIFT 1 /* syn filter queue field */
61 #define E1000_RFCTL_SYNQFP 0x00080000 /* SYNQFP in RFCTL register */
63 #define E1000_ETQF_ETHERTYPE 0x0000FFFF
64 #define E1000_ETQF_QUEUE 0x00070000
65 #define E1000_ETQF_QUEUE_SHIFT 16
66 #define E1000_MAX_ETQF_FILTERS 8
68 #define E1000_IMIR_DSTPORT 0x0000FFFF
69 #define E1000_IMIR_PRIORITY 0xE0000000
70 #define E1000_MAX_TTQF_FILTERS 8
71 #define E1000_2TUPLE_MAX_PRI 7
73 #define E1000_MAX_FLEX_FILTERS 8
74 #define E1000_MAX_FHFT 4
75 #define E1000_MAX_FHFT_EXT 4
76 #define E1000_FHFT_SIZE_IN_DWD 64
77 #define E1000_MAX_FLEX_FILTER_PRI 7
78 #define E1000_MAX_FLEX_FILTER_LEN 128
79 #define E1000_MAX_FLEX_FILTER_DWDS \
80 (E1000_MAX_FLEX_FILTER_LEN / sizeof(uint32_t))
81 #define E1000_FLEX_FILTERS_MASK_SIZE \
82 (E1000_MAX_FLEX_FILTER_DWDS / 4)
83 #define E1000_FHFT_QUEUEING_LEN 0x0000007F
84 #define E1000_FHFT_QUEUEING_QUEUE 0x00000700
85 #define E1000_FHFT_QUEUEING_PRIO 0x00070000
86 #define E1000_FHFT_QUEUEING_OFFSET 0xFC
87 #define E1000_FHFT_QUEUEING_QUEUE_SHIFT 8
88 #define E1000_FHFT_QUEUEING_PRIO_SHIFT 16
89 #define E1000_WUFC_FLEX_HQ 0x00004000
91 #define E1000_SPQF_SRCPORT 0x0000FFFF
93 #define E1000_MAX_FTQF_FILTERS 8
94 #define E1000_FTQF_PROTOCOL_MASK 0x000000FF
95 #define E1000_FTQF_5TUPLE_MASK_SHIFT 28
96 #define E1000_FTQF_QUEUE_MASK 0x03ff0000
97 #define E1000_FTQF_QUEUE_SHIFT 16
98 #define E1000_FTQF_QUEUE_ENABLE 0x00000100
100 #define IGB_RSS_OFFLOAD_ALL ( \
102 ETH_RSS_NONFRAG_IPV4_TCP | \
103 ETH_RSS_NONFRAG_IPV4_UDP | \
105 ETH_RSS_NONFRAG_IPV6_TCP | \
106 ETH_RSS_NONFRAG_IPV6_UDP | \
108 ETH_RSS_IPV6_TCP_EX | \
112 * Maximum number of Ring Descriptors.
114 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring
115 * desscriptors should meet the following condition:
116 * (num_ring_desc * sizeof(struct e1000_rx/tx_desc)) % 128 == 0
118 #define E1000_MIN_RING_DESC 32
119 #define E1000_MAX_RING_DESC 4096
122 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
123 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary.
124 * This will also optimize cache line size effect.
125 * H/W supports up to cache line size 128.
127 #define E1000_ALIGN 128
129 #define IGB_RXD_ALIGN (E1000_ALIGN / sizeof(union e1000_adv_rx_desc))
130 #define IGB_TXD_ALIGN (E1000_ALIGN / sizeof(union e1000_adv_tx_desc))
132 #define EM_RXD_ALIGN (E1000_ALIGN / sizeof(struct e1000_rx_desc))
133 #define EM_TXD_ALIGN (E1000_ALIGN / sizeof(struct e1000_data_desc))
135 /* structure for interrupt relative data */
136 struct e1000_interrupt {
141 /* local vfta copy */
143 uint32_t vfta[IGB_VFTA_SIZE];
147 * VF data which used by PF host only
149 #define E1000_MAX_VF_MC_ENTRIES 30
150 struct e1000_vf_info {
151 uint8_t vf_mac_addresses[ETHER_ADDR_LEN];
152 uint16_t vf_mc_hashes[E1000_MAX_VF_MC_ENTRIES];
153 uint16_t num_vf_mc_hashes;
154 uint16_t default_vf_vlan_id;
155 uint16_t vlans_enabled;
161 TAILQ_HEAD(e1000_flex_filter_list, e1000_flex_filter);
163 struct e1000_flex_filter_info {
165 uint32_t dwords[E1000_MAX_FLEX_FILTER_DWDS]; /* flex bytes in dword. */
166 /* if mask bit is 1b, do not compare corresponding byte in dwords. */
167 uint8_t mask[E1000_FLEX_FILTERS_MASK_SIZE];
171 /* Flex filter structure */
172 struct e1000_flex_filter {
173 TAILQ_ENTRY(e1000_flex_filter) entries;
174 uint16_t index; /* index of flex filter */
175 struct e1000_flex_filter_info filter_info;
176 uint16_t queue; /* rx queue assigned to */
179 TAILQ_HEAD(e1000_5tuple_filter_list, e1000_5tuple_filter);
180 TAILQ_HEAD(e1000_2tuple_filter_list, e1000_2tuple_filter);
182 struct e1000_5tuple_filter_info {
187 uint8_t proto; /* l4 protocol. */
188 /* the packet matched above 5tuple and contain any set bit will hit this filter. */
190 uint8_t priority; /* seven levels (001b-111b), 111b is highest,
191 used when more than one filter matches. */
192 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
193 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
194 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
195 src_port_mask:1, /* if mask is 1b, do not compare src port. */
196 proto_mask:1; /* if mask is 1b, do not compare protocol. */
199 struct e1000_2tuple_filter_info {
201 uint8_t proto; /* l4 protocol. */
202 /* the packet matched above 2tuple and contain any set bit will hit this filter. */
204 uint8_t priority; /* seven levels (001b-111b), 111b is highest,
205 used when more than one filter matches. */
206 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
207 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
208 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
209 src_port_mask:1, /* if mask is 1b, do not compare src port. */
210 proto_mask:1; /* if mask is 1b, do not compare protocol. */
213 /* 5tuple filter structure */
214 struct e1000_5tuple_filter {
215 TAILQ_ENTRY(e1000_5tuple_filter) entries;
216 uint16_t index; /* the index of 5tuple filter */
217 struct e1000_5tuple_filter_info filter_info;
218 uint16_t queue; /* rx queue assigned to */
221 /* 2tuple filter structure */
222 struct e1000_2tuple_filter {
223 TAILQ_ENTRY(e1000_2tuple_filter) entries;
224 uint16_t index; /* the index of 2tuple filter */
225 struct e1000_2tuple_filter_info filter_info;
226 uint16_t queue; /* rx queue assigned to */
230 * Structure to store filters' info.
232 struct e1000_filter_info {
233 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
234 /* store used ethertype filters*/
235 uint16_t ethertype_filters[E1000_MAX_ETQF_FILTERS];
236 uint8_t flex_mask; /* Bit mask for every used flex filter */
237 struct e1000_flex_filter_list flex_list;
238 /* Bit mask for every used 5tuple filter */
239 uint8_t fivetuple_mask;
240 struct e1000_5tuple_filter_list fivetuple_list;
241 /* Bit mask for every used 2tuple filter */
242 uint8_t twotuple_mask;
243 struct e1000_2tuple_filter_list twotuple_list;
247 * Structure to store private data for each driver instance (for each port).
249 struct e1000_adapter {
251 struct e1000_hw_stats stats;
252 struct e1000_interrupt intr;
253 struct e1000_vfta shadow_vfta;
254 struct e1000_vf_info *vfdata;
255 struct e1000_filter_info filter;
259 #define E1000_DEV_PRIVATE(adapter) \
260 ((struct e1000_adapter *)adapter)
262 #define E1000_DEV_PRIVATE_TO_HW(adapter) \
263 (&((struct e1000_adapter *)adapter)->hw)
265 #define E1000_DEV_PRIVATE_TO_STATS(adapter) \
266 (&((struct e1000_adapter *)adapter)->stats)
268 #define E1000_DEV_PRIVATE_TO_INTR(adapter) \
269 (&((struct e1000_adapter *)adapter)->intr)
271 #define E1000_DEV_PRIVATE_TO_VFTA(adapter) \
272 (&((struct e1000_adapter *)adapter)->shadow_vfta)
274 #define E1000_DEV_PRIVATE_TO_P_VFDATA(adapter) \
275 (&((struct e1000_adapter *)adapter)->vfdata)
277 #define E1000_DEV_PRIVATE_TO_FILTER_INFO(adapter) \
278 (&((struct e1000_adapter *)adapter)->filter)
281 * RX/TX IGB function prototypes
283 void eth_igb_tx_queue_release(void *txq);
284 void eth_igb_rx_queue_release(void *rxq);
285 void igb_dev_clear_queues(struct rte_eth_dev *dev);
286 void igb_dev_free_queues(struct rte_eth_dev *dev);
288 int eth_igb_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
289 uint16_t nb_rx_desc, unsigned int socket_id,
290 const struct rte_eth_rxconf *rx_conf,
291 struct rte_mempool *mb_pool);
293 uint32_t eth_igb_rx_queue_count(struct rte_eth_dev *dev,
294 uint16_t rx_queue_id);
296 int eth_igb_rx_descriptor_done(void *rx_queue, uint16_t offset);
298 int eth_igb_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
299 uint16_t nb_tx_desc, unsigned int socket_id,
300 const struct rte_eth_txconf *tx_conf);
302 int eth_igb_rx_init(struct rte_eth_dev *dev);
304 void eth_igb_tx_init(struct rte_eth_dev *dev);
306 uint16_t eth_igb_xmit_pkts(void *txq, struct rte_mbuf **tx_pkts,
309 uint16_t eth_igb_recv_pkts(void *rxq, struct rte_mbuf **rx_pkts,
312 uint16_t eth_igb_recv_scattered_pkts(void *rxq,
313 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
315 int eth_igb_rss_hash_update(struct rte_eth_dev *dev,
316 struct rte_eth_rss_conf *rss_conf);
318 int eth_igb_rss_hash_conf_get(struct rte_eth_dev *dev,
319 struct rte_eth_rss_conf *rss_conf);
321 int eth_igbvf_rx_init(struct rte_eth_dev *dev);
323 void eth_igbvf_tx_init(struct rte_eth_dev *dev);
326 * misc function prototypes
328 void igb_pf_host_init(struct rte_eth_dev *eth_dev);
330 void igb_pf_mbx_process(struct rte_eth_dev *eth_dev);
332 int igb_pf_host_configure(struct rte_eth_dev *eth_dev);
334 void igb_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
335 struct rte_eth_rxq_info *qinfo);
337 void igb_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
338 struct rte_eth_txq_info *qinfo);
341 * RX/TX EM function prototypes
343 void eth_em_tx_queue_release(void *txq);
344 void eth_em_rx_queue_release(void *rxq);
346 void em_dev_clear_queues(struct rte_eth_dev *dev);
347 void em_dev_free_queues(struct rte_eth_dev *dev);
349 int eth_em_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
350 uint16_t nb_rx_desc, unsigned int socket_id,
351 const struct rte_eth_rxconf *rx_conf,
352 struct rte_mempool *mb_pool);
354 uint32_t eth_em_rx_queue_count(struct rte_eth_dev *dev,
355 uint16_t rx_queue_id);
357 int eth_em_rx_descriptor_done(void *rx_queue, uint16_t offset);
359 int eth_em_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
360 uint16_t nb_tx_desc, unsigned int socket_id,
361 const struct rte_eth_txconf *tx_conf);
363 int eth_em_rx_init(struct rte_eth_dev *dev);
365 void eth_em_tx_init(struct rte_eth_dev *dev);
367 uint16_t eth_em_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
370 uint16_t eth_em_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
373 uint16_t eth_em_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
376 void em_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
377 struct rte_eth_rxq_info *qinfo);
379 void em_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
380 struct rte_eth_txq_info *qinfo);
382 void igb_pf_host_uninit(struct rte_eth_dev *dev);
384 #endif /* _E1000_ETHDEV_H_ */