drivers/net/e1000/em_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58
  59 #define EM_EIAC                 0x000DC
  60
  61 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
  62
  63
  64 static int eth_em_configure(struct rte_eth_dev *dev);
  65 static int eth_em_start(struct rte_eth_dev *dev);
  66 static void eth_em_stop(struct rte_eth_dev *dev);
  67 static void eth_em_close(struct rte_eth_dev *dev);
  68 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
  69 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
  70 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
  71 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
  72 static int eth_em_link_update(struct rte_eth_dev *dev,
  73                                 int wait_to_complete);
  74 static void eth_em_stats_get(struct rte_eth_dev *dev,
  75                                 struct rte_eth_stats *rte_stats);
  76 static void eth_em_stats_reset(struct rte_eth_dev *dev);
  77 static void eth_em_infos_get(struct rte_eth_dev *dev,
  78                                 struct rte_eth_dev_info *dev_info);
  79 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
  80                                 struct rte_eth_fc_conf *fc_conf);
  81 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
  82                                 struct rte_eth_fc_conf *fc_conf);
  83 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
  84 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
  85 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
  86 static int eth_em_interrupt_action(struct rte_eth_dev *dev);
  87 static void eth_em_interrupt_handler(struct rte_intr_handle *handle,
  88                                                         void *param);
  89
  90 static int em_hw_init(struct e1000_hw *hw);
  91 static int em_hardware_init(struct e1000_hw *hw);
  92 static void em_hw_control_acquire(struct e1000_hw *hw);
  93 static void em_hw_control_release(struct e1000_hw *hw);
  94 static void em_init_manageability(struct e1000_hw *hw);
  95 static void em_release_manageability(struct e1000_hw *hw);
  96
  97 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  98
  99 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
 100                 uint16_t vlan_id, int on);
 101 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 102 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 103 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 104 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 105 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 106
 107 /*
 108 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
 109                                         uint16_t vlan_id, int on);
 110 */
 111
 112 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
 113 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
 114 static void em_lsc_intr_disable(struct e1000_hw *hw);
 115 static void em_rxq_intr_enable(struct e1000_hw *hw);
 116 static void em_rxq_intr_disable(struct e1000_hw *hw);
 117
 118 static int eth_em_led_on(struct rte_eth_dev *dev);
 119 static int eth_em_led_off(struct rte_eth_dev *dev);
 120
 121 static int em_get_rx_buffer_size(struct e1000_hw *hw);
 122 static void eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 123                 uint32_t index, uint32_t pool);
 124 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 125
 126 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
 127                                    struct ether_addr *mc_addr_set,
 128                                    uint32_t nb_mc_addr);
 129
 130 #define EM_FC_PAUSE_TIME 0x0680
 131 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 132 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 133
 134 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
 135
 136 /*
 137  * The set of PCI devices this driver supports
 138  */
 139 static const struct rte_pci_id pci_id_em_map[] = {
 140
 141 #define RTE_PCI_DEV_ID_DECL_EM(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 142 #include "rte_pci_dev_ids.h"
 143
 144 {0},
 145 };
 146
 147 static const struct eth_dev_ops eth_em_ops = {
 148         .dev_configure        = eth_em_configure,
 149         .dev_start            = eth_em_start,
 150         .dev_stop             = eth_em_stop,
 151         .dev_close            = eth_em_close,
 152         .promiscuous_enable   = eth_em_promiscuous_enable,
 153         .promiscuous_disable  = eth_em_promiscuous_disable,
 154         .allmulticast_enable  = eth_em_allmulticast_enable,
 155         .allmulticast_disable = eth_em_allmulticast_disable,
 156         .link_update          = eth_em_link_update,
 157         .stats_get            = eth_em_stats_get,
 158         .stats_reset          = eth_em_stats_reset,
 159         .dev_infos_get        = eth_em_infos_get,
 160         .mtu_set              = eth_em_mtu_set,
 161         .vlan_filter_set      = eth_em_vlan_filter_set,
 162         .vlan_offload_set     = eth_em_vlan_offload_set,
 163         .rx_queue_setup       = eth_em_rx_queue_setup,
 164         .rx_queue_release     = eth_em_rx_queue_release,
 165         .rx_queue_count       = eth_em_rx_queue_count,
 166         .rx_descriptor_done   = eth_em_rx_descriptor_done,
 167         .tx_queue_setup       = eth_em_tx_queue_setup,
 168         .tx_queue_release     = eth_em_tx_queue_release,
 169         .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
 170         .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
 171         .dev_led_on           = eth_em_led_on,
 172         .dev_led_off          = eth_em_led_off,
 173         .flow_ctrl_get        = eth_em_flow_ctrl_get,
 174         .flow_ctrl_set        = eth_em_flow_ctrl_set,
 175         .mac_addr_add         = eth_em_rar_set,
 176         .mac_addr_remove      = eth_em_rar_clear,
 177         .set_mc_addr_list     = eth_em_set_mc_addr_list,
 178         .rxq_info_get         = em_rxq_info_get,
 179         .txq_info_get         = em_txq_info_get,
 180 };
 181
 182 /**
 183  * Atomically reads the link status information from global
 184  * structure rte_eth_dev.
 185  *
 186  * @param dev
 187  *   - Pointer to the structure rte_eth_dev to read from.
 188  *   - Pointer to the buffer to be saved with the link status.
 189  *
 190  * @return
 191  *   - On success, zero.
 192  *   - On failure, negative value.
 193  */
 194 static inline int
 195 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 196                                 struct rte_eth_link *link)
 197 {
 198         struct rte_eth_link *dst = link;
 199         struct rte_eth_link *src = &(dev->data->dev_link);
 200
 201         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 202                                         *(uint64_t *)src) == 0)
 203                 return -1;
 204
 205         return 0;
 206 }
 207
 208 /**
 209  * Atomically writes the link status information into global
 210  * structure rte_eth_dev.
 211  *
 212  * @param dev
 213  *   - Pointer to the structure rte_eth_dev to read from.
 214  *   - Pointer to the buffer to be saved with the link status.
 215  *
 216  * @return
 217  *   - On success, zero.
 218  *   - On failure, negative value.
 219  */
 220 static inline int
 221 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 222                                 struct rte_eth_link *link)
 223 {
 224         struct rte_eth_link *dst = &(dev->data->dev_link);
 225         struct rte_eth_link *src = link;
 226
 227         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 228                                         *(uint64_t *)src) == 0)
 229                 return -1;
 230
 231         return 0;
 232 }
 233
 234 static int
 235 eth_em_dev_init(struct rte_eth_dev *eth_dev)
 236 {
 237         struct rte_pci_device *pci_dev;
 238         struct e1000_adapter *adapter =
 239                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 240         struct e1000_hw *hw =
 241                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 242         struct e1000_vfta * shadow_vfta =
 243                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 244
 245         pci_dev = eth_dev->pci_dev;
 246         eth_dev->dev_ops = &eth_em_ops;
 247         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
 248         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
 249
 250         /* for secondary processes, we don't initialise any further as primary
 251          * has already done this work. Only check we don't need a different
 252          * RX function */
 253         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 254                 if (eth_dev->data->scattered_rx)
 255                         eth_dev->rx_pkt_burst =
 256                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
 257                 return 0;
 258         }
 259
 260         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 261         hw->device_id = pci_dev->id.device_id;
 262         adapter->stopped = 0;
 263
 264         /* For ICH8 support we'll need to map the flash memory BAR */
 265
 266         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
 267                         em_hw_init(hw) != 0) {
 268                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
 269                         "failed to init HW",
 270                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 271                         pci_dev->id.device_id);
 272                 return -(ENODEV);
 273         }
 274
 275         /* Allocate memory for storing MAC addresses */
 276         eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
 277                         hw->mac.rar_entry_count, 0);
 278         if (eth_dev->data->mac_addrs == NULL) {
 279                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 280                         "store MAC addresses",
 281                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 282                 return -(ENOMEM);
 283         }
 284
 285         /* Copy the permanent MAC address */
 286         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 287                 eth_dev->data->mac_addrs);
 288
 289         /* initialize the vfta */
 290         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 291
 292         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 293                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 294                      pci_dev->id.device_id);
 295
 296         rte_intr_callback_register(&(pci_dev->intr_handle),
 297                 eth_em_interrupt_handler, (void *)eth_dev);
 298
 299         return (0);
 300 }
 301
 302 static int
 303 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
 304 {
 305         struct rte_pci_device *pci_dev;
 306         struct e1000_adapter *adapter =
 307                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 308
 309         PMD_INIT_FUNC_TRACE();
 310
 311         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 312                 return -EPERM;
 313
 314         pci_dev = eth_dev->pci_dev;
 315
 316         if (adapter->stopped == 0)
 317                 eth_em_close(eth_dev);
 318
 319         eth_dev->dev_ops = NULL;
 320         eth_dev->rx_pkt_burst = NULL;
 321         eth_dev->tx_pkt_burst = NULL;
 322
 323         rte_free(eth_dev->data->mac_addrs);
 324         eth_dev->data->mac_addrs = NULL;
 325
 326         /* disable uio intr before callback unregister */
 327         rte_intr_disable(&(pci_dev->intr_handle));
 328         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 329                 eth_em_interrupt_handler, (void *)eth_dev);
 330
 331         return 0;
 332 }
 333
 334 static struct eth_driver rte_em_pmd = {
 335         .pci_drv = {
 336                 .name = "rte_em_pmd",
 337                 .id_table = pci_id_em_map,
 338                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 339                         RTE_PCI_DRV_DETACHABLE,
 340         },
 341         .eth_dev_init = eth_em_dev_init,
 342         .eth_dev_uninit = eth_em_dev_uninit,
 343         .dev_private_size = sizeof(struct e1000_adapter),
 344 };
 345
 346 static int
 347 rte_em_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 348 {
 349         rte_eth_driver_register(&rte_em_pmd);
 350         return 0;
 351 }
 352
 353 static int
 354 em_hw_init(struct e1000_hw *hw)
 355 {
 356         int diag;
 357
 358         diag = hw->mac.ops.init_params(hw);
 359         if (diag != 0) {
 360                 PMD_INIT_LOG(ERR, "MAC Initialization Error");
 361                 return diag;
 362         }
 363         diag = hw->nvm.ops.init_params(hw);
 364         if (diag != 0) {
 365                 PMD_INIT_LOG(ERR, "NVM Initialization Error");
 366                 return diag;
 367         }
 368         diag = hw->phy.ops.init_params(hw);
 369         if (diag != 0) {
 370                 PMD_INIT_LOG(ERR, "PHY Initialization Error");
 371                 return diag;
 372         }
 373         (void) e1000_get_bus_info(hw);
 374
 375         hw->mac.autoneg = 1;
 376         hw->phy.autoneg_wait_to_complete = 0;
 377         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 378
 379         e1000_init_script_state_82541(hw, TRUE);
 380         e1000_set_tbi_compatibility_82543(hw, TRUE);
 381
 382         /* Copper options */
 383         if (hw->phy.media_type == e1000_media_type_copper) {
 384                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 385                 hw->phy.disable_polarity_correction = 0;
 386                 hw->phy.ms_type = e1000_ms_hw_default;
 387         }
 388
 389         /*
 390          * Start from a known state, this is important in reading the nvm
 391          * and mac from that.
 392          */
 393         e1000_reset_hw(hw);
 394
 395         /* Make sure we have a good EEPROM before we read from it */
 396         if (e1000_validate_nvm_checksum(hw) < 0) {
 397                 /*
 398                  * Some PCI-E parts fail the first check due to
 399                  * the link being in sleep state, call it again,
 400                  * if it fails a second time its a real issue.
 401                  */
 402                 diag = e1000_validate_nvm_checksum(hw);
 403                 if (diag < 0) {
 404                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 405                         goto error;
 406                 }
 407         }
 408
 409         /* Read the permanent MAC address out of the EEPROM */
 410         diag = e1000_read_mac_addr(hw);
 411         if (diag != 0) {
 412                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 413                 goto error;
 414         }
 415
 416         /* Now initialize the hardware */
 417         diag = em_hardware_init(hw);
 418         if (diag != 0) {
 419                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 420                 goto error;
 421         }
 422
 423         hw->mac.get_link_status = 1;
 424
 425         /* Indicate SOL/IDER usage */
 426         diag = e1000_check_reset_block(hw);
 427         if (diag < 0) {
 428                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
 429                         "SOL/IDER session");
 430         }
 431         return (0);
 432
 433 error:
 434         em_hw_control_release(hw);
 435         return (diag);
 436 }
 437
 438 static int
 439 eth_em_configure(struct rte_eth_dev *dev)
 440 {
 441         struct e1000_interrupt *intr =
 442                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 443
 444         PMD_INIT_FUNC_TRACE();
 445         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 446         PMD_INIT_FUNC_TRACE();
 447
 448         return (0);
 449 }
 450
 451 static void
 452 em_set_pba(struct e1000_hw *hw)
 453 {
 454         uint32_t pba;
 455
 456         /*
 457          * Packet Buffer Allocation (PBA)
 458          * Writing PBA sets the receive portion of the buffer
 459          * the remainder is used for the transmit buffer.
 460          * Devices before the 82547 had a Packet Buffer of 64K.
 461          * After the 82547 the buffer was reduced to 40K.
 462          */
 463         switch (hw->mac.type) {
 464                 case e1000_82547:
 465                 case e1000_82547_rev_2:
 466                 /* 82547: Total Packet Buffer is 40K */
 467                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
 468                         break;
 469                 case e1000_82571:
 470                 case e1000_82572:
 471                 case e1000_80003es2lan:
 472                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 473                         break;
 474                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
 475                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
 476                         break;
 477                 case e1000_82574:
 478                 case e1000_82583:
 479                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
 480                         break;
 481                 case e1000_ich8lan:
 482                         pba = E1000_PBA_8K;
 483                         break;
 484                 case e1000_ich9lan:
 485                 case e1000_ich10lan:
 486                         pba = E1000_PBA_10K;
 487                         break;
 488                 case e1000_pchlan:
 489                 case e1000_pch2lan:
 490                         pba = E1000_PBA_26K;
 491                         break;
 492                 default:
 493                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
 494         }
 495
 496         E1000_WRITE_REG(hw, E1000_PBA, pba);
 497 }
 498
 499 static int
 500 eth_em_start(struct rte_eth_dev *dev)
 501 {
 502         struct e1000_adapter *adapter =
 503                 E1000_DEV_PRIVATE(dev->data->dev_private);
 504         struct e1000_hw *hw =
 505                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 506         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
 507         int ret, mask;
 508         uint32_t intr_vector = 0;
 509
 510         PMD_INIT_FUNC_TRACE();
 511
 512         eth_em_stop(dev);
 513
 514         e1000_power_up_phy(hw);
 515
 516         /* Set default PBA value */
 517         em_set_pba(hw);
 518
 519         /* Put the address into the Receive Address Array */
 520         e1000_rar_set(hw, hw->mac.addr, 0);
 521
 522         /*
 523          * With the 82571 adapter, RAR[0] may be overwritten
 524          * when the other port is reset, we make a duplicate
 525          * in RAR[14] for that eventuality, this assures
 526          * the interface continues to function.
 527          */
 528         if (hw->mac.type == e1000_82571) {
 529                 e1000_set_laa_state_82571(hw, TRUE);
 530                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
 531         }
 532
 533         /* Initialize the hardware */
 534         if (em_hardware_init(hw)) {
 535                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 536                 return (-EIO);
 537         }
 538
 539         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 540
 541         /* Configure for OS presence */
 542         em_init_manageability(hw);
 543
 544         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 545                 intr_vector = dev->data->nb_rx_queues;
 546                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 547                         return -1;
 548         }
 549
 550         if (rte_intr_dp_is_en(intr_handle)) {
 551                 intr_handle->intr_vec =
 552                         rte_zmalloc("intr_vec",
 553                                         dev->data->nb_rx_queues * sizeof(int), 0);
 554                 if (intr_handle->intr_vec == NULL) {
 555                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 556                                                 " intr_vec\n", dev->data->nb_rx_queues);
 557                         return -ENOMEM;
 558                 }
 559
 560                 /* enable rx interrupt */
 561                 em_rxq_intr_enable(hw);
 562         }
 563
 564         eth_em_tx_init(dev);
 565
 566         ret = eth_em_rx_init(dev);
 567         if (ret) {
 568                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 569                 em_dev_clear_queues(dev);
 570                 return ret;
 571         }
 572
 573         e1000_clear_hw_cntrs_base_generic(hw);
 574
 575         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 576                         ETH_VLAN_EXTEND_MASK;
 577         eth_em_vlan_offload_set(dev, mask);
 578
 579         /* Set Interrupt Throttling Rate to maximum allowed value. */
 580         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
 581
 582         /* Setup link speed and duplex */
 583         switch (dev->data->dev_conf.link_speed) {
 584         case ETH_LINK_SPEED_AUTONEG:
 585                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 586                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 587                 else if (dev->data->dev_conf.link_duplex ==
 588                                         ETH_LINK_HALF_DUPLEX)
 589                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 590                 else if (dev->data->dev_conf.link_duplex ==
 591                                         ETH_LINK_FULL_DUPLEX)
 592                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 593                 else
 594                         goto error_invalid_config;
 595                 break;
 596         case ETH_LINK_SPEED_10:
 597                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 598                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 599                 else if (dev->data->dev_conf.link_duplex ==
 600                                         ETH_LINK_HALF_DUPLEX)
 601                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 602                 else if (dev->data->dev_conf.link_duplex ==
 603                                         ETH_LINK_FULL_DUPLEX)
 604                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 605                 else
 606                         goto error_invalid_config;
 607                 break;
 608         case ETH_LINK_SPEED_100:
 609                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 610                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 611                 else if (dev->data->dev_conf.link_duplex ==
 612                                         ETH_LINK_HALF_DUPLEX)
 613                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 614                 else if (dev->data->dev_conf.link_duplex ==
 615                                         ETH_LINK_FULL_DUPLEX)
 616                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 617                 else
 618                         goto error_invalid_config;
 619                 break;
 620         case ETH_LINK_SPEED_1000:
 621                 if ((dev->data->dev_conf.link_duplex ==
 622                                 ETH_LINK_AUTONEG_DUPLEX) ||
 623                         (dev->data->dev_conf.link_duplex ==
 624                                         ETH_LINK_FULL_DUPLEX))
 625                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 626                 else
 627                         goto error_invalid_config;
 628                 break;
 629         case ETH_LINK_SPEED_10000:
 630         default:
 631                 goto error_invalid_config;
 632         }
 633         e1000_setup_link(hw);
 634
 635         if (rte_intr_allow_others(intr_handle)) {
 636                 /* check if lsc interrupt is enabled */
 637                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 638                         ret = eth_em_interrupt_setup(dev);
 639                         if (ret) {
 640                                 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
 641                                 em_dev_clear_queues(dev);
 642                                 return ret;
 643                         }
 644         } else {
 645                 rte_intr_callback_unregister(intr_handle,
 646                                                 eth_em_interrupt_handler,
 647                                                 (void *)dev);
 648                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 649                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
 650                                      " no intr multiplex\n");
 651         }
 652         /* check if rxq interrupt is enabled */
 653         if (dev->data->dev_conf.intr_conf.rxq != 0)
 654                 eth_em_rxq_interrupt_setup(dev);
 655
 656         rte_intr_enable(intr_handle);
 657
 658         adapter->stopped = 0;
 659
 660         PMD_INIT_LOG(DEBUG, "<<");
 661
 662         return (0);
 663
 664 error_invalid_config:
 665         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
 666                      dev->data->dev_conf.link_speed,
 667                      dev->data->dev_conf.link_duplex, dev->data->port_id);
 668         em_dev_clear_queues(dev);
 669         return (-EINVAL);
 670 }
 671
 672 /*********************************************************************
 673  *
 674  *  This routine disables all traffic on the adapter by issuing a
 675  *  global reset on the MAC.
 676  *
 677  **********************************************************************/
 678 static void
 679 eth_em_stop(struct rte_eth_dev *dev)
 680 {
 681         struct rte_eth_link link;
 682         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 683         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
 684
 685         em_rxq_intr_disable(hw);
 686         em_lsc_intr_disable(hw);
 687
 688         e1000_reset_hw(hw);
 689         if (hw->mac.type >= e1000_82544)
 690                 E1000_WRITE_REG(hw, E1000_WUC, 0);
 691
 692         /* Power down the phy. Needed to make the link go down */
 693         e1000_power_down_phy(hw);
 694
 695         em_dev_clear_queues(dev);
 696
 697         /* clear the recorded link status */
 698         memset(&link, 0, sizeof(link));
 699         rte_em_dev_atomic_write_link_status(dev, &link);
 700
 701         if (!rte_intr_allow_others(intr_handle))
 702                 /* resume to the default handler */
 703                 rte_intr_callback_register(intr_handle,
 704                                            eth_em_interrupt_handler,
 705                                            (void *)dev);
 706
 707         /* Clean datapath event and queue/vec mapping */
 708         rte_intr_efd_disable(intr_handle);
 709         if (intr_handle->intr_vec != NULL) {
 710                 rte_free(intr_handle->intr_vec);
 711                 intr_handle->intr_vec = NULL;
 712         }
 713 }
 714
 715 static void
 716 eth_em_close(struct rte_eth_dev *dev)
 717 {
 718         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 719         struct e1000_adapter *adapter =
 720                 E1000_DEV_PRIVATE(dev->data->dev_private);
 721
 722         eth_em_stop(dev);
 723         adapter->stopped = 1;
 724         em_dev_free_queues(dev);
 725         e1000_phy_hw_reset(hw);
 726         em_release_manageability(hw);
 727         em_hw_control_release(hw);
 728 }
 729
 730 static int
 731 em_get_rx_buffer_size(struct e1000_hw *hw)
 732 {
 733         uint32_t rx_buf_size;
 734
 735         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
 736         return rx_buf_size;
 737 }
 738
 739 /*********************************************************************
 740  *
 741  *  Initialize the hardware
 742  *
 743  **********************************************************************/
 744 static int
 745 em_hardware_init(struct e1000_hw *hw)
 746 {
 747         uint32_t rx_buf_size;
 748         int diag;
 749
 750         /* Issue a global reset */
 751         e1000_reset_hw(hw);
 752
 753         /* Let the firmware know the OS is in control */
 754         em_hw_control_acquire(hw);
 755
 756         /*
 757          * These parameters control the automatic generation (Tx) and
 758          * response (Rx) to Ethernet PAUSE frames.
 759          * - High water mark should allow for at least two standard size (1518)
 760          *   frames to be received after sending an XOFF.
 761          * - Low water mark works best when it is very near the high water mark.
 762          *   This allows the receiver to restart by sending XON when it has
 763          *   drained a bit. Here we use an arbitrary value of 1500 which will
 764          *   restart after one full frame is pulled from the buffer. There
 765          *   could be several smaller frames in the buffer and if so they will
 766          *   not trigger the XON until their total number reduces the buffer
 767          *   by 1500.
 768          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 769          */
 770         rx_buf_size = em_get_rx_buffer_size(hw);
 771
 772         hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
 773         hw->fc.low_water = hw->fc.high_water - 1500;
 774
 775         if (hw->mac.type == e1000_80003es2lan)
 776                 hw->fc.pause_time = UINT16_MAX;
 777         else
 778                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
 779
 780         hw->fc.send_xon = 1;
 781
 782         /* Set Flow control, use the tunable location if sane */
 783         if (em_fc_setting <= e1000_fc_full)
 784                 hw->fc.requested_mode = em_fc_setting;
 785         else
 786                 hw->fc.requested_mode = e1000_fc_none;
 787
 788         /* Workaround: no TX flow ctrl for PCH */
 789         if (hw->mac.type == e1000_pchlan)
 790                 hw->fc.requested_mode = e1000_fc_rx_pause;
 791
 792         /* Override - settings for PCH2LAN, ya its magic :) */
 793         if (hw->mac.type == e1000_pch2lan) {
 794                 hw->fc.high_water = 0x5C20;
 795                 hw->fc.low_water = 0x5048;
 796                 hw->fc.pause_time = 0x0650;
 797                 hw->fc.refresh_time = 0x0400;
 798         }
 799
 800         diag = e1000_init_hw(hw);
 801         if (diag < 0)
 802                 return (diag);
 803         e1000_check_for_link(hw);
 804         return (0);
 805 }
 806
 807 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
 808 static void
 809 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 810 {
 811         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 812         struct e1000_hw_stats *stats =
 813                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 814         int pause_frames;
 815
 816         if(hw->phy.media_type == e1000_media_type_copper ||
 817                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 818                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
 819                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 820         }
 821
 822         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 823         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 824         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 825         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 826
 827         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 828         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 829         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 830         stats->dc += E1000_READ_REG(hw, E1000_DC);
 831         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 832         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 833         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 834
 835         /*
 836          * For watchdog management we need to know if we have been
 837          * paused during the last interval, so capture that here.
 838          */
 839         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 840         stats->xoffrxc += pause_frames;
 841         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 842         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 843         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 844         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 845         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 846         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 847         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 848         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 849         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 850         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 851         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 852         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 853
 854         /*
 855          * For the 64-bit byte counters the low dword must be read first.
 856          * Both registers clear on the read of the high dword.
 857          */
 858
 859         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 860         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 861         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 862         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 863
 864         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 865         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 866         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 867         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 868         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 869
 870         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 871         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 872
 873         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 874         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 875         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 876         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 877         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 878         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 879         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 880         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 881         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 882         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 883
 884         /* Interrupt Counts */
 885
 886         if (hw->mac.type >= e1000_82571) {
 887                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
 888                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 889                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 890                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 891                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 892                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 893                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 894                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 895                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 896         }
 897
 898         if (hw->mac.type >= e1000_82543) {
 899                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 900                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 901                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 902                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 903                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 904                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 905         }
 906
 907         if (rte_stats == NULL)
 908                 return;
 909
 910         /* Rx Errors */
 911         rte_stats->ibadcrc = stats->crcerrs;
 912         rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
 913         rte_stats->imissed = stats->mpc;
 914         rte_stats->ierrors = rte_stats->ibadcrc +
 915                              rte_stats->ibadlen +
 916                              rte_stats->imissed +
 917                              stats->rxerrc + stats->algnerrc + stats->cexterr;
 918
 919         /* Tx Errors */
 920         rte_stats->oerrors = stats->ecol + stats->latecol;
 921
 922         rte_stats->ipackets = stats->gprc;
 923         rte_stats->opackets = stats->gptc;
 924         rte_stats->ibytes   = stats->gorc;
 925         rte_stats->obytes   = stats->gotc;
 926
 927         /* XON/XOFF pause frames stats registers */
 928         rte_stats->tx_pause_xon  = stats->xontxc;
 929         rte_stats->rx_pause_xon  = stats->xonrxc;
 930         rte_stats->tx_pause_xoff = stats->xofftxc;
 931         rte_stats->rx_pause_xoff = stats->xoffrxc;
 932 }
 933
 934 static void
 935 eth_em_stats_reset(struct rte_eth_dev *dev)
 936 {
 937         struct e1000_hw_stats *hw_stats =
 938                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 939
 940         /* HW registers are cleared on read */
 941         eth_em_stats_get(dev, NULL);
 942
 943         /* Reset software totals */
 944         memset(hw_stats, 0, sizeof(*hw_stats));
 945 }
 946
 947 static int
 948 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
 949 {
 950         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 951
 952         em_rxq_intr_enable(hw);
 953         rte_intr_enable(&dev->pci_dev->intr_handle);
 954
 955         return 0;
 956 }
 957
 958 static int
 959 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
 960 {
 961         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 962
 963         em_rxq_intr_disable(hw);
 964
 965         return 0;
 966 }
 967
 968 static uint32_t
 969 em_get_max_pktlen(const struct e1000_hw *hw)
 970 {
 971         switch (hw->mac.type) {
 972         case e1000_82571:
 973         case e1000_82572:
 974         case e1000_ich9lan:
 975         case e1000_ich10lan:
 976         case e1000_pch2lan:
 977         case e1000_82574:
 978         case e1000_80003es2lan: /* 9K Jumbo Frame size */
 979         case e1000_82583:
 980                 return (0x2412);
 981         case e1000_pchlan:
 982                 return (0x1000);
 983         /* Adapters that do not support jumbo frames */
 984         case e1000_ich8lan:
 985                 return (ETHER_MAX_LEN);
 986         default:
 987                 return (MAX_JUMBO_FRAME_SIZE);
 988         }
 989 }
 990
 991 static void
 992 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 993 {
 994         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 995
 996         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
 997         dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
 998         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
 999
1000         /*
1001          * Starting with 631xESB hw supports 2 TX/RX queues per port.
1002          * Unfortunatelly, all these nics have just one TX context.
1003          * So we have few choises for TX:
1004          * - Use just one TX queue.
1005          * - Allow cksum offload only for one TX queue.
1006          * - Don't allow TX cksum offload at all.
1007          * For now, option #1 was chosen.
1008          * To use second RX queue we have to use extended RX descriptor
1009          * (Multiple Receive Queues are mutually exclusive with UDP
1010          * fragmentation and are not supported when a legacy receive
1011          * descriptor format is used).
1012          * Which means separate RX routinies - as legacy nics (82540, 82545)
1013          * don't support extended RXD.
1014          * To avoid it we support just one RX queue for now (no RSS).
1015          */
1016
1017         dev_info->max_rx_queues = 1;
1018         dev_info->max_tx_queues = 1;
1019
1020         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1021                 .nb_max = E1000_MAX_RING_DESC,
1022                 .nb_min = E1000_MIN_RING_DESC,
1023                 .nb_align = EM_RXD_ALIGN,
1024         };
1025
1026         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1027                 .nb_max = E1000_MAX_RING_DESC,
1028                 .nb_min = E1000_MIN_RING_DESC,
1029                 .nb_align = EM_TXD_ALIGN,
1030         };
1031 }
1032
1033 /* return 0 means link status changed, -1 means not changed */
1034 static int
1035 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1036 {
1037         struct e1000_hw *hw =
1038                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1039         struct rte_eth_link link, old;
1040         int link_check, count;
1041
1042         link_check = 0;
1043         hw->mac.get_link_status = 1;
1044
1045         /* possible wait-to-complete in up to 9 seconds */
1046         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1047                 /* Read the real link status */
1048                 switch (hw->phy.media_type) {
1049                 case e1000_media_type_copper:
1050                         /* Do the work to read phy */
1051                         e1000_check_for_link(hw);
1052                         link_check = !hw->mac.get_link_status;
1053                         break;
1054
1055                 case e1000_media_type_fiber:
1056                         e1000_check_for_link(hw);
1057                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1058                                         E1000_STATUS_LU);
1059                         break;
1060
1061                 case e1000_media_type_internal_serdes:
1062                         e1000_check_for_link(hw);
1063                         link_check = hw->mac.serdes_has_link;
1064                         break;
1065
1066                 default:
1067                         break;
1068                 }
1069                 if (link_check || wait_to_complete == 0)
1070                         break;
1071                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1072         }
1073         memset(&link, 0, sizeof(link));
1074         rte_em_dev_atomic_read_link_status(dev, &link);
1075         old = link;
1076
1077         /* Now we check if a transition has happened */
1078         if (link_check && (link.link_status == 0)) {
1079                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1080                         &link.link_duplex);
1081                 link.link_status = 1;
1082         } else if (!link_check && (link.link_status == 1)) {
1083                 link.link_speed = 0;
1084                 link.link_duplex = 0;
1085                 link.link_status = 0;
1086         }
1087         rte_em_dev_atomic_write_link_status(dev, &link);
1088
1089         /* not changed */
1090         if (old.link_status == link.link_status)
1091                 return -1;
1092
1093         /* changed */
1094         return 0;
1095 }
1096
1097 /*
1098  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1099  * For ASF and Pass Through versions of f/w this means
1100  * that the driver is loaded. For AMT version type f/w
1101  * this means that the network i/f is open.
1102  */
1103 static void
1104 em_hw_control_acquire(struct e1000_hw *hw)
1105 {
1106         uint32_t ctrl_ext, swsm;
1107
1108         /* Let firmware know the driver has taken over */
1109         if (hw->mac.type == e1000_82573) {
1110                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1111                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1112
1113         } else {
1114                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1115                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1116                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1117         }
1118 }
1119
1120 /*
1121  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1122  * For ASF and Pass Through versions of f/w this means that the
1123  * driver is no longer loaded. For AMT versions of the
1124  * f/w this means that the network i/f is closed.
1125  */
1126 static void
1127 em_hw_control_release(struct e1000_hw *hw)
1128 {
1129         uint32_t ctrl_ext, swsm;
1130
1131         /* Let firmware taken over control of h/w */
1132         if (hw->mac.type == e1000_82573) {
1133                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1134                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1135         } else {
1136                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1137                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1138                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1139         }
1140 }
1141
1142 /*
1143  * Bit of a misnomer, what this really means is
1144  * to enable OS management of the system... aka
1145  * to disable special hardware management features.
1146  */
1147 static void
1148 em_init_manageability(struct e1000_hw *hw)
1149 {
1150         if (e1000_enable_mng_pass_thru(hw)) {
1151                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1152                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1153
1154                 /* disable hardware interception of ARP */
1155                 manc &= ~(E1000_MANC_ARP_EN);
1156
1157                 /* enable receiving management packets to the host */
1158                 manc |= E1000_MANC_EN_MNG2HOST;
1159                 manc2h |= 1 << 5;  /* Mng Port 623 */
1160                 manc2h |= 1 << 6;  /* Mng Port 664 */
1161                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1162                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1163         }
1164 }
1165
1166 /*
1167  * Give control back to hardware management
1168  * controller if there is one.
1169  */
1170 static void
1171 em_release_manageability(struct e1000_hw *hw)
1172 {
1173         uint32_t manc;
1174
1175         if (e1000_enable_mng_pass_thru(hw)) {
1176                 manc = E1000_READ_REG(hw, E1000_MANC);
1177
1178                 /* re-enable hardware interception of ARP */
1179                 manc |= E1000_MANC_ARP_EN;
1180                 manc &= ~E1000_MANC_EN_MNG2HOST;
1181
1182                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1183         }
1184 }
1185
1186 static void
1187 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1188 {
1189         struct e1000_hw *hw =
1190                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1191         uint32_t rctl;
1192
1193         rctl = E1000_READ_REG(hw, E1000_RCTL);
1194         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1195         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1196 }
1197
1198 static void
1199 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1200 {
1201         struct e1000_hw *hw =
1202                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1203         uint32_t rctl;
1204
1205         rctl = E1000_READ_REG(hw, E1000_RCTL);
1206         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1207         if (dev->data->all_multicast == 1)
1208                 rctl |= E1000_RCTL_MPE;
1209         else
1210                 rctl &= (~E1000_RCTL_MPE);
1211         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1212 }
1213
1214 static void
1215 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1216 {
1217         struct e1000_hw *hw =
1218                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1219         uint32_t rctl;
1220
1221         rctl = E1000_READ_REG(hw, E1000_RCTL);
1222         rctl |= E1000_RCTL_MPE;
1223         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1224 }
1225
1226 static void
1227 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1228 {
1229         struct e1000_hw *hw =
1230                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1231         uint32_t rctl;
1232
1233         if (dev->data->promiscuous == 1)
1234                 return; /* must remain in all_multicast mode */
1235         rctl = E1000_READ_REG(hw, E1000_RCTL);
1236         rctl &= (~E1000_RCTL_MPE);
1237         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1238 }
1239
1240 static int
1241 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1242 {
1243         struct e1000_hw *hw =
1244                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1245         struct e1000_vfta * shadow_vfta =
1246                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1247         uint32_t vfta;
1248         uint32_t vid_idx;
1249         uint32_t vid_bit;
1250
1251         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1252                               E1000_VFTA_ENTRY_MASK);
1253         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1254         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1255         if (on)
1256                 vfta |= vid_bit;
1257         else
1258                 vfta &= ~vid_bit;
1259         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1260
1261         /* update local VFTA copy */
1262         shadow_vfta->vfta[vid_idx] = vfta;
1263
1264         return 0;
1265 }
1266
1267 static void
1268 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1269 {
1270         struct e1000_hw *hw =
1271                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1272         uint32_t reg;
1273
1274         /* Filter Table Disable */
1275         reg = E1000_READ_REG(hw, E1000_RCTL);
1276         reg &= ~E1000_RCTL_CFIEN;
1277         reg &= ~E1000_RCTL_VFE;
1278         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1279 }
1280
1281 static void
1282 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1283 {
1284         struct e1000_hw *hw =
1285                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1286         struct e1000_vfta * shadow_vfta =
1287                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1288         uint32_t reg;
1289         int i;
1290
1291         /* Filter Table Enable, CFI not used for packet acceptance */
1292         reg = E1000_READ_REG(hw, E1000_RCTL);
1293         reg &= ~E1000_RCTL_CFIEN;
1294         reg |= E1000_RCTL_VFE;
1295         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1296
1297         /* restore vfta from local copy */
1298         for (i = 0; i < IGB_VFTA_SIZE; i++)
1299                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1300 }
1301
1302 static void
1303 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1304 {
1305         struct e1000_hw *hw =
1306                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1307         uint32_t reg;
1308
1309         /* VLAN Mode Disable */
1310         reg = E1000_READ_REG(hw, E1000_CTRL);
1311         reg &= ~E1000_CTRL_VME;
1312         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1313
1314 }
1315
1316 static void
1317 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1318 {
1319         struct e1000_hw *hw =
1320                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1321         uint32_t reg;
1322
1323         /* VLAN Mode Enable */
1324         reg = E1000_READ_REG(hw, E1000_CTRL);
1325         reg |= E1000_CTRL_VME;
1326         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1327 }
1328
1329 static void
1330 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1331 {
1332         if(mask & ETH_VLAN_STRIP_MASK){
1333                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1334                         em_vlan_hw_strip_enable(dev);
1335                 else
1336                         em_vlan_hw_strip_disable(dev);
1337         }
1338
1339         if(mask & ETH_VLAN_FILTER_MASK){
1340                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1341                         em_vlan_hw_filter_enable(dev);
1342                 else
1343                         em_vlan_hw_filter_disable(dev);
1344         }
1345 }
1346
1347 /*
1348  * It enables the interrupt mask and then enable the interrupt.
1349  *
1350  * @param dev
1351  *  Pointer to struct rte_eth_dev.
1352  *
1353  * @return
1354  *  - On success, zero.
1355  *  - On failure, a negative value.
1356  */
1357 static int
1358 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1359 {
1360         uint32_t regval;
1361         struct e1000_hw *hw =
1362                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1363
1364         /* clear interrupt */
1365         E1000_READ_REG(hw, E1000_ICR);
1366         regval = E1000_READ_REG(hw, E1000_IMS);
1367         E1000_WRITE_REG(hw, E1000_IMS, regval | E1000_ICR_LSC);
1368         return (0);
1369 }
1370
1371 /*
1372  * It clears the interrupt causes and enables the interrupt.
1373  * It will be called once only during nic initialized.
1374  *
1375  * @param dev
1376  *  Pointer to struct rte_eth_dev.
1377  *
1378  * @return
1379  *  - On success, zero.
1380  *  - On failure, a negative value.
1381  */
1382 static int
1383 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1384 {
1385         struct e1000_hw *hw =
1386         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1387
1388         E1000_READ_REG(hw, E1000_ICR);
1389         em_rxq_intr_enable(hw);
1390         return 0;
1391 }
1392
1393 /*
1394  * It enable receive packet interrupt.
1395  * @param hw
1396  * Pointer to struct e1000_hw
1397  *
1398  * @return
1399  */
1400 static void
1401 em_rxq_intr_enable(struct e1000_hw *hw)
1402 {
1403         E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1404         E1000_WRITE_FLUSH(hw);
1405 }
1406
1407 /*
1408  * It disabled lsc interrupt.
1409  * @param hw
1410  * Pointer to struct e1000_hw
1411  *
1412  * @return
1413  */
1414 static void
1415 em_lsc_intr_disable(struct e1000_hw *hw)
1416 {
1417         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC);
1418         E1000_WRITE_FLUSH(hw);
1419 }
1420
1421 /*
1422  * It disabled receive packet interrupt.
1423  * @param hw
1424  * Pointer to struct e1000_hw
1425  *
1426  * @return
1427  */
1428 static void
1429 em_rxq_intr_disable(struct e1000_hw *hw)
1430 {
1431         E1000_READ_REG(hw, E1000_ICR);
1432         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1433         E1000_WRITE_FLUSH(hw);
1434 }
1435
1436 /*
1437  * It reads ICR and gets interrupt causes, check it and set a bit flag
1438  * to update link status.
1439  *
1440  * @param dev
1441  *  Pointer to struct rte_eth_dev.
1442  *
1443  * @return
1444  *  - On success, zero.
1445  *  - On failure, a negative value.
1446  */
1447 static int
1448 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1449 {
1450         uint32_t icr;
1451         struct e1000_hw *hw =
1452                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1453         struct e1000_interrupt *intr =
1454                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1455
1456         /* read-on-clear nic registers here */
1457         icr = E1000_READ_REG(hw, E1000_ICR);
1458         if (icr & E1000_ICR_LSC) {
1459                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1460         }
1461
1462         return 0;
1463 }
1464
1465 /*
1466  * It executes link_update after knowing an interrupt is prsent.
1467  *
1468  * @param dev
1469  *  Pointer to struct rte_eth_dev.
1470  *
1471  * @return
1472  *  - On success, zero.
1473  *  - On failure, a negative value.
1474  */
1475 static int
1476 eth_em_interrupt_action(struct rte_eth_dev *dev)
1477 {
1478         struct e1000_hw *hw =
1479                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1480         struct e1000_interrupt *intr =
1481                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1482         uint32_t tctl, rctl;
1483         struct rte_eth_link link;
1484         int ret;
1485
1486         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1487                 return -1;
1488
1489         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1490         rte_intr_enable(&(dev->pci_dev->intr_handle));
1491
1492         /* set get_link_status to check register later */
1493         hw->mac.get_link_status = 1;
1494         ret = eth_em_link_update(dev, 0);
1495
1496         /* check if link has changed */
1497         if (ret < 0)
1498                 return 0;
1499
1500         memset(&link, 0, sizeof(link));
1501         rte_em_dev_atomic_read_link_status(dev, &link);
1502         if (link.link_status) {
1503                 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1504                              dev->data->port_id, (unsigned)link.link_speed,
1505                              link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1506                              "full-duplex" : "half-duplex");
1507         } else {
1508                 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1509         }
1510         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1511                      dev->pci_dev->addr.domain, dev->pci_dev->addr.bus,
1512                      dev->pci_dev->addr.devid, dev->pci_dev->addr.function);
1513
1514         tctl = E1000_READ_REG(hw, E1000_TCTL);
1515         rctl = E1000_READ_REG(hw, E1000_RCTL);
1516         if (link.link_status) {
1517                 /* enable Tx/Rx */
1518                 tctl |= E1000_TCTL_EN;
1519                 rctl |= E1000_RCTL_EN;
1520         } else {
1521                 /* disable Tx/Rx */
1522                 tctl &= ~E1000_TCTL_EN;
1523                 rctl &= ~E1000_RCTL_EN;
1524         }
1525         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1526         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1527         E1000_WRITE_FLUSH(hw);
1528
1529         return 0;
1530 }
1531
1532 /**
1533  * Interrupt handler which shall be registered at first.
1534  *
1535  * @param handle
1536  *  Pointer to interrupt handle.
1537  * @param param
1538  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1539  *
1540  * @return
1541  *  void
1542  */
1543 static void
1544 eth_em_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1545                                                         void *param)
1546 {
1547         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1548
1549         eth_em_interrupt_get_status(dev);
1550         eth_em_interrupt_action(dev);
1551         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1552 }
1553
1554 static int
1555 eth_em_led_on(struct rte_eth_dev *dev)
1556 {
1557         struct e1000_hw *hw;
1558
1559         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1560         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1561 }
1562
1563 static int
1564 eth_em_led_off(struct rte_eth_dev *dev)
1565 {
1566         struct e1000_hw *hw;
1567
1568         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1569         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1570 }
1571
1572 static int
1573 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1574 {
1575         struct e1000_hw *hw;
1576         uint32_t ctrl;
1577         int tx_pause;
1578         int rx_pause;
1579
1580         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1581         fc_conf->pause_time = hw->fc.pause_time;
1582         fc_conf->high_water = hw->fc.high_water;
1583         fc_conf->low_water = hw->fc.low_water;
1584         fc_conf->send_xon = hw->fc.send_xon;
1585         fc_conf->autoneg = hw->mac.autoneg;
1586
1587         /*
1588          * Return rx_pause and tx_pause status according to actual setting of
1589          * the TFCE and RFCE bits in the CTRL register.
1590          */
1591         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1592         if (ctrl & E1000_CTRL_TFCE)
1593                 tx_pause = 1;
1594         else
1595                 tx_pause = 0;
1596
1597         if (ctrl & E1000_CTRL_RFCE)
1598                 rx_pause = 1;
1599         else
1600                 rx_pause = 0;
1601
1602         if (rx_pause && tx_pause)
1603                 fc_conf->mode = RTE_FC_FULL;
1604         else if (rx_pause)
1605                 fc_conf->mode = RTE_FC_RX_PAUSE;
1606         else if (tx_pause)
1607                 fc_conf->mode = RTE_FC_TX_PAUSE;
1608         else
1609                 fc_conf->mode = RTE_FC_NONE;
1610
1611         return 0;
1612 }
1613
1614 static int
1615 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1616 {
1617         struct e1000_hw *hw;
1618         int err;
1619         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1620                 e1000_fc_none,
1621                 e1000_fc_rx_pause,
1622                 e1000_fc_tx_pause,
1623                 e1000_fc_full
1624         };
1625         uint32_t rx_buf_size;
1626         uint32_t max_high_water;
1627         uint32_t rctl;
1628
1629         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1630         if (fc_conf->autoneg != hw->mac.autoneg)
1631                 return -ENOTSUP;
1632         rx_buf_size = em_get_rx_buffer_size(hw);
1633         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1634
1635         /* At least reserve one Ethernet frame for watermark */
1636         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1637         if ((fc_conf->high_water > max_high_water) ||
1638             (fc_conf->high_water < fc_conf->low_water)) {
1639                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1640                 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1641                 return (-EINVAL);
1642         }
1643
1644         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1645         hw->fc.pause_time     = fc_conf->pause_time;
1646         hw->fc.high_water     = fc_conf->high_water;
1647         hw->fc.low_water      = fc_conf->low_water;
1648         hw->fc.send_xon       = fc_conf->send_xon;
1649
1650         err = e1000_setup_link_generic(hw);
1651         if (err == E1000_SUCCESS) {
1652
1653                 /* check if we want to forward MAC frames - driver doesn't have native
1654                  * capability to do that, so we'll write the registers ourselves */
1655
1656                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1657
1658                 /* set or clear MFLCN.PMCF bit depending on configuration */
1659                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1660                         rctl |= E1000_RCTL_PMCF;
1661                 else
1662                         rctl &= ~E1000_RCTL_PMCF;
1663
1664                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1665                 E1000_WRITE_FLUSH(hw);
1666
1667                 return 0;
1668         }
1669
1670         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1671         return (-EIO);
1672 }
1673
1674 static void
1675 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1676                 uint32_t index, __rte_unused uint32_t pool)
1677 {
1678         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1679
1680         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1681 }
1682
1683 static void
1684 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1685 {
1686         uint8_t addr[ETHER_ADDR_LEN];
1687         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1688
1689         memset(addr, 0, sizeof(addr));
1690
1691         e1000_rar_set(hw, addr, index);
1692 }
1693
1694 static int
1695 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1696 {
1697         struct rte_eth_dev_info dev_info;
1698         struct e1000_hw *hw;
1699         uint32_t frame_size;
1700         uint32_t rctl;
1701
1702         eth_em_infos_get(dev, &dev_info);
1703         frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1704
1705         /* check that mtu is within the allowed range */
1706         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1707                 return -EINVAL;
1708
1709         /* refuse mtu that requires the support of scattered packets when this
1710          * feature has not been enabled before. */
1711         if (!dev->data->scattered_rx &&
1712             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1713                 return -EINVAL;
1714
1715         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1716         rctl = E1000_READ_REG(hw, E1000_RCTL);
1717
1718         /* switch to jumbo mode if needed */
1719         if (frame_size > ETHER_MAX_LEN) {
1720                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1721                 rctl |= E1000_RCTL_LPE;
1722         } else {
1723                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1724                 rctl &= ~E1000_RCTL_LPE;
1725         }
1726         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1727
1728         /* update max frame size */
1729         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1730         return 0;
1731 }
1732
1733 static int
1734 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1735                         struct ether_addr *mc_addr_set,
1736                         uint32_t nb_mc_addr)
1737 {
1738         struct e1000_hw *hw;
1739
1740         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1741         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1742         return 0;
1743 }
1744
1745 struct rte_driver em_pmd_drv = {
1746         .type = PMD_PDEV,
1747         .init = rte_em_pmd_init,
1748 };
1749
1750 PMD_REGISTER_DRIVER(em_pmd_drv);