drivers/net/e1000/em_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58
  59 #define EM_EIAC                 0x000DC
  60
  61 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
  62
  63
  64 static int eth_em_configure(struct rte_eth_dev *dev);
  65 static int eth_em_start(struct rte_eth_dev *dev);
  66 static void eth_em_stop(struct rte_eth_dev *dev);
  67 static void eth_em_close(struct rte_eth_dev *dev);
  68 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
  69 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
  70 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
  71 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
  72 static int eth_em_link_update(struct rte_eth_dev *dev,
  73                                 int wait_to_complete);
  74 static void eth_em_stats_get(struct rte_eth_dev *dev,
  75                                 struct rte_eth_stats *rte_stats);
  76 static void eth_em_stats_reset(struct rte_eth_dev *dev);
  77 static void eth_em_infos_get(struct rte_eth_dev *dev,
  78                                 struct rte_eth_dev_info *dev_info);
  79 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
  80                                 struct rte_eth_fc_conf *fc_conf);
  81 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
  82                                 struct rte_eth_fc_conf *fc_conf);
  83 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
  84 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
  85 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
  86 static int eth_em_interrupt_action(struct rte_eth_dev *dev);
  87 static void eth_em_interrupt_handler(struct rte_intr_handle *handle,
  88                                                         void *param);
  89
  90 static int em_hw_init(struct e1000_hw *hw);
  91 static int em_hardware_init(struct e1000_hw *hw);
  92 static void em_hw_control_acquire(struct e1000_hw *hw);
  93 static void em_hw_control_release(struct e1000_hw *hw);
  94 static void em_init_manageability(struct e1000_hw *hw);
  95 static void em_release_manageability(struct e1000_hw *hw);
  96
  97 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  98
  99 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
 100                 uint16_t vlan_id, int on);
 101 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 102 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 103 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 104 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 105 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 106
 107 /*
 108 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
 109                                         uint16_t vlan_id, int on);
 110 */
 111
 112 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
 113 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
 114 static void em_lsc_intr_disable(struct e1000_hw *hw);
 115 static void em_rxq_intr_enable(struct e1000_hw *hw);
 116 static void em_rxq_intr_disable(struct e1000_hw *hw);
 117
 118 static int eth_em_led_on(struct rte_eth_dev *dev);
 119 static int eth_em_led_off(struct rte_eth_dev *dev);
 120
 121 static int em_get_rx_buffer_size(struct e1000_hw *hw);
 122 static void eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 123                 uint32_t index, uint32_t pool);
 124 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 125
 126 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
 127                                    struct ether_addr *mc_addr_set,
 128                                    uint32_t nb_mc_addr);
 129
 130 #define EM_FC_PAUSE_TIME 0x0680
 131 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 132 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 133
 134 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
 135
 136 /*
 137  * The set of PCI devices this driver supports
 138  */
 139 static const struct rte_pci_id pci_id_em_map[] = {
 140         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
 141         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
 142         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
 143         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
 144         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
 145         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
 146         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
 147         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
 148         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
 149         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
 150         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
 151         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
 152         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
 153         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
 154         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
 155         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
 156         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
 157         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
 158         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
 159         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
 160         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
 161         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
 162         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
 163         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
 164         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
 165         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
 166         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
 167         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
 168         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
 169         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
 170         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
 171         { .vendor_id = 0, /* sentinel */ },
 172 };
 173
 174 static const struct eth_dev_ops eth_em_ops = {
 175         .dev_configure        = eth_em_configure,
 176         .dev_start            = eth_em_start,
 177         .dev_stop             = eth_em_stop,
 178         .dev_close            = eth_em_close,
 179         .promiscuous_enable   = eth_em_promiscuous_enable,
 180         .promiscuous_disable  = eth_em_promiscuous_disable,
 181         .allmulticast_enable  = eth_em_allmulticast_enable,
 182         .allmulticast_disable = eth_em_allmulticast_disable,
 183         .link_update          = eth_em_link_update,
 184         .stats_get            = eth_em_stats_get,
 185         .stats_reset          = eth_em_stats_reset,
 186         .dev_infos_get        = eth_em_infos_get,
 187         .mtu_set              = eth_em_mtu_set,
 188         .vlan_filter_set      = eth_em_vlan_filter_set,
 189         .vlan_offload_set     = eth_em_vlan_offload_set,
 190         .rx_queue_setup       = eth_em_rx_queue_setup,
 191         .rx_queue_release     = eth_em_rx_queue_release,
 192         .rx_queue_count       = eth_em_rx_queue_count,
 193         .rx_descriptor_done   = eth_em_rx_descriptor_done,
 194         .tx_queue_setup       = eth_em_tx_queue_setup,
 195         .tx_queue_release     = eth_em_tx_queue_release,
 196         .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
 197         .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
 198         .dev_led_on           = eth_em_led_on,
 199         .dev_led_off          = eth_em_led_off,
 200         .flow_ctrl_get        = eth_em_flow_ctrl_get,
 201         .flow_ctrl_set        = eth_em_flow_ctrl_set,
 202         .mac_addr_add         = eth_em_rar_set,
 203         .mac_addr_remove      = eth_em_rar_clear,
 204         .set_mc_addr_list     = eth_em_set_mc_addr_list,
 205         .rxq_info_get         = em_rxq_info_get,
 206         .txq_info_get         = em_txq_info_get,
 207 };
 208
 209 /**
 210  * Atomically reads the link status information from global
 211  * structure rte_eth_dev.
 212  *
 213  * @param dev
 214  *   - Pointer to the structure rte_eth_dev to read from.
 215  *   - Pointer to the buffer to be saved with the link status.
 216  *
 217  * @return
 218  *   - On success, zero.
 219  *   - On failure, negative value.
 220  */
 221 static inline int
 222 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 223                                 struct rte_eth_link *link)
 224 {
 225         struct rte_eth_link *dst = link;
 226         struct rte_eth_link *src = &(dev->data->dev_link);
 227
 228         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 229                                         *(uint64_t *)src) == 0)
 230                 return -1;
 231
 232         return 0;
 233 }
 234
 235 /**
 236  * Atomically writes the link status information into global
 237  * structure rte_eth_dev.
 238  *
 239  * @param dev
 240  *   - Pointer to the structure rte_eth_dev to read from.
 241  *   - Pointer to the buffer to be saved with the link status.
 242  *
 243  * @return
 244  *   - On success, zero.
 245  *   - On failure, negative value.
 246  */
 247 static inline int
 248 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 249                                 struct rte_eth_link *link)
 250 {
 251         struct rte_eth_link *dst = &(dev->data->dev_link);
 252         struct rte_eth_link *src = link;
 253
 254         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 255                                         *(uint64_t *)src) == 0)
 256                 return -1;
 257
 258         return 0;
 259 }
 260
 261 /**
 262  *  eth_em_dev_is_ich8 - Check for ICH8 device
 263  *  @hw: pointer to the HW structure
 264  *
 265  *  return TRUE for ICH8, otherwise FALSE
 266  **/
 267 static bool
 268 eth_em_dev_is_ich8(struct e1000_hw *hw)
 269 {
 270         DEBUGFUNC("eth_em_dev_is_ich8");
 271
 272         switch (hw->device_id) {
 273         case E1000_DEV_ID_PCH_LPT_I217_LM:
 274         case E1000_DEV_ID_PCH_LPT_I217_V:
 275         case E1000_DEV_ID_PCH_LPTLP_I218_LM:
 276         case E1000_DEV_ID_PCH_LPTLP_I218_V:
 277         case E1000_DEV_ID_PCH_I218_V2:
 278         case E1000_DEV_ID_PCH_I218_LM2:
 279         case E1000_DEV_ID_PCH_I218_V3:
 280         case E1000_DEV_ID_PCH_I218_LM3:
 281                 return 1;
 282         default:
 283                 return 0;
 284         }
 285 }
 286
 287 static int
 288 eth_em_dev_init(struct rte_eth_dev *eth_dev)
 289 {
 290         struct rte_pci_device *pci_dev;
 291         struct e1000_adapter *adapter =
 292                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 293         struct e1000_hw *hw =
 294                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 295         struct e1000_vfta * shadow_vfta =
 296                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 297
 298         pci_dev = eth_dev->pci_dev;
 299
 300         eth_dev->dev_ops = &eth_em_ops;
 301         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
 302         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
 303
 304         /* for secondary processes, we don't initialise any further as primary
 305          * has already done this work. Only check we don't need a different
 306          * RX function */
 307         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 308                 if (eth_dev->data->scattered_rx)
 309                         eth_dev->rx_pkt_burst =
 310                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
 311                 return 0;
 312         }
 313
 314         rte_eth_copy_pci_info(eth_dev, pci_dev);
 315
 316         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 317         hw->device_id = pci_dev->id.device_id;
 318         adapter->stopped = 0;
 319
 320         /* For ICH8 support we'll need to map the flash memory BAR */
 321         if (eth_em_dev_is_ich8(hw))
 322                 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
 323
 324         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
 325                         em_hw_init(hw) != 0) {
 326                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
 327                         "failed to init HW",
 328                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 329                         pci_dev->id.device_id);
 330                 return -ENODEV;
 331         }
 332
 333         /* Allocate memory for storing MAC addresses */
 334         eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
 335                         hw->mac.rar_entry_count, 0);
 336         if (eth_dev->data->mac_addrs == NULL) {
 337                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 338                         "store MAC addresses",
 339                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 340                 return -ENOMEM;
 341         }
 342
 343         /* Copy the permanent MAC address */
 344         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 345                 eth_dev->data->mac_addrs);
 346
 347         /* initialize the vfta */
 348         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 349
 350         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 351                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 352                      pci_dev->id.device_id);
 353
 354         rte_intr_callback_register(&(pci_dev->intr_handle),
 355                 eth_em_interrupt_handler, (void *)eth_dev);
 356
 357         return 0;
 358 }
 359
 360 static int
 361 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
 362 {
 363         struct rte_pci_device *pci_dev;
 364         struct e1000_adapter *adapter =
 365                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 366
 367         PMD_INIT_FUNC_TRACE();
 368
 369         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 370                 return -EPERM;
 371
 372         pci_dev = eth_dev->pci_dev;
 373
 374         if (adapter->stopped == 0)
 375                 eth_em_close(eth_dev);
 376
 377         eth_dev->dev_ops = NULL;
 378         eth_dev->rx_pkt_burst = NULL;
 379         eth_dev->tx_pkt_burst = NULL;
 380
 381         rte_free(eth_dev->data->mac_addrs);
 382         eth_dev->data->mac_addrs = NULL;
 383
 384         /* disable uio intr before callback unregister */
 385         rte_intr_disable(&(pci_dev->intr_handle));
 386         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 387                 eth_em_interrupt_handler, (void *)eth_dev);
 388
 389         return 0;
 390 }
 391
 392 static struct eth_driver rte_em_pmd = {
 393         .pci_drv = {
 394                 .name = "rte_em_pmd",
 395                 .id_table = pci_id_em_map,
 396                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 397                         RTE_PCI_DRV_DETACHABLE,
 398                 .probe = rte_eth_dev_pci_probe,
 399                 .remove = rte_eth_dev_pci_remove,
 400         },
 401         .eth_dev_init = eth_em_dev_init,
 402         .eth_dev_uninit = eth_em_dev_uninit,
 403         .dev_private_size = sizeof(struct e1000_adapter),
 404 };
 405
 406 static int
 407 em_hw_init(struct e1000_hw *hw)
 408 {
 409         int diag;
 410
 411         diag = hw->mac.ops.init_params(hw);
 412         if (diag != 0) {
 413                 PMD_INIT_LOG(ERR, "MAC Initialization Error");
 414                 return diag;
 415         }
 416         diag = hw->nvm.ops.init_params(hw);
 417         if (diag != 0) {
 418                 PMD_INIT_LOG(ERR, "NVM Initialization Error");
 419                 return diag;
 420         }
 421         diag = hw->phy.ops.init_params(hw);
 422         if (diag != 0) {
 423                 PMD_INIT_LOG(ERR, "PHY Initialization Error");
 424                 return diag;
 425         }
 426         (void) e1000_get_bus_info(hw);
 427
 428         hw->mac.autoneg = 1;
 429         hw->phy.autoneg_wait_to_complete = 0;
 430         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 431
 432         e1000_init_script_state_82541(hw, TRUE);
 433         e1000_set_tbi_compatibility_82543(hw, TRUE);
 434
 435         /* Copper options */
 436         if (hw->phy.media_type == e1000_media_type_copper) {
 437                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 438                 hw->phy.disable_polarity_correction = 0;
 439                 hw->phy.ms_type = e1000_ms_hw_default;
 440         }
 441
 442         /*
 443          * Start from a known state, this is important in reading the nvm
 444          * and mac from that.
 445          */
 446         e1000_reset_hw(hw);
 447
 448         /* Make sure we have a good EEPROM before we read from it */
 449         if (e1000_validate_nvm_checksum(hw) < 0) {
 450                 /*
 451                  * Some PCI-E parts fail the first check due to
 452                  * the link being in sleep state, call it again,
 453                  * if it fails a second time its a real issue.
 454                  */
 455                 diag = e1000_validate_nvm_checksum(hw);
 456                 if (diag < 0) {
 457                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 458                         goto error;
 459                 }
 460         }
 461
 462         /* Read the permanent MAC address out of the EEPROM */
 463         diag = e1000_read_mac_addr(hw);
 464         if (diag != 0) {
 465                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 466                 goto error;
 467         }
 468
 469         /* Now initialize the hardware */
 470         diag = em_hardware_init(hw);
 471         if (diag != 0) {
 472                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 473                 goto error;
 474         }
 475
 476         hw->mac.get_link_status = 1;
 477
 478         /* Indicate SOL/IDER usage */
 479         diag = e1000_check_reset_block(hw);
 480         if (diag < 0) {
 481                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
 482                         "SOL/IDER session");
 483         }
 484         return 0;
 485
 486 error:
 487         em_hw_control_release(hw);
 488         return diag;
 489 }
 490
 491 static int
 492 eth_em_configure(struct rte_eth_dev *dev)
 493 {
 494         struct e1000_interrupt *intr =
 495                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 496
 497         PMD_INIT_FUNC_TRACE();
 498         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 499         PMD_INIT_FUNC_TRACE();
 500
 501         return 0;
 502 }
 503
 504 static void
 505 em_set_pba(struct e1000_hw *hw)
 506 {
 507         uint32_t pba;
 508
 509         /*
 510          * Packet Buffer Allocation (PBA)
 511          * Writing PBA sets the receive portion of the buffer
 512          * the remainder is used for the transmit buffer.
 513          * Devices before the 82547 had a Packet Buffer of 64K.
 514          * After the 82547 the buffer was reduced to 40K.
 515          */
 516         switch (hw->mac.type) {
 517                 case e1000_82547:
 518                 case e1000_82547_rev_2:
 519                 /* 82547: Total Packet Buffer is 40K */
 520                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
 521                         break;
 522                 case e1000_82571:
 523                 case e1000_82572:
 524                 case e1000_80003es2lan:
 525                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 526                         break;
 527                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
 528                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
 529                         break;
 530                 case e1000_82574:
 531                 case e1000_82583:
 532                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
 533                         break;
 534                 case e1000_ich8lan:
 535                         pba = E1000_PBA_8K;
 536                         break;
 537                 case e1000_ich9lan:
 538                 case e1000_ich10lan:
 539                         pba = E1000_PBA_10K;
 540                         break;
 541                 case e1000_pchlan:
 542                 case e1000_pch2lan:
 543                 case e1000_pch_lpt:
 544                         pba = E1000_PBA_26K;
 545                         break;
 546                 default:
 547                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
 548         }
 549
 550         E1000_WRITE_REG(hw, E1000_PBA, pba);
 551 }
 552
 553 static int
 554 eth_em_start(struct rte_eth_dev *dev)
 555 {
 556         struct e1000_adapter *adapter =
 557                 E1000_DEV_PRIVATE(dev->data->dev_private);
 558         struct e1000_hw *hw =
 559                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 560         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
 561         int ret, mask;
 562         uint32_t intr_vector = 0;
 563         uint32_t *speeds;
 564         int num_speeds;
 565         bool autoneg;
 566
 567         PMD_INIT_FUNC_TRACE();
 568
 569         eth_em_stop(dev);
 570
 571         e1000_power_up_phy(hw);
 572
 573         /* Set default PBA value */
 574         em_set_pba(hw);
 575
 576         /* Put the address into the Receive Address Array */
 577         e1000_rar_set(hw, hw->mac.addr, 0);
 578
 579         /*
 580          * With the 82571 adapter, RAR[0] may be overwritten
 581          * when the other port is reset, we make a duplicate
 582          * in RAR[14] for that eventuality, this assures
 583          * the interface continues to function.
 584          */
 585         if (hw->mac.type == e1000_82571) {
 586                 e1000_set_laa_state_82571(hw, TRUE);
 587                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
 588         }
 589
 590         /* Initialize the hardware */
 591         if (em_hardware_init(hw)) {
 592                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 593                 return -EIO;
 594         }
 595
 596         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 597
 598         /* Configure for OS presence */
 599         em_init_manageability(hw);
 600
 601         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 602                 intr_vector = dev->data->nb_rx_queues;
 603                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 604                         return -1;
 605         }
 606
 607         if (rte_intr_dp_is_en(intr_handle)) {
 608                 intr_handle->intr_vec =
 609                         rte_zmalloc("intr_vec",
 610                                         dev->data->nb_rx_queues * sizeof(int), 0);
 611                 if (intr_handle->intr_vec == NULL) {
 612                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 613                                                 " intr_vec\n", dev->data->nb_rx_queues);
 614                         return -ENOMEM;
 615                 }
 616
 617                 /* enable rx interrupt */
 618                 em_rxq_intr_enable(hw);
 619         }
 620
 621         eth_em_tx_init(dev);
 622
 623         ret = eth_em_rx_init(dev);
 624         if (ret) {
 625                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 626                 em_dev_clear_queues(dev);
 627                 return ret;
 628         }
 629
 630         e1000_clear_hw_cntrs_base_generic(hw);
 631
 632         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 633                         ETH_VLAN_EXTEND_MASK;
 634         eth_em_vlan_offload_set(dev, mask);
 635
 636         /* Set Interrupt Throttling Rate to maximum allowed value. */
 637         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
 638
 639         /* Setup link speed and duplex */
 640         speeds = &dev->data->dev_conf.link_speeds;
 641         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
 642                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 643         } else {
 644                 num_speeds = 0;
 645                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
 646
 647                 /* Reset */
 648                 hw->phy.autoneg_advertised = 0;
 649
 650                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
 651                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
 652                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
 653                         num_speeds = -1;
 654                         goto error_invalid_config;
 655                 }
 656                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
 657                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
 658                         num_speeds++;
 659                 }
 660                 if (*speeds & ETH_LINK_SPEED_10M) {
 661                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
 662                         num_speeds++;
 663                 }
 664                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
 665                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
 666                         num_speeds++;
 667                 }
 668                 if (*speeds & ETH_LINK_SPEED_100M) {
 669                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
 670                         num_speeds++;
 671                 }
 672                 if (*speeds & ETH_LINK_SPEED_1G) {
 673                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
 674                         num_speeds++;
 675                 }
 676                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
 677                         goto error_invalid_config;
 678         }
 679
 680         e1000_setup_link(hw);
 681
 682         if (rte_intr_allow_others(intr_handle)) {
 683                 /* check if lsc interrupt is enabled */
 684                 if (dev->data->dev_conf.intr_conf.lsc != 0) {
 685                         ret = eth_em_interrupt_setup(dev);
 686                         if (ret) {
 687                                 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
 688                                 em_dev_clear_queues(dev);
 689                                 return ret;
 690                         }
 691                 }
 692         } else {
 693                 rte_intr_callback_unregister(intr_handle,
 694                                                 eth_em_interrupt_handler,
 695                                                 (void *)dev);
 696                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 697                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
 698                                      " no intr multiplex\n");
 699         }
 700         /* check if rxq interrupt is enabled */
 701         if (dev->data->dev_conf.intr_conf.rxq != 0)
 702                 eth_em_rxq_interrupt_setup(dev);
 703
 704         rte_intr_enable(intr_handle);
 705
 706         adapter->stopped = 0;
 707
 708         PMD_INIT_LOG(DEBUG, "<<");
 709
 710         return 0;
 711
 712 error_invalid_config:
 713         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
 714                      dev->data->dev_conf.link_speeds, dev->data->port_id);
 715         em_dev_clear_queues(dev);
 716         return -EINVAL;
 717 }
 718
 719 /*********************************************************************
 720  *
 721  *  This routine disables all traffic on the adapter by issuing a
 722  *  global reset on the MAC.
 723  *
 724  **********************************************************************/
 725 static void
 726 eth_em_stop(struct rte_eth_dev *dev)
 727 {
 728         struct rte_eth_link link;
 729         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 730         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
 731
 732         em_rxq_intr_disable(hw);
 733         em_lsc_intr_disable(hw);
 734
 735         e1000_reset_hw(hw);
 736         if (hw->mac.type >= e1000_82544)
 737                 E1000_WRITE_REG(hw, E1000_WUC, 0);
 738
 739         /* Power down the phy. Needed to make the link go down */
 740         e1000_power_down_phy(hw);
 741
 742         em_dev_clear_queues(dev);
 743
 744         /* clear the recorded link status */
 745         memset(&link, 0, sizeof(link));
 746         rte_em_dev_atomic_write_link_status(dev, &link);
 747
 748         if (!rte_intr_allow_others(intr_handle))
 749                 /* resume to the default handler */
 750                 rte_intr_callback_register(intr_handle,
 751                                            eth_em_interrupt_handler,
 752                                            (void *)dev);
 753
 754         /* Clean datapath event and queue/vec mapping */
 755         rte_intr_efd_disable(intr_handle);
 756         if (intr_handle->intr_vec != NULL) {
 757                 rte_free(intr_handle->intr_vec);
 758                 intr_handle->intr_vec = NULL;
 759         }
 760 }
 761
 762 static void
 763 eth_em_close(struct rte_eth_dev *dev)
 764 {
 765         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 766         struct e1000_adapter *adapter =
 767                 E1000_DEV_PRIVATE(dev->data->dev_private);
 768
 769         eth_em_stop(dev);
 770         adapter->stopped = 1;
 771         em_dev_free_queues(dev);
 772         e1000_phy_hw_reset(hw);
 773         em_release_manageability(hw);
 774         em_hw_control_release(hw);
 775 }
 776
 777 static int
 778 em_get_rx_buffer_size(struct e1000_hw *hw)
 779 {
 780         uint32_t rx_buf_size;
 781
 782         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
 783         return rx_buf_size;
 784 }
 785
 786 /*********************************************************************
 787  *
 788  *  Initialize the hardware
 789  *
 790  **********************************************************************/
 791 static int
 792 em_hardware_init(struct e1000_hw *hw)
 793 {
 794         uint32_t rx_buf_size;
 795         int diag;
 796
 797         /* Issue a global reset */
 798         e1000_reset_hw(hw);
 799
 800         /* Let the firmware know the OS is in control */
 801         em_hw_control_acquire(hw);
 802
 803         /*
 804          * These parameters control the automatic generation (Tx) and
 805          * response (Rx) to Ethernet PAUSE frames.
 806          * - High water mark should allow for at least two standard size (1518)
 807          *   frames to be received after sending an XOFF.
 808          * - Low water mark works best when it is very near the high water mark.
 809          *   This allows the receiver to restart by sending XON when it has
 810          *   drained a bit. Here we use an arbitrary value of 1500 which will
 811          *   restart after one full frame is pulled from the buffer. There
 812          *   could be several smaller frames in the buffer and if so they will
 813          *   not trigger the XON until their total number reduces the buffer
 814          *   by 1500.
 815          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 816          */
 817         rx_buf_size = em_get_rx_buffer_size(hw);
 818
 819         hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
 820         hw->fc.low_water = hw->fc.high_water - 1500;
 821
 822         if (hw->mac.type == e1000_80003es2lan)
 823                 hw->fc.pause_time = UINT16_MAX;
 824         else
 825                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
 826
 827         hw->fc.send_xon = 1;
 828
 829         /* Set Flow control, use the tunable location if sane */
 830         if (em_fc_setting <= e1000_fc_full)
 831                 hw->fc.requested_mode = em_fc_setting;
 832         else
 833                 hw->fc.requested_mode = e1000_fc_none;
 834
 835         /* Workaround: no TX flow ctrl for PCH */
 836         if (hw->mac.type == e1000_pchlan)
 837                 hw->fc.requested_mode = e1000_fc_rx_pause;
 838
 839         /* Override - settings for PCH2LAN, ya its magic :) */
 840         if (hw->mac.type == e1000_pch2lan) {
 841                 hw->fc.high_water = 0x5C20;
 842                 hw->fc.low_water = 0x5048;
 843                 hw->fc.pause_time = 0x0650;
 844                 hw->fc.refresh_time = 0x0400;
 845         } else if (hw->mac.type == e1000_pch_lpt) {
 846                 hw->fc.requested_mode = e1000_fc_full;
 847         }
 848
 849         diag = e1000_init_hw(hw);
 850         if (diag < 0)
 851                 return diag;
 852         e1000_check_for_link(hw);
 853         return 0;
 854 }
 855
 856 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
 857 static void
 858 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 859 {
 860         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 861         struct e1000_hw_stats *stats =
 862                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 863         int pause_frames;
 864
 865         if(hw->phy.media_type == e1000_media_type_copper ||
 866                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 867                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
 868                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 869         }
 870
 871         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 872         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 873         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 874         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 875
 876         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 877         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 878         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 879         stats->dc += E1000_READ_REG(hw, E1000_DC);
 880         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 881         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 882         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 883
 884         /*
 885          * For watchdog management we need to know if we have been
 886          * paused during the last interval, so capture that here.
 887          */
 888         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 889         stats->xoffrxc += pause_frames;
 890         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 891         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 892         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 893         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 894         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 895         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 896         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 897         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 898         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 899         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 900         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 901         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 902
 903         /*
 904          * For the 64-bit byte counters the low dword must be read first.
 905          * Both registers clear on the read of the high dword.
 906          */
 907
 908         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 909         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 910         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 911         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 912
 913         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 914         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 915         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 916         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 917         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 918
 919         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 920         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 921
 922         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 923         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 924         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 925         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 926         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 927         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 928         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 929         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 930         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 931         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 932
 933         /* Interrupt Counts */
 934
 935         if (hw->mac.type >= e1000_82571) {
 936                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
 937                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 938                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 939                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 940                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 941                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 942                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 943                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 944                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 945         }
 946
 947         if (hw->mac.type >= e1000_82543) {
 948                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 949                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 950                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 951                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 952                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 953                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 954         }
 955
 956         if (rte_stats == NULL)
 957                 return;
 958
 959         /* Rx Errors */
 960         rte_stats->imissed = stats->mpc;
 961         rte_stats->ierrors = stats->crcerrs +
 962                              stats->rlec + stats->ruc + stats->roc +
 963                              stats->rxerrc + stats->algnerrc + stats->cexterr;
 964
 965         /* Tx Errors */
 966         rte_stats->oerrors = stats->ecol + stats->latecol;
 967
 968         rte_stats->ipackets = stats->gprc;
 969         rte_stats->opackets = stats->gptc;
 970         rte_stats->ibytes   = stats->gorc;
 971         rte_stats->obytes   = stats->gotc;
 972 }
 973
 974 static void
 975 eth_em_stats_reset(struct rte_eth_dev *dev)
 976 {
 977         struct e1000_hw_stats *hw_stats =
 978                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 979
 980         /* HW registers are cleared on read */
 981         eth_em_stats_get(dev, NULL);
 982
 983         /* Reset software totals */
 984         memset(hw_stats, 0, sizeof(*hw_stats));
 985 }
 986
 987 static int
 988 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
 989 {
 990         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 991
 992         em_rxq_intr_enable(hw);
 993         rte_intr_enable(&dev->pci_dev->intr_handle);
 994
 995         return 0;
 996 }
 997
 998 static int
 999 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1000 {
1001         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1002
1003         em_rxq_intr_disable(hw);
1004
1005         return 0;
1006 }
1007
1008 static uint32_t
1009 em_get_max_pktlen(const struct e1000_hw *hw)
1010 {
1011         switch (hw->mac.type) {
1012         case e1000_82571:
1013         case e1000_82572:
1014         case e1000_ich9lan:
1015         case e1000_ich10lan:
1016         case e1000_pch2lan:
1017         case e1000_pch_lpt:
1018         case e1000_82574:
1019         case e1000_80003es2lan: /* 9K Jumbo Frame size */
1020         case e1000_82583:
1021                 return 0x2412;
1022         case e1000_pchlan:
1023                 return 0x1000;
1024         /* Adapters that do not support jumbo frames */
1025         case e1000_ich8lan:
1026                 return ETHER_MAX_LEN;
1027         default:
1028                 return MAX_JUMBO_FRAME_SIZE;
1029         }
1030 }
1031
1032 static void
1033 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1034 {
1035         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1036
1037         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1038         dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
1039         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1040
1041         /*
1042          * Starting with 631xESB hw supports 2 TX/RX queues per port.
1043          * Unfortunatelly, all these nics have just one TX context.
1044          * So we have few choises for TX:
1045          * - Use just one TX queue.
1046          * - Allow cksum offload only for one TX queue.
1047          * - Don't allow TX cksum offload at all.
1048          * For now, option #1 was chosen.
1049          * To use second RX queue we have to use extended RX descriptor
1050          * (Multiple Receive Queues are mutually exclusive with UDP
1051          * fragmentation and are not supported when a legacy receive
1052          * descriptor format is used).
1053          * Which means separate RX routinies - as legacy nics (82540, 82545)
1054          * don't support extended RXD.
1055          * To avoid it we support just one RX queue for now (no RSS).
1056          */
1057
1058         dev_info->max_rx_queues = 1;
1059         dev_info->max_tx_queues = 1;
1060
1061         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1062                 .nb_max = E1000_MAX_RING_DESC,
1063                 .nb_min = E1000_MIN_RING_DESC,
1064                 .nb_align = EM_RXD_ALIGN,
1065         };
1066
1067         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1068                 .nb_max = E1000_MAX_RING_DESC,
1069                 .nb_min = E1000_MIN_RING_DESC,
1070                 .nb_align = EM_TXD_ALIGN,
1071         };
1072
1073         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1074                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1075                         ETH_LINK_SPEED_1G;
1076 }
1077
1078 /* return 0 means link status changed, -1 means not changed */
1079 static int
1080 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1081 {
1082         struct e1000_hw *hw =
1083                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1084         struct rte_eth_link link, old;
1085         int link_check, count;
1086
1087         link_check = 0;
1088         hw->mac.get_link_status = 1;
1089
1090         /* possible wait-to-complete in up to 9 seconds */
1091         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1092                 /* Read the real link status */
1093                 switch (hw->phy.media_type) {
1094                 case e1000_media_type_copper:
1095                         /* Do the work to read phy */
1096                         e1000_check_for_link(hw);
1097                         link_check = !hw->mac.get_link_status;
1098                         break;
1099
1100                 case e1000_media_type_fiber:
1101                         e1000_check_for_link(hw);
1102                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1103                                         E1000_STATUS_LU);
1104                         break;
1105
1106                 case e1000_media_type_internal_serdes:
1107                         e1000_check_for_link(hw);
1108                         link_check = hw->mac.serdes_has_link;
1109                         break;
1110
1111                 default:
1112                         break;
1113                 }
1114                 if (link_check || wait_to_complete == 0)
1115                         break;
1116                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1117         }
1118         memset(&link, 0, sizeof(link));
1119         rte_em_dev_atomic_read_link_status(dev, &link);
1120         old = link;
1121
1122         /* Now we check if a transition has happened */
1123         if (link_check && (link.link_status == ETH_LINK_DOWN)) {
1124                 uint16_t duplex, speed;
1125                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1126                 link.link_duplex = (duplex == FULL_DUPLEX) ?
1127                                 ETH_LINK_FULL_DUPLEX :
1128                                 ETH_LINK_HALF_DUPLEX;
1129                 link.link_speed = speed;
1130                 link.link_status = ETH_LINK_UP;
1131                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1132                                 ETH_LINK_SPEED_FIXED);
1133         } else if (!link_check && (link.link_status == ETH_LINK_UP)) {
1134                 link.link_speed = 0;
1135                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1136                 link.link_status = ETH_LINK_DOWN;
1137                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
1138         }
1139         rte_em_dev_atomic_write_link_status(dev, &link);
1140
1141         /* not changed */
1142         if (old.link_status == link.link_status)
1143                 return -1;
1144
1145         /* changed */
1146         return 0;
1147 }
1148
1149 /*
1150  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1151  * For ASF and Pass Through versions of f/w this means
1152  * that the driver is loaded. For AMT version type f/w
1153  * this means that the network i/f is open.
1154  */
1155 static void
1156 em_hw_control_acquire(struct e1000_hw *hw)
1157 {
1158         uint32_t ctrl_ext, swsm;
1159
1160         /* Let firmware know the driver has taken over */
1161         if (hw->mac.type == e1000_82573) {
1162                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1163                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1164
1165         } else {
1166                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1167                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1168                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1169         }
1170 }
1171
1172 /*
1173  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1174  * For ASF and Pass Through versions of f/w this means that the
1175  * driver is no longer loaded. For AMT versions of the
1176  * f/w this means that the network i/f is closed.
1177  */
1178 static void
1179 em_hw_control_release(struct e1000_hw *hw)
1180 {
1181         uint32_t ctrl_ext, swsm;
1182
1183         /* Let firmware taken over control of h/w */
1184         if (hw->mac.type == e1000_82573) {
1185                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1186                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1187         } else {
1188                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1189                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1190                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1191         }
1192 }
1193
1194 /*
1195  * Bit of a misnomer, what this really means is
1196  * to enable OS management of the system... aka
1197  * to disable special hardware management features.
1198  */
1199 static void
1200 em_init_manageability(struct e1000_hw *hw)
1201 {
1202         if (e1000_enable_mng_pass_thru(hw)) {
1203                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1204                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1205
1206                 /* disable hardware interception of ARP */
1207                 manc &= ~(E1000_MANC_ARP_EN);
1208
1209                 /* enable receiving management packets to the host */
1210                 manc |= E1000_MANC_EN_MNG2HOST;
1211                 manc2h |= 1 << 5;  /* Mng Port 623 */
1212                 manc2h |= 1 << 6;  /* Mng Port 664 */
1213                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1214                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1215         }
1216 }
1217
1218 /*
1219  * Give control back to hardware management
1220  * controller if there is one.
1221  */
1222 static void
1223 em_release_manageability(struct e1000_hw *hw)
1224 {
1225         uint32_t manc;
1226
1227         if (e1000_enable_mng_pass_thru(hw)) {
1228                 manc = E1000_READ_REG(hw, E1000_MANC);
1229
1230                 /* re-enable hardware interception of ARP */
1231                 manc |= E1000_MANC_ARP_EN;
1232                 manc &= ~E1000_MANC_EN_MNG2HOST;
1233
1234                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1235         }
1236 }
1237
1238 static void
1239 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1240 {
1241         struct e1000_hw *hw =
1242                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1243         uint32_t rctl;
1244
1245         rctl = E1000_READ_REG(hw, E1000_RCTL);
1246         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1247         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1248 }
1249
1250 static void
1251 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1252 {
1253         struct e1000_hw *hw =
1254                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1255         uint32_t rctl;
1256
1257         rctl = E1000_READ_REG(hw, E1000_RCTL);
1258         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1259         if (dev->data->all_multicast == 1)
1260                 rctl |= E1000_RCTL_MPE;
1261         else
1262                 rctl &= (~E1000_RCTL_MPE);
1263         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1264 }
1265
1266 static void
1267 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1268 {
1269         struct e1000_hw *hw =
1270                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1271         uint32_t rctl;
1272
1273         rctl = E1000_READ_REG(hw, E1000_RCTL);
1274         rctl |= E1000_RCTL_MPE;
1275         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1276 }
1277
1278 static void
1279 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1280 {
1281         struct e1000_hw *hw =
1282                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1283         uint32_t rctl;
1284
1285         if (dev->data->promiscuous == 1)
1286                 return; /* must remain in all_multicast mode */
1287         rctl = E1000_READ_REG(hw, E1000_RCTL);
1288         rctl &= (~E1000_RCTL_MPE);
1289         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1290 }
1291
1292 static int
1293 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1294 {
1295         struct e1000_hw *hw =
1296                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1297         struct e1000_vfta * shadow_vfta =
1298                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1299         uint32_t vfta;
1300         uint32_t vid_idx;
1301         uint32_t vid_bit;
1302
1303         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1304                               E1000_VFTA_ENTRY_MASK);
1305         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1306         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1307         if (on)
1308                 vfta |= vid_bit;
1309         else
1310                 vfta &= ~vid_bit;
1311         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1312
1313         /* update local VFTA copy */
1314         shadow_vfta->vfta[vid_idx] = vfta;
1315
1316         return 0;
1317 }
1318
1319 static void
1320 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1321 {
1322         struct e1000_hw *hw =
1323                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1324         uint32_t reg;
1325
1326         /* Filter Table Disable */
1327         reg = E1000_READ_REG(hw, E1000_RCTL);
1328         reg &= ~E1000_RCTL_CFIEN;
1329         reg &= ~E1000_RCTL_VFE;
1330         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1331 }
1332
1333 static void
1334 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1335 {
1336         struct e1000_hw *hw =
1337                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1338         struct e1000_vfta * shadow_vfta =
1339                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1340         uint32_t reg;
1341         int i;
1342
1343         /* Filter Table Enable, CFI not used for packet acceptance */
1344         reg = E1000_READ_REG(hw, E1000_RCTL);
1345         reg &= ~E1000_RCTL_CFIEN;
1346         reg |= E1000_RCTL_VFE;
1347         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1348
1349         /* restore vfta from local copy */
1350         for (i = 0; i < IGB_VFTA_SIZE; i++)
1351                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1352 }
1353
1354 static void
1355 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1356 {
1357         struct e1000_hw *hw =
1358                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1359         uint32_t reg;
1360
1361         /* VLAN Mode Disable */
1362         reg = E1000_READ_REG(hw, E1000_CTRL);
1363         reg &= ~E1000_CTRL_VME;
1364         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1365
1366 }
1367
1368 static void
1369 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1370 {
1371         struct e1000_hw *hw =
1372                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1373         uint32_t reg;
1374
1375         /* VLAN Mode Enable */
1376         reg = E1000_READ_REG(hw, E1000_CTRL);
1377         reg |= E1000_CTRL_VME;
1378         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1379 }
1380
1381 static void
1382 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1383 {
1384         if(mask & ETH_VLAN_STRIP_MASK){
1385                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1386                         em_vlan_hw_strip_enable(dev);
1387                 else
1388                         em_vlan_hw_strip_disable(dev);
1389         }
1390
1391         if(mask & ETH_VLAN_FILTER_MASK){
1392                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1393                         em_vlan_hw_filter_enable(dev);
1394                 else
1395                         em_vlan_hw_filter_disable(dev);
1396         }
1397 }
1398
1399 /*
1400  * It enables the interrupt mask and then enable the interrupt.
1401  *
1402  * @param dev
1403  *  Pointer to struct rte_eth_dev.
1404  *
1405  * @return
1406  *  - On success, zero.
1407  *  - On failure, a negative value.
1408  */
1409 static int
1410 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1411 {
1412         uint32_t regval;
1413         struct e1000_hw *hw =
1414                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1415
1416         /* clear interrupt */
1417         E1000_READ_REG(hw, E1000_ICR);
1418         regval = E1000_READ_REG(hw, E1000_IMS);
1419         E1000_WRITE_REG(hw, E1000_IMS, regval | E1000_ICR_LSC);
1420         return 0;
1421 }
1422
1423 /*
1424  * It clears the interrupt causes and enables the interrupt.
1425  * It will be called once only during nic initialized.
1426  *
1427  * @param dev
1428  *  Pointer to struct rte_eth_dev.
1429  *
1430  * @return
1431  *  - On success, zero.
1432  *  - On failure, a negative value.
1433  */
1434 static int
1435 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1436 {
1437         struct e1000_hw *hw =
1438         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1439
1440         E1000_READ_REG(hw, E1000_ICR);
1441         em_rxq_intr_enable(hw);
1442         return 0;
1443 }
1444
1445 /*
1446  * It enable receive packet interrupt.
1447  * @param hw
1448  * Pointer to struct e1000_hw
1449  *
1450  * @return
1451  */
1452 static void
1453 em_rxq_intr_enable(struct e1000_hw *hw)
1454 {
1455         E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1456         E1000_WRITE_FLUSH(hw);
1457 }
1458
1459 /*
1460  * It disabled lsc interrupt.
1461  * @param hw
1462  * Pointer to struct e1000_hw
1463  *
1464  * @return
1465  */
1466 static void
1467 em_lsc_intr_disable(struct e1000_hw *hw)
1468 {
1469         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC);
1470         E1000_WRITE_FLUSH(hw);
1471 }
1472
1473 /*
1474  * It disabled receive packet interrupt.
1475  * @param hw
1476  * Pointer to struct e1000_hw
1477  *
1478  * @return
1479  */
1480 static void
1481 em_rxq_intr_disable(struct e1000_hw *hw)
1482 {
1483         E1000_READ_REG(hw, E1000_ICR);
1484         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1485         E1000_WRITE_FLUSH(hw);
1486 }
1487
1488 /*
1489  * It reads ICR and gets interrupt causes, check it and set a bit flag
1490  * to update link status.
1491  *
1492  * @param dev
1493  *  Pointer to struct rte_eth_dev.
1494  *
1495  * @return
1496  *  - On success, zero.
1497  *  - On failure, a negative value.
1498  */
1499 static int
1500 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1501 {
1502         uint32_t icr;
1503         struct e1000_hw *hw =
1504                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1505         struct e1000_interrupt *intr =
1506                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1507
1508         /* read-on-clear nic registers here */
1509         icr = E1000_READ_REG(hw, E1000_ICR);
1510         if (icr & E1000_ICR_LSC) {
1511                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1512         }
1513
1514         return 0;
1515 }
1516
1517 /*
1518  * It executes link_update after knowing an interrupt is prsent.
1519  *
1520  * @param dev
1521  *  Pointer to struct rte_eth_dev.
1522  *
1523  * @return
1524  *  - On success, zero.
1525  *  - On failure, a negative value.
1526  */
1527 static int
1528 eth_em_interrupt_action(struct rte_eth_dev *dev)
1529 {
1530         struct e1000_hw *hw =
1531                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1532         struct e1000_interrupt *intr =
1533                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1534         uint32_t tctl, rctl;
1535         struct rte_eth_link link;
1536         int ret;
1537
1538         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1539                 return -1;
1540
1541         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1542         rte_intr_enable(&(dev->pci_dev->intr_handle));
1543
1544         /* set get_link_status to check register later */
1545         hw->mac.get_link_status = 1;
1546         ret = eth_em_link_update(dev, 0);
1547
1548         /* check if link has changed */
1549         if (ret < 0)
1550                 return 0;
1551
1552         memset(&link, 0, sizeof(link));
1553         rte_em_dev_atomic_read_link_status(dev, &link);
1554         if (link.link_status) {
1555                 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1556                              dev->data->port_id, (unsigned)link.link_speed,
1557                              link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1558                              "full-duplex" : "half-duplex");
1559         } else {
1560                 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1561         }
1562         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1563                      dev->pci_dev->addr.domain, dev->pci_dev->addr.bus,
1564                      dev->pci_dev->addr.devid, dev->pci_dev->addr.function);
1565
1566         tctl = E1000_READ_REG(hw, E1000_TCTL);
1567         rctl = E1000_READ_REG(hw, E1000_RCTL);
1568         if (link.link_status) {
1569                 /* enable Tx/Rx */
1570                 tctl |= E1000_TCTL_EN;
1571                 rctl |= E1000_RCTL_EN;
1572         } else {
1573                 /* disable Tx/Rx */
1574                 tctl &= ~E1000_TCTL_EN;
1575                 rctl &= ~E1000_RCTL_EN;
1576         }
1577         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1578         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1579         E1000_WRITE_FLUSH(hw);
1580
1581         return 0;
1582 }
1583
1584 /**
1585  * Interrupt handler which shall be registered at first.
1586  *
1587  * @param handle
1588  *  Pointer to interrupt handle.
1589  * @param param
1590  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1591  *
1592  * @return
1593  *  void
1594  */
1595 static void
1596 eth_em_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1597                                                         void *param)
1598 {
1599         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1600
1601         eth_em_interrupt_get_status(dev);
1602         eth_em_interrupt_action(dev);
1603         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1604 }
1605
1606 static int
1607 eth_em_led_on(struct rte_eth_dev *dev)
1608 {
1609         struct e1000_hw *hw;
1610
1611         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1612         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1613 }
1614
1615 static int
1616 eth_em_led_off(struct rte_eth_dev *dev)
1617 {
1618         struct e1000_hw *hw;
1619
1620         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1621         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1622 }
1623
1624 static int
1625 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1626 {
1627         struct e1000_hw *hw;
1628         uint32_t ctrl;
1629         int tx_pause;
1630         int rx_pause;
1631
1632         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1633         fc_conf->pause_time = hw->fc.pause_time;
1634         fc_conf->high_water = hw->fc.high_water;
1635         fc_conf->low_water = hw->fc.low_water;
1636         fc_conf->send_xon = hw->fc.send_xon;
1637         fc_conf->autoneg = hw->mac.autoneg;
1638
1639         /*
1640          * Return rx_pause and tx_pause status according to actual setting of
1641          * the TFCE and RFCE bits in the CTRL register.
1642          */
1643         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1644         if (ctrl & E1000_CTRL_TFCE)
1645                 tx_pause = 1;
1646         else
1647                 tx_pause = 0;
1648
1649         if (ctrl & E1000_CTRL_RFCE)
1650                 rx_pause = 1;
1651         else
1652                 rx_pause = 0;
1653
1654         if (rx_pause && tx_pause)
1655                 fc_conf->mode = RTE_FC_FULL;
1656         else if (rx_pause)
1657                 fc_conf->mode = RTE_FC_RX_PAUSE;
1658         else if (tx_pause)
1659                 fc_conf->mode = RTE_FC_TX_PAUSE;
1660         else
1661                 fc_conf->mode = RTE_FC_NONE;
1662
1663         return 0;
1664 }
1665
1666 static int
1667 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1668 {
1669         struct e1000_hw *hw;
1670         int err;
1671         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1672                 e1000_fc_none,
1673                 e1000_fc_rx_pause,
1674                 e1000_fc_tx_pause,
1675                 e1000_fc_full
1676         };
1677         uint32_t rx_buf_size;
1678         uint32_t max_high_water;
1679         uint32_t rctl;
1680
1681         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1682         if (fc_conf->autoneg != hw->mac.autoneg)
1683                 return -ENOTSUP;
1684         rx_buf_size = em_get_rx_buffer_size(hw);
1685         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1686
1687         /* At least reserve one Ethernet frame for watermark */
1688         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1689         if ((fc_conf->high_water > max_high_water) ||
1690             (fc_conf->high_water < fc_conf->low_water)) {
1691                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1692                 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1693                 return -EINVAL;
1694         }
1695
1696         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1697         hw->fc.pause_time     = fc_conf->pause_time;
1698         hw->fc.high_water     = fc_conf->high_water;
1699         hw->fc.low_water      = fc_conf->low_water;
1700         hw->fc.send_xon       = fc_conf->send_xon;
1701
1702         err = e1000_setup_link_generic(hw);
1703         if (err == E1000_SUCCESS) {
1704
1705                 /* check if we want to forward MAC frames - driver doesn't have native
1706                  * capability to do that, so we'll write the registers ourselves */
1707
1708                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1709
1710                 /* set or clear MFLCN.PMCF bit depending on configuration */
1711                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1712                         rctl |= E1000_RCTL_PMCF;
1713                 else
1714                         rctl &= ~E1000_RCTL_PMCF;
1715
1716                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1717                 E1000_WRITE_FLUSH(hw);
1718
1719                 return 0;
1720         }
1721
1722         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1723         return -EIO;
1724 }
1725
1726 static void
1727 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1728                 uint32_t index, __rte_unused uint32_t pool)
1729 {
1730         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1731
1732         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1733 }
1734
1735 static void
1736 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1737 {
1738         uint8_t addr[ETHER_ADDR_LEN];
1739         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1740
1741         memset(addr, 0, sizeof(addr));
1742
1743         e1000_rar_set(hw, addr, index);
1744 }
1745
1746 static int
1747 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1748 {
1749         struct rte_eth_dev_info dev_info;
1750         struct e1000_hw *hw;
1751         uint32_t frame_size;
1752         uint32_t rctl;
1753
1754         eth_em_infos_get(dev, &dev_info);
1755         frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1756
1757         /* check that mtu is within the allowed range */
1758         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1759                 return -EINVAL;
1760
1761         /* refuse mtu that requires the support of scattered packets when this
1762          * feature has not been enabled before. */
1763         if (!dev->data->scattered_rx &&
1764             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1765                 return -EINVAL;
1766
1767         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1768         rctl = E1000_READ_REG(hw, E1000_RCTL);
1769
1770         /* switch to jumbo mode if needed */
1771         if (frame_size > ETHER_MAX_LEN) {
1772                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1773                 rctl |= E1000_RCTL_LPE;
1774         } else {
1775                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1776                 rctl &= ~E1000_RCTL_LPE;
1777         }
1778         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1779
1780         /* update max frame size */
1781         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1782         return 0;
1783 }
1784
1785 static int
1786 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1787                         struct ether_addr *mc_addr_set,
1788                         uint32_t nb_mc_addr)
1789 {
1790         struct e1000_hw *hw;
1791
1792         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1793         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1794         return 0;
1795 }
1796
1797 DRIVER_REGISTER_PCI(net_e1000_em, rte_em_pmd.pci_drv);
1798 DRIVER_REGISTER_PCI_TABLE(net_e1000_em, pci_id_em_map);