drivers/net/e1000/em_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <stdarg.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_interrupts.h>
  13 #include <rte_byteorder.h>
  14 #include <rte_log.h>
  15 #include <rte_debug.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_memory.h>
  22 #include <rte_eal.h>
  23 #include <rte_malloc.h>
  24 #include <rte_dev.h>
  25
  26 #include "e1000_logs.h"
  27 #include "base/e1000_api.h"
  28 #include "e1000_ethdev.h"
  29
  30 #define EM_EIAC                 0x000DC
  31
  32 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
  33
  34
  35 static int eth_em_configure(struct rte_eth_dev *dev);
  36 static int eth_em_start(struct rte_eth_dev *dev);
  37 static void eth_em_stop(struct rte_eth_dev *dev);
  38 static void eth_em_close(struct rte_eth_dev *dev);
  39 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
  40 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
  41 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
  42 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
  43 static int eth_em_link_update(struct rte_eth_dev *dev,
  44                                 int wait_to_complete);
  45 static int eth_em_stats_get(struct rte_eth_dev *dev,
  46                                 struct rte_eth_stats *rte_stats);
  47 static void eth_em_stats_reset(struct rte_eth_dev *dev);
  48 static void eth_em_infos_get(struct rte_eth_dev *dev,
  49                                 struct rte_eth_dev_info *dev_info);
  50 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
  51                                 struct rte_eth_fc_conf *fc_conf);
  52 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
  53                                 struct rte_eth_fc_conf *fc_conf);
  54 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
  55 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
  56 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
  57 static int eth_em_interrupt_action(struct rte_eth_dev *dev,
  58                                    struct rte_intr_handle *handle);
  59 static void eth_em_interrupt_handler(void *param);
  60
  61 static int em_hw_init(struct e1000_hw *hw);
  62 static int em_hardware_init(struct e1000_hw *hw);
  63 static void em_hw_control_acquire(struct e1000_hw *hw);
  64 static void em_hw_control_release(struct e1000_hw *hw);
  65 static void em_init_manageability(struct e1000_hw *hw);
  66 static void em_release_manageability(struct e1000_hw *hw);
  67
  68 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  69
  70 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
  71                 uint16_t vlan_id, int on);
  72 static int eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  73 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
  74 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
  75 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
  76 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
  77
  78 /*
  79 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
  80                                         uint16_t vlan_id, int on);
  81 */
  82
  83 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
  84 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
  85 static void em_lsc_intr_disable(struct e1000_hw *hw);
  86 static void em_rxq_intr_enable(struct e1000_hw *hw);
  87 static void em_rxq_intr_disable(struct e1000_hw *hw);
  88
  89 static int eth_em_led_on(struct rte_eth_dev *dev);
  90 static int eth_em_led_off(struct rte_eth_dev *dev);
  91
  92 static int em_get_rx_buffer_size(struct e1000_hw *hw);
  93 static int eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
  94                           uint32_t index, uint32_t pool);
  95 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
  96 static int eth_em_default_mac_addr_set(struct rte_eth_dev *dev,
  97                                          struct ether_addr *addr);
  98
  99 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
 100                                    struct ether_addr *mc_addr_set,
 101                                    uint32_t nb_mc_addr);
 102
 103 #define EM_FC_PAUSE_TIME 0x0680
 104 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 105 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 106
 107 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
 108
 109 int e1000_logtype_init;
 110 int e1000_logtype_driver;
 111
 112 /*
 113  * The set of PCI devices this driver supports
 114  */
 115 static const struct rte_pci_id pci_id_em_map[] = {
 116         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
 117         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
 118         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
 119         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
 120         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
 121         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
 122         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
 123         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
 124         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
 125         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
 126         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
 127         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
 128         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
 129         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
 130         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
 131         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
 132         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
 133         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
 134         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
 135         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
 136         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
 137         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
 138         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
 139         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH2_LV_LM) },
 140         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
 141         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
 142         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
 143         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
 144         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
 145         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
 146         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
 147         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
 148         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM) },
 149         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V) },
 150         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM2) },
 151         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V2) },
 152         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LBG_I219_LM3) },
 153         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM4) },
 154         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V4) },
 155         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM5) },
 156         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V5) },
 157         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM6) },
 158         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V6) },
 159         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM7) },
 160         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V7) },
 161         { .vendor_id = 0, /* sentinel */ },
 162 };
 163
 164 static const struct eth_dev_ops eth_em_ops = {
 165         .dev_configure        = eth_em_configure,
 166         .dev_start            = eth_em_start,
 167         .dev_stop             = eth_em_stop,
 168         .dev_close            = eth_em_close,
 169         .promiscuous_enable   = eth_em_promiscuous_enable,
 170         .promiscuous_disable  = eth_em_promiscuous_disable,
 171         .allmulticast_enable  = eth_em_allmulticast_enable,
 172         .allmulticast_disable = eth_em_allmulticast_disable,
 173         .link_update          = eth_em_link_update,
 174         .stats_get            = eth_em_stats_get,
 175         .stats_reset          = eth_em_stats_reset,
 176         .dev_infos_get        = eth_em_infos_get,
 177         .mtu_set              = eth_em_mtu_set,
 178         .vlan_filter_set      = eth_em_vlan_filter_set,
 179         .vlan_offload_set     = eth_em_vlan_offload_set,
 180         .rx_queue_setup       = eth_em_rx_queue_setup,
 181         .rx_queue_release     = eth_em_rx_queue_release,
 182         .rx_queue_count       = eth_em_rx_queue_count,
 183         .rx_descriptor_done   = eth_em_rx_descriptor_done,
 184         .rx_descriptor_status = eth_em_rx_descriptor_status,
 185         .tx_descriptor_status = eth_em_tx_descriptor_status,
 186         .tx_queue_setup       = eth_em_tx_queue_setup,
 187         .tx_queue_release     = eth_em_tx_queue_release,
 188         .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
 189         .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
 190         .dev_led_on           = eth_em_led_on,
 191         .dev_led_off          = eth_em_led_off,
 192         .flow_ctrl_get        = eth_em_flow_ctrl_get,
 193         .flow_ctrl_set        = eth_em_flow_ctrl_set,
 194         .mac_addr_set         = eth_em_default_mac_addr_set,
 195         .mac_addr_add         = eth_em_rar_set,
 196         .mac_addr_remove      = eth_em_rar_clear,
 197         .set_mc_addr_list     = eth_em_set_mc_addr_list,
 198         .rxq_info_get         = em_rxq_info_get,
 199         .txq_info_get         = em_txq_info_get,
 200 };
 201
 202
 203 /**
 204  *  eth_em_dev_is_ich8 - Check for ICH8 device
 205  *  @hw: pointer to the HW structure
 206  *
 207  *  return TRUE for ICH8, otherwise FALSE
 208  **/
 209 static bool
 210 eth_em_dev_is_ich8(struct e1000_hw *hw)
 211 {
 212         DEBUGFUNC("eth_em_dev_is_ich8");
 213
 214         switch (hw->device_id) {
 215         case E1000_DEV_ID_PCH2_LV_LM:
 216         case E1000_DEV_ID_PCH_LPT_I217_LM:
 217         case E1000_DEV_ID_PCH_LPT_I217_V:
 218         case E1000_DEV_ID_PCH_LPTLP_I218_LM:
 219         case E1000_DEV_ID_PCH_LPTLP_I218_V:
 220         case E1000_DEV_ID_PCH_I218_V2:
 221         case E1000_DEV_ID_PCH_I218_LM2:
 222         case E1000_DEV_ID_PCH_I218_V3:
 223         case E1000_DEV_ID_PCH_I218_LM3:
 224         case E1000_DEV_ID_PCH_SPT_I219_LM:
 225         case E1000_DEV_ID_PCH_SPT_I219_V:
 226         case E1000_DEV_ID_PCH_SPT_I219_LM2:
 227         case E1000_DEV_ID_PCH_SPT_I219_V2:
 228         case E1000_DEV_ID_PCH_LBG_I219_LM3:
 229         case E1000_DEV_ID_PCH_SPT_I219_LM4:
 230         case E1000_DEV_ID_PCH_SPT_I219_V4:
 231         case E1000_DEV_ID_PCH_SPT_I219_LM5:
 232         case E1000_DEV_ID_PCH_SPT_I219_V5:
 233         case E1000_DEV_ID_PCH_CNP_I219_LM6:
 234         case E1000_DEV_ID_PCH_CNP_I219_V6:
 235         case E1000_DEV_ID_PCH_CNP_I219_LM7:
 236         case E1000_DEV_ID_PCH_CNP_I219_V7:
 237                 return 1;
 238         default:
 239                 return 0;
 240         }
 241 }
 242
 243 static int
 244 eth_em_dev_init(struct rte_eth_dev *eth_dev)
 245 {
 246         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 247         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 248         struct e1000_adapter *adapter =
 249                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 250         struct e1000_hw *hw =
 251                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 252         struct e1000_vfta * shadow_vfta =
 253                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 254
 255         eth_dev->dev_ops = &eth_em_ops;
 256         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
 257         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
 258         eth_dev->tx_pkt_prepare = (eth_tx_prep_t)&eth_em_prep_pkts;
 259
 260         /* for secondary processes, we don't initialise any further as primary
 261          * has already done this work. Only check we don't need a different
 262          * RX function */
 263         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 264                 if (eth_dev->data->scattered_rx)
 265                         eth_dev->rx_pkt_burst =
 266                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
 267                 return 0;
 268         }
 269
 270         rte_eth_copy_pci_info(eth_dev, pci_dev);
 271
 272         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 273         hw->device_id = pci_dev->id.device_id;
 274         adapter->stopped = 0;
 275
 276         /* For ICH8 support we'll need to map the flash memory BAR */
 277         if (eth_em_dev_is_ich8(hw))
 278                 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
 279
 280         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
 281                         em_hw_init(hw) != 0) {
 282                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
 283                         "failed to init HW",
 284                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 285                         pci_dev->id.device_id);
 286                 return -ENODEV;
 287         }
 288
 289         /* Allocate memory for storing MAC addresses */
 290         eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
 291                         hw->mac.rar_entry_count, 0);
 292         if (eth_dev->data->mac_addrs == NULL) {
 293                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 294                         "store MAC addresses",
 295                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 296                 return -ENOMEM;
 297         }
 298
 299         /* Copy the permanent MAC address */
 300         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 301                 eth_dev->data->mac_addrs);
 302
 303         /* initialize the vfta */
 304         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 305
 306         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 307                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 308                      pci_dev->id.device_id);
 309
 310         rte_intr_callback_register(intr_handle,
 311                                    eth_em_interrupt_handler, eth_dev);
 312
 313         return 0;
 314 }
 315
 316 static int
 317 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
 318 {
 319         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 320         struct e1000_adapter *adapter =
 321                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 322         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 323
 324         PMD_INIT_FUNC_TRACE();
 325
 326         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 327                 return -EPERM;
 328
 329         if (adapter->stopped == 0)
 330                 eth_em_close(eth_dev);
 331
 332         eth_dev->dev_ops = NULL;
 333         eth_dev->rx_pkt_burst = NULL;
 334         eth_dev->tx_pkt_burst = NULL;
 335
 336         rte_free(eth_dev->data->mac_addrs);
 337         eth_dev->data->mac_addrs = NULL;
 338
 339         /* disable uio intr before callback unregister */
 340         rte_intr_disable(intr_handle);
 341         rte_intr_callback_unregister(intr_handle,
 342                                      eth_em_interrupt_handler, eth_dev);
 343
 344         return 0;
 345 }
 346
 347 static int eth_em_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 348         struct rte_pci_device *pci_dev)
 349 {
 350         return rte_eth_dev_pci_generic_probe(pci_dev,
 351                 sizeof(struct e1000_adapter), eth_em_dev_init);
 352 }
 353
 354 static int eth_em_pci_remove(struct rte_pci_device *pci_dev)
 355 {
 356         return rte_eth_dev_pci_generic_remove(pci_dev, eth_em_dev_uninit);
 357 }
 358
 359 static struct rte_pci_driver rte_em_pmd = {
 360         .id_table = pci_id_em_map,
 361         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 362                      RTE_PCI_DRV_IOVA_AS_VA,
 363         .probe = eth_em_pci_probe,
 364         .remove = eth_em_pci_remove,
 365 };
 366
 367 static int
 368 em_hw_init(struct e1000_hw *hw)
 369 {
 370         int diag;
 371
 372         diag = hw->mac.ops.init_params(hw);
 373         if (diag != 0) {
 374                 PMD_INIT_LOG(ERR, "MAC Initialization Error");
 375                 return diag;
 376         }
 377         diag = hw->nvm.ops.init_params(hw);
 378         if (diag != 0) {
 379                 PMD_INIT_LOG(ERR, "NVM Initialization Error");
 380                 return diag;
 381         }
 382         diag = hw->phy.ops.init_params(hw);
 383         if (diag != 0) {
 384                 PMD_INIT_LOG(ERR, "PHY Initialization Error");
 385                 return diag;
 386         }
 387         (void) e1000_get_bus_info(hw);
 388
 389         hw->mac.autoneg = 1;
 390         hw->phy.autoneg_wait_to_complete = 0;
 391         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 392
 393         e1000_init_script_state_82541(hw, TRUE);
 394         e1000_set_tbi_compatibility_82543(hw, TRUE);
 395
 396         /* Copper options */
 397         if (hw->phy.media_type == e1000_media_type_copper) {
 398                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 399                 hw->phy.disable_polarity_correction = 0;
 400                 hw->phy.ms_type = e1000_ms_hw_default;
 401         }
 402
 403         /*
 404          * Start from a known state, this is important in reading the nvm
 405          * and mac from that.
 406          */
 407         e1000_reset_hw(hw);
 408
 409         /* Make sure we have a good EEPROM before we read from it */
 410         if (e1000_validate_nvm_checksum(hw) < 0) {
 411                 /*
 412                  * Some PCI-E parts fail the first check due to
 413                  * the link being in sleep state, call it again,
 414                  * if it fails a second time its a real issue.
 415                  */
 416                 diag = e1000_validate_nvm_checksum(hw);
 417                 if (diag < 0) {
 418                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 419                         goto error;
 420                 }
 421         }
 422
 423         /* Read the permanent MAC address out of the EEPROM */
 424         diag = e1000_read_mac_addr(hw);
 425         if (diag != 0) {
 426                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 427                 goto error;
 428         }
 429
 430         /* Now initialize the hardware */
 431         diag = em_hardware_init(hw);
 432         if (diag != 0) {
 433                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 434                 goto error;
 435         }
 436
 437         hw->mac.get_link_status = 1;
 438
 439         /* Indicate SOL/IDER usage */
 440         diag = e1000_check_reset_block(hw);
 441         if (diag < 0) {
 442                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
 443                         "SOL/IDER session");
 444         }
 445         return 0;
 446
 447 error:
 448         em_hw_control_release(hw);
 449         return diag;
 450 }
 451
 452 static int
 453 eth_em_configure(struct rte_eth_dev *dev)
 454 {
 455         struct e1000_interrupt *intr =
 456                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 457         struct rte_eth_dev_info dev_info;
 458         uint64_t rx_offloads;
 459         uint64_t tx_offloads;
 460
 461         PMD_INIT_FUNC_TRACE();
 462         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 463
 464         eth_em_infos_get(dev, &dev_info);
 465         rx_offloads = dev->data->dev_conf.rxmode.offloads;
 466         if ((rx_offloads & dev_info.rx_offload_capa) != rx_offloads) {
 467                 PMD_DRV_LOG(ERR, "Some Rx offloads are not supported "
 468                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
 469                             rx_offloads, dev_info.rx_offload_capa);
 470                 return -ENOTSUP;
 471         }
 472         tx_offloads = dev->data->dev_conf.txmode.offloads;
 473         if ((tx_offloads & dev_info.tx_offload_capa) != tx_offloads) {
 474                 PMD_DRV_LOG(ERR, "Some Tx offloads are not supported "
 475                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
 476                             tx_offloads, dev_info.tx_offload_capa);
 477                 return -ENOTSUP;
 478         }
 479
 480         PMD_INIT_FUNC_TRACE();
 481
 482         return 0;
 483 }
 484
 485 static void
 486 em_set_pba(struct e1000_hw *hw)
 487 {
 488         uint32_t pba;
 489
 490         /*
 491          * Packet Buffer Allocation (PBA)
 492          * Writing PBA sets the receive portion of the buffer
 493          * the remainder is used for the transmit buffer.
 494          * Devices before the 82547 had a Packet Buffer of 64K.
 495          * After the 82547 the buffer was reduced to 40K.
 496          */
 497         switch (hw->mac.type) {
 498                 case e1000_82547:
 499                 case e1000_82547_rev_2:
 500                 /* 82547: Total Packet Buffer is 40K */
 501                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
 502                         break;
 503                 case e1000_82571:
 504                 case e1000_82572:
 505                 case e1000_80003es2lan:
 506                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 507                         break;
 508                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
 509                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
 510                         break;
 511                 case e1000_82574:
 512                 case e1000_82583:
 513                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
 514                         break;
 515                 case e1000_ich8lan:
 516                         pba = E1000_PBA_8K;
 517                         break;
 518                 case e1000_ich9lan:
 519                 case e1000_ich10lan:
 520                         pba = E1000_PBA_10K;
 521                         break;
 522                 case e1000_pchlan:
 523                 case e1000_pch2lan:
 524                 case e1000_pch_lpt:
 525                 case e1000_pch_spt:
 526                 case e1000_pch_cnp:
 527                         pba = E1000_PBA_26K;
 528                         break;
 529                 default:
 530                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
 531         }
 532
 533         E1000_WRITE_REG(hw, E1000_PBA, pba);
 534 }
 535
 536 static void
 537 eth_em_rxtx_control(struct rte_eth_dev *dev,
 538                     bool enable)
 539 {
 540         struct e1000_hw *hw =
 541                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 542         uint32_t tctl, rctl;
 543
 544         tctl = E1000_READ_REG(hw, E1000_TCTL);
 545         rctl = E1000_READ_REG(hw, E1000_RCTL);
 546         if (enable) {
 547                 /* enable Tx/Rx */
 548                 tctl |= E1000_TCTL_EN;
 549                 rctl |= E1000_RCTL_EN;
 550         } else {
 551                 /* disable Tx/Rx */
 552                 tctl &= ~E1000_TCTL_EN;
 553                 rctl &= ~E1000_RCTL_EN;
 554         }
 555         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
 556         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
 557         E1000_WRITE_FLUSH(hw);
 558 }
 559
 560 static int
 561 eth_em_start(struct rte_eth_dev *dev)
 562 {
 563         struct e1000_adapter *adapter =
 564                 E1000_DEV_PRIVATE(dev->data->dev_private);
 565         struct e1000_hw *hw =
 566                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 567         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 568         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 569         int ret, mask;
 570         uint32_t intr_vector = 0;
 571         uint32_t *speeds;
 572         int num_speeds;
 573         bool autoneg;
 574
 575         PMD_INIT_FUNC_TRACE();
 576
 577         eth_em_stop(dev);
 578
 579         e1000_power_up_phy(hw);
 580
 581         /* Set default PBA value */
 582         em_set_pba(hw);
 583
 584         /* Put the address into the Receive Address Array */
 585         e1000_rar_set(hw, hw->mac.addr, 0);
 586
 587         /*
 588          * With the 82571 adapter, RAR[0] may be overwritten
 589          * when the other port is reset, we make a duplicate
 590          * in RAR[14] for that eventuality, this assures
 591          * the interface continues to function.
 592          */
 593         if (hw->mac.type == e1000_82571) {
 594                 e1000_set_laa_state_82571(hw, TRUE);
 595                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
 596         }
 597
 598         /* Initialize the hardware */
 599         if (em_hardware_init(hw)) {
 600                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 601                 return -EIO;
 602         }
 603
 604         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 605
 606         /* Configure for OS presence */
 607         em_init_manageability(hw);
 608
 609         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 610                 intr_vector = dev->data->nb_rx_queues;
 611                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 612                         return -1;
 613         }
 614
 615         if (rte_intr_dp_is_en(intr_handle)) {
 616                 intr_handle->intr_vec =
 617                         rte_zmalloc("intr_vec",
 618                                         dev->data->nb_rx_queues * sizeof(int), 0);
 619                 if (intr_handle->intr_vec == NULL) {
 620                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 621                                                 " intr_vec", dev->data->nb_rx_queues);
 622                         return -ENOMEM;
 623                 }
 624
 625                 /* enable rx interrupt */
 626                 em_rxq_intr_enable(hw);
 627         }
 628
 629         eth_em_tx_init(dev);
 630
 631         ret = eth_em_rx_init(dev);
 632         if (ret) {
 633                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 634                 em_dev_clear_queues(dev);
 635                 return ret;
 636         }
 637
 638         e1000_clear_hw_cntrs_base_generic(hw);
 639
 640         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 641                         ETH_VLAN_EXTEND_MASK;
 642         ret = eth_em_vlan_offload_set(dev, mask);
 643         if (ret) {
 644                 PMD_INIT_LOG(ERR, "Unable to update vlan offload");
 645                 em_dev_clear_queues(dev);
 646                 return ret;
 647         }
 648
 649         /* Set Interrupt Throttling Rate to maximum allowed value. */
 650         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
 651
 652         /* Setup link speed and duplex */
 653         speeds = &dev->data->dev_conf.link_speeds;
 654         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
 655                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 656                 hw->mac.autoneg = 1;
 657         } else {
 658                 num_speeds = 0;
 659                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
 660
 661                 /* Reset */
 662                 hw->phy.autoneg_advertised = 0;
 663
 664                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
 665                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
 666                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
 667                         num_speeds = -1;
 668                         goto error_invalid_config;
 669                 }
 670                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
 671                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
 672                         num_speeds++;
 673                 }
 674                 if (*speeds & ETH_LINK_SPEED_10M) {
 675                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
 676                         num_speeds++;
 677                 }
 678                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
 679                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
 680                         num_speeds++;
 681                 }
 682                 if (*speeds & ETH_LINK_SPEED_100M) {
 683                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
 684                         num_speeds++;
 685                 }
 686                 if (*speeds & ETH_LINK_SPEED_1G) {
 687                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
 688                         num_speeds++;
 689                 }
 690                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
 691                         goto error_invalid_config;
 692
 693                 /* Set/reset the mac.autoneg based on the link speed,
 694                  * fixed or not
 695                  */
 696                 if (!autoneg) {
 697                         hw->mac.autoneg = 0;
 698                         hw->mac.forced_speed_duplex =
 699                                         hw->phy.autoneg_advertised;
 700                 } else {
 701                         hw->mac.autoneg = 1;
 702                 }
 703         }
 704
 705         e1000_setup_link(hw);
 706
 707         if (rte_intr_allow_others(intr_handle)) {
 708                 /* check if lsc interrupt is enabled */
 709                 if (dev->data->dev_conf.intr_conf.lsc != 0) {
 710                         ret = eth_em_interrupt_setup(dev);
 711                         if (ret) {
 712                                 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
 713                                 em_dev_clear_queues(dev);
 714                                 return ret;
 715                         }
 716                 }
 717         } else {
 718                 rte_intr_callback_unregister(intr_handle,
 719                                                 eth_em_interrupt_handler,
 720                                                 (void *)dev);
 721                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 722                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
 723                                      " no intr multiplexn");
 724         }
 725         /* check if rxq interrupt is enabled */
 726         if (dev->data->dev_conf.intr_conf.rxq != 0)
 727                 eth_em_rxq_interrupt_setup(dev);
 728
 729         rte_intr_enable(intr_handle);
 730
 731         adapter->stopped = 0;
 732
 733         eth_em_rxtx_control(dev, true);
 734         eth_em_link_update(dev, 0);
 735
 736         PMD_INIT_LOG(DEBUG, "<<");
 737
 738         return 0;
 739
 740 error_invalid_config:
 741         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
 742                      dev->data->dev_conf.link_speeds, dev->data->port_id);
 743         em_dev_clear_queues(dev);
 744         return -EINVAL;
 745 }
 746
 747 /*********************************************************************
 748  *
 749  *  This routine disables all traffic on the adapter by issuing a
 750  *  global reset on the MAC.
 751  *
 752  **********************************************************************/
 753 static void
 754 eth_em_stop(struct rte_eth_dev *dev)
 755 {
 756         struct rte_eth_link link;
 757         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 758         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 759         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 760
 761         eth_em_rxtx_control(dev, false);
 762         em_rxq_intr_disable(hw);
 763         em_lsc_intr_disable(hw);
 764
 765         e1000_reset_hw(hw);
 766         if (hw->mac.type >= e1000_82544)
 767                 E1000_WRITE_REG(hw, E1000_WUC, 0);
 768
 769         /* Power down the phy. Needed to make the link go down */
 770         e1000_power_down_phy(hw);
 771
 772         em_dev_clear_queues(dev);
 773
 774         /* clear the recorded link status */
 775         memset(&link, 0, sizeof(link));
 776         rte_eth_linkstatus_set(dev, &link);
 777
 778         if (!rte_intr_allow_others(intr_handle))
 779                 /* resume to the default handler */
 780                 rte_intr_callback_register(intr_handle,
 781                                            eth_em_interrupt_handler,
 782                                            (void *)dev);
 783
 784         /* Clean datapath event and queue/vec mapping */
 785         rte_intr_efd_disable(intr_handle);
 786         if (intr_handle->intr_vec != NULL) {
 787                 rte_free(intr_handle->intr_vec);
 788                 intr_handle->intr_vec = NULL;
 789         }
 790 }
 791
 792 static void
 793 eth_em_close(struct rte_eth_dev *dev)
 794 {
 795         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 796         struct e1000_adapter *adapter =
 797                 E1000_DEV_PRIVATE(dev->data->dev_private);
 798
 799         eth_em_stop(dev);
 800         adapter->stopped = 1;
 801         em_dev_free_queues(dev);
 802         e1000_phy_hw_reset(hw);
 803         em_release_manageability(hw);
 804         em_hw_control_release(hw);
 805 }
 806
 807 static int
 808 em_get_rx_buffer_size(struct e1000_hw *hw)
 809 {
 810         uint32_t rx_buf_size;
 811
 812         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
 813         return rx_buf_size;
 814 }
 815
 816 /*********************************************************************
 817  *
 818  *  Initialize the hardware
 819  *
 820  **********************************************************************/
 821 static int
 822 em_hardware_init(struct e1000_hw *hw)
 823 {
 824         uint32_t rx_buf_size;
 825         int diag;
 826
 827         /* Issue a global reset */
 828         e1000_reset_hw(hw);
 829
 830         /* Let the firmware know the OS is in control */
 831         em_hw_control_acquire(hw);
 832
 833         /*
 834          * These parameters control the automatic generation (Tx) and
 835          * response (Rx) to Ethernet PAUSE frames.
 836          * - High water mark should allow for at least two standard size (1518)
 837          *   frames to be received after sending an XOFF.
 838          * - Low water mark works best when it is very near the high water mark.
 839          *   This allows the receiver to restart by sending XON when it has
 840          *   drained a bit. Here we use an arbitrary value of 1500 which will
 841          *   restart after one full frame is pulled from the buffer. There
 842          *   could be several smaller frames in the buffer and if so they will
 843          *   not trigger the XON until their total number reduces the buffer
 844          *   by 1500.
 845          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 846          */
 847         rx_buf_size = em_get_rx_buffer_size(hw);
 848
 849         hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
 850         hw->fc.low_water = hw->fc.high_water - 1500;
 851
 852         if (hw->mac.type == e1000_80003es2lan)
 853                 hw->fc.pause_time = UINT16_MAX;
 854         else
 855                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
 856
 857         hw->fc.send_xon = 1;
 858
 859         /* Set Flow control, use the tunable location if sane */
 860         if (em_fc_setting <= e1000_fc_full)
 861                 hw->fc.requested_mode = em_fc_setting;
 862         else
 863                 hw->fc.requested_mode = e1000_fc_none;
 864
 865         /* Workaround: no TX flow ctrl for PCH */
 866         if (hw->mac.type == e1000_pchlan)
 867                 hw->fc.requested_mode = e1000_fc_rx_pause;
 868
 869         /* Override - settings for PCH2LAN, ya its magic :) */
 870         if (hw->mac.type == e1000_pch2lan) {
 871                 hw->fc.high_water = 0x5C20;
 872                 hw->fc.low_water = 0x5048;
 873                 hw->fc.pause_time = 0x0650;
 874                 hw->fc.refresh_time = 0x0400;
 875         } else if (hw->mac.type == e1000_pch_lpt ||
 876                    hw->mac.type == e1000_pch_spt ||
 877                    hw->mac.type == e1000_pch_cnp) {
 878                 hw->fc.requested_mode = e1000_fc_full;
 879         }
 880
 881         diag = e1000_init_hw(hw);
 882         if (diag < 0)
 883                 return diag;
 884         e1000_check_for_link(hw);
 885         return 0;
 886 }
 887
 888 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
 889 static int
 890 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 891 {
 892         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 893         struct e1000_hw_stats *stats =
 894                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 895         int pause_frames;
 896
 897         if(hw->phy.media_type == e1000_media_type_copper ||
 898                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 899                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
 900                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 901         }
 902
 903         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 904         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 905         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 906         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 907
 908         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 909         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 910         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 911         stats->dc += E1000_READ_REG(hw, E1000_DC);
 912         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 913         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 914         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 915
 916         /*
 917          * For watchdog management we need to know if we have been
 918          * paused during the last interval, so capture that here.
 919          */
 920         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 921         stats->xoffrxc += pause_frames;
 922         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 923         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 924         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 925         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 926         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 927         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 928         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 929         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 930         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 931         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 932         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 933         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 934
 935         /*
 936          * For the 64-bit byte counters the low dword must be read first.
 937          * Both registers clear on the read of the high dword.
 938          */
 939
 940         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 941         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 942         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 943         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 944
 945         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 946         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 947         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 948         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 949         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 950
 951         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 952         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 953
 954         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 955         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 956         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 957         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 958         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 959         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 960         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 961         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 962         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 963         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 964
 965         /* Interrupt Counts */
 966
 967         if (hw->mac.type >= e1000_82571) {
 968                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
 969                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 970                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 971                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 972                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 973                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 974                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 975                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 976                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 977         }
 978
 979         if (hw->mac.type >= e1000_82543) {
 980                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 981                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 982                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 983                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 984                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 985                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 986         }
 987
 988         if (rte_stats == NULL)
 989                 return -EINVAL;
 990
 991         /* Rx Errors */
 992         rte_stats->imissed = stats->mpc;
 993         rte_stats->ierrors = stats->crcerrs +
 994                              stats->rlec + stats->ruc + stats->roc +
 995                              stats->rxerrc + stats->algnerrc + stats->cexterr;
 996
 997         /* Tx Errors */
 998         rte_stats->oerrors = stats->ecol + stats->latecol;
 999
1000         rte_stats->ipackets = stats->gprc;
1001         rte_stats->opackets = stats->gptc;
1002         rte_stats->ibytes   = stats->gorc;
1003         rte_stats->obytes   = stats->gotc;
1004         return 0;
1005 }
1006
1007 static void
1008 eth_em_stats_reset(struct rte_eth_dev *dev)
1009 {
1010         struct e1000_hw_stats *hw_stats =
1011                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1012
1013         /* HW registers are cleared on read */
1014         eth_em_stats_get(dev, NULL);
1015
1016         /* Reset software totals */
1017         memset(hw_stats, 0, sizeof(*hw_stats));
1018 }
1019
1020 static int
1021 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1022 {
1023         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1024         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1025         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1026
1027         em_rxq_intr_enable(hw);
1028         rte_intr_enable(intr_handle);
1029
1030         return 0;
1031 }
1032
1033 static int
1034 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1035 {
1036         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1037
1038         em_rxq_intr_disable(hw);
1039
1040         return 0;
1041 }
1042
1043 uint32_t
1044 em_get_max_pktlen(struct rte_eth_dev *dev)
1045 {
1046         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1047
1048         switch (hw->mac.type) {
1049         case e1000_82571:
1050         case e1000_82572:
1051         case e1000_ich9lan:
1052         case e1000_ich10lan:
1053         case e1000_pch2lan:
1054         case e1000_pch_lpt:
1055         case e1000_pch_spt:
1056         case e1000_pch_cnp:
1057         case e1000_82574:
1058         case e1000_80003es2lan: /* 9K Jumbo Frame size */
1059         case e1000_82583:
1060                 return 0x2412;
1061         case e1000_pchlan:
1062                 return 0x1000;
1063         /* Adapters that do not support jumbo frames */
1064         case e1000_ich8lan:
1065                 return ETHER_MAX_LEN;
1066         default:
1067                 return MAX_JUMBO_FRAME_SIZE;
1068         }
1069 }
1070
1071 static void
1072 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1073 {
1074         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1075
1076         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1077         dev_info->max_rx_pktlen = em_get_max_pktlen(dev);
1078         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1079
1080         /*
1081          * Starting with 631xESB hw supports 2 TX/RX queues per port.
1082          * Unfortunatelly, all these nics have just one TX context.
1083          * So we have few choises for TX:
1084          * - Use just one TX queue.
1085          * - Allow cksum offload only for one TX queue.
1086          * - Don't allow TX cksum offload at all.
1087          * For now, option #1 was chosen.
1088          * To use second RX queue we have to use extended RX descriptor
1089          * (Multiple Receive Queues are mutually exclusive with UDP
1090          * fragmentation and are not supported when a legacy receive
1091          * descriptor format is used).
1092          * Which means separate RX routinies - as legacy nics (82540, 82545)
1093          * don't support extended RXD.
1094          * To avoid it we support just one RX queue for now (no RSS).
1095          */
1096
1097         dev_info->max_rx_queues = 1;
1098         dev_info->max_tx_queues = 1;
1099
1100         dev_info->rx_queue_offload_capa = em_get_rx_queue_offloads_capa(dev);
1101         dev_info->rx_offload_capa = em_get_rx_port_offloads_capa(dev) |
1102                                     dev_info->rx_queue_offload_capa;
1103         dev_info->tx_queue_offload_capa = em_get_tx_queue_offloads_capa(dev);
1104         dev_info->tx_offload_capa = em_get_tx_port_offloads_capa(dev) |
1105                                     dev_info->tx_queue_offload_capa;
1106
1107         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1108                 .nb_max = E1000_MAX_RING_DESC,
1109                 .nb_min = E1000_MIN_RING_DESC,
1110                 .nb_align = EM_RXD_ALIGN,
1111         };
1112
1113         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1114                 .nb_max = E1000_MAX_RING_DESC,
1115                 .nb_min = E1000_MIN_RING_DESC,
1116                 .nb_align = EM_TXD_ALIGN,
1117                 .nb_seg_max = EM_TX_MAX_SEG,
1118                 .nb_mtu_seg_max = EM_TX_MAX_MTU_SEG,
1119         };
1120
1121         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1122                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1123                         ETH_LINK_SPEED_1G;
1124
1125         /* Preferred queue parameters */
1126         dev_info->default_rxportconf.nb_queues = 1;
1127         dev_info->default_txportconf.nb_queues = 1;
1128         dev_info->default_txportconf.ring_size = 256;
1129         dev_info->default_rxportconf.ring_size = 256;
1130 }
1131
1132 /* return 0 means link status changed, -1 means not changed */
1133 static int
1134 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1135 {
1136         struct e1000_hw *hw =
1137                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1138         struct rte_eth_link link;
1139         int link_check, count;
1140
1141         link_check = 0;
1142         hw->mac.get_link_status = 1;
1143
1144         /* possible wait-to-complete in up to 9 seconds */
1145         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1146                 /* Read the real link status */
1147                 switch (hw->phy.media_type) {
1148                 case e1000_media_type_copper:
1149                         /* Do the work to read phy */
1150                         e1000_check_for_link(hw);
1151                         link_check = !hw->mac.get_link_status;
1152                         break;
1153
1154                 case e1000_media_type_fiber:
1155                         e1000_check_for_link(hw);
1156                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1157                                         E1000_STATUS_LU);
1158                         break;
1159
1160                 case e1000_media_type_internal_serdes:
1161                         e1000_check_for_link(hw);
1162                         link_check = hw->mac.serdes_has_link;
1163                         break;
1164
1165                 default:
1166                         break;
1167                 }
1168                 if (link_check || wait_to_complete == 0)
1169                         break;
1170                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1171         }
1172         memset(&link, 0, sizeof(link));
1173
1174         /* Now we check if a transition has happened */
1175         if (link_check && (link.link_status == ETH_LINK_DOWN)) {
1176                 uint16_t duplex, speed;
1177                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1178                 link.link_duplex = (duplex == FULL_DUPLEX) ?
1179                                 ETH_LINK_FULL_DUPLEX :
1180                                 ETH_LINK_HALF_DUPLEX;
1181                 link.link_speed = speed;
1182                 link.link_status = ETH_LINK_UP;
1183                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1184                                 ETH_LINK_SPEED_FIXED);
1185         } else if (!link_check && (link.link_status == ETH_LINK_UP)) {
1186                 link.link_speed = 0;
1187                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1188                 link.link_status = ETH_LINK_DOWN;
1189                 link.link_autoneg = ETH_LINK_FIXED;
1190         }
1191
1192         return rte_eth_linkstatus_set(dev, &link);
1193 }
1194
1195 /*
1196  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1197  * For ASF and Pass Through versions of f/w this means
1198  * that the driver is loaded. For AMT version type f/w
1199  * this means that the network i/f is open.
1200  */
1201 static void
1202 em_hw_control_acquire(struct e1000_hw *hw)
1203 {
1204         uint32_t ctrl_ext, swsm;
1205
1206         /* Let firmware know the driver has taken over */
1207         if (hw->mac.type == e1000_82573) {
1208                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1209                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1210
1211         } else {
1212                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1213                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1214                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1215         }
1216 }
1217
1218 /*
1219  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1220  * For ASF and Pass Through versions of f/w this means that the
1221  * driver is no longer loaded. For AMT versions of the
1222  * f/w this means that the network i/f is closed.
1223  */
1224 static void
1225 em_hw_control_release(struct e1000_hw *hw)
1226 {
1227         uint32_t ctrl_ext, swsm;
1228
1229         /* Let firmware taken over control of h/w */
1230         if (hw->mac.type == e1000_82573) {
1231                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1232                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1233         } else {
1234                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1235                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1236                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1237         }
1238 }
1239
1240 /*
1241  * Bit of a misnomer, what this really means is
1242  * to enable OS management of the system... aka
1243  * to disable special hardware management features.
1244  */
1245 static void
1246 em_init_manageability(struct e1000_hw *hw)
1247 {
1248         if (e1000_enable_mng_pass_thru(hw)) {
1249                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1250                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1251
1252                 /* disable hardware interception of ARP */
1253                 manc &= ~(E1000_MANC_ARP_EN);
1254
1255                 /* enable receiving management packets to the host */
1256                 manc |= E1000_MANC_EN_MNG2HOST;
1257                 manc2h |= 1 << 5;  /* Mng Port 623 */
1258                 manc2h |= 1 << 6;  /* Mng Port 664 */
1259                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1260                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1261         }
1262 }
1263
1264 /*
1265  * Give control back to hardware management
1266  * controller if there is one.
1267  */
1268 static void
1269 em_release_manageability(struct e1000_hw *hw)
1270 {
1271         uint32_t manc;
1272
1273         if (e1000_enable_mng_pass_thru(hw)) {
1274                 manc = E1000_READ_REG(hw, E1000_MANC);
1275
1276                 /* re-enable hardware interception of ARP */
1277                 manc |= E1000_MANC_ARP_EN;
1278                 manc &= ~E1000_MANC_EN_MNG2HOST;
1279
1280                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1281         }
1282 }
1283
1284 static void
1285 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1286 {
1287         struct e1000_hw *hw =
1288                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1289         uint32_t rctl;
1290
1291         rctl = E1000_READ_REG(hw, E1000_RCTL);
1292         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1293         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1294 }
1295
1296 static void
1297 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1298 {
1299         struct e1000_hw *hw =
1300                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1301         uint32_t rctl;
1302
1303         rctl = E1000_READ_REG(hw, E1000_RCTL);
1304         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1305         if (dev->data->all_multicast == 1)
1306                 rctl |= E1000_RCTL_MPE;
1307         else
1308                 rctl &= (~E1000_RCTL_MPE);
1309         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1310 }
1311
1312 static void
1313 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1314 {
1315         struct e1000_hw *hw =
1316                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1317         uint32_t rctl;
1318
1319         rctl = E1000_READ_REG(hw, E1000_RCTL);
1320         rctl |= E1000_RCTL_MPE;
1321         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1322 }
1323
1324 static void
1325 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1326 {
1327         struct e1000_hw *hw =
1328                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1329         uint32_t rctl;
1330
1331         if (dev->data->promiscuous == 1)
1332                 return; /* must remain in all_multicast mode */
1333         rctl = E1000_READ_REG(hw, E1000_RCTL);
1334         rctl &= (~E1000_RCTL_MPE);
1335         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1336 }
1337
1338 static int
1339 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1340 {
1341         struct e1000_hw *hw =
1342                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1343         struct e1000_vfta * shadow_vfta =
1344                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1345         uint32_t vfta;
1346         uint32_t vid_idx;
1347         uint32_t vid_bit;
1348
1349         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1350                               E1000_VFTA_ENTRY_MASK);
1351         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1352         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1353         if (on)
1354                 vfta |= vid_bit;
1355         else
1356                 vfta &= ~vid_bit;
1357         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1358
1359         /* update local VFTA copy */
1360         shadow_vfta->vfta[vid_idx] = vfta;
1361
1362         return 0;
1363 }
1364
1365 static void
1366 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1367 {
1368         struct e1000_hw *hw =
1369                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1370         uint32_t reg;
1371
1372         /* Filter Table Disable */
1373         reg = E1000_READ_REG(hw, E1000_RCTL);
1374         reg &= ~E1000_RCTL_CFIEN;
1375         reg &= ~E1000_RCTL_VFE;
1376         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1377 }
1378
1379 static void
1380 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1381 {
1382         struct e1000_hw *hw =
1383                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1384         struct e1000_vfta * shadow_vfta =
1385                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1386         uint32_t reg;
1387         int i;
1388
1389         /* Filter Table Enable, CFI not used for packet acceptance */
1390         reg = E1000_READ_REG(hw, E1000_RCTL);
1391         reg &= ~E1000_RCTL_CFIEN;
1392         reg |= E1000_RCTL_VFE;
1393         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1394
1395         /* restore vfta from local copy */
1396         for (i = 0; i < IGB_VFTA_SIZE; i++)
1397                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1398 }
1399
1400 static void
1401 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1402 {
1403         struct e1000_hw *hw =
1404                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1405         uint32_t reg;
1406
1407         /* VLAN Mode Disable */
1408         reg = E1000_READ_REG(hw, E1000_CTRL);
1409         reg &= ~E1000_CTRL_VME;
1410         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1411
1412 }
1413
1414 static void
1415 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1416 {
1417         struct e1000_hw *hw =
1418                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1419         uint32_t reg;
1420
1421         /* VLAN Mode Enable */
1422         reg = E1000_READ_REG(hw, E1000_CTRL);
1423         reg |= E1000_CTRL_VME;
1424         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1425 }
1426
1427 static int
1428 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1429 {
1430         struct rte_eth_rxmode *rxmode;
1431
1432         rxmode = &dev->data->dev_conf.rxmode;
1433         if(mask & ETH_VLAN_STRIP_MASK){
1434                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1435                         em_vlan_hw_strip_enable(dev);
1436                 else
1437                         em_vlan_hw_strip_disable(dev);
1438         }
1439
1440         if(mask & ETH_VLAN_FILTER_MASK){
1441                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1442                         em_vlan_hw_filter_enable(dev);
1443                 else
1444                         em_vlan_hw_filter_disable(dev);
1445         }
1446
1447         return 0;
1448 }
1449
1450 /*
1451  * It enables the interrupt mask and then enable the interrupt.
1452  *
1453  * @param dev
1454  *  Pointer to struct rte_eth_dev.
1455  *
1456  * @return
1457  *  - On success, zero.
1458  *  - On failure, a negative value.
1459  */
1460 static int
1461 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1462 {
1463         uint32_t regval;
1464         struct e1000_hw *hw =
1465                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1466
1467         /* clear interrupt */
1468         E1000_READ_REG(hw, E1000_ICR);
1469         regval = E1000_READ_REG(hw, E1000_IMS);
1470         E1000_WRITE_REG(hw, E1000_IMS, regval | E1000_ICR_LSC);
1471         return 0;
1472 }
1473
1474 /*
1475  * It clears the interrupt causes and enables the interrupt.
1476  * It will be called once only during nic initialized.
1477  *
1478  * @param dev
1479  *  Pointer to struct rte_eth_dev.
1480  *
1481  * @return
1482  *  - On success, zero.
1483  *  - On failure, a negative value.
1484  */
1485 static int
1486 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1487 {
1488         struct e1000_hw *hw =
1489         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1490
1491         E1000_READ_REG(hw, E1000_ICR);
1492         em_rxq_intr_enable(hw);
1493         return 0;
1494 }
1495
1496 /*
1497  * It enable receive packet interrupt.
1498  * @param hw
1499  * Pointer to struct e1000_hw
1500  *
1501  * @return
1502  */
1503 static void
1504 em_rxq_intr_enable(struct e1000_hw *hw)
1505 {
1506         E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1507         E1000_WRITE_FLUSH(hw);
1508 }
1509
1510 /*
1511  * It disabled lsc interrupt.
1512  * @param hw
1513  * Pointer to struct e1000_hw
1514  *
1515  * @return
1516  */
1517 static void
1518 em_lsc_intr_disable(struct e1000_hw *hw)
1519 {
1520         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC);
1521         E1000_WRITE_FLUSH(hw);
1522 }
1523
1524 /*
1525  * It disabled receive packet interrupt.
1526  * @param hw
1527  * Pointer to struct e1000_hw
1528  *
1529  * @return
1530  */
1531 static void
1532 em_rxq_intr_disable(struct e1000_hw *hw)
1533 {
1534         E1000_READ_REG(hw, E1000_ICR);
1535         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1536         E1000_WRITE_FLUSH(hw);
1537 }
1538
1539 /*
1540  * It reads ICR and gets interrupt causes, check it and set a bit flag
1541  * to update link status.
1542  *
1543  * @param dev
1544  *  Pointer to struct rte_eth_dev.
1545  *
1546  * @return
1547  *  - On success, zero.
1548  *  - On failure, a negative value.
1549  */
1550 static int
1551 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1552 {
1553         uint32_t icr;
1554         struct e1000_hw *hw =
1555                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1556         struct e1000_interrupt *intr =
1557                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1558
1559         /* read-on-clear nic registers here */
1560         icr = E1000_READ_REG(hw, E1000_ICR);
1561         if (icr & E1000_ICR_LSC) {
1562                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1563         }
1564
1565         return 0;
1566 }
1567
1568 /*
1569  * It executes link_update after knowing an interrupt is prsent.
1570  *
1571  * @param dev
1572  *  Pointer to struct rte_eth_dev.
1573  *
1574  * @return
1575  *  - On success, zero.
1576  *  - On failure, a negative value.
1577  */
1578 static int
1579 eth_em_interrupt_action(struct rte_eth_dev *dev,
1580                         struct rte_intr_handle *intr_handle)
1581 {
1582         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1583         struct e1000_hw *hw =
1584                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1585         struct e1000_interrupt *intr =
1586                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1587         struct rte_eth_link link;
1588         int ret;
1589
1590         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1591                 return -1;
1592
1593         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1594         rte_intr_enable(intr_handle);
1595
1596         /* set get_link_status to check register later */
1597         hw->mac.get_link_status = 1;
1598         ret = eth_em_link_update(dev, 0);
1599
1600         /* check if link has changed */
1601         if (ret < 0)
1602                 return 0;
1603
1604         rte_eth_linkstatus_get(dev, &link);
1605
1606         if (link.link_status) {
1607                 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1608                              dev->data->port_id, link.link_speed,
1609                              link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1610                              "full-duplex" : "half-duplex");
1611         } else {
1612                 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1613         }
1614         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1615                      pci_dev->addr.domain, pci_dev->addr.bus,
1616                      pci_dev->addr.devid, pci_dev->addr.function);
1617
1618         return 0;
1619 }
1620
1621 /**
1622  * Interrupt handler which shall be registered at first.
1623  *
1624  * @param handle
1625  *  Pointer to interrupt handle.
1626  * @param param
1627  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1628  *
1629  * @return
1630  *  void
1631  */
1632 static void
1633 eth_em_interrupt_handler(void *param)
1634 {
1635         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1636
1637         eth_em_interrupt_get_status(dev);
1638         eth_em_interrupt_action(dev, dev->intr_handle);
1639         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1640 }
1641
1642 static int
1643 eth_em_led_on(struct rte_eth_dev *dev)
1644 {
1645         struct e1000_hw *hw;
1646
1647         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1648         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1649 }
1650
1651 static int
1652 eth_em_led_off(struct rte_eth_dev *dev)
1653 {
1654         struct e1000_hw *hw;
1655
1656         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1657         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1658 }
1659
1660 static int
1661 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1662 {
1663         struct e1000_hw *hw;
1664         uint32_t ctrl;
1665         int tx_pause;
1666         int rx_pause;
1667
1668         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1669         fc_conf->pause_time = hw->fc.pause_time;
1670         fc_conf->high_water = hw->fc.high_water;
1671         fc_conf->low_water = hw->fc.low_water;
1672         fc_conf->send_xon = hw->fc.send_xon;
1673         fc_conf->autoneg = hw->mac.autoneg;
1674
1675         /*
1676          * Return rx_pause and tx_pause status according to actual setting of
1677          * the TFCE and RFCE bits in the CTRL register.
1678          */
1679         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1680         if (ctrl & E1000_CTRL_TFCE)
1681                 tx_pause = 1;
1682         else
1683                 tx_pause = 0;
1684
1685         if (ctrl & E1000_CTRL_RFCE)
1686                 rx_pause = 1;
1687         else
1688                 rx_pause = 0;
1689
1690         if (rx_pause && tx_pause)
1691                 fc_conf->mode = RTE_FC_FULL;
1692         else if (rx_pause)
1693                 fc_conf->mode = RTE_FC_RX_PAUSE;
1694         else if (tx_pause)
1695                 fc_conf->mode = RTE_FC_TX_PAUSE;
1696         else
1697                 fc_conf->mode = RTE_FC_NONE;
1698
1699         return 0;
1700 }
1701
1702 static int
1703 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1704 {
1705         struct e1000_hw *hw;
1706         int err;
1707         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1708                 e1000_fc_none,
1709                 e1000_fc_rx_pause,
1710                 e1000_fc_tx_pause,
1711                 e1000_fc_full
1712         };
1713         uint32_t rx_buf_size;
1714         uint32_t max_high_water;
1715         uint32_t rctl;
1716
1717         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1718         if (fc_conf->autoneg != hw->mac.autoneg)
1719                 return -ENOTSUP;
1720         rx_buf_size = em_get_rx_buffer_size(hw);
1721         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1722
1723         /* At least reserve one Ethernet frame for watermark */
1724         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1725         if ((fc_conf->high_water > max_high_water) ||
1726             (fc_conf->high_water < fc_conf->low_water)) {
1727                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1728                 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1729                 return -EINVAL;
1730         }
1731
1732         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1733         hw->fc.pause_time     = fc_conf->pause_time;
1734         hw->fc.high_water     = fc_conf->high_water;
1735         hw->fc.low_water      = fc_conf->low_water;
1736         hw->fc.send_xon       = fc_conf->send_xon;
1737
1738         err = e1000_setup_link_generic(hw);
1739         if (err == E1000_SUCCESS) {
1740
1741                 /* check if we want to forward MAC frames - driver doesn't have native
1742                  * capability to do that, so we'll write the registers ourselves */
1743
1744                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1745
1746                 /* set or clear MFLCN.PMCF bit depending on configuration */
1747                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1748                         rctl |= E1000_RCTL_PMCF;
1749                 else
1750                         rctl &= ~E1000_RCTL_PMCF;
1751
1752                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1753                 E1000_WRITE_FLUSH(hw);
1754
1755                 return 0;
1756         }
1757
1758         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1759         return -EIO;
1760 }
1761
1762 static int
1763 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1764                 uint32_t index, __rte_unused uint32_t pool)
1765 {
1766         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1767
1768         return e1000_rar_set(hw, mac_addr->addr_bytes, index);
1769 }
1770
1771 static void
1772 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1773 {
1774         uint8_t addr[ETHER_ADDR_LEN];
1775         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1776
1777         memset(addr, 0, sizeof(addr));
1778
1779         e1000_rar_set(hw, addr, index);
1780 }
1781
1782 static int
1783 eth_em_default_mac_addr_set(struct rte_eth_dev *dev,
1784                             struct ether_addr *addr)
1785 {
1786         eth_em_rar_clear(dev, 0);
1787
1788         return eth_em_rar_set(dev, (void *)addr, 0, 0);
1789 }
1790
1791 static int
1792 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1793 {
1794         struct rte_eth_dev_info dev_info;
1795         struct e1000_hw *hw;
1796         uint32_t frame_size;
1797         uint32_t rctl;
1798
1799         eth_em_infos_get(dev, &dev_info);
1800         frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1801
1802         /* check that mtu is within the allowed range */
1803         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1804                 return -EINVAL;
1805
1806         /* refuse mtu that requires the support of scattered packets when this
1807          * feature has not been enabled before. */
1808         if (!dev->data->scattered_rx &&
1809             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1810                 return -EINVAL;
1811
1812         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1813         rctl = E1000_READ_REG(hw, E1000_RCTL);
1814
1815         /* switch to jumbo mode if needed */
1816         if (frame_size > ETHER_MAX_LEN) {
1817                 dev->data->dev_conf.rxmode.offloads |=
1818                         DEV_RX_OFFLOAD_JUMBO_FRAME;
1819                 rctl |= E1000_RCTL_LPE;
1820         } else {
1821                 dev->data->dev_conf.rxmode.offloads &=
1822                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1823                 rctl &= ~E1000_RCTL_LPE;
1824         }
1825         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1826
1827         /* update max frame size */
1828         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1829         return 0;
1830 }
1831
1832 static int
1833 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1834                         struct ether_addr *mc_addr_set,
1835                         uint32_t nb_mc_addr)
1836 {
1837         struct e1000_hw *hw;
1838
1839         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1840         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1841         return 0;
1842 }
1843
1844 RTE_PMD_REGISTER_PCI(net_e1000_em, rte_em_pmd);
1845 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_em, pci_id_em_map);
1846 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_em, "* igb_uio | uio_pci_generic | vfio-pci");
1847
1848 RTE_INIT(e1000_init_log);
1849 static void
1850 e1000_init_log(void)
1851 {
1852         e1000_logtype_init = rte_log_register("pmd.net.e1000.init");
1853         if (e1000_logtype_init >= 0)
1854                 rte_log_set_level(e1000_logtype_init, RTE_LOG_NOTICE);
1855         e1000_logtype_driver = rte_log_register("pmd.net.e1000.driver");
1856         if (e1000_logtype_driver >= 0)
1857                 rte_log_set_level(e1000_logtype_driver, RTE_LOG_NOTICE);
1858 }