drivers/net/e1000/em_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <stdarg.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_interrupts.h>
  13 #include <rte_byteorder.h>
  14 #include <rte_log.h>
  15 #include <rte_debug.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_memory.h>
  22 #include <rte_eal.h>
  23 #include <rte_atomic.h>
  24 #include <rte_malloc.h>
  25 #include <rte_dev.h>
  26
  27 #include "e1000_logs.h"
  28 #include "base/e1000_api.h"
  29 #include "e1000_ethdev.h"
  30
  31 #define EM_EIAC                 0x000DC
  32
  33 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
  34
  35
  36 static int eth_em_configure(struct rte_eth_dev *dev);
  37 static int eth_em_start(struct rte_eth_dev *dev);
  38 static void eth_em_stop(struct rte_eth_dev *dev);
  39 static void eth_em_close(struct rte_eth_dev *dev);
  40 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
  41 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
  42 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
  43 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
  44 static int eth_em_link_update(struct rte_eth_dev *dev,
  45                                 int wait_to_complete);
  46 static int eth_em_stats_get(struct rte_eth_dev *dev,
  47                                 struct rte_eth_stats *rte_stats);
  48 static void eth_em_stats_reset(struct rte_eth_dev *dev);
  49 static void eth_em_infos_get(struct rte_eth_dev *dev,
  50                                 struct rte_eth_dev_info *dev_info);
  51 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
  52                                 struct rte_eth_fc_conf *fc_conf);
  53 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
  54                                 struct rte_eth_fc_conf *fc_conf);
  55 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
  56 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
  57 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
  58 static int eth_em_interrupt_action(struct rte_eth_dev *dev,
  59                                    struct rte_intr_handle *handle);
  60 static void eth_em_interrupt_handler(void *param);
  61
  62 static int em_hw_init(struct e1000_hw *hw);
  63 static int em_hardware_init(struct e1000_hw *hw);
  64 static void em_hw_control_acquire(struct e1000_hw *hw);
  65 static void em_hw_control_release(struct e1000_hw *hw);
  66 static void em_init_manageability(struct e1000_hw *hw);
  67 static void em_release_manageability(struct e1000_hw *hw);
  68
  69 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  70
  71 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
  72                 uint16_t vlan_id, int on);
  73 static int eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  74 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
  75 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
  76 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
  77 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
  78
  79 /*
  80 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
  81                                         uint16_t vlan_id, int on);
  82 */
  83
  84 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
  85 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
  86 static void em_lsc_intr_disable(struct e1000_hw *hw);
  87 static void em_rxq_intr_enable(struct e1000_hw *hw);
  88 static void em_rxq_intr_disable(struct e1000_hw *hw);
  89
  90 static int eth_em_led_on(struct rte_eth_dev *dev);
  91 static int eth_em_led_off(struct rte_eth_dev *dev);
  92
  93 static int em_get_rx_buffer_size(struct e1000_hw *hw);
  94 static int eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
  95                           uint32_t index, uint32_t pool);
  96 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
  97
  98 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
  99                                    struct ether_addr *mc_addr_set,
 100                                    uint32_t nb_mc_addr);
 101
 102 #define EM_FC_PAUSE_TIME 0x0680
 103 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 104 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 105
 106 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
 107
 108 /*
 109  * The set of PCI devices this driver supports
 110  */
 111 static const struct rte_pci_id pci_id_em_map[] = {
 112         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
 113         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
 114         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
 115         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
 116         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
 117         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
 118         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
 119         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
 120         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
 121         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
 122         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
 123         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
 124         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
 125         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
 126         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
 127         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
 128         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
 129         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
 130         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
 131         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
 132         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
 133         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
 134         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
 135         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
 136         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
 137         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
 138         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
 139         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
 140         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
 141         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
 142         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
 143         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM) },
 144         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V) },
 145         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM2) },
 146         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V2) },
 147         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LBG_I219_LM3) },
 148         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM4) },
 149         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V4) },
 150         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM5) },
 151         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V5) },
 152         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM6) },
 153         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V6) },
 154         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM7) },
 155         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V7) },
 156         { .vendor_id = 0, /* sentinel */ },
 157 };
 158
 159 static const struct eth_dev_ops eth_em_ops = {
 160         .dev_configure        = eth_em_configure,
 161         .dev_start            = eth_em_start,
 162         .dev_stop             = eth_em_stop,
 163         .dev_close            = eth_em_close,
 164         .promiscuous_enable   = eth_em_promiscuous_enable,
 165         .promiscuous_disable  = eth_em_promiscuous_disable,
 166         .allmulticast_enable  = eth_em_allmulticast_enable,
 167         .allmulticast_disable = eth_em_allmulticast_disable,
 168         .link_update          = eth_em_link_update,
 169         .stats_get            = eth_em_stats_get,
 170         .stats_reset          = eth_em_stats_reset,
 171         .dev_infos_get        = eth_em_infos_get,
 172         .mtu_set              = eth_em_mtu_set,
 173         .vlan_filter_set      = eth_em_vlan_filter_set,
 174         .vlan_offload_set     = eth_em_vlan_offload_set,
 175         .rx_queue_setup       = eth_em_rx_queue_setup,
 176         .rx_queue_release     = eth_em_rx_queue_release,
 177         .rx_queue_count       = eth_em_rx_queue_count,
 178         .rx_descriptor_done   = eth_em_rx_descriptor_done,
 179         .rx_descriptor_status = eth_em_rx_descriptor_status,
 180         .tx_descriptor_status = eth_em_tx_descriptor_status,
 181         .tx_queue_setup       = eth_em_tx_queue_setup,
 182         .tx_queue_release     = eth_em_tx_queue_release,
 183         .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
 184         .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
 185         .dev_led_on           = eth_em_led_on,
 186         .dev_led_off          = eth_em_led_off,
 187         .flow_ctrl_get        = eth_em_flow_ctrl_get,
 188         .flow_ctrl_set        = eth_em_flow_ctrl_set,
 189         .mac_addr_add         = eth_em_rar_set,
 190         .mac_addr_remove      = eth_em_rar_clear,
 191         .set_mc_addr_list     = eth_em_set_mc_addr_list,
 192         .rxq_info_get         = em_rxq_info_get,
 193         .txq_info_get         = em_txq_info_get,
 194 };
 195
 196 /**
 197  * Atomically reads the link status information from global
 198  * structure rte_eth_dev.
 199  *
 200  * @param dev
 201  *   - Pointer to the structure rte_eth_dev to read from.
 202  *   - Pointer to the buffer to be saved with the link status.
 203  *
 204  * @return
 205  *   - On success, zero.
 206  *   - On failure, negative value.
 207  */
 208 static inline int
 209 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 210                                 struct rte_eth_link *link)
 211 {
 212         struct rte_eth_link *dst = link;
 213         struct rte_eth_link *src = &(dev->data->dev_link);
 214
 215         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 216                                         *(uint64_t *)src) == 0)
 217                 return -1;
 218
 219         return 0;
 220 }
 221
 222 /**
 223  * Atomically writes the link status information into global
 224  * structure rte_eth_dev.
 225  *
 226  * @param dev
 227  *   - Pointer to the structure rte_eth_dev to read from.
 228  *   - Pointer to the buffer to be saved with the link status.
 229  *
 230  * @return
 231  *   - On success, zero.
 232  *   - On failure, negative value.
 233  */
 234 static inline int
 235 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 236                                 struct rte_eth_link *link)
 237 {
 238         struct rte_eth_link *dst = &(dev->data->dev_link);
 239         struct rte_eth_link *src = link;
 240
 241         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 242                                         *(uint64_t *)src) == 0)
 243                 return -1;
 244
 245         return 0;
 246 }
 247
 248 /**
 249  *  eth_em_dev_is_ich8 - Check for ICH8 device
 250  *  @hw: pointer to the HW structure
 251  *
 252  *  return TRUE for ICH8, otherwise FALSE
 253  **/
 254 static bool
 255 eth_em_dev_is_ich8(struct e1000_hw *hw)
 256 {
 257         DEBUGFUNC("eth_em_dev_is_ich8");
 258
 259         switch (hw->device_id) {
 260         case E1000_DEV_ID_PCH_LPT_I217_LM:
 261         case E1000_DEV_ID_PCH_LPT_I217_V:
 262         case E1000_DEV_ID_PCH_LPTLP_I218_LM:
 263         case E1000_DEV_ID_PCH_LPTLP_I218_V:
 264         case E1000_DEV_ID_PCH_I218_V2:
 265         case E1000_DEV_ID_PCH_I218_LM2:
 266         case E1000_DEV_ID_PCH_I218_V3:
 267         case E1000_DEV_ID_PCH_I218_LM3:
 268         case E1000_DEV_ID_PCH_SPT_I219_LM:
 269         case E1000_DEV_ID_PCH_SPT_I219_V:
 270         case E1000_DEV_ID_PCH_SPT_I219_LM2:
 271         case E1000_DEV_ID_PCH_SPT_I219_V2:
 272         case E1000_DEV_ID_PCH_LBG_I219_LM3:
 273         case E1000_DEV_ID_PCH_SPT_I219_LM4:
 274         case E1000_DEV_ID_PCH_SPT_I219_V4:
 275         case E1000_DEV_ID_PCH_SPT_I219_LM5:
 276         case E1000_DEV_ID_PCH_SPT_I219_V5:
 277         case E1000_DEV_ID_PCH_CNP_I219_LM6:
 278         case E1000_DEV_ID_PCH_CNP_I219_V6:
 279         case E1000_DEV_ID_PCH_CNP_I219_LM7:
 280         case E1000_DEV_ID_PCH_CNP_I219_V7:
 281                 return 1;
 282         default:
 283                 return 0;
 284         }
 285 }
 286
 287 static int
 288 eth_em_dev_init(struct rte_eth_dev *eth_dev)
 289 {
 290         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 291         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 292         struct e1000_adapter *adapter =
 293                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 294         struct e1000_hw *hw =
 295                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 296         struct e1000_vfta * shadow_vfta =
 297                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 298
 299         eth_dev->dev_ops = &eth_em_ops;
 300         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
 301         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
 302         eth_dev->tx_pkt_prepare = (eth_tx_prep_t)&eth_em_prep_pkts;
 303
 304         /* for secondary processes, we don't initialise any further as primary
 305          * has already done this work. Only check we don't need a different
 306          * RX function */
 307         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 308                 if (eth_dev->data->scattered_rx)
 309                         eth_dev->rx_pkt_burst =
 310                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
 311                 return 0;
 312         }
 313
 314         rte_eth_copy_pci_info(eth_dev, pci_dev);
 315
 316         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 317         hw->device_id = pci_dev->id.device_id;
 318         adapter->stopped = 0;
 319
 320         /* For ICH8 support we'll need to map the flash memory BAR */
 321         if (eth_em_dev_is_ich8(hw))
 322                 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
 323
 324         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
 325                         em_hw_init(hw) != 0) {
 326                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
 327                         "failed to init HW",
 328                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 329                         pci_dev->id.device_id);
 330                 return -ENODEV;
 331         }
 332
 333         /* Allocate memory for storing MAC addresses */
 334         eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
 335                         hw->mac.rar_entry_count, 0);
 336         if (eth_dev->data->mac_addrs == NULL) {
 337                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 338                         "store MAC addresses",
 339                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 340                 return -ENOMEM;
 341         }
 342
 343         /* Copy the permanent MAC address */
 344         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 345                 eth_dev->data->mac_addrs);
 346
 347         /* initialize the vfta */
 348         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 349
 350         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 351                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 352                      pci_dev->id.device_id);
 353
 354         rte_intr_callback_register(intr_handle,
 355                                    eth_em_interrupt_handler, eth_dev);
 356
 357         return 0;
 358 }
 359
 360 static int
 361 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
 362 {
 363         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 364         struct e1000_adapter *adapter =
 365                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 366         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 367
 368         PMD_INIT_FUNC_TRACE();
 369
 370         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 371                 return -EPERM;
 372
 373         if (adapter->stopped == 0)
 374                 eth_em_close(eth_dev);
 375
 376         eth_dev->dev_ops = NULL;
 377         eth_dev->rx_pkt_burst = NULL;
 378         eth_dev->tx_pkt_burst = NULL;
 379
 380         rte_free(eth_dev->data->mac_addrs);
 381         eth_dev->data->mac_addrs = NULL;
 382
 383         /* disable uio intr before callback unregister */
 384         rte_intr_disable(intr_handle);
 385         rte_intr_callback_unregister(intr_handle,
 386                                      eth_em_interrupt_handler, eth_dev);
 387
 388         return 0;
 389 }
 390
 391 static int eth_em_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 392         struct rte_pci_device *pci_dev)
 393 {
 394         return rte_eth_dev_pci_generic_probe(pci_dev,
 395                 sizeof(struct e1000_adapter), eth_em_dev_init);
 396 }
 397
 398 static int eth_em_pci_remove(struct rte_pci_device *pci_dev)
 399 {
 400         return rte_eth_dev_pci_generic_remove(pci_dev, eth_em_dev_uninit);
 401 }
 402
 403 static struct rte_pci_driver rte_em_pmd = {
 404         .id_table = pci_id_em_map,
 405         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 406                      RTE_PCI_DRV_IOVA_AS_VA,
 407         .probe = eth_em_pci_probe,
 408         .remove = eth_em_pci_remove,
 409 };
 410
 411 static int
 412 em_hw_init(struct e1000_hw *hw)
 413 {
 414         int diag;
 415
 416         diag = hw->mac.ops.init_params(hw);
 417         if (diag != 0) {
 418                 PMD_INIT_LOG(ERR, "MAC Initialization Error");
 419                 return diag;
 420         }
 421         diag = hw->nvm.ops.init_params(hw);
 422         if (diag != 0) {
 423                 PMD_INIT_LOG(ERR, "NVM Initialization Error");
 424                 return diag;
 425         }
 426         diag = hw->phy.ops.init_params(hw);
 427         if (diag != 0) {
 428                 PMD_INIT_LOG(ERR, "PHY Initialization Error");
 429                 return diag;
 430         }
 431         (void) e1000_get_bus_info(hw);
 432
 433         hw->mac.autoneg = 1;
 434         hw->phy.autoneg_wait_to_complete = 0;
 435         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 436
 437         e1000_init_script_state_82541(hw, TRUE);
 438         e1000_set_tbi_compatibility_82543(hw, TRUE);
 439
 440         /* Copper options */
 441         if (hw->phy.media_type == e1000_media_type_copper) {
 442                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 443                 hw->phy.disable_polarity_correction = 0;
 444                 hw->phy.ms_type = e1000_ms_hw_default;
 445         }
 446
 447         /*
 448          * Start from a known state, this is important in reading the nvm
 449          * and mac from that.
 450          */
 451         e1000_reset_hw(hw);
 452
 453         /* Make sure we have a good EEPROM before we read from it */
 454         if (e1000_validate_nvm_checksum(hw) < 0) {
 455                 /*
 456                  * Some PCI-E parts fail the first check due to
 457                  * the link being in sleep state, call it again,
 458                  * if it fails a second time its a real issue.
 459                  */
 460                 diag = e1000_validate_nvm_checksum(hw);
 461                 if (diag < 0) {
 462                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 463                         goto error;
 464                 }
 465         }
 466
 467         /* Read the permanent MAC address out of the EEPROM */
 468         diag = e1000_read_mac_addr(hw);
 469         if (diag != 0) {
 470                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 471                 goto error;
 472         }
 473
 474         /* Now initialize the hardware */
 475         diag = em_hardware_init(hw);
 476         if (diag != 0) {
 477                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 478                 goto error;
 479         }
 480
 481         hw->mac.get_link_status = 1;
 482
 483         /* Indicate SOL/IDER usage */
 484         diag = e1000_check_reset_block(hw);
 485         if (diag < 0) {
 486                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
 487                         "SOL/IDER session");
 488         }
 489         return 0;
 490
 491 error:
 492         em_hw_control_release(hw);
 493         return diag;
 494 }
 495
 496 static int
 497 eth_em_configure(struct rte_eth_dev *dev)
 498 {
 499         struct e1000_interrupt *intr =
 500                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 501
 502         PMD_INIT_FUNC_TRACE();
 503         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 504         PMD_INIT_FUNC_TRACE();
 505
 506         return 0;
 507 }
 508
 509 static void
 510 em_set_pba(struct e1000_hw *hw)
 511 {
 512         uint32_t pba;
 513
 514         /*
 515          * Packet Buffer Allocation (PBA)
 516          * Writing PBA sets the receive portion of the buffer
 517          * the remainder is used for the transmit buffer.
 518          * Devices before the 82547 had a Packet Buffer of 64K.
 519          * After the 82547 the buffer was reduced to 40K.
 520          */
 521         switch (hw->mac.type) {
 522                 case e1000_82547:
 523                 case e1000_82547_rev_2:
 524                 /* 82547: Total Packet Buffer is 40K */
 525                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
 526                         break;
 527                 case e1000_82571:
 528                 case e1000_82572:
 529                 case e1000_80003es2lan:
 530                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 531                         break;
 532                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
 533                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
 534                         break;
 535                 case e1000_82574:
 536                 case e1000_82583:
 537                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
 538                         break;
 539                 case e1000_ich8lan:
 540                         pba = E1000_PBA_8K;
 541                         break;
 542                 case e1000_ich9lan:
 543                 case e1000_ich10lan:
 544                         pba = E1000_PBA_10K;
 545                         break;
 546                 case e1000_pchlan:
 547                 case e1000_pch2lan:
 548                 case e1000_pch_lpt:
 549                 case e1000_pch_spt:
 550                 case e1000_pch_cnp:
 551                         pba = E1000_PBA_26K;
 552                         break;
 553                 default:
 554                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
 555         }
 556
 557         E1000_WRITE_REG(hw, E1000_PBA, pba);
 558 }
 559
 560 static int
 561 eth_em_start(struct rte_eth_dev *dev)
 562 {
 563         struct e1000_adapter *adapter =
 564                 E1000_DEV_PRIVATE(dev->data->dev_private);
 565         struct e1000_hw *hw =
 566                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 567         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 568         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 569         int ret, mask;
 570         uint32_t intr_vector = 0;
 571         uint32_t *speeds;
 572         int num_speeds;
 573         bool autoneg;
 574
 575         PMD_INIT_FUNC_TRACE();
 576
 577         eth_em_stop(dev);
 578
 579         e1000_power_up_phy(hw);
 580
 581         /* Set default PBA value */
 582         em_set_pba(hw);
 583
 584         /* Put the address into the Receive Address Array */
 585         e1000_rar_set(hw, hw->mac.addr, 0);
 586
 587         /*
 588          * With the 82571 adapter, RAR[0] may be overwritten
 589          * when the other port is reset, we make a duplicate
 590          * in RAR[14] for that eventuality, this assures
 591          * the interface continues to function.
 592          */
 593         if (hw->mac.type == e1000_82571) {
 594                 e1000_set_laa_state_82571(hw, TRUE);
 595                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
 596         }
 597
 598         /* Initialize the hardware */
 599         if (em_hardware_init(hw)) {
 600                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 601                 return -EIO;
 602         }
 603
 604         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 605
 606         /* Configure for OS presence */
 607         em_init_manageability(hw);
 608
 609         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 610                 intr_vector = dev->data->nb_rx_queues;
 611                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 612                         return -1;
 613         }
 614
 615         if (rte_intr_dp_is_en(intr_handle)) {
 616                 intr_handle->intr_vec =
 617                         rte_zmalloc("intr_vec",
 618                                         dev->data->nb_rx_queues * sizeof(int), 0);
 619                 if (intr_handle->intr_vec == NULL) {
 620                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 621                                                 " intr_vec", dev->data->nb_rx_queues);
 622                         return -ENOMEM;
 623                 }
 624
 625                 /* enable rx interrupt */
 626                 em_rxq_intr_enable(hw);
 627         }
 628
 629         eth_em_tx_init(dev);
 630
 631         ret = eth_em_rx_init(dev);
 632         if (ret) {
 633                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 634                 em_dev_clear_queues(dev);
 635                 return ret;
 636         }
 637
 638         e1000_clear_hw_cntrs_base_generic(hw);
 639
 640         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 641                         ETH_VLAN_EXTEND_MASK;
 642         ret = eth_em_vlan_offload_set(dev, mask);
 643         if (ret) {
 644                 PMD_INIT_LOG(ERR, "Unable to update vlan offload");
 645                 em_dev_clear_queues(dev);
 646                 return ret;
 647         }
 648
 649         /* Set Interrupt Throttling Rate to maximum allowed value. */
 650         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
 651
 652         /* Setup link speed and duplex */
 653         speeds = &dev->data->dev_conf.link_speeds;
 654         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
 655                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 656                 hw->mac.autoneg = 1;
 657         } else {
 658                 num_speeds = 0;
 659                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
 660
 661                 /* Reset */
 662                 hw->phy.autoneg_advertised = 0;
 663
 664                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
 665                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
 666                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
 667                         num_speeds = -1;
 668                         goto error_invalid_config;
 669                 }
 670                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
 671                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
 672                         num_speeds++;
 673                 }
 674                 if (*speeds & ETH_LINK_SPEED_10M) {
 675                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
 676                         num_speeds++;
 677                 }
 678                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
 679                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
 680                         num_speeds++;
 681                 }
 682                 if (*speeds & ETH_LINK_SPEED_100M) {
 683                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
 684                         num_speeds++;
 685                 }
 686                 if (*speeds & ETH_LINK_SPEED_1G) {
 687                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
 688                         num_speeds++;
 689                 }
 690                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
 691                         goto error_invalid_config;
 692
 693                 /* Set/reset the mac.autoneg based on the link speed,
 694                  * fixed or not
 695                  */
 696                 if (!autoneg) {
 697                         hw->mac.autoneg = 0;
 698                         hw->mac.forced_speed_duplex =
 699                                         hw->phy.autoneg_advertised;
 700                 } else {
 701                         hw->mac.autoneg = 1;
 702                 }
 703         }
 704
 705         e1000_setup_link(hw);
 706
 707         if (rte_intr_allow_others(intr_handle)) {
 708                 /* check if lsc interrupt is enabled */
 709                 if (dev->data->dev_conf.intr_conf.lsc != 0) {
 710                         ret = eth_em_interrupt_setup(dev);
 711                         if (ret) {
 712                                 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
 713                                 em_dev_clear_queues(dev);
 714                                 return ret;
 715                         }
 716                 }
 717         } else {
 718                 rte_intr_callback_unregister(intr_handle,
 719                                                 eth_em_interrupt_handler,
 720                                                 (void *)dev);
 721                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 722                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
 723                                      " no intr multiplexn");
 724         }
 725         /* check if rxq interrupt is enabled */
 726         if (dev->data->dev_conf.intr_conf.rxq != 0)
 727                 eth_em_rxq_interrupt_setup(dev);
 728
 729         rte_intr_enable(intr_handle);
 730
 731         adapter->stopped = 0;
 732
 733         PMD_INIT_LOG(DEBUG, "<<");
 734
 735         return 0;
 736
 737 error_invalid_config:
 738         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
 739                      dev->data->dev_conf.link_speeds, dev->data->port_id);
 740         em_dev_clear_queues(dev);
 741         return -EINVAL;
 742 }
 743
 744 /*********************************************************************
 745  *
 746  *  This routine disables all traffic on the adapter by issuing a
 747  *  global reset on the MAC.
 748  *
 749  **********************************************************************/
 750 static void
 751 eth_em_stop(struct rte_eth_dev *dev)
 752 {
 753         struct rte_eth_link link;
 754         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 755         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 756         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 757
 758         em_rxq_intr_disable(hw);
 759         em_lsc_intr_disable(hw);
 760
 761         e1000_reset_hw(hw);
 762         if (hw->mac.type >= e1000_82544)
 763                 E1000_WRITE_REG(hw, E1000_WUC, 0);
 764
 765         /* Power down the phy. Needed to make the link go down */
 766         e1000_power_down_phy(hw);
 767
 768         em_dev_clear_queues(dev);
 769
 770         /* clear the recorded link status */
 771         memset(&link, 0, sizeof(link));
 772         rte_em_dev_atomic_write_link_status(dev, &link);
 773
 774         if (!rte_intr_allow_others(intr_handle))
 775                 /* resume to the default handler */
 776                 rte_intr_callback_register(intr_handle,
 777                                            eth_em_interrupt_handler,
 778                                            (void *)dev);
 779
 780         /* Clean datapath event and queue/vec mapping */
 781         rte_intr_efd_disable(intr_handle);
 782         if (intr_handle->intr_vec != NULL) {
 783                 rte_free(intr_handle->intr_vec);
 784                 intr_handle->intr_vec = NULL;
 785         }
 786 }
 787
 788 static void
 789 eth_em_close(struct rte_eth_dev *dev)
 790 {
 791         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 792         struct e1000_adapter *adapter =
 793                 E1000_DEV_PRIVATE(dev->data->dev_private);
 794
 795         eth_em_stop(dev);
 796         adapter->stopped = 1;
 797         em_dev_free_queues(dev);
 798         e1000_phy_hw_reset(hw);
 799         em_release_manageability(hw);
 800         em_hw_control_release(hw);
 801 }
 802
 803 static int
 804 em_get_rx_buffer_size(struct e1000_hw *hw)
 805 {
 806         uint32_t rx_buf_size;
 807
 808         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
 809         return rx_buf_size;
 810 }
 811
 812 /*********************************************************************
 813  *
 814  *  Initialize the hardware
 815  *
 816  **********************************************************************/
 817 static int
 818 em_hardware_init(struct e1000_hw *hw)
 819 {
 820         uint32_t rx_buf_size;
 821         int diag;
 822
 823         /* Issue a global reset */
 824         e1000_reset_hw(hw);
 825
 826         /* Let the firmware know the OS is in control */
 827         em_hw_control_acquire(hw);
 828
 829         /*
 830          * These parameters control the automatic generation (Tx) and
 831          * response (Rx) to Ethernet PAUSE frames.
 832          * - High water mark should allow for at least two standard size (1518)
 833          *   frames to be received after sending an XOFF.
 834          * - Low water mark works best when it is very near the high water mark.
 835          *   This allows the receiver to restart by sending XON when it has
 836          *   drained a bit. Here we use an arbitrary value of 1500 which will
 837          *   restart after one full frame is pulled from the buffer. There
 838          *   could be several smaller frames in the buffer and if so they will
 839          *   not trigger the XON until their total number reduces the buffer
 840          *   by 1500.
 841          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 842          */
 843         rx_buf_size = em_get_rx_buffer_size(hw);
 844
 845         hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
 846         hw->fc.low_water = hw->fc.high_water - 1500;
 847
 848         if (hw->mac.type == e1000_80003es2lan)
 849                 hw->fc.pause_time = UINT16_MAX;
 850         else
 851                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
 852
 853         hw->fc.send_xon = 1;
 854
 855         /* Set Flow control, use the tunable location if sane */
 856         if (em_fc_setting <= e1000_fc_full)
 857                 hw->fc.requested_mode = em_fc_setting;
 858         else
 859                 hw->fc.requested_mode = e1000_fc_none;
 860
 861         /* Workaround: no TX flow ctrl for PCH */
 862         if (hw->mac.type == e1000_pchlan)
 863                 hw->fc.requested_mode = e1000_fc_rx_pause;
 864
 865         /* Override - settings for PCH2LAN, ya its magic :) */
 866         if (hw->mac.type == e1000_pch2lan) {
 867                 hw->fc.high_water = 0x5C20;
 868                 hw->fc.low_water = 0x5048;
 869                 hw->fc.pause_time = 0x0650;
 870                 hw->fc.refresh_time = 0x0400;
 871         } else if (hw->mac.type == e1000_pch_lpt ||
 872                    hw->mac.type == e1000_pch_spt ||
 873                    hw->mac.type == e1000_pch_cnp) {
 874                 hw->fc.requested_mode = e1000_fc_full;
 875         }
 876
 877         diag = e1000_init_hw(hw);
 878         if (diag < 0)
 879                 return diag;
 880         e1000_check_for_link(hw);
 881         return 0;
 882 }
 883
 884 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
 885 static int
 886 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 887 {
 888         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 889         struct e1000_hw_stats *stats =
 890                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 891         int pause_frames;
 892
 893         if(hw->phy.media_type == e1000_media_type_copper ||
 894                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 895                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
 896                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 897         }
 898
 899         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 900         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 901         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 902         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 903
 904         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 905         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 906         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 907         stats->dc += E1000_READ_REG(hw, E1000_DC);
 908         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 909         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 910         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 911
 912         /*
 913          * For watchdog management we need to know if we have been
 914          * paused during the last interval, so capture that here.
 915          */
 916         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 917         stats->xoffrxc += pause_frames;
 918         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 919         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 920         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 921         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 922         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 923         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 924         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 925         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 926         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 927         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 928         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 929         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 930
 931         /*
 932          * For the 64-bit byte counters the low dword must be read first.
 933          * Both registers clear on the read of the high dword.
 934          */
 935
 936         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 937         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 938         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 939         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 940
 941         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 942         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 943         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 944         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 945         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 946
 947         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 948         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 949
 950         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 951         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 952         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 953         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 954         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 955         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 956         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 957         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 958         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 959         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 960
 961         /* Interrupt Counts */
 962
 963         if (hw->mac.type >= e1000_82571) {
 964                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
 965                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 966                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 967                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 968                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 969                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 970                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 971                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 972                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 973         }
 974
 975         if (hw->mac.type >= e1000_82543) {
 976                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 977                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 978                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 979                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 980                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 981                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 982         }
 983
 984         if (rte_stats == NULL)
 985                 return -EINVAL;
 986
 987         /* Rx Errors */
 988         rte_stats->imissed = stats->mpc;
 989         rte_stats->ierrors = stats->crcerrs +
 990                              stats->rlec + stats->ruc + stats->roc +
 991                              stats->rxerrc + stats->algnerrc + stats->cexterr;
 992
 993         /* Tx Errors */
 994         rte_stats->oerrors = stats->ecol + stats->latecol;
 995
 996         rte_stats->ipackets = stats->gprc;
 997         rte_stats->opackets = stats->gptc;
 998         rte_stats->ibytes   = stats->gorc;
 999         rte_stats->obytes   = stats->gotc;
1000         return 0;
1001 }
1002
1003 static void
1004 eth_em_stats_reset(struct rte_eth_dev *dev)
1005 {
1006         struct e1000_hw_stats *hw_stats =
1007                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1008
1009         /* HW registers are cleared on read */
1010         eth_em_stats_get(dev, NULL);
1011
1012         /* Reset software totals */
1013         memset(hw_stats, 0, sizeof(*hw_stats));
1014 }
1015
1016 static int
1017 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1018 {
1019         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1020         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1021         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1022
1023         em_rxq_intr_enable(hw);
1024         rte_intr_enable(intr_handle);
1025
1026         return 0;
1027 }
1028
1029 static int
1030 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1031 {
1032         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1033
1034         em_rxq_intr_disable(hw);
1035
1036         return 0;
1037 }
1038
1039 static uint32_t
1040 em_get_max_pktlen(const struct e1000_hw *hw)
1041 {
1042         switch (hw->mac.type) {
1043         case e1000_82571:
1044         case e1000_82572:
1045         case e1000_ich9lan:
1046         case e1000_ich10lan:
1047         case e1000_pch2lan:
1048         case e1000_pch_lpt:
1049         case e1000_pch_spt:
1050         case e1000_pch_cnp:
1051         case e1000_82574:
1052         case e1000_80003es2lan: /* 9K Jumbo Frame size */
1053         case e1000_82583:
1054                 return 0x2412;
1055         case e1000_pchlan:
1056                 return 0x1000;
1057         /* Adapters that do not support jumbo frames */
1058         case e1000_ich8lan:
1059                 return ETHER_MAX_LEN;
1060         default:
1061                 return MAX_JUMBO_FRAME_SIZE;
1062         }
1063 }
1064
1065 static void
1066 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1067 {
1068         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1069
1070         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1071         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1072         dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
1073         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1074         dev_info->rx_offload_capa =
1075                 DEV_RX_OFFLOAD_VLAN_STRIP |
1076                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1077                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1078                 DEV_RX_OFFLOAD_TCP_CKSUM;
1079         dev_info->tx_offload_capa =
1080                 DEV_TX_OFFLOAD_VLAN_INSERT |
1081                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1082                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1083                 DEV_TX_OFFLOAD_TCP_CKSUM;
1084
1085         /*
1086          * Starting with 631xESB hw supports 2 TX/RX queues per port.
1087          * Unfortunatelly, all these nics have just one TX context.
1088          * So we have few choises for TX:
1089          * - Use just one TX queue.
1090          * - Allow cksum offload only for one TX queue.
1091          * - Don't allow TX cksum offload at all.
1092          * For now, option #1 was chosen.
1093          * To use second RX queue we have to use extended RX descriptor
1094          * (Multiple Receive Queues are mutually exclusive with UDP
1095          * fragmentation and are not supported when a legacy receive
1096          * descriptor format is used).
1097          * Which means separate RX routinies - as legacy nics (82540, 82545)
1098          * don't support extended RXD.
1099          * To avoid it we support just one RX queue for now (no RSS).
1100          */
1101
1102         dev_info->max_rx_queues = 1;
1103         dev_info->max_tx_queues = 1;
1104
1105         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1106                 .nb_max = E1000_MAX_RING_DESC,
1107                 .nb_min = E1000_MIN_RING_DESC,
1108                 .nb_align = EM_RXD_ALIGN,
1109         };
1110
1111         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1112                 .nb_max = E1000_MAX_RING_DESC,
1113                 .nb_min = E1000_MIN_RING_DESC,
1114                 .nb_align = EM_TXD_ALIGN,
1115                 .nb_seg_max = EM_TX_MAX_SEG,
1116                 .nb_mtu_seg_max = EM_TX_MAX_MTU_SEG,
1117         };
1118
1119         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1120                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1121                         ETH_LINK_SPEED_1G;
1122 }
1123
1124 /* return 0 means link status changed, -1 means not changed */
1125 static int
1126 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1127 {
1128         struct e1000_hw *hw =
1129                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1130         struct rte_eth_link link, old;
1131         int link_check, count;
1132
1133         link_check = 0;
1134         hw->mac.get_link_status = 1;
1135
1136         /* possible wait-to-complete in up to 9 seconds */
1137         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1138                 /* Read the real link status */
1139                 switch (hw->phy.media_type) {
1140                 case e1000_media_type_copper:
1141                         /* Do the work to read phy */
1142                         e1000_check_for_link(hw);
1143                         link_check = !hw->mac.get_link_status;
1144                         break;
1145
1146                 case e1000_media_type_fiber:
1147                         e1000_check_for_link(hw);
1148                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1149                                         E1000_STATUS_LU);
1150                         break;
1151
1152                 case e1000_media_type_internal_serdes:
1153                         e1000_check_for_link(hw);
1154                         link_check = hw->mac.serdes_has_link;
1155                         break;
1156
1157                 default:
1158                         break;
1159                 }
1160                 if (link_check || wait_to_complete == 0)
1161                         break;
1162                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1163         }
1164         memset(&link, 0, sizeof(link));
1165         rte_em_dev_atomic_read_link_status(dev, &link);
1166         old = link;
1167
1168         /* Now we check if a transition has happened */
1169         if (link_check && (link.link_status == ETH_LINK_DOWN)) {
1170                 uint16_t duplex, speed;
1171                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1172                 link.link_duplex = (duplex == FULL_DUPLEX) ?
1173                                 ETH_LINK_FULL_DUPLEX :
1174                                 ETH_LINK_HALF_DUPLEX;
1175                 link.link_speed = speed;
1176                 link.link_status = ETH_LINK_UP;
1177                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1178                                 ETH_LINK_SPEED_FIXED);
1179         } else if (!link_check && (link.link_status == ETH_LINK_UP)) {
1180                 link.link_speed = 0;
1181                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1182                 link.link_status = ETH_LINK_DOWN;
1183                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
1184         }
1185         rte_em_dev_atomic_write_link_status(dev, &link);
1186
1187         /* not changed */
1188         if (old.link_status == link.link_status)
1189                 return -1;
1190
1191         /* changed */
1192         return 0;
1193 }
1194
1195 /*
1196  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1197  * For ASF and Pass Through versions of f/w this means
1198  * that the driver is loaded. For AMT version type f/w
1199  * this means that the network i/f is open.
1200  */
1201 static void
1202 em_hw_control_acquire(struct e1000_hw *hw)
1203 {
1204         uint32_t ctrl_ext, swsm;
1205
1206         /* Let firmware know the driver has taken over */
1207         if (hw->mac.type == e1000_82573) {
1208                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1209                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1210
1211         } else {
1212                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1213                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1214                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1215         }
1216 }
1217
1218 /*
1219  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1220  * For ASF and Pass Through versions of f/w this means that the
1221  * driver is no longer loaded. For AMT versions of the
1222  * f/w this means that the network i/f is closed.
1223  */
1224 static void
1225 em_hw_control_release(struct e1000_hw *hw)
1226 {
1227         uint32_t ctrl_ext, swsm;
1228
1229         /* Let firmware taken over control of h/w */
1230         if (hw->mac.type == e1000_82573) {
1231                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1232                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1233         } else {
1234                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1235                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1236                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1237         }
1238 }
1239
1240 /*
1241  * Bit of a misnomer, what this really means is
1242  * to enable OS management of the system... aka
1243  * to disable special hardware management features.
1244  */
1245 static void
1246 em_init_manageability(struct e1000_hw *hw)
1247 {
1248         if (e1000_enable_mng_pass_thru(hw)) {
1249                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1250                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1251
1252                 /* disable hardware interception of ARP */
1253                 manc &= ~(E1000_MANC_ARP_EN);
1254
1255                 /* enable receiving management packets to the host */
1256                 manc |= E1000_MANC_EN_MNG2HOST;
1257                 manc2h |= 1 << 5;  /* Mng Port 623 */
1258                 manc2h |= 1 << 6;  /* Mng Port 664 */
1259                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1260                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1261         }
1262 }
1263
1264 /*
1265  * Give control back to hardware management
1266  * controller if there is one.
1267  */
1268 static void
1269 em_release_manageability(struct e1000_hw *hw)
1270 {
1271         uint32_t manc;
1272
1273         if (e1000_enable_mng_pass_thru(hw)) {
1274                 manc = E1000_READ_REG(hw, E1000_MANC);
1275
1276                 /* re-enable hardware interception of ARP */
1277                 manc |= E1000_MANC_ARP_EN;
1278                 manc &= ~E1000_MANC_EN_MNG2HOST;
1279
1280                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1281         }
1282 }
1283
1284 static void
1285 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1286 {
1287         struct e1000_hw *hw =
1288                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1289         uint32_t rctl;
1290
1291         rctl = E1000_READ_REG(hw, E1000_RCTL);
1292         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1293         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1294 }
1295
1296 static void
1297 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1298 {
1299         struct e1000_hw *hw =
1300                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1301         uint32_t rctl;
1302
1303         rctl = E1000_READ_REG(hw, E1000_RCTL);
1304         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1305         if (dev->data->all_multicast == 1)
1306                 rctl |= E1000_RCTL_MPE;
1307         else
1308                 rctl &= (~E1000_RCTL_MPE);
1309         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1310 }
1311
1312 static void
1313 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1314 {
1315         struct e1000_hw *hw =
1316                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1317         uint32_t rctl;
1318
1319         rctl = E1000_READ_REG(hw, E1000_RCTL);
1320         rctl |= E1000_RCTL_MPE;
1321         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1322 }
1323
1324 static void
1325 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1326 {
1327         struct e1000_hw *hw =
1328                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1329         uint32_t rctl;
1330
1331         if (dev->data->promiscuous == 1)
1332                 return; /* must remain in all_multicast mode */
1333         rctl = E1000_READ_REG(hw, E1000_RCTL);
1334         rctl &= (~E1000_RCTL_MPE);
1335         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1336 }
1337
1338 static int
1339 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1340 {
1341         struct e1000_hw *hw =
1342                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1343         struct e1000_vfta * shadow_vfta =
1344                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1345         uint32_t vfta;
1346         uint32_t vid_idx;
1347         uint32_t vid_bit;
1348
1349         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1350                               E1000_VFTA_ENTRY_MASK);
1351         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1352         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1353         if (on)
1354                 vfta |= vid_bit;
1355         else
1356                 vfta &= ~vid_bit;
1357         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1358
1359         /* update local VFTA copy */
1360         shadow_vfta->vfta[vid_idx] = vfta;
1361
1362         return 0;
1363 }
1364
1365 static void
1366 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1367 {
1368         struct e1000_hw *hw =
1369                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1370         uint32_t reg;
1371
1372         /* Filter Table Disable */
1373         reg = E1000_READ_REG(hw, E1000_RCTL);
1374         reg &= ~E1000_RCTL_CFIEN;
1375         reg &= ~E1000_RCTL_VFE;
1376         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1377 }
1378
1379 static void
1380 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1381 {
1382         struct e1000_hw *hw =
1383                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1384         struct e1000_vfta * shadow_vfta =
1385                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1386         uint32_t reg;
1387         int i;
1388
1389         /* Filter Table Enable, CFI not used for packet acceptance */
1390         reg = E1000_READ_REG(hw, E1000_RCTL);
1391         reg &= ~E1000_RCTL_CFIEN;
1392         reg |= E1000_RCTL_VFE;
1393         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1394
1395         /* restore vfta from local copy */
1396         for (i = 0; i < IGB_VFTA_SIZE; i++)
1397                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1398 }
1399
1400 static void
1401 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1402 {
1403         struct e1000_hw *hw =
1404                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1405         uint32_t reg;
1406
1407         /* VLAN Mode Disable */
1408         reg = E1000_READ_REG(hw, E1000_CTRL);
1409         reg &= ~E1000_CTRL_VME;
1410         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1411
1412 }
1413
1414 static void
1415 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1416 {
1417         struct e1000_hw *hw =
1418                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1419         uint32_t reg;
1420
1421         /* VLAN Mode Enable */
1422         reg = E1000_READ_REG(hw, E1000_CTRL);
1423         reg |= E1000_CTRL_VME;
1424         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1425 }
1426
1427 static int
1428 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1429 {
1430         if(mask & ETH_VLAN_STRIP_MASK){
1431                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1432                         em_vlan_hw_strip_enable(dev);
1433                 else
1434                         em_vlan_hw_strip_disable(dev);
1435         }
1436
1437         if(mask & ETH_VLAN_FILTER_MASK){
1438                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1439                         em_vlan_hw_filter_enable(dev);
1440                 else
1441                         em_vlan_hw_filter_disable(dev);
1442         }
1443
1444         return 0;
1445 }
1446
1447 /*
1448  * It enables the interrupt mask and then enable the interrupt.
1449  *
1450  * @param dev
1451  *  Pointer to struct rte_eth_dev.
1452  *
1453  * @return
1454  *  - On success, zero.
1455  *  - On failure, a negative value.
1456  */
1457 static int
1458 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1459 {
1460         uint32_t regval;
1461         struct e1000_hw *hw =
1462                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1463
1464         /* clear interrupt */
1465         E1000_READ_REG(hw, E1000_ICR);
1466         regval = E1000_READ_REG(hw, E1000_IMS);
1467         E1000_WRITE_REG(hw, E1000_IMS, regval | E1000_ICR_LSC);
1468         return 0;
1469 }
1470
1471 /*
1472  * It clears the interrupt causes and enables the interrupt.
1473  * It will be called once only during nic initialized.
1474  *
1475  * @param dev
1476  *  Pointer to struct rte_eth_dev.
1477  *
1478  * @return
1479  *  - On success, zero.
1480  *  - On failure, a negative value.
1481  */
1482 static int
1483 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1484 {
1485         struct e1000_hw *hw =
1486         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1487
1488         E1000_READ_REG(hw, E1000_ICR);
1489         em_rxq_intr_enable(hw);
1490         return 0;
1491 }
1492
1493 /*
1494  * It enable receive packet interrupt.
1495  * @param hw
1496  * Pointer to struct e1000_hw
1497  *
1498  * @return
1499  */
1500 static void
1501 em_rxq_intr_enable(struct e1000_hw *hw)
1502 {
1503         E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1504         E1000_WRITE_FLUSH(hw);
1505 }
1506
1507 /*
1508  * It disabled lsc interrupt.
1509  * @param hw
1510  * Pointer to struct e1000_hw
1511  *
1512  * @return
1513  */
1514 static void
1515 em_lsc_intr_disable(struct e1000_hw *hw)
1516 {
1517         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC);
1518         E1000_WRITE_FLUSH(hw);
1519 }
1520
1521 /*
1522  * It disabled receive packet interrupt.
1523  * @param hw
1524  * Pointer to struct e1000_hw
1525  *
1526  * @return
1527  */
1528 static void
1529 em_rxq_intr_disable(struct e1000_hw *hw)
1530 {
1531         E1000_READ_REG(hw, E1000_ICR);
1532         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1533         E1000_WRITE_FLUSH(hw);
1534 }
1535
1536 /*
1537  * It reads ICR and gets interrupt causes, check it and set a bit flag
1538  * to update link status.
1539  *
1540  * @param dev
1541  *  Pointer to struct rte_eth_dev.
1542  *
1543  * @return
1544  *  - On success, zero.
1545  *  - On failure, a negative value.
1546  */
1547 static int
1548 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1549 {
1550         uint32_t icr;
1551         struct e1000_hw *hw =
1552                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1553         struct e1000_interrupt *intr =
1554                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1555
1556         /* read-on-clear nic registers here */
1557         icr = E1000_READ_REG(hw, E1000_ICR);
1558         if (icr & E1000_ICR_LSC) {
1559                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1560         }
1561
1562         return 0;
1563 }
1564
1565 /*
1566  * It executes link_update after knowing an interrupt is prsent.
1567  *
1568  * @param dev
1569  *  Pointer to struct rte_eth_dev.
1570  *
1571  * @return
1572  *  - On success, zero.
1573  *  - On failure, a negative value.
1574  */
1575 static int
1576 eth_em_interrupt_action(struct rte_eth_dev *dev,
1577                         struct rte_intr_handle *intr_handle)
1578 {
1579         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1580         struct e1000_hw *hw =
1581                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1582         struct e1000_interrupt *intr =
1583                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1584         uint32_t tctl, rctl;
1585         struct rte_eth_link link;
1586         int ret;
1587
1588         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1589                 return -1;
1590
1591         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1592         rte_intr_enable(intr_handle);
1593
1594         /* set get_link_status to check register later */
1595         hw->mac.get_link_status = 1;
1596         ret = eth_em_link_update(dev, 0);
1597
1598         /* check if link has changed */
1599         if (ret < 0)
1600                 return 0;
1601
1602         memset(&link, 0, sizeof(link));
1603         rte_em_dev_atomic_read_link_status(dev, &link);
1604         if (link.link_status) {
1605                 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1606                              dev->data->port_id, link.link_speed,
1607                              link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1608                              "full-duplex" : "half-duplex");
1609         } else {
1610                 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1611         }
1612         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1613                      pci_dev->addr.domain, pci_dev->addr.bus,
1614                      pci_dev->addr.devid, pci_dev->addr.function);
1615
1616         tctl = E1000_READ_REG(hw, E1000_TCTL);
1617         rctl = E1000_READ_REG(hw, E1000_RCTL);
1618         if (link.link_status) {
1619                 /* enable Tx/Rx */
1620                 tctl |= E1000_TCTL_EN;
1621                 rctl |= E1000_RCTL_EN;
1622         } else {
1623                 /* disable Tx/Rx */
1624                 tctl &= ~E1000_TCTL_EN;
1625                 rctl &= ~E1000_RCTL_EN;
1626         }
1627         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1628         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1629         E1000_WRITE_FLUSH(hw);
1630
1631         return 0;
1632 }
1633
1634 /**
1635  * Interrupt handler which shall be registered at first.
1636  *
1637  * @param handle
1638  *  Pointer to interrupt handle.
1639  * @param param
1640  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1641  *
1642  * @return
1643  *  void
1644  */
1645 static void
1646 eth_em_interrupt_handler(void *param)
1647 {
1648         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1649
1650         eth_em_interrupt_get_status(dev);
1651         eth_em_interrupt_action(dev, dev->intr_handle);
1652         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
1653 }
1654
1655 static int
1656 eth_em_led_on(struct rte_eth_dev *dev)
1657 {
1658         struct e1000_hw *hw;
1659
1660         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1661         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1662 }
1663
1664 static int
1665 eth_em_led_off(struct rte_eth_dev *dev)
1666 {
1667         struct e1000_hw *hw;
1668
1669         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1670         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1671 }
1672
1673 static int
1674 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1675 {
1676         struct e1000_hw *hw;
1677         uint32_t ctrl;
1678         int tx_pause;
1679         int rx_pause;
1680
1681         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1682         fc_conf->pause_time = hw->fc.pause_time;
1683         fc_conf->high_water = hw->fc.high_water;
1684         fc_conf->low_water = hw->fc.low_water;
1685         fc_conf->send_xon = hw->fc.send_xon;
1686         fc_conf->autoneg = hw->mac.autoneg;
1687
1688         /*
1689          * Return rx_pause and tx_pause status according to actual setting of
1690          * the TFCE and RFCE bits in the CTRL register.
1691          */
1692         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1693         if (ctrl & E1000_CTRL_TFCE)
1694                 tx_pause = 1;
1695         else
1696                 tx_pause = 0;
1697
1698         if (ctrl & E1000_CTRL_RFCE)
1699                 rx_pause = 1;
1700         else
1701                 rx_pause = 0;
1702
1703         if (rx_pause && tx_pause)
1704                 fc_conf->mode = RTE_FC_FULL;
1705         else if (rx_pause)
1706                 fc_conf->mode = RTE_FC_RX_PAUSE;
1707         else if (tx_pause)
1708                 fc_conf->mode = RTE_FC_TX_PAUSE;
1709         else
1710                 fc_conf->mode = RTE_FC_NONE;
1711
1712         return 0;
1713 }
1714
1715 static int
1716 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1717 {
1718         struct e1000_hw *hw;
1719         int err;
1720         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1721                 e1000_fc_none,
1722                 e1000_fc_rx_pause,
1723                 e1000_fc_tx_pause,
1724                 e1000_fc_full
1725         };
1726         uint32_t rx_buf_size;
1727         uint32_t max_high_water;
1728         uint32_t rctl;
1729
1730         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1731         if (fc_conf->autoneg != hw->mac.autoneg)
1732                 return -ENOTSUP;
1733         rx_buf_size = em_get_rx_buffer_size(hw);
1734         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1735
1736         /* At least reserve one Ethernet frame for watermark */
1737         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1738         if ((fc_conf->high_water > max_high_water) ||
1739             (fc_conf->high_water < fc_conf->low_water)) {
1740                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1741                 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1742                 return -EINVAL;
1743         }
1744
1745         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1746         hw->fc.pause_time     = fc_conf->pause_time;
1747         hw->fc.high_water     = fc_conf->high_water;
1748         hw->fc.low_water      = fc_conf->low_water;
1749         hw->fc.send_xon       = fc_conf->send_xon;
1750
1751         err = e1000_setup_link_generic(hw);
1752         if (err == E1000_SUCCESS) {
1753
1754                 /* check if we want to forward MAC frames - driver doesn't have native
1755                  * capability to do that, so we'll write the registers ourselves */
1756
1757                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1758
1759                 /* set or clear MFLCN.PMCF bit depending on configuration */
1760                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1761                         rctl |= E1000_RCTL_PMCF;
1762                 else
1763                         rctl &= ~E1000_RCTL_PMCF;
1764
1765                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1766                 E1000_WRITE_FLUSH(hw);
1767
1768                 return 0;
1769         }
1770
1771         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1772         return -EIO;
1773 }
1774
1775 static int
1776 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1777                 uint32_t index, __rte_unused uint32_t pool)
1778 {
1779         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1780
1781         return e1000_rar_set(hw, mac_addr->addr_bytes, index);
1782 }
1783
1784 static void
1785 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1786 {
1787         uint8_t addr[ETHER_ADDR_LEN];
1788         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1789
1790         memset(addr, 0, sizeof(addr));
1791
1792         e1000_rar_set(hw, addr, index);
1793 }
1794
1795 static int
1796 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1797 {
1798         struct rte_eth_dev_info dev_info;
1799         struct e1000_hw *hw;
1800         uint32_t frame_size;
1801         uint32_t rctl;
1802
1803         eth_em_infos_get(dev, &dev_info);
1804         frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1805
1806         /* check that mtu is within the allowed range */
1807         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1808                 return -EINVAL;
1809
1810         /* refuse mtu that requires the support of scattered packets when this
1811          * feature has not been enabled before. */
1812         if (!dev->data->scattered_rx &&
1813             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1814                 return -EINVAL;
1815
1816         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1817         rctl = E1000_READ_REG(hw, E1000_RCTL);
1818
1819         /* switch to jumbo mode if needed */
1820         if (frame_size > ETHER_MAX_LEN) {
1821                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1822                 rctl |= E1000_RCTL_LPE;
1823         } else {
1824                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1825                 rctl &= ~E1000_RCTL_LPE;
1826         }
1827         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1828
1829         /* update max frame size */
1830         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1831         return 0;
1832 }
1833
1834 static int
1835 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1836                         struct ether_addr *mc_addr_set,
1837                         uint32_t nb_mc_addr)
1838 {
1839         struct e1000_hw *hw;
1840
1841         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1842         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1843         return 0;
1844 }
1845
1846 RTE_PMD_REGISTER_PCI(net_e1000_em, rte_em_pmd);
1847 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_em, pci_id_em_map);
1848 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_em, "* igb_uio | uio_pci_generic | vfio-pci");