drivers/net/e1000/em_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58
  59 #define EM_EIAC                 0x000DC
  60
  61 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
  62
  63
  64 static int eth_em_configure(struct rte_eth_dev *dev);
  65 static int eth_em_start(struct rte_eth_dev *dev);
  66 static void eth_em_stop(struct rte_eth_dev *dev);
  67 static void eth_em_close(struct rte_eth_dev *dev);
  68 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
  69 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
  70 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
  71 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
  72 static int eth_em_link_update(struct rte_eth_dev *dev,
  73                                 int wait_to_complete);
  74 static void eth_em_stats_get(struct rte_eth_dev *dev,
  75                                 struct rte_eth_stats *rte_stats);
  76 static void eth_em_stats_reset(struct rte_eth_dev *dev);
  77 static void eth_em_infos_get(struct rte_eth_dev *dev,
  78                                 struct rte_eth_dev_info *dev_info);
  79 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
  80                                 struct rte_eth_fc_conf *fc_conf);
  81 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
  82                                 struct rte_eth_fc_conf *fc_conf);
  83 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
  84 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
  85 static int eth_em_interrupt_action(struct rte_eth_dev *dev);
  86 static void eth_em_interrupt_handler(struct rte_intr_handle *handle,
  87                                                         void *param);
  88
  89 static int em_hw_init(struct e1000_hw *hw);
  90 static int em_hardware_init(struct e1000_hw *hw);
  91 static void em_hw_control_acquire(struct e1000_hw *hw);
  92 static void em_hw_control_release(struct e1000_hw *hw);
  93 static void em_init_manageability(struct e1000_hw *hw);
  94 static void em_release_manageability(struct e1000_hw *hw);
  95
  96 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  97
  98 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
  99                 uint16_t vlan_id, int on);
 100 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 101 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 102 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 103 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 104 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 105
 106 /*
 107 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
 108                                         uint16_t vlan_id, int on);
 109 */
 110 static void em_lsc_intr_disable(struct e1000_hw *hw);
 111 static void em_rxq_intr_disable(struct e1000_hw *hw);
 112 static int eth_em_led_on(struct rte_eth_dev *dev);
 113 static int eth_em_led_off(struct rte_eth_dev *dev);
 114
 115 static int em_get_rx_buffer_size(struct e1000_hw *hw);
 116 static void eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 117                 uint32_t index, uint32_t pool);
 118 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 119
 120 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
 121                                    struct ether_addr *mc_addr_set,
 122                                    uint32_t nb_mc_addr);
 123
 124 #define EM_FC_PAUSE_TIME 0x0680
 125 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 126 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 127
 128 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
 129
 130 /*
 131  * The set of PCI devices this driver supports
 132  */
 133 static const struct rte_pci_id pci_id_em_map[] = {
 134
 135 #define RTE_PCI_DEV_ID_DECL_EM(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 136 #include "rte_pci_dev_ids.h"
 137
 138 {0},
 139 };
 140
 141 static const struct eth_dev_ops eth_em_ops = {
 142         .dev_configure        = eth_em_configure,
 143         .dev_start            = eth_em_start,
 144         .dev_stop             = eth_em_stop,
 145         .dev_close            = eth_em_close,
 146         .promiscuous_enable   = eth_em_promiscuous_enable,
 147         .promiscuous_disable  = eth_em_promiscuous_disable,
 148         .allmulticast_enable  = eth_em_allmulticast_enable,
 149         .allmulticast_disable = eth_em_allmulticast_disable,
 150         .link_update          = eth_em_link_update,
 151         .stats_get            = eth_em_stats_get,
 152         .stats_reset          = eth_em_stats_reset,
 153         .dev_infos_get        = eth_em_infos_get,
 154         .mtu_set              = eth_em_mtu_set,
 155         .vlan_filter_set      = eth_em_vlan_filter_set,
 156         .vlan_offload_set     = eth_em_vlan_offload_set,
 157         .rx_queue_setup       = eth_em_rx_queue_setup,
 158         .rx_queue_release     = eth_em_rx_queue_release,
 159         .rx_queue_count       = eth_em_rx_queue_count,
 160         .rx_descriptor_done   = eth_em_rx_descriptor_done,
 161         .tx_queue_setup       = eth_em_tx_queue_setup,
 162         .tx_queue_release     = eth_em_tx_queue_release,
 163         .dev_led_on           = eth_em_led_on,
 164         .dev_led_off          = eth_em_led_off,
 165         .flow_ctrl_get        = eth_em_flow_ctrl_get,
 166         .flow_ctrl_set        = eth_em_flow_ctrl_set,
 167         .mac_addr_add         = eth_em_rar_set,
 168         .mac_addr_remove      = eth_em_rar_clear,
 169         .set_mc_addr_list     = eth_em_set_mc_addr_list,
 170 };
 171
 172 /**
 173  * Atomically reads the link status information from global
 174  * structure rte_eth_dev.
 175  *
 176  * @param dev
 177  *   - Pointer to the structure rte_eth_dev to read from.
 178  *   - Pointer to the buffer to be saved with the link status.
 179  *
 180  * @return
 181  *   - On success, zero.
 182  *   - On failure, negative value.
 183  */
 184 static inline int
 185 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 186                                 struct rte_eth_link *link)
 187 {
 188         struct rte_eth_link *dst = link;
 189         struct rte_eth_link *src = &(dev->data->dev_link);
 190
 191         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 192                                         *(uint64_t *)src) == 0)
 193                 return -1;
 194
 195         return 0;
 196 }
 197
 198 /**
 199  * Atomically writes the link status information into global
 200  * structure rte_eth_dev.
 201  *
 202  * @param dev
 203  *   - Pointer to the structure rte_eth_dev to read from.
 204  *   - Pointer to the buffer to be saved with the link status.
 205  *
 206  * @return
 207  *   - On success, zero.
 208  *   - On failure, negative value.
 209  */
 210 static inline int
 211 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 212                                 struct rte_eth_link *link)
 213 {
 214         struct rte_eth_link *dst = &(dev->data->dev_link);
 215         struct rte_eth_link *src = link;
 216
 217         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 218                                         *(uint64_t *)src) == 0)
 219                 return -1;
 220
 221         return 0;
 222 }
 223
 224 static int
 225 eth_em_dev_init(struct rte_eth_dev *eth_dev)
 226 {
 227         struct rte_pci_device *pci_dev;
 228         struct e1000_adapter *adapter =
 229                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 230         struct e1000_hw *hw =
 231                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 232         struct e1000_vfta * shadow_vfta =
 233                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 234
 235         pci_dev = eth_dev->pci_dev;
 236         eth_dev->dev_ops = &eth_em_ops;
 237         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
 238         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
 239
 240         /* for secondary processes, we don't initialise any further as primary
 241          * has already done this work. Only check we don't need a different
 242          * RX function */
 243         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 244                 if (eth_dev->data->scattered_rx)
 245                         eth_dev->rx_pkt_burst =
 246                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
 247                 return 0;
 248         }
 249
 250         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 251         hw->device_id = pci_dev->id.device_id;
 252         adapter->stopped = 0;
 253
 254         /* For ICH8 support we'll need to map the flash memory BAR */
 255
 256         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
 257                         em_hw_init(hw) != 0) {
 258                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
 259                         "failed to init HW",
 260                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 261                         pci_dev->id.device_id);
 262                 return -(ENODEV);
 263         }
 264
 265         /* Allocate memory for storing MAC addresses */
 266         eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
 267                         hw->mac.rar_entry_count, 0);
 268         if (eth_dev->data->mac_addrs == NULL) {
 269                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 270                         "store MAC addresses",
 271                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 272                 return -(ENOMEM);
 273         }
 274
 275         /* Copy the permanent MAC address */
 276         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 277                 eth_dev->data->mac_addrs);
 278
 279         /* initialize the vfta */
 280         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 281
 282         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 283                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 284                      pci_dev->id.device_id);
 285
 286         rte_intr_callback_register(&(pci_dev->intr_handle),
 287                 eth_em_interrupt_handler, (void *)eth_dev);
 288
 289         return (0);
 290 }
 291
 292 static int
 293 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
 294 {
 295         struct rte_pci_device *pci_dev;
 296         struct e1000_adapter *adapter =
 297                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 298
 299         PMD_INIT_FUNC_TRACE();
 300
 301         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 302                 return -EPERM;
 303
 304         pci_dev = eth_dev->pci_dev;
 305
 306         if (adapter->stopped == 0)
 307                 eth_em_close(eth_dev);
 308
 309         eth_dev->dev_ops = NULL;
 310         eth_dev->rx_pkt_burst = NULL;
 311         eth_dev->tx_pkt_burst = NULL;
 312
 313         rte_free(eth_dev->data->mac_addrs);
 314         eth_dev->data->mac_addrs = NULL;
 315
 316         /* disable uio intr before callback unregister */
 317         rte_intr_disable(&(pci_dev->intr_handle));
 318         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 319                 eth_em_interrupt_handler, (void *)eth_dev);
 320
 321         return 0;
 322 }
 323
 324 static struct eth_driver rte_em_pmd = {
 325         .pci_drv = {
 326                 .name = "rte_em_pmd",
 327                 .id_table = pci_id_em_map,
 328                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 329                         RTE_PCI_DRV_DETACHABLE,
 330         },
 331         .eth_dev_init = eth_em_dev_init,
 332         .eth_dev_uninit = eth_em_dev_uninit,
 333         .dev_private_size = sizeof(struct e1000_adapter),
 334 };
 335
 336 static int
 337 rte_em_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 338 {
 339         rte_eth_driver_register(&rte_em_pmd);
 340         return 0;
 341 }
 342
 343 static int
 344 em_hw_init(struct e1000_hw *hw)
 345 {
 346         int diag;
 347
 348         diag = hw->mac.ops.init_params(hw);
 349         if (diag != 0) {
 350                 PMD_INIT_LOG(ERR, "MAC Initialization Error");
 351                 return diag;
 352         }
 353         diag = hw->nvm.ops.init_params(hw);
 354         if (diag != 0) {
 355                 PMD_INIT_LOG(ERR, "NVM Initialization Error");
 356                 return diag;
 357         }
 358         diag = hw->phy.ops.init_params(hw);
 359         if (diag != 0) {
 360                 PMD_INIT_LOG(ERR, "PHY Initialization Error");
 361                 return diag;
 362         }
 363         (void) e1000_get_bus_info(hw);
 364
 365         hw->mac.autoneg = 1;
 366         hw->phy.autoneg_wait_to_complete = 0;
 367         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 368
 369         e1000_init_script_state_82541(hw, TRUE);
 370         e1000_set_tbi_compatibility_82543(hw, TRUE);
 371
 372         /* Copper options */
 373         if (hw->phy.media_type == e1000_media_type_copper) {
 374                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 375                 hw->phy.disable_polarity_correction = 0;
 376                 hw->phy.ms_type = e1000_ms_hw_default;
 377         }
 378
 379         /*
 380          * Start from a known state, this is important in reading the nvm
 381          * and mac from that.
 382          */
 383         e1000_reset_hw(hw);
 384
 385         /* Make sure we have a good EEPROM before we read from it */
 386         if (e1000_validate_nvm_checksum(hw) < 0) {
 387                 /*
 388                  * Some PCI-E parts fail the first check due to
 389                  * the link being in sleep state, call it again,
 390                  * if it fails a second time its a real issue.
 391                  */
 392                 diag = e1000_validate_nvm_checksum(hw);
 393                 if (diag < 0) {
 394                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 395                         goto error;
 396                 }
 397         }
 398
 399         /* Read the permanent MAC address out of the EEPROM */
 400         diag = e1000_read_mac_addr(hw);
 401         if (diag != 0) {
 402                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 403                 goto error;
 404         }
 405
 406         /* Now initialize the hardware */
 407         diag = em_hardware_init(hw);
 408         if (diag != 0) {
 409                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 410                 goto error;
 411         }
 412
 413         hw->mac.get_link_status = 1;
 414
 415         /* Indicate SOL/IDER usage */
 416         diag = e1000_check_reset_block(hw);
 417         if (diag < 0) {
 418                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
 419                         "SOL/IDER session");
 420         }
 421         return (0);
 422
 423 error:
 424         em_hw_control_release(hw);
 425         return (diag);
 426 }
 427
 428 static int
 429 eth_em_configure(struct rte_eth_dev *dev)
 430 {
 431         struct e1000_interrupt *intr =
 432                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 433
 434         PMD_INIT_FUNC_TRACE();
 435         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 436         PMD_INIT_FUNC_TRACE();
 437
 438         return (0);
 439 }
 440
 441 static void
 442 em_set_pba(struct e1000_hw *hw)
 443 {
 444         uint32_t pba;
 445
 446         /*
 447          * Packet Buffer Allocation (PBA)
 448          * Writing PBA sets the receive portion of the buffer
 449          * the remainder is used for the transmit buffer.
 450          * Devices before the 82547 had a Packet Buffer of 64K.
 451          * After the 82547 the buffer was reduced to 40K.
 452          */
 453         switch (hw->mac.type) {
 454                 case e1000_82547:
 455                 case e1000_82547_rev_2:
 456                 /* 82547: Total Packet Buffer is 40K */
 457                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
 458                         break;
 459                 case e1000_82571:
 460                 case e1000_82572:
 461                 case e1000_80003es2lan:
 462                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 463                         break;
 464                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
 465                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
 466                         break;
 467                 case e1000_82574:
 468                 case e1000_82583:
 469                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
 470                         break;
 471                 case e1000_ich8lan:
 472                         pba = E1000_PBA_8K;
 473                         break;
 474                 case e1000_ich9lan:
 475                 case e1000_ich10lan:
 476                         pba = E1000_PBA_10K;
 477                         break;
 478                 case e1000_pchlan:
 479                 case e1000_pch2lan:
 480                         pba = E1000_PBA_26K;
 481                         break;
 482                 default:
 483                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
 484         }
 485
 486         E1000_WRITE_REG(hw, E1000_PBA, pba);
 487 }
 488
 489 static int
 490 eth_em_start(struct rte_eth_dev *dev)
 491 {
 492         struct e1000_adapter *adapter =
 493                 E1000_DEV_PRIVATE(dev->data->dev_private);
 494         struct e1000_hw *hw =
 495                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 496         int ret, mask;
 497
 498         PMD_INIT_FUNC_TRACE();
 499
 500         eth_em_stop(dev);
 501
 502         e1000_power_up_phy(hw);
 503
 504         /* Set default PBA value */
 505         em_set_pba(hw);
 506
 507         /* Put the address into the Receive Address Array */
 508         e1000_rar_set(hw, hw->mac.addr, 0);
 509
 510         /*
 511          * With the 82571 adapter, RAR[0] may be overwritten
 512          * when the other port is reset, we make a duplicate
 513          * in RAR[14] for that eventuality, this assures
 514          * the interface continues to function.
 515          */
 516         if (hw->mac.type == e1000_82571) {
 517                 e1000_set_laa_state_82571(hw, TRUE);
 518                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
 519         }
 520
 521         /* Initialize the hardware */
 522         if (em_hardware_init(hw)) {
 523                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 524                 return (-EIO);
 525         }
 526
 527         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 528
 529         /* Configure for OS presence */
 530         em_init_manageability(hw);
 531
 532         eth_em_tx_init(dev);
 533
 534         ret = eth_em_rx_init(dev);
 535         if (ret) {
 536                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 537                 em_dev_clear_queues(dev);
 538                 return ret;
 539         }
 540
 541         e1000_clear_hw_cntrs_base_generic(hw);
 542
 543         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 544                         ETH_VLAN_EXTEND_MASK;
 545         eth_em_vlan_offload_set(dev, mask);
 546
 547         /* Set Interrupt Throttling Rate to maximum allowed value. */
 548         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
 549
 550         /* Setup link speed and duplex */
 551         switch (dev->data->dev_conf.link_speed) {
 552         case ETH_LINK_SPEED_AUTONEG:
 553                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 554                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 555                 else if (dev->data->dev_conf.link_duplex ==
 556                                         ETH_LINK_HALF_DUPLEX)
 557                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 558                 else if (dev->data->dev_conf.link_duplex ==
 559                                         ETH_LINK_FULL_DUPLEX)
 560                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 561                 else
 562                         goto error_invalid_config;
 563                 break;
 564         case ETH_LINK_SPEED_10:
 565                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 566                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 567                 else if (dev->data->dev_conf.link_duplex ==
 568                                         ETH_LINK_HALF_DUPLEX)
 569                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 570                 else if (dev->data->dev_conf.link_duplex ==
 571                                         ETH_LINK_FULL_DUPLEX)
 572                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 573                 else
 574                         goto error_invalid_config;
 575                 break;
 576         case ETH_LINK_SPEED_100:
 577                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 578                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 579                 else if (dev->data->dev_conf.link_duplex ==
 580                                         ETH_LINK_HALF_DUPLEX)
 581                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 582                 else if (dev->data->dev_conf.link_duplex ==
 583                                         ETH_LINK_FULL_DUPLEX)
 584                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 585                 else
 586                         goto error_invalid_config;
 587                 break;
 588         case ETH_LINK_SPEED_1000:
 589                 if ((dev->data->dev_conf.link_duplex ==
 590                                 ETH_LINK_AUTONEG_DUPLEX) ||
 591                         (dev->data->dev_conf.link_duplex ==
 592                                         ETH_LINK_FULL_DUPLEX))
 593                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 594                 else
 595                         goto error_invalid_config;
 596                 break;
 597         case ETH_LINK_SPEED_10000:
 598         default:
 599                 goto error_invalid_config;
 600         }
 601         e1000_setup_link(hw);
 602
 603         /* check if lsc interrupt feature is enabled */
 604         if (dev->data->dev_conf.intr_conf.lsc != 0) {
 605                 ret = eth_em_interrupt_setup(dev);
 606                 if (ret) {
 607                         PMD_INIT_LOG(ERR, "Unable to setup interrupts");
 608                         em_dev_clear_queues(dev);
 609                         return ret;
 610                 }
 611         }
 612
 613         adapter->stopped = 0;
 614
 615         PMD_INIT_LOG(DEBUG, "<<");
 616
 617         return (0);
 618
 619 error_invalid_config:
 620         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
 621                      dev->data->dev_conf.link_speed,
 622                      dev->data->dev_conf.link_duplex, dev->data->port_id);
 623         em_dev_clear_queues(dev);
 624         return (-EINVAL);
 625 }
 626
 627 /*********************************************************************
 628  *
 629  *  This routine disables all traffic on the adapter by issuing a
 630  *  global reset on the MAC.
 631  *
 632  **********************************************************************/
 633 static void
 634 eth_em_stop(struct rte_eth_dev *dev)
 635 {
 636         struct rte_eth_link link;
 637         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 638
 639         em_rxq_intr_disable(hw);
 640         em_lsc_intr_disable(hw);
 641
 642         e1000_reset_hw(hw);
 643         if (hw->mac.type >= e1000_82544)
 644                 E1000_WRITE_REG(hw, E1000_WUC, 0);
 645
 646         /* Power down the phy. Needed to make the link go down */
 647         e1000_power_down_phy(hw);
 648
 649         em_dev_clear_queues(dev);
 650
 651         /* clear the recorded link status */
 652         memset(&link, 0, sizeof(link));
 653         rte_em_dev_atomic_write_link_status(dev, &link);
 654 }
 655
 656 static void
 657 eth_em_close(struct rte_eth_dev *dev)
 658 {
 659         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 660         struct e1000_adapter *adapter =
 661                 E1000_DEV_PRIVATE(dev->data->dev_private);
 662
 663         eth_em_stop(dev);
 664         adapter->stopped = 1;
 665         em_dev_free_queues(dev);
 666         e1000_phy_hw_reset(hw);
 667         em_release_manageability(hw);
 668         em_hw_control_release(hw);
 669 }
 670
 671 static int
 672 em_get_rx_buffer_size(struct e1000_hw *hw)
 673 {
 674         uint32_t rx_buf_size;
 675
 676         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
 677         return rx_buf_size;
 678 }
 679
 680 /*********************************************************************
 681  *
 682  *  Initialize the hardware
 683  *
 684  **********************************************************************/
 685 static int
 686 em_hardware_init(struct e1000_hw *hw)
 687 {
 688         uint32_t rx_buf_size;
 689         int diag;
 690
 691         /* Issue a global reset */
 692         e1000_reset_hw(hw);
 693
 694         /* Let the firmware know the OS is in control */
 695         em_hw_control_acquire(hw);
 696
 697         /*
 698          * These parameters control the automatic generation (Tx) and
 699          * response (Rx) to Ethernet PAUSE frames.
 700          * - High water mark should allow for at least two standard size (1518)
 701          *   frames to be received after sending an XOFF.
 702          * - Low water mark works best when it is very near the high water mark.
 703          *   This allows the receiver to restart by sending XON when it has
 704          *   drained a bit. Here we use an arbitrary value of 1500 which will
 705          *   restart after one full frame is pulled from the buffer. There
 706          *   could be several smaller frames in the buffer and if so they will
 707          *   not trigger the XON until their total number reduces the buffer
 708          *   by 1500.
 709          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 710          */
 711         rx_buf_size = em_get_rx_buffer_size(hw);
 712
 713         hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
 714         hw->fc.low_water = hw->fc.high_water - 1500;
 715
 716         if (hw->mac.type == e1000_80003es2lan)
 717                 hw->fc.pause_time = UINT16_MAX;
 718         else
 719                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
 720
 721         hw->fc.send_xon = 1;
 722
 723         /* Set Flow control, use the tunable location if sane */
 724         if (em_fc_setting <= e1000_fc_full)
 725                 hw->fc.requested_mode = em_fc_setting;
 726         else
 727                 hw->fc.requested_mode = e1000_fc_none;
 728
 729         /* Workaround: no TX flow ctrl for PCH */
 730         if (hw->mac.type == e1000_pchlan)
 731                 hw->fc.requested_mode = e1000_fc_rx_pause;
 732
 733         /* Override - settings for PCH2LAN, ya its magic :) */
 734         if (hw->mac.type == e1000_pch2lan) {
 735                 hw->fc.high_water = 0x5C20;
 736                 hw->fc.low_water = 0x5048;
 737                 hw->fc.pause_time = 0x0650;
 738                 hw->fc.refresh_time = 0x0400;
 739         }
 740
 741         diag = e1000_init_hw(hw);
 742         if (diag < 0)
 743                 return (diag);
 744         e1000_check_for_link(hw);
 745         return (0);
 746 }
 747
 748 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
 749 static void
 750 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 751 {
 752         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 753         struct e1000_hw_stats *stats =
 754                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 755         int pause_frames;
 756
 757         if(hw->phy.media_type == e1000_media_type_copper ||
 758                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 759                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
 760                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 761         }
 762
 763         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 764         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 765         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 766         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 767
 768         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 769         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 770         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 771         stats->dc += E1000_READ_REG(hw, E1000_DC);
 772         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 773         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 774         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 775
 776         /*
 777          * For watchdog management we need to know if we have been
 778          * paused during the last interval, so capture that here.
 779          */
 780         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 781         stats->xoffrxc += pause_frames;
 782         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 783         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 784         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 785         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 786         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 787         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 788         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 789         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 790         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 791         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 792         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 793         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 794
 795         /*
 796          * For the 64-bit byte counters the low dword must be read first.
 797          * Both registers clear on the read of the high dword.
 798          */
 799
 800         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 801         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 802         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 803         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 804
 805         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 806         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 807         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 808         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 809         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 810
 811         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 812         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 813
 814         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 815         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 816         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 817         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 818         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 819         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 820         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 821         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 822         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 823         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 824
 825         /* Interrupt Counts */
 826
 827         if (hw->mac.type >= e1000_82571) {
 828                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
 829                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 830                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 831                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 832                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 833                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 834                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 835                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 836                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 837         }
 838
 839         if (hw->mac.type >= e1000_82543) {
 840                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 841                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 842                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 843                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 844                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 845                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 846         }
 847
 848         if (rte_stats == NULL)
 849                 return;
 850
 851         /* Rx Errors */
 852         rte_stats->ibadcrc = stats->crcerrs;
 853         rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
 854         rte_stats->imissed = stats->mpc;
 855         rte_stats->ierrors = rte_stats->ibadcrc +
 856                              rte_stats->ibadlen +
 857                              rte_stats->imissed +
 858                              stats->rxerrc + stats->algnerrc + stats->cexterr;
 859
 860         /* Tx Errors */
 861         rte_stats->oerrors = stats->ecol + stats->latecol;
 862
 863         rte_stats->ipackets = stats->gprc;
 864         rte_stats->opackets = stats->gptc;
 865         rte_stats->ibytes   = stats->gorc;
 866         rte_stats->obytes   = stats->gotc;
 867
 868         /* XON/XOFF pause frames stats registers */
 869         rte_stats->tx_pause_xon  = stats->xontxc;
 870         rte_stats->rx_pause_xon  = stats->xonrxc;
 871         rte_stats->tx_pause_xoff = stats->xofftxc;
 872         rte_stats->rx_pause_xoff = stats->xoffrxc;
 873 }
 874
 875 static void
 876 eth_em_stats_reset(struct rte_eth_dev *dev)
 877 {
 878         struct e1000_hw_stats *hw_stats =
 879                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 880
 881         /* HW registers are cleared on read */
 882         eth_em_stats_get(dev, NULL);
 883
 884         /* Reset software totals */
 885         memset(hw_stats, 0, sizeof(*hw_stats));
 886 }
 887
 888 static uint32_t
 889 em_get_max_pktlen(const struct e1000_hw *hw)
 890 {
 891         switch (hw->mac.type) {
 892         case e1000_82571:
 893         case e1000_82572:
 894         case e1000_ich9lan:
 895         case e1000_ich10lan:
 896         case e1000_pch2lan:
 897         case e1000_82574:
 898         case e1000_80003es2lan: /* 9K Jumbo Frame size */
 899         case e1000_82583:
 900                 return (0x2412);
 901         case e1000_pchlan:
 902                 return (0x1000);
 903         /* Adapters that do not support jumbo frames */
 904         case e1000_ich8lan:
 905                 return (ETHER_MAX_LEN);
 906         default:
 907                 return (MAX_JUMBO_FRAME_SIZE);
 908         }
 909 }
 910
 911 static void
 912 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 913 {
 914         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 915
 916         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
 917         dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
 918         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
 919
 920         /*
 921          * Starting with 631xESB hw supports 2 TX/RX queues per port.
 922          * Unfortunatelly, all these nics have just one TX context.
 923          * So we have few choises for TX:
 924          * - Use just one TX queue.
 925          * - Allow cksum offload only for one TX queue.
 926          * - Don't allow TX cksum offload at all.
 927          * For now, option #1 was chosen.
 928          * To use second RX queue we have to use extended RX descriptor
 929          * (Multiple Receive Queues are mutually exclusive with UDP
 930          * fragmentation and are not supported when a legacy receive
 931          * descriptor format is used).
 932          * Which means separate RX routinies - as legacy nics (82540, 82545)
 933          * don't support extended RXD.
 934          * To avoid it we support just one RX queue for now (no RSS).
 935          */
 936
 937         dev_info->max_rx_queues = 1;
 938         dev_info->max_tx_queues = 1;
 939 }
 940
 941 /* return 0 means link status changed, -1 means not changed */
 942 static int
 943 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
 944 {
 945         struct e1000_hw *hw =
 946                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 947         struct rte_eth_link link, old;
 948         int link_check, count;
 949
 950         link_check = 0;
 951         hw->mac.get_link_status = 1;
 952
 953         /* possible wait-to-complete in up to 9 seconds */
 954         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
 955                 /* Read the real link status */
 956                 switch (hw->phy.media_type) {
 957                 case e1000_media_type_copper:
 958                         /* Do the work to read phy */
 959                         e1000_check_for_link(hw);
 960                         link_check = !hw->mac.get_link_status;
 961                         break;
 962
 963                 case e1000_media_type_fiber:
 964                         e1000_check_for_link(hw);
 965                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
 966                                         E1000_STATUS_LU);
 967                         break;
 968
 969                 case e1000_media_type_internal_serdes:
 970                         e1000_check_for_link(hw);
 971                         link_check = hw->mac.serdes_has_link;
 972                         break;
 973
 974                 default:
 975                         break;
 976                 }
 977                 if (link_check || wait_to_complete == 0)
 978                         break;
 979                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
 980         }
 981         memset(&link, 0, sizeof(link));
 982         rte_em_dev_atomic_read_link_status(dev, &link);
 983         old = link;
 984
 985         /* Now we check if a transition has happened */
 986         if (link_check && (link.link_status == 0)) {
 987                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
 988                         &link.link_duplex);
 989                 link.link_status = 1;
 990         } else if (!link_check && (link.link_status == 1)) {
 991                 link.link_speed = 0;
 992                 link.link_duplex = 0;
 993                 link.link_status = 0;
 994         }
 995         rte_em_dev_atomic_write_link_status(dev, &link);
 996
 997         /* not changed */
 998         if (old.link_status == link.link_status)
 999                 return -1;
1000
1001         /* changed */
1002         return 0;
1003 }
1004
1005 /*
1006  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1007  * For ASF and Pass Through versions of f/w this means
1008  * that the driver is loaded. For AMT version type f/w
1009  * this means that the network i/f is open.
1010  */
1011 static void
1012 em_hw_control_acquire(struct e1000_hw *hw)
1013 {
1014         uint32_t ctrl_ext, swsm;
1015
1016         /* Let firmware know the driver has taken over */
1017         if (hw->mac.type == e1000_82573) {
1018                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1019                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1020
1021         } else {
1022                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1023                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1024                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1025         }
1026 }
1027
1028 /*
1029  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1030  * For ASF and Pass Through versions of f/w this means that the
1031  * driver is no longer loaded. For AMT versions of the
1032  * f/w this means that the network i/f is closed.
1033  */
1034 static void
1035 em_hw_control_release(struct e1000_hw *hw)
1036 {
1037         uint32_t ctrl_ext, swsm;
1038
1039         /* Let firmware taken over control of h/w */
1040         if (hw->mac.type == e1000_82573) {
1041                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1042                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1043         } else {
1044                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1045                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1046                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1047         }
1048 }
1049
1050 /*
1051  * Bit of a misnomer, what this really means is
1052  * to enable OS management of the system... aka
1053  * to disable special hardware management features.
1054  */
1055 static void
1056 em_init_manageability(struct e1000_hw *hw)
1057 {
1058         if (e1000_enable_mng_pass_thru(hw)) {
1059                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1060                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1061
1062                 /* disable hardware interception of ARP */
1063                 manc &= ~(E1000_MANC_ARP_EN);
1064
1065                 /* enable receiving management packets to the host */
1066                 manc |= E1000_MANC_EN_MNG2HOST;
1067                 manc2h |= 1 << 5;  /* Mng Port 623 */
1068                 manc2h |= 1 << 6;  /* Mng Port 664 */
1069                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1070                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1071         }
1072 }
1073
1074 /*
1075  * Give control back to hardware management
1076  * controller if there is one.
1077  */
1078 static void
1079 em_release_manageability(struct e1000_hw *hw)
1080 {
1081         uint32_t manc;
1082
1083         if (e1000_enable_mng_pass_thru(hw)) {
1084                 manc = E1000_READ_REG(hw, E1000_MANC);
1085
1086                 /* re-enable hardware interception of ARP */
1087                 manc |= E1000_MANC_ARP_EN;
1088                 manc &= ~E1000_MANC_EN_MNG2HOST;
1089
1090                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1091         }
1092 }
1093
1094 static void
1095 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1096 {
1097         struct e1000_hw *hw =
1098                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1099         uint32_t rctl;
1100
1101         rctl = E1000_READ_REG(hw, E1000_RCTL);
1102         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1103         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1104 }
1105
1106 static void
1107 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1108 {
1109         struct e1000_hw *hw =
1110                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1111         uint32_t rctl;
1112
1113         rctl = E1000_READ_REG(hw, E1000_RCTL);
1114         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1115         if (dev->data->all_multicast == 1)
1116                 rctl |= E1000_RCTL_MPE;
1117         else
1118                 rctl &= (~E1000_RCTL_MPE);
1119         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1120 }
1121
1122 static void
1123 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1124 {
1125         struct e1000_hw *hw =
1126                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1127         uint32_t rctl;
1128
1129         rctl = E1000_READ_REG(hw, E1000_RCTL);
1130         rctl |= E1000_RCTL_MPE;
1131         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1132 }
1133
1134 static void
1135 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1136 {
1137         struct e1000_hw *hw =
1138                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1139         uint32_t rctl;
1140
1141         if (dev->data->promiscuous == 1)
1142                 return; /* must remain in all_multicast mode */
1143         rctl = E1000_READ_REG(hw, E1000_RCTL);
1144         rctl &= (~E1000_RCTL_MPE);
1145         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1146 }
1147
1148 static int
1149 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1150 {
1151         struct e1000_hw *hw =
1152                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1153         struct e1000_vfta * shadow_vfta =
1154                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1155         uint32_t vfta;
1156         uint32_t vid_idx;
1157         uint32_t vid_bit;
1158
1159         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1160                               E1000_VFTA_ENTRY_MASK);
1161         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1162         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1163         if (on)
1164                 vfta |= vid_bit;
1165         else
1166                 vfta &= ~vid_bit;
1167         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1168
1169         /* update local VFTA copy */
1170         shadow_vfta->vfta[vid_idx] = vfta;
1171
1172         return 0;
1173 }
1174
1175 static void
1176 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1177 {
1178         struct e1000_hw *hw =
1179                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1180         uint32_t reg;
1181
1182         /* Filter Table Disable */
1183         reg = E1000_READ_REG(hw, E1000_RCTL);
1184         reg &= ~E1000_RCTL_CFIEN;
1185         reg &= ~E1000_RCTL_VFE;
1186         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1187 }
1188
1189 static void
1190 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1191 {
1192         struct e1000_hw *hw =
1193                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1194         struct e1000_vfta * shadow_vfta =
1195                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1196         uint32_t reg;
1197         int i;
1198
1199         /* Filter Table Enable, CFI not used for packet acceptance */
1200         reg = E1000_READ_REG(hw, E1000_RCTL);
1201         reg &= ~E1000_RCTL_CFIEN;
1202         reg |= E1000_RCTL_VFE;
1203         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1204
1205         /* restore vfta from local copy */
1206         for (i = 0; i < IGB_VFTA_SIZE; i++)
1207                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1208 }
1209
1210 static void
1211 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1212 {
1213         struct e1000_hw *hw =
1214                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1215         uint32_t reg;
1216
1217         /* VLAN Mode Disable */
1218         reg = E1000_READ_REG(hw, E1000_CTRL);
1219         reg &= ~E1000_CTRL_VME;
1220         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1221
1222 }
1223
1224 static void
1225 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1226 {
1227         struct e1000_hw *hw =
1228                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1229         uint32_t reg;
1230
1231         /* VLAN Mode Enable */
1232         reg = E1000_READ_REG(hw, E1000_CTRL);
1233         reg |= E1000_CTRL_VME;
1234         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1235 }
1236
1237 static void
1238 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1239 {
1240         if(mask & ETH_VLAN_STRIP_MASK){
1241                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1242                         em_vlan_hw_strip_enable(dev);
1243                 else
1244                         em_vlan_hw_strip_disable(dev);
1245         }
1246
1247         if(mask & ETH_VLAN_FILTER_MASK){
1248                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1249                         em_vlan_hw_filter_enable(dev);
1250                 else
1251                         em_vlan_hw_filter_disable(dev);
1252         }
1253 }
1254
1255 /*
1256  * It enables the interrupt mask and then enable the interrupt.
1257  *
1258  * @param dev
1259  *  Pointer to struct rte_eth_dev.
1260  *
1261  * @return
1262  *  - On success, zero.
1263  *  - On failure, a negative value.
1264  */
1265 static int
1266 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1267 {
1268         uint32_t regval;
1269         struct e1000_hw *hw =
1270                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1271
1272         /* clear interrupt */
1273         E1000_READ_REG(hw, E1000_ICR);
1274         regval = E1000_READ_REG(hw, E1000_IMS);
1275         E1000_WRITE_REG(hw, E1000_IMS, regval | E1000_ICR_LSC);
1276         return (0);
1277 }
1278
1279 /*
1280  * It disabled lsc interrupt.
1281  * @param hw
1282  * Pointer to struct e1000_hw
1283  *
1284  * @return
1285  */
1286 static void
1287 em_lsc_intr_disable(struct e1000_hw *hw)
1288 {
1289         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC);
1290         E1000_WRITE_FLUSH(hw);
1291 }
1292
1293 /*
1294  * It disabled receive packet interrupt.
1295  * @param hw
1296  * Pointer to struct e1000_hw
1297  *
1298  * @return
1299  */
1300 static void
1301 em_rxq_intr_disable(struct e1000_hw *hw)
1302 {
1303         E1000_READ_REG(hw, E1000_ICR);
1304         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1305         E1000_WRITE_FLUSH(hw);
1306 }
1307
1308 /*
1309  * It reads ICR and gets interrupt causes, check it and set a bit flag
1310  * to update link status.
1311  *
1312  * @param dev
1313  *  Pointer to struct rte_eth_dev.
1314  *
1315  * @return
1316  *  - On success, zero.
1317  *  - On failure, a negative value.
1318  */
1319 static int
1320 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1321 {
1322         uint32_t icr;
1323         struct e1000_hw *hw =
1324                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1325         struct e1000_interrupt *intr =
1326                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1327
1328         /* read-on-clear nic registers here */
1329         icr = E1000_READ_REG(hw, E1000_ICR);
1330         if (icr & E1000_ICR_LSC) {
1331                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1332         }
1333
1334         return 0;
1335 }
1336
1337 /*
1338  * It executes link_update after knowing an interrupt is prsent.
1339  *
1340  * @param dev
1341  *  Pointer to struct rte_eth_dev.
1342  *
1343  * @return
1344  *  - On success, zero.
1345  *  - On failure, a negative value.
1346  */
1347 static int
1348 eth_em_interrupt_action(struct rte_eth_dev *dev)
1349 {
1350         struct e1000_hw *hw =
1351                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1352         struct e1000_interrupt *intr =
1353                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1354         uint32_t tctl, rctl;
1355         struct rte_eth_link link;
1356         int ret;
1357
1358         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1359                 return -1;
1360
1361         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1362         rte_intr_enable(&(dev->pci_dev->intr_handle));
1363
1364         /* set get_link_status to check register later */
1365         hw->mac.get_link_status = 1;
1366         ret = eth_em_link_update(dev, 0);
1367
1368         /* check if link has changed */
1369         if (ret < 0)
1370                 return 0;
1371
1372         memset(&link, 0, sizeof(link));
1373         rte_em_dev_atomic_read_link_status(dev, &link);
1374         if (link.link_status) {
1375                 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1376                              dev->data->port_id, (unsigned)link.link_speed,
1377                              link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1378                              "full-duplex" : "half-duplex");
1379         } else {
1380                 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1381         }
1382         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1383                      dev->pci_dev->addr.domain, dev->pci_dev->addr.bus,
1384                      dev->pci_dev->addr.devid, dev->pci_dev->addr.function);
1385
1386         tctl = E1000_READ_REG(hw, E1000_TCTL);
1387         rctl = E1000_READ_REG(hw, E1000_RCTL);
1388         if (link.link_status) {
1389                 /* enable Tx/Rx */
1390                 tctl |= E1000_TCTL_EN;
1391                 rctl |= E1000_RCTL_EN;
1392         } else {
1393                 /* disable Tx/Rx */
1394                 tctl &= ~E1000_TCTL_EN;
1395                 rctl &= ~E1000_RCTL_EN;
1396         }
1397         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1398         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1399         E1000_WRITE_FLUSH(hw);
1400
1401         return 0;
1402 }
1403
1404 /**
1405  * Interrupt handler which shall be registered at first.
1406  *
1407  * @param handle
1408  *  Pointer to interrupt handle.
1409  * @param param
1410  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1411  *
1412  * @return
1413  *  void
1414  */
1415 static void
1416 eth_em_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1417                                                         void *param)
1418 {
1419         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1420
1421         eth_em_interrupt_get_status(dev);
1422         eth_em_interrupt_action(dev);
1423         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1424 }
1425
1426 static int
1427 eth_em_led_on(struct rte_eth_dev *dev)
1428 {
1429         struct e1000_hw *hw;
1430
1431         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1432         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1433 }
1434
1435 static int
1436 eth_em_led_off(struct rte_eth_dev *dev)
1437 {
1438         struct e1000_hw *hw;
1439
1440         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1441         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1442 }
1443
1444 static int
1445 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1446 {
1447         struct e1000_hw *hw;
1448         uint32_t ctrl;
1449         int tx_pause;
1450         int rx_pause;
1451
1452         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1453         fc_conf->pause_time = hw->fc.pause_time;
1454         fc_conf->high_water = hw->fc.high_water;
1455         fc_conf->low_water = hw->fc.low_water;
1456         fc_conf->send_xon = hw->fc.send_xon;
1457         fc_conf->autoneg = hw->mac.autoneg;
1458
1459         /*
1460          * Return rx_pause and tx_pause status according to actual setting of
1461          * the TFCE and RFCE bits in the CTRL register.
1462          */
1463         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1464         if (ctrl & E1000_CTRL_TFCE)
1465                 tx_pause = 1;
1466         else
1467                 tx_pause = 0;
1468
1469         if (ctrl & E1000_CTRL_RFCE)
1470                 rx_pause = 1;
1471         else
1472                 rx_pause = 0;
1473
1474         if (rx_pause && tx_pause)
1475                 fc_conf->mode = RTE_FC_FULL;
1476         else if (rx_pause)
1477                 fc_conf->mode = RTE_FC_RX_PAUSE;
1478         else if (tx_pause)
1479                 fc_conf->mode = RTE_FC_TX_PAUSE;
1480         else
1481                 fc_conf->mode = RTE_FC_NONE;
1482
1483         return 0;
1484 }
1485
1486 static int
1487 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1488 {
1489         struct e1000_hw *hw;
1490         int err;
1491         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1492                 e1000_fc_none,
1493                 e1000_fc_rx_pause,
1494                 e1000_fc_tx_pause,
1495                 e1000_fc_full
1496         };
1497         uint32_t rx_buf_size;
1498         uint32_t max_high_water;
1499         uint32_t rctl;
1500
1501         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1502         if (fc_conf->autoneg != hw->mac.autoneg)
1503                 return -ENOTSUP;
1504         rx_buf_size = em_get_rx_buffer_size(hw);
1505         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1506
1507         /* At least reserve one Ethernet frame for watermark */
1508         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1509         if ((fc_conf->high_water > max_high_water) ||
1510             (fc_conf->high_water < fc_conf->low_water)) {
1511                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1512                 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1513                 return (-EINVAL);
1514         }
1515
1516         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1517         hw->fc.pause_time     = fc_conf->pause_time;
1518         hw->fc.high_water     = fc_conf->high_water;
1519         hw->fc.low_water      = fc_conf->low_water;
1520         hw->fc.send_xon       = fc_conf->send_xon;
1521
1522         err = e1000_setup_link_generic(hw);
1523         if (err == E1000_SUCCESS) {
1524
1525                 /* check if we want to forward MAC frames - driver doesn't have native
1526                  * capability to do that, so we'll write the registers ourselves */
1527
1528                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1529
1530                 /* set or clear MFLCN.PMCF bit depending on configuration */
1531                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1532                         rctl |= E1000_RCTL_PMCF;
1533                 else
1534                         rctl &= ~E1000_RCTL_PMCF;
1535
1536                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1537                 E1000_WRITE_FLUSH(hw);
1538
1539                 return 0;
1540         }
1541
1542         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1543         return (-EIO);
1544 }
1545
1546 static void
1547 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1548                 uint32_t index, __rte_unused uint32_t pool)
1549 {
1550         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1551
1552         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1553 }
1554
1555 static void
1556 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1557 {
1558         uint8_t addr[ETHER_ADDR_LEN];
1559         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1560
1561         memset(addr, 0, sizeof(addr));
1562
1563         e1000_rar_set(hw, addr, index);
1564 }
1565
1566 static int
1567 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1568 {
1569         struct rte_eth_dev_info dev_info;
1570         struct e1000_hw *hw;
1571         uint32_t frame_size;
1572         uint32_t rctl;
1573
1574         eth_em_infos_get(dev, &dev_info);
1575         frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1576
1577         /* check that mtu is within the allowed range */
1578         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1579                 return -EINVAL;
1580
1581         /* refuse mtu that requires the support of scattered packets when this
1582          * feature has not been enabled before. */
1583         if (!dev->data->scattered_rx &&
1584             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1585                 return -EINVAL;
1586
1587         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1588         rctl = E1000_READ_REG(hw, E1000_RCTL);
1589
1590         /* switch to jumbo mode if needed */
1591         if (frame_size > ETHER_MAX_LEN) {
1592                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1593                 rctl |= E1000_RCTL_LPE;
1594         } else {
1595                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1596                 rctl &= ~E1000_RCTL_LPE;
1597         }
1598         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1599
1600         /* update max frame size */
1601         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1602         return 0;
1603 }
1604
1605 static int
1606 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1607                         struct ether_addr *mc_addr_set,
1608                         uint32_t nb_mc_addr)
1609 {
1610         struct e1000_hw *hw;
1611
1612         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1613         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1614         return 0;
1615 }
1616
1617 struct rte_driver em_pmd_drv = {
1618         .type = PMD_PDEV,
1619         .init = rte_em_pmd_init,
1620 };
1621
1622 PMD_REGISTER_DRIVER(em_pmd_drv);