drivers/net/e1000/em_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <stdarg.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_interrupts.h>
  13 #include <rte_byteorder.h>
  14 #include <rte_log.h>
  15 #include <rte_debug.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_memory.h>
  22 #include <rte_eal.h>
  23 #include <rte_malloc.h>
  24 #include <rte_dev.h>
  25
  26 #include "e1000_logs.h"
  27 #include "base/e1000_api.h"
  28 #include "e1000_ethdev.h"
  29
  30 #define EM_EIAC                 0x000DC
  31
  32 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
  33
  34
  35 static int eth_em_configure(struct rte_eth_dev *dev);
  36 static int eth_em_start(struct rte_eth_dev *dev);
  37 static void eth_em_stop(struct rte_eth_dev *dev);
  38 static void eth_em_close(struct rte_eth_dev *dev);
  39 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
  40 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
  41 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
  42 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
  43 static int eth_em_link_update(struct rte_eth_dev *dev,
  44                                 int wait_to_complete);
  45 static int eth_em_stats_get(struct rte_eth_dev *dev,
  46                                 struct rte_eth_stats *rte_stats);
  47 static void eth_em_stats_reset(struct rte_eth_dev *dev);
  48 static void eth_em_infos_get(struct rte_eth_dev *dev,
  49                                 struct rte_eth_dev_info *dev_info);
  50 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
  51                                 struct rte_eth_fc_conf *fc_conf);
  52 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
  53                                 struct rte_eth_fc_conf *fc_conf);
  54 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
  55 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
  56 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
  57 static int eth_em_interrupt_action(struct rte_eth_dev *dev,
  58                                    struct rte_intr_handle *handle);
  59 static void eth_em_interrupt_handler(void *param);
  60
  61 static int em_hw_init(struct e1000_hw *hw);
  62 static int em_hardware_init(struct e1000_hw *hw);
  63 static void em_hw_control_acquire(struct e1000_hw *hw);
  64 static void em_hw_control_release(struct e1000_hw *hw);
  65 static void em_init_manageability(struct e1000_hw *hw);
  66 static void em_release_manageability(struct e1000_hw *hw);
  67
  68 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  69
  70 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
  71                 uint16_t vlan_id, int on);
  72 static int eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  73 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
  74 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
  75 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
  76 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
  77
  78 /*
  79 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
  80                                         uint16_t vlan_id, int on);
  81 */
  82
  83 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
  84 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
  85 static void em_lsc_intr_disable(struct e1000_hw *hw);
  86 static void em_rxq_intr_enable(struct e1000_hw *hw);
  87 static void em_rxq_intr_disable(struct e1000_hw *hw);
  88
  89 static int eth_em_led_on(struct rte_eth_dev *dev);
  90 static int eth_em_led_off(struct rte_eth_dev *dev);
  91
  92 static int em_get_rx_buffer_size(struct e1000_hw *hw);
  93 static int eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
  94                           uint32_t index, uint32_t pool);
  95 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
  96
  97 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
  98                                    struct ether_addr *mc_addr_set,
  99                                    uint32_t nb_mc_addr);
 100
 101 #define EM_FC_PAUSE_TIME 0x0680
 102 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 103 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 104
 105 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
 106
 107 int e1000_logtype_init;
 108 int e1000_logtype_driver;
 109
 110 /*
 111  * The set of PCI devices this driver supports
 112  */
 113 static const struct rte_pci_id pci_id_em_map[] = {
 114         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
 115         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
 116         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
 117         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
 118         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
 119         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
 120         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
 121         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
 122         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
 123         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
 124         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
 125         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
 126         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
 127         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
 128         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
 129         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
 130         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
 131         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
 132         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
 133         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
 134         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
 135         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
 136         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
 137         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH2_LV_LM) },
 138         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
 139         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
 140         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
 141         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
 142         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
 143         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
 144         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
 145         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
 146         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM) },
 147         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V) },
 148         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM2) },
 149         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V2) },
 150         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LBG_I219_LM3) },
 151         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM4) },
 152         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V4) },
 153         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM5) },
 154         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V5) },
 155         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM6) },
 156         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V6) },
 157         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM7) },
 158         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V7) },
 159         { .vendor_id = 0, /* sentinel */ },
 160 };
 161
 162 static const struct eth_dev_ops eth_em_ops = {
 163         .dev_configure        = eth_em_configure,
 164         .dev_start            = eth_em_start,
 165         .dev_stop             = eth_em_stop,
 166         .dev_close            = eth_em_close,
 167         .promiscuous_enable   = eth_em_promiscuous_enable,
 168         .promiscuous_disable  = eth_em_promiscuous_disable,
 169         .allmulticast_enable  = eth_em_allmulticast_enable,
 170         .allmulticast_disable = eth_em_allmulticast_disable,
 171         .link_update          = eth_em_link_update,
 172         .stats_get            = eth_em_stats_get,
 173         .stats_reset          = eth_em_stats_reset,
 174         .dev_infos_get        = eth_em_infos_get,
 175         .mtu_set              = eth_em_mtu_set,
 176         .vlan_filter_set      = eth_em_vlan_filter_set,
 177         .vlan_offload_set     = eth_em_vlan_offload_set,
 178         .rx_queue_setup       = eth_em_rx_queue_setup,
 179         .rx_queue_release     = eth_em_rx_queue_release,
 180         .rx_queue_count       = eth_em_rx_queue_count,
 181         .rx_descriptor_done   = eth_em_rx_descriptor_done,
 182         .rx_descriptor_status = eth_em_rx_descriptor_status,
 183         .tx_descriptor_status = eth_em_tx_descriptor_status,
 184         .tx_queue_setup       = eth_em_tx_queue_setup,
 185         .tx_queue_release     = eth_em_tx_queue_release,
 186         .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
 187         .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
 188         .dev_led_on           = eth_em_led_on,
 189         .dev_led_off          = eth_em_led_off,
 190         .flow_ctrl_get        = eth_em_flow_ctrl_get,
 191         .flow_ctrl_set        = eth_em_flow_ctrl_set,
 192         .mac_addr_add         = eth_em_rar_set,
 193         .mac_addr_remove      = eth_em_rar_clear,
 194         .set_mc_addr_list     = eth_em_set_mc_addr_list,
 195         .rxq_info_get         = em_rxq_info_get,
 196         .txq_info_get         = em_txq_info_get,
 197 };
 198
 199
 200 /**
 201  *  eth_em_dev_is_ich8 - Check for ICH8 device
 202  *  @hw: pointer to the HW structure
 203  *
 204  *  return TRUE for ICH8, otherwise FALSE
 205  **/
 206 static bool
 207 eth_em_dev_is_ich8(struct e1000_hw *hw)
 208 {
 209         DEBUGFUNC("eth_em_dev_is_ich8");
 210
 211         switch (hw->device_id) {
 212         case E1000_DEV_ID_PCH2_LV_LM:
 213         case E1000_DEV_ID_PCH_LPT_I217_LM:
 214         case E1000_DEV_ID_PCH_LPT_I217_V:
 215         case E1000_DEV_ID_PCH_LPTLP_I218_LM:
 216         case E1000_DEV_ID_PCH_LPTLP_I218_V:
 217         case E1000_DEV_ID_PCH_I218_V2:
 218         case E1000_DEV_ID_PCH_I218_LM2:
 219         case E1000_DEV_ID_PCH_I218_V3:
 220         case E1000_DEV_ID_PCH_I218_LM3:
 221         case E1000_DEV_ID_PCH_SPT_I219_LM:
 222         case E1000_DEV_ID_PCH_SPT_I219_V:
 223         case E1000_DEV_ID_PCH_SPT_I219_LM2:
 224         case E1000_DEV_ID_PCH_SPT_I219_V2:
 225         case E1000_DEV_ID_PCH_LBG_I219_LM3:
 226         case E1000_DEV_ID_PCH_SPT_I219_LM4:
 227         case E1000_DEV_ID_PCH_SPT_I219_V4:
 228         case E1000_DEV_ID_PCH_SPT_I219_LM5:
 229         case E1000_DEV_ID_PCH_SPT_I219_V5:
 230         case E1000_DEV_ID_PCH_CNP_I219_LM6:
 231         case E1000_DEV_ID_PCH_CNP_I219_V6:
 232         case E1000_DEV_ID_PCH_CNP_I219_LM7:
 233         case E1000_DEV_ID_PCH_CNP_I219_V7:
 234                 return 1;
 235         default:
 236                 return 0;
 237         }
 238 }
 239
 240 static int
 241 eth_em_dev_init(struct rte_eth_dev *eth_dev)
 242 {
 243         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 244         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 245         struct e1000_adapter *adapter =
 246                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 247         struct e1000_hw *hw =
 248                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 249         struct e1000_vfta * shadow_vfta =
 250                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 251
 252         eth_dev->dev_ops = &eth_em_ops;
 253         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
 254         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
 255         eth_dev->tx_pkt_prepare = (eth_tx_prep_t)&eth_em_prep_pkts;
 256
 257         /* for secondary processes, we don't initialise any further as primary
 258          * has already done this work. Only check we don't need a different
 259          * RX function */
 260         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 261                 if (eth_dev->data->scattered_rx)
 262                         eth_dev->rx_pkt_burst =
 263                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
 264                 return 0;
 265         }
 266
 267         rte_eth_copy_pci_info(eth_dev, pci_dev);
 268
 269         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 270         hw->device_id = pci_dev->id.device_id;
 271         adapter->stopped = 0;
 272
 273         /* For ICH8 support we'll need to map the flash memory BAR */
 274         if (eth_em_dev_is_ich8(hw))
 275                 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
 276
 277         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
 278                         em_hw_init(hw) != 0) {
 279                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
 280                         "failed to init HW",
 281                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 282                         pci_dev->id.device_id);
 283                 return -ENODEV;
 284         }
 285
 286         /* Allocate memory for storing MAC addresses */
 287         eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
 288                         hw->mac.rar_entry_count, 0);
 289         if (eth_dev->data->mac_addrs == NULL) {
 290                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 291                         "store MAC addresses",
 292                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 293                 return -ENOMEM;
 294         }
 295
 296         /* Copy the permanent MAC address */
 297         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 298                 eth_dev->data->mac_addrs);
 299
 300         /* initialize the vfta */
 301         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 302
 303         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 304                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 305                      pci_dev->id.device_id);
 306
 307         rte_intr_callback_register(intr_handle,
 308                                    eth_em_interrupt_handler, eth_dev);
 309
 310         return 0;
 311 }
 312
 313 static int
 314 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
 315 {
 316         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 317         struct e1000_adapter *adapter =
 318                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 319         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 320
 321         PMD_INIT_FUNC_TRACE();
 322
 323         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 324                 return -EPERM;
 325
 326         if (adapter->stopped == 0)
 327                 eth_em_close(eth_dev);
 328
 329         eth_dev->dev_ops = NULL;
 330         eth_dev->rx_pkt_burst = NULL;
 331         eth_dev->tx_pkt_burst = NULL;
 332
 333         rte_free(eth_dev->data->mac_addrs);
 334         eth_dev->data->mac_addrs = NULL;
 335
 336         /* disable uio intr before callback unregister */
 337         rte_intr_disable(intr_handle);
 338         rte_intr_callback_unregister(intr_handle,
 339                                      eth_em_interrupt_handler, eth_dev);
 340
 341         return 0;
 342 }
 343
 344 static int eth_em_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 345         struct rte_pci_device *pci_dev)
 346 {
 347         return rte_eth_dev_pci_generic_probe(pci_dev,
 348                 sizeof(struct e1000_adapter), eth_em_dev_init);
 349 }
 350
 351 static int eth_em_pci_remove(struct rte_pci_device *pci_dev)
 352 {
 353         return rte_eth_dev_pci_generic_remove(pci_dev, eth_em_dev_uninit);
 354 }
 355
 356 static struct rte_pci_driver rte_em_pmd = {
 357         .id_table = pci_id_em_map,
 358         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 359                      RTE_PCI_DRV_IOVA_AS_VA,
 360         .probe = eth_em_pci_probe,
 361         .remove = eth_em_pci_remove,
 362 };
 363
 364 static int
 365 em_hw_init(struct e1000_hw *hw)
 366 {
 367         int diag;
 368
 369         diag = hw->mac.ops.init_params(hw);
 370         if (diag != 0) {
 371                 PMD_INIT_LOG(ERR, "MAC Initialization Error");
 372                 return diag;
 373         }
 374         diag = hw->nvm.ops.init_params(hw);
 375         if (diag != 0) {
 376                 PMD_INIT_LOG(ERR, "NVM Initialization Error");
 377                 return diag;
 378         }
 379         diag = hw->phy.ops.init_params(hw);
 380         if (diag != 0) {
 381                 PMD_INIT_LOG(ERR, "PHY Initialization Error");
 382                 return diag;
 383         }
 384         (void) e1000_get_bus_info(hw);
 385
 386         hw->mac.autoneg = 1;
 387         hw->phy.autoneg_wait_to_complete = 0;
 388         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 389
 390         e1000_init_script_state_82541(hw, TRUE);
 391         e1000_set_tbi_compatibility_82543(hw, TRUE);
 392
 393         /* Copper options */
 394         if (hw->phy.media_type == e1000_media_type_copper) {
 395                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 396                 hw->phy.disable_polarity_correction = 0;
 397                 hw->phy.ms_type = e1000_ms_hw_default;
 398         }
 399
 400         /*
 401          * Start from a known state, this is important in reading the nvm
 402          * and mac from that.
 403          */
 404         e1000_reset_hw(hw);
 405
 406         /* Make sure we have a good EEPROM before we read from it */
 407         if (e1000_validate_nvm_checksum(hw) < 0) {
 408                 /*
 409                  * Some PCI-E parts fail the first check due to
 410                  * the link being in sleep state, call it again,
 411                  * if it fails a second time its a real issue.
 412                  */
 413                 diag = e1000_validate_nvm_checksum(hw);
 414                 if (diag < 0) {
 415                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 416                         goto error;
 417                 }
 418         }
 419
 420         /* Read the permanent MAC address out of the EEPROM */
 421         diag = e1000_read_mac_addr(hw);
 422         if (diag != 0) {
 423                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 424                 goto error;
 425         }
 426
 427         /* Now initialize the hardware */
 428         diag = em_hardware_init(hw);
 429         if (diag != 0) {
 430                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 431                 goto error;
 432         }
 433
 434         hw->mac.get_link_status = 1;
 435
 436         /* Indicate SOL/IDER usage */
 437         diag = e1000_check_reset_block(hw);
 438         if (diag < 0) {
 439                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
 440                         "SOL/IDER session");
 441         }
 442         return 0;
 443
 444 error:
 445         em_hw_control_release(hw);
 446         return diag;
 447 }
 448
 449 static int
 450 eth_em_configure(struct rte_eth_dev *dev)
 451 {
 452         struct e1000_interrupt *intr =
 453                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 454
 455         PMD_INIT_FUNC_TRACE();
 456         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 457         PMD_INIT_FUNC_TRACE();
 458
 459         return 0;
 460 }
 461
 462 static void
 463 em_set_pba(struct e1000_hw *hw)
 464 {
 465         uint32_t pba;
 466
 467         /*
 468          * Packet Buffer Allocation (PBA)
 469          * Writing PBA sets the receive portion of the buffer
 470          * the remainder is used for the transmit buffer.
 471          * Devices before the 82547 had a Packet Buffer of 64K.
 472          * After the 82547 the buffer was reduced to 40K.
 473          */
 474         switch (hw->mac.type) {
 475                 case e1000_82547:
 476                 case e1000_82547_rev_2:
 477                 /* 82547: Total Packet Buffer is 40K */
 478                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
 479                         break;
 480                 case e1000_82571:
 481                 case e1000_82572:
 482                 case e1000_80003es2lan:
 483                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 484                         break;
 485                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
 486                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
 487                         break;
 488                 case e1000_82574:
 489                 case e1000_82583:
 490                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
 491                         break;
 492                 case e1000_ich8lan:
 493                         pba = E1000_PBA_8K;
 494                         break;
 495                 case e1000_ich9lan:
 496                 case e1000_ich10lan:
 497                         pba = E1000_PBA_10K;
 498                         break;
 499                 case e1000_pchlan:
 500                 case e1000_pch2lan:
 501                 case e1000_pch_lpt:
 502                 case e1000_pch_spt:
 503                 case e1000_pch_cnp:
 504                         pba = E1000_PBA_26K;
 505                         break;
 506                 default:
 507                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
 508         }
 509
 510         E1000_WRITE_REG(hw, E1000_PBA, pba);
 511 }
 512
 513 static void
 514 eth_em_rxtx_control(struct rte_eth_dev *dev,
 515                     bool enable)
 516 {
 517         struct e1000_hw *hw =
 518                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 519         uint32_t tctl, rctl;
 520
 521         tctl = E1000_READ_REG(hw, E1000_TCTL);
 522         rctl = E1000_READ_REG(hw, E1000_RCTL);
 523         if (enable) {
 524                 /* enable Tx/Rx */
 525                 tctl |= E1000_TCTL_EN;
 526                 rctl |= E1000_RCTL_EN;
 527         } else {
 528                 /* disable Tx/Rx */
 529                 tctl &= ~E1000_TCTL_EN;
 530                 rctl &= ~E1000_RCTL_EN;
 531         }
 532         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
 533         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
 534         E1000_WRITE_FLUSH(hw);
 535 }
 536
 537 static int
 538 eth_em_start(struct rte_eth_dev *dev)
 539 {
 540         struct e1000_adapter *adapter =
 541                 E1000_DEV_PRIVATE(dev->data->dev_private);
 542         struct e1000_hw *hw =
 543                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 544         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 545         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 546         int ret, mask;
 547         uint32_t intr_vector = 0;
 548         uint32_t *speeds;
 549         int num_speeds;
 550         bool autoneg;
 551
 552         PMD_INIT_FUNC_TRACE();
 553
 554         eth_em_stop(dev);
 555
 556         e1000_power_up_phy(hw);
 557
 558         /* Set default PBA value */
 559         em_set_pba(hw);
 560
 561         /* Put the address into the Receive Address Array */
 562         e1000_rar_set(hw, hw->mac.addr, 0);
 563
 564         /*
 565          * With the 82571 adapter, RAR[0] may be overwritten
 566          * when the other port is reset, we make a duplicate
 567          * in RAR[14] for that eventuality, this assures
 568          * the interface continues to function.
 569          */
 570         if (hw->mac.type == e1000_82571) {
 571                 e1000_set_laa_state_82571(hw, TRUE);
 572                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
 573         }
 574
 575         /* Initialize the hardware */
 576         if (em_hardware_init(hw)) {
 577                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 578                 return -EIO;
 579         }
 580
 581         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 582
 583         /* Configure for OS presence */
 584         em_init_manageability(hw);
 585
 586         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 587                 intr_vector = dev->data->nb_rx_queues;
 588                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 589                         return -1;
 590         }
 591
 592         if (rte_intr_dp_is_en(intr_handle)) {
 593                 intr_handle->intr_vec =
 594                         rte_zmalloc("intr_vec",
 595                                         dev->data->nb_rx_queues * sizeof(int), 0);
 596                 if (intr_handle->intr_vec == NULL) {
 597                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 598                                                 " intr_vec", dev->data->nb_rx_queues);
 599                         return -ENOMEM;
 600                 }
 601
 602                 /* enable rx interrupt */
 603                 em_rxq_intr_enable(hw);
 604         }
 605
 606         eth_em_tx_init(dev);
 607
 608         ret = eth_em_rx_init(dev);
 609         if (ret) {
 610                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 611                 em_dev_clear_queues(dev);
 612                 return ret;
 613         }
 614
 615         e1000_clear_hw_cntrs_base_generic(hw);
 616
 617         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 618                         ETH_VLAN_EXTEND_MASK;
 619         ret = eth_em_vlan_offload_set(dev, mask);
 620         if (ret) {
 621                 PMD_INIT_LOG(ERR, "Unable to update vlan offload");
 622                 em_dev_clear_queues(dev);
 623                 return ret;
 624         }
 625
 626         /* Set Interrupt Throttling Rate to maximum allowed value. */
 627         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
 628
 629         /* Setup link speed and duplex */
 630         speeds = &dev->data->dev_conf.link_speeds;
 631         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
 632                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 633                 hw->mac.autoneg = 1;
 634         } else {
 635                 num_speeds = 0;
 636                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
 637
 638                 /* Reset */
 639                 hw->phy.autoneg_advertised = 0;
 640
 641                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
 642                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
 643                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
 644                         num_speeds = -1;
 645                         goto error_invalid_config;
 646                 }
 647                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
 648                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
 649                         num_speeds++;
 650                 }
 651                 if (*speeds & ETH_LINK_SPEED_10M) {
 652                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
 653                         num_speeds++;
 654                 }
 655                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
 656                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
 657                         num_speeds++;
 658                 }
 659                 if (*speeds & ETH_LINK_SPEED_100M) {
 660                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
 661                         num_speeds++;
 662                 }
 663                 if (*speeds & ETH_LINK_SPEED_1G) {
 664                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
 665                         num_speeds++;
 666                 }
 667                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
 668                         goto error_invalid_config;
 669
 670                 /* Set/reset the mac.autoneg based on the link speed,
 671                  * fixed or not
 672                  */
 673                 if (!autoneg) {
 674                         hw->mac.autoneg = 0;
 675                         hw->mac.forced_speed_duplex =
 676                                         hw->phy.autoneg_advertised;
 677                 } else {
 678                         hw->mac.autoneg = 1;
 679                 }
 680         }
 681
 682         e1000_setup_link(hw);
 683
 684         if (rte_intr_allow_others(intr_handle)) {
 685                 /* check if lsc interrupt is enabled */
 686                 if (dev->data->dev_conf.intr_conf.lsc != 0) {
 687                         ret = eth_em_interrupt_setup(dev);
 688                         if (ret) {
 689                                 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
 690                                 em_dev_clear_queues(dev);
 691                                 return ret;
 692                         }
 693                 }
 694         } else {
 695                 rte_intr_callback_unregister(intr_handle,
 696                                                 eth_em_interrupt_handler,
 697                                                 (void *)dev);
 698                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 699                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
 700                                      " no intr multiplexn");
 701         }
 702         /* check if rxq interrupt is enabled */
 703         if (dev->data->dev_conf.intr_conf.rxq != 0)
 704                 eth_em_rxq_interrupt_setup(dev);
 705
 706         rte_intr_enable(intr_handle);
 707
 708         adapter->stopped = 0;
 709
 710         eth_em_rxtx_control(dev, true);
 711         eth_em_link_update(dev, 0);
 712
 713         PMD_INIT_LOG(DEBUG, "<<");
 714
 715         return 0;
 716
 717 error_invalid_config:
 718         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
 719                      dev->data->dev_conf.link_speeds, dev->data->port_id);
 720         em_dev_clear_queues(dev);
 721         return -EINVAL;
 722 }
 723
 724 /*********************************************************************
 725  *
 726  *  This routine disables all traffic on the adapter by issuing a
 727  *  global reset on the MAC.
 728  *
 729  **********************************************************************/
 730 static void
 731 eth_em_stop(struct rte_eth_dev *dev)
 732 {
 733         struct rte_eth_link link;
 734         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 735         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 736         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 737
 738         eth_em_rxtx_control(dev, false);
 739         em_rxq_intr_disable(hw);
 740         em_lsc_intr_disable(hw);
 741
 742         e1000_reset_hw(hw);
 743         if (hw->mac.type >= e1000_82544)
 744                 E1000_WRITE_REG(hw, E1000_WUC, 0);
 745
 746         /* Power down the phy. Needed to make the link go down */
 747         e1000_power_down_phy(hw);
 748
 749         em_dev_clear_queues(dev);
 750
 751         /* clear the recorded link status */
 752         memset(&link, 0, sizeof(link));
 753         rte_eth_linkstatus_set(dev, &link);
 754
 755         if (!rte_intr_allow_others(intr_handle))
 756                 /* resume to the default handler */
 757                 rte_intr_callback_register(intr_handle,
 758                                            eth_em_interrupt_handler,
 759                                            (void *)dev);
 760
 761         /* Clean datapath event and queue/vec mapping */
 762         rte_intr_efd_disable(intr_handle);
 763         if (intr_handle->intr_vec != NULL) {
 764                 rte_free(intr_handle->intr_vec);
 765                 intr_handle->intr_vec = NULL;
 766         }
 767 }
 768
 769 static void
 770 eth_em_close(struct rte_eth_dev *dev)
 771 {
 772         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 773         struct e1000_adapter *adapter =
 774                 E1000_DEV_PRIVATE(dev->data->dev_private);
 775
 776         eth_em_stop(dev);
 777         adapter->stopped = 1;
 778         em_dev_free_queues(dev);
 779         e1000_phy_hw_reset(hw);
 780         em_release_manageability(hw);
 781         em_hw_control_release(hw);
 782 }
 783
 784 static int
 785 em_get_rx_buffer_size(struct e1000_hw *hw)
 786 {
 787         uint32_t rx_buf_size;
 788
 789         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
 790         return rx_buf_size;
 791 }
 792
 793 /*********************************************************************
 794  *
 795  *  Initialize the hardware
 796  *
 797  **********************************************************************/
 798 static int
 799 em_hardware_init(struct e1000_hw *hw)
 800 {
 801         uint32_t rx_buf_size;
 802         int diag;
 803
 804         /* Issue a global reset */
 805         e1000_reset_hw(hw);
 806
 807         /* Let the firmware know the OS is in control */
 808         em_hw_control_acquire(hw);
 809
 810         /*
 811          * These parameters control the automatic generation (Tx) and
 812          * response (Rx) to Ethernet PAUSE frames.
 813          * - High water mark should allow for at least two standard size (1518)
 814          *   frames to be received after sending an XOFF.
 815          * - Low water mark works best when it is very near the high water mark.
 816          *   This allows the receiver to restart by sending XON when it has
 817          *   drained a bit. Here we use an arbitrary value of 1500 which will
 818          *   restart after one full frame is pulled from the buffer. There
 819          *   could be several smaller frames in the buffer and if so they will
 820          *   not trigger the XON until their total number reduces the buffer
 821          *   by 1500.
 822          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 823          */
 824         rx_buf_size = em_get_rx_buffer_size(hw);
 825
 826         hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
 827         hw->fc.low_water = hw->fc.high_water - 1500;
 828
 829         if (hw->mac.type == e1000_80003es2lan)
 830                 hw->fc.pause_time = UINT16_MAX;
 831         else
 832                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
 833
 834         hw->fc.send_xon = 1;
 835
 836         /* Set Flow control, use the tunable location if sane */
 837         if (em_fc_setting <= e1000_fc_full)
 838                 hw->fc.requested_mode = em_fc_setting;
 839         else
 840                 hw->fc.requested_mode = e1000_fc_none;
 841
 842         /* Workaround: no TX flow ctrl for PCH */
 843         if (hw->mac.type == e1000_pchlan)
 844                 hw->fc.requested_mode = e1000_fc_rx_pause;
 845
 846         /* Override - settings for PCH2LAN, ya its magic :) */
 847         if (hw->mac.type == e1000_pch2lan) {
 848                 hw->fc.high_water = 0x5C20;
 849                 hw->fc.low_water = 0x5048;
 850                 hw->fc.pause_time = 0x0650;
 851                 hw->fc.refresh_time = 0x0400;
 852         } else if (hw->mac.type == e1000_pch_lpt ||
 853                    hw->mac.type == e1000_pch_spt ||
 854                    hw->mac.type == e1000_pch_cnp) {
 855                 hw->fc.requested_mode = e1000_fc_full;
 856         }
 857
 858         diag = e1000_init_hw(hw);
 859         if (diag < 0)
 860                 return diag;
 861         e1000_check_for_link(hw);
 862         return 0;
 863 }
 864
 865 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
 866 static int
 867 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 868 {
 869         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 870         struct e1000_hw_stats *stats =
 871                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 872         int pause_frames;
 873
 874         if(hw->phy.media_type == e1000_media_type_copper ||
 875                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 876                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
 877                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 878         }
 879
 880         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 881         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 882         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 883         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 884
 885         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 886         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 887         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 888         stats->dc += E1000_READ_REG(hw, E1000_DC);
 889         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 890         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 891         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 892
 893         /*
 894          * For watchdog management we need to know if we have been
 895          * paused during the last interval, so capture that here.
 896          */
 897         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 898         stats->xoffrxc += pause_frames;
 899         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 900         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 901         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 902         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 903         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 904         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 905         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 906         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 907         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 908         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 909         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 910         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 911
 912         /*
 913          * For the 64-bit byte counters the low dword must be read first.
 914          * Both registers clear on the read of the high dword.
 915          */
 916
 917         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 918         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 919         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 920         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 921
 922         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 923         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 924         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 925         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 926         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 927
 928         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 929         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 930
 931         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 932         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 933         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 934         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 935         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 936         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 937         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 938         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 939         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 940         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 941
 942         /* Interrupt Counts */
 943
 944         if (hw->mac.type >= e1000_82571) {
 945                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
 946                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 947                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 948                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 949                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 950                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 951                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 952                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 953                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 954         }
 955
 956         if (hw->mac.type >= e1000_82543) {
 957                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 958                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 959                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 960                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 961                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 962                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 963         }
 964
 965         if (rte_stats == NULL)
 966                 return -EINVAL;
 967
 968         /* Rx Errors */
 969         rte_stats->imissed = stats->mpc;
 970         rte_stats->ierrors = stats->crcerrs +
 971                              stats->rlec + stats->ruc + stats->roc +
 972                              stats->rxerrc + stats->algnerrc + stats->cexterr;
 973
 974         /* Tx Errors */
 975         rte_stats->oerrors = stats->ecol + stats->latecol;
 976
 977         rte_stats->ipackets = stats->gprc;
 978         rte_stats->opackets = stats->gptc;
 979         rte_stats->ibytes   = stats->gorc;
 980         rte_stats->obytes   = stats->gotc;
 981         return 0;
 982 }
 983
 984 static void
 985 eth_em_stats_reset(struct rte_eth_dev *dev)
 986 {
 987         struct e1000_hw_stats *hw_stats =
 988                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 989
 990         /* HW registers are cleared on read */
 991         eth_em_stats_get(dev, NULL);
 992
 993         /* Reset software totals */
 994         memset(hw_stats, 0, sizeof(*hw_stats));
 995 }
 996
 997 static int
 998 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
 999 {
1000         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1001         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1002         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1003
1004         em_rxq_intr_enable(hw);
1005         rte_intr_enable(intr_handle);
1006
1007         return 0;
1008 }
1009
1010 static int
1011 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1012 {
1013         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1014
1015         em_rxq_intr_disable(hw);
1016
1017         return 0;
1018 }
1019
1020 static uint32_t
1021 em_get_max_pktlen(const struct e1000_hw *hw)
1022 {
1023         switch (hw->mac.type) {
1024         case e1000_82571:
1025         case e1000_82572:
1026         case e1000_ich9lan:
1027         case e1000_ich10lan:
1028         case e1000_pch2lan:
1029         case e1000_pch_lpt:
1030         case e1000_pch_spt:
1031         case e1000_pch_cnp:
1032         case e1000_82574:
1033         case e1000_80003es2lan: /* 9K Jumbo Frame size */
1034         case e1000_82583:
1035                 return 0x2412;
1036         case e1000_pchlan:
1037                 return 0x1000;
1038         /* Adapters that do not support jumbo frames */
1039         case e1000_ich8lan:
1040                 return ETHER_MAX_LEN;
1041         default:
1042                 return MAX_JUMBO_FRAME_SIZE;
1043         }
1044 }
1045
1046 static void
1047 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1048 {
1049         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1050
1051         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1052         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1053         dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
1054         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1055         dev_info->rx_offload_capa =
1056                 DEV_RX_OFFLOAD_VLAN_STRIP |
1057                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1058                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1059                 DEV_RX_OFFLOAD_TCP_CKSUM;
1060         dev_info->tx_offload_capa =
1061                 DEV_TX_OFFLOAD_VLAN_INSERT |
1062                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1063                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1064                 DEV_TX_OFFLOAD_TCP_CKSUM;
1065
1066         /*
1067          * Starting with 631xESB hw supports 2 TX/RX queues per port.
1068          * Unfortunatelly, all these nics have just one TX context.
1069          * So we have few choises for TX:
1070          * - Use just one TX queue.
1071          * - Allow cksum offload only for one TX queue.
1072          * - Don't allow TX cksum offload at all.
1073          * For now, option #1 was chosen.
1074          * To use second RX queue we have to use extended RX descriptor
1075          * (Multiple Receive Queues are mutually exclusive with UDP
1076          * fragmentation and are not supported when a legacy receive
1077          * descriptor format is used).
1078          * Which means separate RX routinies - as legacy nics (82540, 82545)
1079          * don't support extended RXD.
1080          * To avoid it we support just one RX queue for now (no RSS).
1081          */
1082
1083         dev_info->max_rx_queues = 1;
1084         dev_info->max_tx_queues = 1;
1085
1086         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1087                 .nb_max = E1000_MAX_RING_DESC,
1088                 .nb_min = E1000_MIN_RING_DESC,
1089                 .nb_align = EM_RXD_ALIGN,
1090         };
1091
1092         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1093                 .nb_max = E1000_MAX_RING_DESC,
1094                 .nb_min = E1000_MIN_RING_DESC,
1095                 .nb_align = EM_TXD_ALIGN,
1096                 .nb_seg_max = EM_TX_MAX_SEG,
1097                 .nb_mtu_seg_max = EM_TX_MAX_MTU_SEG,
1098         };
1099
1100         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1101                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1102                         ETH_LINK_SPEED_1G;
1103 }
1104
1105 /* return 0 means link status changed, -1 means not changed */
1106 static int
1107 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1108 {
1109         struct e1000_hw *hw =
1110                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1111         struct rte_eth_link link;
1112         int link_check, count;
1113
1114         link_check = 0;
1115         hw->mac.get_link_status = 1;
1116
1117         /* possible wait-to-complete in up to 9 seconds */
1118         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1119                 /* Read the real link status */
1120                 switch (hw->phy.media_type) {
1121                 case e1000_media_type_copper:
1122                         /* Do the work to read phy */
1123                         e1000_check_for_link(hw);
1124                         link_check = !hw->mac.get_link_status;
1125                         break;
1126
1127                 case e1000_media_type_fiber:
1128                         e1000_check_for_link(hw);
1129                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1130                                         E1000_STATUS_LU);
1131                         break;
1132
1133                 case e1000_media_type_internal_serdes:
1134                         e1000_check_for_link(hw);
1135                         link_check = hw->mac.serdes_has_link;
1136                         break;
1137
1138                 default:
1139                         break;
1140                 }
1141                 if (link_check || wait_to_complete == 0)
1142                         break;
1143                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1144         }
1145         memset(&link, 0, sizeof(link));
1146
1147         /* Now we check if a transition has happened */
1148         if (link_check && (link.link_status == ETH_LINK_DOWN)) {
1149                 uint16_t duplex, speed;
1150                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1151                 link.link_duplex = (duplex == FULL_DUPLEX) ?
1152                                 ETH_LINK_FULL_DUPLEX :
1153                                 ETH_LINK_HALF_DUPLEX;
1154                 link.link_speed = speed;
1155                 link.link_status = ETH_LINK_UP;
1156                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1157                                 ETH_LINK_SPEED_FIXED);
1158         } else if (!link_check && (link.link_status == ETH_LINK_UP)) {
1159                 link.link_speed = 0;
1160                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1161                 link.link_status = ETH_LINK_DOWN;
1162                 link.link_autoneg = ETH_LINK_FIXED;
1163         }
1164
1165         return rte_eth_linkstatus_set(dev, &link);
1166 }
1167
1168 /*
1169  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1170  * For ASF and Pass Through versions of f/w this means
1171  * that the driver is loaded. For AMT version type f/w
1172  * this means that the network i/f is open.
1173  */
1174 static void
1175 em_hw_control_acquire(struct e1000_hw *hw)
1176 {
1177         uint32_t ctrl_ext, swsm;
1178
1179         /* Let firmware know the driver has taken over */
1180         if (hw->mac.type == e1000_82573) {
1181                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1182                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1183
1184         } else {
1185                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1186                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1187                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1188         }
1189 }
1190
1191 /*
1192  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1193  * For ASF and Pass Through versions of f/w this means that the
1194  * driver is no longer loaded. For AMT versions of the
1195  * f/w this means that the network i/f is closed.
1196  */
1197 static void
1198 em_hw_control_release(struct e1000_hw *hw)
1199 {
1200         uint32_t ctrl_ext, swsm;
1201
1202         /* Let firmware taken over control of h/w */
1203         if (hw->mac.type == e1000_82573) {
1204                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1205                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1206         } else {
1207                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1208                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1209                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1210         }
1211 }
1212
1213 /*
1214  * Bit of a misnomer, what this really means is
1215  * to enable OS management of the system... aka
1216  * to disable special hardware management features.
1217  */
1218 static void
1219 em_init_manageability(struct e1000_hw *hw)
1220 {
1221         if (e1000_enable_mng_pass_thru(hw)) {
1222                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1223                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1224
1225                 /* disable hardware interception of ARP */
1226                 manc &= ~(E1000_MANC_ARP_EN);
1227
1228                 /* enable receiving management packets to the host */
1229                 manc |= E1000_MANC_EN_MNG2HOST;
1230                 manc2h |= 1 << 5;  /* Mng Port 623 */
1231                 manc2h |= 1 << 6;  /* Mng Port 664 */
1232                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1233                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1234         }
1235 }
1236
1237 /*
1238  * Give control back to hardware management
1239  * controller if there is one.
1240  */
1241 static void
1242 em_release_manageability(struct e1000_hw *hw)
1243 {
1244         uint32_t manc;
1245
1246         if (e1000_enable_mng_pass_thru(hw)) {
1247                 manc = E1000_READ_REG(hw, E1000_MANC);
1248
1249                 /* re-enable hardware interception of ARP */
1250                 manc |= E1000_MANC_ARP_EN;
1251                 manc &= ~E1000_MANC_EN_MNG2HOST;
1252
1253                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1254         }
1255 }
1256
1257 static void
1258 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1259 {
1260         struct e1000_hw *hw =
1261                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1262         uint32_t rctl;
1263
1264         rctl = E1000_READ_REG(hw, E1000_RCTL);
1265         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1266         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1267 }
1268
1269 static void
1270 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1271 {
1272         struct e1000_hw *hw =
1273                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1274         uint32_t rctl;
1275
1276         rctl = E1000_READ_REG(hw, E1000_RCTL);
1277         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1278         if (dev->data->all_multicast == 1)
1279                 rctl |= E1000_RCTL_MPE;
1280         else
1281                 rctl &= (~E1000_RCTL_MPE);
1282         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1283 }
1284
1285 static void
1286 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1287 {
1288         struct e1000_hw *hw =
1289                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1290         uint32_t rctl;
1291
1292         rctl = E1000_READ_REG(hw, E1000_RCTL);
1293         rctl |= E1000_RCTL_MPE;
1294         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1295 }
1296
1297 static void
1298 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1299 {
1300         struct e1000_hw *hw =
1301                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1302         uint32_t rctl;
1303
1304         if (dev->data->promiscuous == 1)
1305                 return; /* must remain in all_multicast mode */
1306         rctl = E1000_READ_REG(hw, E1000_RCTL);
1307         rctl &= (~E1000_RCTL_MPE);
1308         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1309 }
1310
1311 static int
1312 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1313 {
1314         struct e1000_hw *hw =
1315                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1316         struct e1000_vfta * shadow_vfta =
1317                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1318         uint32_t vfta;
1319         uint32_t vid_idx;
1320         uint32_t vid_bit;
1321
1322         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1323                               E1000_VFTA_ENTRY_MASK);
1324         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1325         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1326         if (on)
1327                 vfta |= vid_bit;
1328         else
1329                 vfta &= ~vid_bit;
1330         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1331
1332         /* update local VFTA copy */
1333         shadow_vfta->vfta[vid_idx] = vfta;
1334
1335         return 0;
1336 }
1337
1338 static void
1339 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1340 {
1341         struct e1000_hw *hw =
1342                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1343         uint32_t reg;
1344
1345         /* Filter Table Disable */
1346         reg = E1000_READ_REG(hw, E1000_RCTL);
1347         reg &= ~E1000_RCTL_CFIEN;
1348         reg &= ~E1000_RCTL_VFE;
1349         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1350 }
1351
1352 static void
1353 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1354 {
1355         struct e1000_hw *hw =
1356                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1357         struct e1000_vfta * shadow_vfta =
1358                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1359         uint32_t reg;
1360         int i;
1361
1362         /* Filter Table Enable, CFI not used for packet acceptance */
1363         reg = E1000_READ_REG(hw, E1000_RCTL);
1364         reg &= ~E1000_RCTL_CFIEN;
1365         reg |= E1000_RCTL_VFE;
1366         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1367
1368         /* restore vfta from local copy */
1369         for (i = 0; i < IGB_VFTA_SIZE; i++)
1370                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1371 }
1372
1373 static void
1374 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1375 {
1376         struct e1000_hw *hw =
1377                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1378         uint32_t reg;
1379
1380         /* VLAN Mode Disable */
1381         reg = E1000_READ_REG(hw, E1000_CTRL);
1382         reg &= ~E1000_CTRL_VME;
1383         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1384
1385 }
1386
1387 static void
1388 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1389 {
1390         struct e1000_hw *hw =
1391                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1392         uint32_t reg;
1393
1394         /* VLAN Mode Enable */
1395         reg = E1000_READ_REG(hw, E1000_CTRL);
1396         reg |= E1000_CTRL_VME;
1397         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1398 }
1399
1400 static int
1401 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1402 {
1403         if(mask & ETH_VLAN_STRIP_MASK){
1404                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1405                         em_vlan_hw_strip_enable(dev);
1406                 else
1407                         em_vlan_hw_strip_disable(dev);
1408         }
1409
1410         if(mask & ETH_VLAN_FILTER_MASK){
1411                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1412                         em_vlan_hw_filter_enable(dev);
1413                 else
1414                         em_vlan_hw_filter_disable(dev);
1415         }
1416
1417         return 0;
1418 }
1419
1420 /*
1421  * It enables the interrupt mask and then enable the interrupt.
1422  *
1423  * @param dev
1424  *  Pointer to struct rte_eth_dev.
1425  *
1426  * @return
1427  *  - On success, zero.
1428  *  - On failure, a negative value.
1429  */
1430 static int
1431 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1432 {
1433         uint32_t regval;
1434         struct e1000_hw *hw =
1435                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1436
1437         /* clear interrupt */
1438         E1000_READ_REG(hw, E1000_ICR);
1439         regval = E1000_READ_REG(hw, E1000_IMS);
1440         E1000_WRITE_REG(hw, E1000_IMS, regval | E1000_ICR_LSC);
1441         return 0;
1442 }
1443
1444 /*
1445  * It clears the interrupt causes and enables the interrupt.
1446  * It will be called once only during nic initialized.
1447  *
1448  * @param dev
1449  *  Pointer to struct rte_eth_dev.
1450  *
1451  * @return
1452  *  - On success, zero.
1453  *  - On failure, a negative value.
1454  */
1455 static int
1456 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1457 {
1458         struct e1000_hw *hw =
1459         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1460
1461         E1000_READ_REG(hw, E1000_ICR);
1462         em_rxq_intr_enable(hw);
1463         return 0;
1464 }
1465
1466 /*
1467  * It enable receive packet interrupt.
1468  * @param hw
1469  * Pointer to struct e1000_hw
1470  *
1471  * @return
1472  */
1473 static void
1474 em_rxq_intr_enable(struct e1000_hw *hw)
1475 {
1476         E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1477         E1000_WRITE_FLUSH(hw);
1478 }
1479
1480 /*
1481  * It disabled lsc interrupt.
1482  * @param hw
1483  * Pointer to struct e1000_hw
1484  *
1485  * @return
1486  */
1487 static void
1488 em_lsc_intr_disable(struct e1000_hw *hw)
1489 {
1490         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC);
1491         E1000_WRITE_FLUSH(hw);
1492 }
1493
1494 /*
1495  * It disabled receive packet interrupt.
1496  * @param hw
1497  * Pointer to struct e1000_hw
1498  *
1499  * @return
1500  */
1501 static void
1502 em_rxq_intr_disable(struct e1000_hw *hw)
1503 {
1504         E1000_READ_REG(hw, E1000_ICR);
1505         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1506         E1000_WRITE_FLUSH(hw);
1507 }
1508
1509 /*
1510  * It reads ICR and gets interrupt causes, check it and set a bit flag
1511  * to update link status.
1512  *
1513  * @param dev
1514  *  Pointer to struct rte_eth_dev.
1515  *
1516  * @return
1517  *  - On success, zero.
1518  *  - On failure, a negative value.
1519  */
1520 static int
1521 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1522 {
1523         uint32_t icr;
1524         struct e1000_hw *hw =
1525                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1526         struct e1000_interrupt *intr =
1527                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1528
1529         /* read-on-clear nic registers here */
1530         icr = E1000_READ_REG(hw, E1000_ICR);
1531         if (icr & E1000_ICR_LSC) {
1532                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1533         }
1534
1535         return 0;
1536 }
1537
1538 /*
1539  * It executes link_update after knowing an interrupt is prsent.
1540  *
1541  * @param dev
1542  *  Pointer to struct rte_eth_dev.
1543  *
1544  * @return
1545  *  - On success, zero.
1546  *  - On failure, a negative value.
1547  */
1548 static int
1549 eth_em_interrupt_action(struct rte_eth_dev *dev,
1550                         struct rte_intr_handle *intr_handle)
1551 {
1552         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1553         struct e1000_hw *hw =
1554                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1555         struct e1000_interrupt *intr =
1556                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1557         struct rte_eth_link link;
1558         int ret;
1559
1560         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1561                 return -1;
1562
1563         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1564         rte_intr_enable(intr_handle);
1565
1566         /* set get_link_status to check register later */
1567         hw->mac.get_link_status = 1;
1568         ret = eth_em_link_update(dev, 0);
1569
1570         /* check if link has changed */
1571         if (ret < 0)
1572                 return 0;
1573
1574         rte_eth_linkstatus_get(dev, &link);
1575
1576         if (link.link_status) {
1577                 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1578                              dev->data->port_id, link.link_speed,
1579                              link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1580                              "full-duplex" : "half-duplex");
1581         } else {
1582                 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1583         }
1584         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1585                      pci_dev->addr.domain, pci_dev->addr.bus,
1586                      pci_dev->addr.devid, pci_dev->addr.function);
1587
1588         return 0;
1589 }
1590
1591 /**
1592  * Interrupt handler which shall be registered at first.
1593  *
1594  * @param handle
1595  *  Pointer to interrupt handle.
1596  * @param param
1597  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1598  *
1599  * @return
1600  *  void
1601  */
1602 static void
1603 eth_em_interrupt_handler(void *param)
1604 {
1605         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1606
1607         eth_em_interrupt_get_status(dev);
1608         eth_em_interrupt_action(dev, dev->intr_handle);
1609         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1610 }
1611
1612 static int
1613 eth_em_led_on(struct rte_eth_dev *dev)
1614 {
1615         struct e1000_hw *hw;
1616
1617         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1618         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1619 }
1620
1621 static int
1622 eth_em_led_off(struct rte_eth_dev *dev)
1623 {
1624         struct e1000_hw *hw;
1625
1626         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1627         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1628 }
1629
1630 static int
1631 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1632 {
1633         struct e1000_hw *hw;
1634         uint32_t ctrl;
1635         int tx_pause;
1636         int rx_pause;
1637
1638         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1639         fc_conf->pause_time = hw->fc.pause_time;
1640         fc_conf->high_water = hw->fc.high_water;
1641         fc_conf->low_water = hw->fc.low_water;
1642         fc_conf->send_xon = hw->fc.send_xon;
1643         fc_conf->autoneg = hw->mac.autoneg;
1644
1645         /*
1646          * Return rx_pause and tx_pause status according to actual setting of
1647          * the TFCE and RFCE bits in the CTRL register.
1648          */
1649         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1650         if (ctrl & E1000_CTRL_TFCE)
1651                 tx_pause = 1;
1652         else
1653                 tx_pause = 0;
1654
1655         if (ctrl & E1000_CTRL_RFCE)
1656                 rx_pause = 1;
1657         else
1658                 rx_pause = 0;
1659
1660         if (rx_pause && tx_pause)
1661                 fc_conf->mode = RTE_FC_FULL;
1662         else if (rx_pause)
1663                 fc_conf->mode = RTE_FC_RX_PAUSE;
1664         else if (tx_pause)
1665                 fc_conf->mode = RTE_FC_TX_PAUSE;
1666         else
1667                 fc_conf->mode = RTE_FC_NONE;
1668
1669         return 0;
1670 }
1671
1672 static int
1673 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1674 {
1675         struct e1000_hw *hw;
1676         int err;
1677         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1678                 e1000_fc_none,
1679                 e1000_fc_rx_pause,
1680                 e1000_fc_tx_pause,
1681                 e1000_fc_full
1682         };
1683         uint32_t rx_buf_size;
1684         uint32_t max_high_water;
1685         uint32_t rctl;
1686
1687         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1688         if (fc_conf->autoneg != hw->mac.autoneg)
1689                 return -ENOTSUP;
1690         rx_buf_size = em_get_rx_buffer_size(hw);
1691         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1692
1693         /* At least reserve one Ethernet frame for watermark */
1694         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1695         if ((fc_conf->high_water > max_high_water) ||
1696             (fc_conf->high_water < fc_conf->low_water)) {
1697                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1698                 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1699                 return -EINVAL;
1700         }
1701
1702         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1703         hw->fc.pause_time     = fc_conf->pause_time;
1704         hw->fc.high_water     = fc_conf->high_water;
1705         hw->fc.low_water      = fc_conf->low_water;
1706         hw->fc.send_xon       = fc_conf->send_xon;
1707
1708         err = e1000_setup_link_generic(hw);
1709         if (err == E1000_SUCCESS) {
1710
1711                 /* check if we want to forward MAC frames - driver doesn't have native
1712                  * capability to do that, so we'll write the registers ourselves */
1713
1714                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1715
1716                 /* set or clear MFLCN.PMCF bit depending on configuration */
1717                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1718                         rctl |= E1000_RCTL_PMCF;
1719                 else
1720                         rctl &= ~E1000_RCTL_PMCF;
1721
1722                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1723                 E1000_WRITE_FLUSH(hw);
1724
1725                 return 0;
1726         }
1727
1728         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1729         return -EIO;
1730 }
1731
1732 static int
1733 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1734                 uint32_t index, __rte_unused uint32_t pool)
1735 {
1736         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1737
1738         return e1000_rar_set(hw, mac_addr->addr_bytes, index);
1739 }
1740
1741 static void
1742 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1743 {
1744         uint8_t addr[ETHER_ADDR_LEN];
1745         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1746
1747         memset(addr, 0, sizeof(addr));
1748
1749         e1000_rar_set(hw, addr, index);
1750 }
1751
1752 static int
1753 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1754 {
1755         struct rte_eth_dev_info dev_info;
1756         struct e1000_hw *hw;
1757         uint32_t frame_size;
1758         uint32_t rctl;
1759
1760         eth_em_infos_get(dev, &dev_info);
1761         frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1762
1763         /* check that mtu is within the allowed range */
1764         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1765                 return -EINVAL;
1766
1767         /* refuse mtu that requires the support of scattered packets when this
1768          * feature has not been enabled before. */
1769         if (!dev->data->scattered_rx &&
1770             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1771                 return -EINVAL;
1772
1773         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1774         rctl = E1000_READ_REG(hw, E1000_RCTL);
1775
1776         /* switch to jumbo mode if needed */
1777         if (frame_size > ETHER_MAX_LEN) {
1778                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1779                 rctl |= E1000_RCTL_LPE;
1780         } else {
1781                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1782                 rctl &= ~E1000_RCTL_LPE;
1783         }
1784         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1785
1786         /* update max frame size */
1787         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1788         return 0;
1789 }
1790
1791 static int
1792 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1793                         struct ether_addr *mc_addr_set,
1794                         uint32_t nb_mc_addr)
1795 {
1796         struct e1000_hw *hw;
1797
1798         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1799         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1800         return 0;
1801 }
1802
1803 RTE_PMD_REGISTER_PCI(net_e1000_em, rte_em_pmd);
1804 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_em, pci_id_em_map);
1805 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_em, "* igb_uio | uio_pci_generic | vfio-pci");
1806
1807 RTE_INIT(e1000_init_log);
1808 static void
1809 e1000_init_log(void)
1810 {
1811         e1000_logtype_init = rte_log_register("pmd.net.e1000.init");
1812         if (e1000_logtype_init >= 0)
1813                 rte_log_set_level(e1000_logtype_init, RTE_LOG_NOTICE);
1814         e1000_logtype_driver = rte_log_register("pmd.net.e1000.driver");
1815         if (e1000_logtype_driver >= 0)
1816                 rte_log_set_level(e1000_logtype_driver, RTE_LOG_NOTICE);
1817 }