drivers/net/e1000/em_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58
  59 #define EM_EIAC                 0x000DC
  60
  61 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
  62
  63
  64 static int eth_em_configure(struct rte_eth_dev *dev);
  65 static int eth_em_start(struct rte_eth_dev *dev);
  66 static void eth_em_stop(struct rte_eth_dev *dev);
  67 static void eth_em_close(struct rte_eth_dev *dev);
  68 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
  69 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
  70 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
  71 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
  72 static int eth_em_link_update(struct rte_eth_dev *dev,
  73                                 int wait_to_complete);
  74 static void eth_em_stats_get(struct rte_eth_dev *dev,
  75                                 struct rte_eth_stats *rte_stats);
  76 static void eth_em_stats_reset(struct rte_eth_dev *dev);
  77 static void eth_em_infos_get(struct rte_eth_dev *dev,
  78                                 struct rte_eth_dev_info *dev_info);
  79 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
  80                                 struct rte_eth_fc_conf *fc_conf);
  81 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
  82                                 struct rte_eth_fc_conf *fc_conf);
  83 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
  84 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
  85 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
  86 static int eth_em_interrupt_action(struct rte_eth_dev *dev,
  87                                    struct rte_intr_handle *handle);
  88 static void eth_em_interrupt_handler(struct rte_intr_handle *handle,
  89                                                         void *param);
  90
  91 static int em_hw_init(struct e1000_hw *hw);
  92 static int em_hardware_init(struct e1000_hw *hw);
  93 static void em_hw_control_acquire(struct e1000_hw *hw);
  94 static void em_hw_control_release(struct e1000_hw *hw);
  95 static void em_init_manageability(struct e1000_hw *hw);
  96 static void em_release_manageability(struct e1000_hw *hw);
  97
  98 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  99
 100 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
 101                 uint16_t vlan_id, int on);
 102 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 103 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 104 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 105 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 106 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 107
 108 /*
 109 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
 110                                         uint16_t vlan_id, int on);
 111 */
 112
 113 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
 114 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
 115 static void em_lsc_intr_disable(struct e1000_hw *hw);
 116 static void em_rxq_intr_enable(struct e1000_hw *hw);
 117 static void em_rxq_intr_disable(struct e1000_hw *hw);
 118
 119 static int eth_em_led_on(struct rte_eth_dev *dev);
 120 static int eth_em_led_off(struct rte_eth_dev *dev);
 121
 122 static int em_get_rx_buffer_size(struct e1000_hw *hw);
 123 static void eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 124                 uint32_t index, uint32_t pool);
 125 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 126
 127 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
 128                                    struct ether_addr *mc_addr_set,
 129                                    uint32_t nb_mc_addr);
 130
 131 #define EM_FC_PAUSE_TIME 0x0680
 132 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 133 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 134
 135 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
 136
 137 /*
 138  * The set of PCI devices this driver supports
 139  */
 140 static const struct rte_pci_id pci_id_em_map[] = {
 141         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
 142         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
 143         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
 144         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
 145         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
 146         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
 147         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
 148         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
 149         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
 150         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
 151         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
 152         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
 153         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
 154         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
 155         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
 156         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
 157         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
 158         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
 159         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
 160         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
 161         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
 162         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
 163         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
 164         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
 165         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
 166         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
 167         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
 168         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
 169         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
 170         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
 171         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
 172         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM) },
 173         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V) },
 174         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM2) },
 175         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V2) },
 176         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LBG_I219_LM3) },
 177         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM4) },
 178         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V4) },
 179         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM5) },
 180         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V5) },
 181         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM6) },
 182         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V6) },
 183         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM7) },
 184         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V7) },
 185         { .vendor_id = 0, /* sentinel */ },
 186 };
 187
 188 static const struct eth_dev_ops eth_em_ops = {
 189         .dev_configure        = eth_em_configure,
 190         .dev_start            = eth_em_start,
 191         .dev_stop             = eth_em_stop,
 192         .dev_close            = eth_em_close,
 193         .promiscuous_enable   = eth_em_promiscuous_enable,
 194         .promiscuous_disable  = eth_em_promiscuous_disable,
 195         .allmulticast_enable  = eth_em_allmulticast_enable,
 196         .allmulticast_disable = eth_em_allmulticast_disable,
 197         .link_update          = eth_em_link_update,
 198         .stats_get            = eth_em_stats_get,
 199         .stats_reset          = eth_em_stats_reset,
 200         .dev_infos_get        = eth_em_infos_get,
 201         .mtu_set              = eth_em_mtu_set,
 202         .vlan_filter_set      = eth_em_vlan_filter_set,
 203         .vlan_offload_set     = eth_em_vlan_offload_set,
 204         .rx_queue_setup       = eth_em_rx_queue_setup,
 205         .rx_queue_release     = eth_em_rx_queue_release,
 206         .rx_queue_count       = eth_em_rx_queue_count,
 207         .rx_descriptor_done   = eth_em_rx_descriptor_done,
 208         .rx_descriptor_status = eth_em_rx_descriptor_status,
 209         .tx_descriptor_status = eth_em_tx_descriptor_status,
 210         .tx_queue_setup       = eth_em_tx_queue_setup,
 211         .tx_queue_release     = eth_em_tx_queue_release,
 212         .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
 213         .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
 214         .dev_led_on           = eth_em_led_on,
 215         .dev_led_off          = eth_em_led_off,
 216         .flow_ctrl_get        = eth_em_flow_ctrl_get,
 217         .flow_ctrl_set        = eth_em_flow_ctrl_set,
 218         .mac_addr_add         = eth_em_rar_set,
 219         .mac_addr_remove      = eth_em_rar_clear,
 220         .set_mc_addr_list     = eth_em_set_mc_addr_list,
 221         .rxq_info_get         = em_rxq_info_get,
 222         .txq_info_get         = em_txq_info_get,
 223 };
 224
 225 /**
 226  * Atomically reads the link status information from global
 227  * structure rte_eth_dev.
 228  *
 229  * @param dev
 230  *   - Pointer to the structure rte_eth_dev to read from.
 231  *   - Pointer to the buffer to be saved with the link status.
 232  *
 233  * @return
 234  *   - On success, zero.
 235  *   - On failure, negative value.
 236  */
 237 static inline int
 238 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 239                                 struct rte_eth_link *link)
 240 {
 241         struct rte_eth_link *dst = link;
 242         struct rte_eth_link *src = &(dev->data->dev_link);
 243
 244         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 245                                         *(uint64_t *)src) == 0)
 246                 return -1;
 247
 248         return 0;
 249 }
 250
 251 /**
 252  * Atomically writes the link status information into global
 253  * structure rte_eth_dev.
 254  *
 255  * @param dev
 256  *   - Pointer to the structure rte_eth_dev to read from.
 257  *   - Pointer to the buffer to be saved with the link status.
 258  *
 259  * @return
 260  *   - On success, zero.
 261  *   - On failure, negative value.
 262  */
 263 static inline int
 264 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 265                                 struct rte_eth_link *link)
 266 {
 267         struct rte_eth_link *dst = &(dev->data->dev_link);
 268         struct rte_eth_link *src = link;
 269
 270         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 271                                         *(uint64_t *)src) == 0)
 272                 return -1;
 273
 274         return 0;
 275 }
 276
 277 /**
 278  *  eth_em_dev_is_ich8 - Check for ICH8 device
 279  *  @hw: pointer to the HW structure
 280  *
 281  *  return TRUE for ICH8, otherwise FALSE
 282  **/
 283 static bool
 284 eth_em_dev_is_ich8(struct e1000_hw *hw)
 285 {
 286         DEBUGFUNC("eth_em_dev_is_ich8");
 287
 288         switch (hw->device_id) {
 289         case E1000_DEV_ID_PCH_LPT_I217_LM:
 290         case E1000_DEV_ID_PCH_LPT_I217_V:
 291         case E1000_DEV_ID_PCH_LPTLP_I218_LM:
 292         case E1000_DEV_ID_PCH_LPTLP_I218_V:
 293         case E1000_DEV_ID_PCH_I218_V2:
 294         case E1000_DEV_ID_PCH_I218_LM2:
 295         case E1000_DEV_ID_PCH_I218_V3:
 296         case E1000_DEV_ID_PCH_I218_LM3:
 297         case E1000_DEV_ID_PCH_SPT_I219_LM:
 298         case E1000_DEV_ID_PCH_SPT_I219_V:
 299         case E1000_DEV_ID_PCH_SPT_I219_LM2:
 300         case E1000_DEV_ID_PCH_SPT_I219_V2:
 301         case E1000_DEV_ID_PCH_LBG_I219_LM3:
 302         case E1000_DEV_ID_PCH_SPT_I219_LM4:
 303         case E1000_DEV_ID_PCH_SPT_I219_V4:
 304         case E1000_DEV_ID_PCH_SPT_I219_LM5:
 305         case E1000_DEV_ID_PCH_SPT_I219_V5:
 306         case E1000_DEV_ID_PCH_CNP_I219_LM6:
 307         case E1000_DEV_ID_PCH_CNP_I219_V6:
 308         case E1000_DEV_ID_PCH_CNP_I219_LM7:
 309         case E1000_DEV_ID_PCH_CNP_I219_V7:
 310                 return 1;
 311         default:
 312                 return 0;
 313         }
 314 }
 315
 316 static int
 317 eth_em_dev_init(struct rte_eth_dev *eth_dev)
 318 {
 319         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
 320         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 321         struct e1000_adapter *adapter =
 322                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 323         struct e1000_hw *hw =
 324                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 325         struct e1000_vfta * shadow_vfta =
 326                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 327
 328         eth_dev->dev_ops = &eth_em_ops;
 329         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
 330         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
 331         eth_dev->tx_pkt_prepare = (eth_tx_prep_t)&eth_em_prep_pkts;
 332
 333         /* for secondary processes, we don't initialise any further as primary
 334          * has already done this work. Only check we don't need a different
 335          * RX function */
 336         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 337                 if (eth_dev->data->scattered_rx)
 338                         eth_dev->rx_pkt_burst =
 339                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
 340                 return 0;
 341         }
 342
 343         rte_eth_copy_pci_info(eth_dev, pci_dev);
 344         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
 345
 346         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 347         hw->device_id = pci_dev->id.device_id;
 348         adapter->stopped = 0;
 349
 350         /* For ICH8 support we'll need to map the flash memory BAR */
 351         if (eth_em_dev_is_ich8(hw))
 352                 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
 353
 354         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
 355                         em_hw_init(hw) != 0) {
 356                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
 357                         "failed to init HW",
 358                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 359                         pci_dev->id.device_id);
 360                 return -ENODEV;
 361         }
 362
 363         /* Allocate memory for storing MAC addresses */
 364         eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
 365                         hw->mac.rar_entry_count, 0);
 366         if (eth_dev->data->mac_addrs == NULL) {
 367                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 368                         "store MAC addresses",
 369                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 370                 return -ENOMEM;
 371         }
 372
 373         /* Copy the permanent MAC address */
 374         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 375                 eth_dev->data->mac_addrs);
 376
 377         /* initialize the vfta */
 378         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 379
 380         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 381                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 382                      pci_dev->id.device_id);
 383
 384         rte_intr_callback_register(intr_handle,
 385                                    eth_em_interrupt_handler, eth_dev);
 386
 387         return 0;
 388 }
 389
 390 static int
 391 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
 392 {
 393         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
 394         struct e1000_adapter *adapter =
 395                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 396         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 397
 398         PMD_INIT_FUNC_TRACE();
 399
 400         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 401                 return -EPERM;
 402
 403         if (adapter->stopped == 0)
 404                 eth_em_close(eth_dev);
 405
 406         eth_dev->dev_ops = NULL;
 407         eth_dev->rx_pkt_burst = NULL;
 408         eth_dev->tx_pkt_burst = NULL;
 409
 410         rte_free(eth_dev->data->mac_addrs);
 411         eth_dev->data->mac_addrs = NULL;
 412
 413         /* disable uio intr before callback unregister */
 414         rte_intr_disable(intr_handle);
 415         rte_intr_callback_unregister(intr_handle,
 416                                      eth_em_interrupt_handler, eth_dev);
 417
 418         return 0;
 419 }
 420
 421 static struct eth_driver rte_em_pmd = {
 422         .pci_drv = {
 423                 .id_table = pci_id_em_map,
 424                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 425                 .probe = rte_eth_dev_pci_probe,
 426                 .remove = rte_eth_dev_pci_remove,
 427         },
 428         .eth_dev_init = eth_em_dev_init,
 429         .eth_dev_uninit = eth_em_dev_uninit,
 430         .dev_private_size = sizeof(struct e1000_adapter),
 431 };
 432
 433 static int
 434 em_hw_init(struct e1000_hw *hw)
 435 {
 436         int diag;
 437
 438         diag = hw->mac.ops.init_params(hw);
 439         if (diag != 0) {
 440                 PMD_INIT_LOG(ERR, "MAC Initialization Error");
 441                 return diag;
 442         }
 443         diag = hw->nvm.ops.init_params(hw);
 444         if (diag != 0) {
 445                 PMD_INIT_LOG(ERR, "NVM Initialization Error");
 446                 return diag;
 447         }
 448         diag = hw->phy.ops.init_params(hw);
 449         if (diag != 0) {
 450                 PMD_INIT_LOG(ERR, "PHY Initialization Error");
 451                 return diag;
 452         }
 453         (void) e1000_get_bus_info(hw);
 454
 455         hw->mac.autoneg = 1;
 456         hw->phy.autoneg_wait_to_complete = 0;
 457         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 458
 459         e1000_init_script_state_82541(hw, TRUE);
 460         e1000_set_tbi_compatibility_82543(hw, TRUE);
 461
 462         /* Copper options */
 463         if (hw->phy.media_type == e1000_media_type_copper) {
 464                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 465                 hw->phy.disable_polarity_correction = 0;
 466                 hw->phy.ms_type = e1000_ms_hw_default;
 467         }
 468
 469         /*
 470          * Start from a known state, this is important in reading the nvm
 471          * and mac from that.
 472          */
 473         e1000_reset_hw(hw);
 474
 475         /* Make sure we have a good EEPROM before we read from it */
 476         if (e1000_validate_nvm_checksum(hw) < 0) {
 477                 /*
 478                  * Some PCI-E parts fail the first check due to
 479                  * the link being in sleep state, call it again,
 480                  * if it fails a second time its a real issue.
 481                  */
 482                 diag = e1000_validate_nvm_checksum(hw);
 483                 if (diag < 0) {
 484                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 485                         goto error;
 486                 }
 487         }
 488
 489         /* Read the permanent MAC address out of the EEPROM */
 490         diag = e1000_read_mac_addr(hw);
 491         if (diag != 0) {
 492                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 493                 goto error;
 494         }
 495
 496         /* Now initialize the hardware */
 497         diag = em_hardware_init(hw);
 498         if (diag != 0) {
 499                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 500                 goto error;
 501         }
 502
 503         hw->mac.get_link_status = 1;
 504
 505         /* Indicate SOL/IDER usage */
 506         diag = e1000_check_reset_block(hw);
 507         if (diag < 0) {
 508                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
 509                         "SOL/IDER session");
 510         }
 511         return 0;
 512
 513 error:
 514         em_hw_control_release(hw);
 515         return diag;
 516 }
 517
 518 static int
 519 eth_em_configure(struct rte_eth_dev *dev)
 520 {
 521         struct e1000_interrupt *intr =
 522                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 523
 524         PMD_INIT_FUNC_TRACE();
 525         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 526         PMD_INIT_FUNC_TRACE();
 527
 528         return 0;
 529 }
 530
 531 static void
 532 em_set_pba(struct e1000_hw *hw)
 533 {
 534         uint32_t pba;
 535
 536         /*
 537          * Packet Buffer Allocation (PBA)
 538          * Writing PBA sets the receive portion of the buffer
 539          * the remainder is used for the transmit buffer.
 540          * Devices before the 82547 had a Packet Buffer of 64K.
 541          * After the 82547 the buffer was reduced to 40K.
 542          */
 543         switch (hw->mac.type) {
 544                 case e1000_82547:
 545                 case e1000_82547_rev_2:
 546                 /* 82547: Total Packet Buffer is 40K */
 547                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
 548                         break;
 549                 case e1000_82571:
 550                 case e1000_82572:
 551                 case e1000_80003es2lan:
 552                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 553                         break;
 554                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
 555                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
 556                         break;
 557                 case e1000_82574:
 558                 case e1000_82583:
 559                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
 560                         break;
 561                 case e1000_ich8lan:
 562                         pba = E1000_PBA_8K;
 563                         break;
 564                 case e1000_ich9lan:
 565                 case e1000_ich10lan:
 566                         pba = E1000_PBA_10K;
 567                         break;
 568                 case e1000_pchlan:
 569                 case e1000_pch2lan:
 570                 case e1000_pch_lpt:
 571                 case e1000_pch_spt:
 572                 case e1000_pch_cnp:
 573                         pba = E1000_PBA_26K;
 574                         break;
 575                 default:
 576                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
 577         }
 578
 579         E1000_WRITE_REG(hw, E1000_PBA, pba);
 580 }
 581
 582 static int
 583 eth_em_start(struct rte_eth_dev *dev)
 584 {
 585         struct e1000_adapter *adapter =
 586                 E1000_DEV_PRIVATE(dev->data->dev_private);
 587         struct e1000_hw *hw =
 588                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 589         struct rte_pci_device *pci_dev =
 590                 E1000_DEV_TO_PCI(dev);
 591         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 592         int ret, mask;
 593         uint32_t intr_vector = 0;
 594         uint32_t *speeds;
 595         int num_speeds;
 596         bool autoneg;
 597
 598         PMD_INIT_FUNC_TRACE();
 599
 600         eth_em_stop(dev);
 601
 602         e1000_power_up_phy(hw);
 603
 604         /* Set default PBA value */
 605         em_set_pba(hw);
 606
 607         /* Put the address into the Receive Address Array */
 608         e1000_rar_set(hw, hw->mac.addr, 0);
 609
 610         /*
 611          * With the 82571 adapter, RAR[0] may be overwritten
 612          * when the other port is reset, we make a duplicate
 613          * in RAR[14] for that eventuality, this assures
 614          * the interface continues to function.
 615          */
 616         if (hw->mac.type == e1000_82571) {
 617                 e1000_set_laa_state_82571(hw, TRUE);
 618                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
 619         }
 620
 621         /* Initialize the hardware */
 622         if (em_hardware_init(hw)) {
 623                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 624                 return -EIO;
 625         }
 626
 627         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 628
 629         /* Configure for OS presence */
 630         em_init_manageability(hw);
 631
 632         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 633                 intr_vector = dev->data->nb_rx_queues;
 634                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 635                         return -1;
 636         }
 637
 638         if (rte_intr_dp_is_en(intr_handle)) {
 639                 intr_handle->intr_vec =
 640                         rte_zmalloc("intr_vec",
 641                                         dev->data->nb_rx_queues * sizeof(int), 0);
 642                 if (intr_handle->intr_vec == NULL) {
 643                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 644                                                 " intr_vec", dev->data->nb_rx_queues);
 645                         return -ENOMEM;
 646                 }
 647
 648                 /* enable rx interrupt */
 649                 em_rxq_intr_enable(hw);
 650         }
 651
 652         eth_em_tx_init(dev);
 653
 654         ret = eth_em_rx_init(dev);
 655         if (ret) {
 656                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 657                 em_dev_clear_queues(dev);
 658                 return ret;
 659         }
 660
 661         e1000_clear_hw_cntrs_base_generic(hw);
 662
 663         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 664                         ETH_VLAN_EXTEND_MASK;
 665         eth_em_vlan_offload_set(dev, mask);
 666
 667         /* Set Interrupt Throttling Rate to maximum allowed value. */
 668         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
 669
 670         /* Setup link speed and duplex */
 671         speeds = &dev->data->dev_conf.link_speeds;
 672         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
 673                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 674                 hw->mac.autoneg = 1;
 675         } else {
 676                 num_speeds = 0;
 677                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
 678
 679                 /* Reset */
 680                 hw->phy.autoneg_advertised = 0;
 681
 682                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
 683                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
 684                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
 685                         num_speeds = -1;
 686                         goto error_invalid_config;
 687                 }
 688                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
 689                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
 690                         num_speeds++;
 691                 }
 692                 if (*speeds & ETH_LINK_SPEED_10M) {
 693                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
 694                         num_speeds++;
 695                 }
 696                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
 697                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
 698                         num_speeds++;
 699                 }
 700                 if (*speeds & ETH_LINK_SPEED_100M) {
 701                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
 702                         num_speeds++;
 703                 }
 704                 if (*speeds & ETH_LINK_SPEED_1G) {
 705                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
 706                         num_speeds++;
 707                 }
 708                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
 709                         goto error_invalid_config;
 710
 711                 /* Set/reset the mac.autoneg based on the link speed,
 712                  * fixed or not
 713                  */
 714                 if (!autoneg) {
 715                         hw->mac.autoneg = 0;
 716                         hw->mac.forced_speed_duplex =
 717                                         hw->phy.autoneg_advertised;
 718                 } else {
 719                         hw->mac.autoneg = 1;
 720                 }
 721         }
 722
 723         e1000_setup_link(hw);
 724
 725         if (rte_intr_allow_others(intr_handle)) {
 726                 /* check if lsc interrupt is enabled */
 727                 if (dev->data->dev_conf.intr_conf.lsc != 0) {
 728                         ret = eth_em_interrupt_setup(dev);
 729                         if (ret) {
 730                                 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
 731                                 em_dev_clear_queues(dev);
 732                                 return ret;
 733                         }
 734                 }
 735         } else {
 736                 rte_intr_callback_unregister(intr_handle,
 737                                                 eth_em_interrupt_handler,
 738                                                 (void *)dev);
 739                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 740                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
 741                                      " no intr multiplexn");
 742         }
 743         /* check if rxq interrupt is enabled */
 744         if (dev->data->dev_conf.intr_conf.rxq != 0)
 745                 eth_em_rxq_interrupt_setup(dev);
 746
 747         rte_intr_enable(intr_handle);
 748
 749         adapter->stopped = 0;
 750
 751         PMD_INIT_LOG(DEBUG, "<<");
 752
 753         return 0;
 754
 755 error_invalid_config:
 756         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
 757                      dev->data->dev_conf.link_speeds, dev->data->port_id);
 758         em_dev_clear_queues(dev);
 759         return -EINVAL;
 760 }
 761
 762 /*********************************************************************
 763  *
 764  *  This routine disables all traffic on the adapter by issuing a
 765  *  global reset on the MAC.
 766  *
 767  **********************************************************************/
 768 static void
 769 eth_em_stop(struct rte_eth_dev *dev)
 770 {
 771         struct rte_eth_link link;
 772         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 773         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
 774         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 775
 776         em_rxq_intr_disable(hw);
 777         em_lsc_intr_disable(hw);
 778
 779         e1000_reset_hw(hw);
 780         if (hw->mac.type >= e1000_82544)
 781                 E1000_WRITE_REG(hw, E1000_WUC, 0);
 782
 783         /* Power down the phy. Needed to make the link go down */
 784         e1000_power_down_phy(hw);
 785
 786         em_dev_clear_queues(dev);
 787
 788         /* clear the recorded link status */
 789         memset(&link, 0, sizeof(link));
 790         rte_em_dev_atomic_write_link_status(dev, &link);
 791
 792         if (!rte_intr_allow_others(intr_handle))
 793                 /* resume to the default handler */
 794                 rte_intr_callback_register(intr_handle,
 795                                            eth_em_interrupt_handler,
 796                                            (void *)dev);
 797
 798         /* Clean datapath event and queue/vec mapping */
 799         rte_intr_efd_disable(intr_handle);
 800         if (intr_handle->intr_vec != NULL) {
 801                 rte_free(intr_handle->intr_vec);
 802                 intr_handle->intr_vec = NULL;
 803         }
 804 }
 805
 806 static void
 807 eth_em_close(struct rte_eth_dev *dev)
 808 {
 809         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 810         struct e1000_adapter *adapter =
 811                 E1000_DEV_PRIVATE(dev->data->dev_private);
 812
 813         eth_em_stop(dev);
 814         adapter->stopped = 1;
 815         em_dev_free_queues(dev);
 816         e1000_phy_hw_reset(hw);
 817         em_release_manageability(hw);
 818         em_hw_control_release(hw);
 819 }
 820
 821 static int
 822 em_get_rx_buffer_size(struct e1000_hw *hw)
 823 {
 824         uint32_t rx_buf_size;
 825
 826         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
 827         return rx_buf_size;
 828 }
 829
 830 /*********************************************************************
 831  *
 832  *  Initialize the hardware
 833  *
 834  **********************************************************************/
 835 static int
 836 em_hardware_init(struct e1000_hw *hw)
 837 {
 838         uint32_t rx_buf_size;
 839         int diag;
 840
 841         /* Issue a global reset */
 842         e1000_reset_hw(hw);
 843
 844         /* Let the firmware know the OS is in control */
 845         em_hw_control_acquire(hw);
 846
 847         /*
 848          * These parameters control the automatic generation (Tx) and
 849          * response (Rx) to Ethernet PAUSE frames.
 850          * - High water mark should allow for at least two standard size (1518)
 851          *   frames to be received after sending an XOFF.
 852          * - Low water mark works best when it is very near the high water mark.
 853          *   This allows the receiver to restart by sending XON when it has
 854          *   drained a bit. Here we use an arbitrary value of 1500 which will
 855          *   restart after one full frame is pulled from the buffer. There
 856          *   could be several smaller frames in the buffer and if so they will
 857          *   not trigger the XON until their total number reduces the buffer
 858          *   by 1500.
 859          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 860          */
 861         rx_buf_size = em_get_rx_buffer_size(hw);
 862
 863         hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
 864         hw->fc.low_water = hw->fc.high_water - 1500;
 865
 866         if (hw->mac.type == e1000_80003es2lan)
 867                 hw->fc.pause_time = UINT16_MAX;
 868         else
 869                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
 870
 871         hw->fc.send_xon = 1;
 872
 873         /* Set Flow control, use the tunable location if sane */
 874         if (em_fc_setting <= e1000_fc_full)
 875                 hw->fc.requested_mode = em_fc_setting;
 876         else
 877                 hw->fc.requested_mode = e1000_fc_none;
 878
 879         /* Workaround: no TX flow ctrl for PCH */
 880         if (hw->mac.type == e1000_pchlan)
 881                 hw->fc.requested_mode = e1000_fc_rx_pause;
 882
 883         /* Override - settings for PCH2LAN, ya its magic :) */
 884         if (hw->mac.type == e1000_pch2lan) {
 885                 hw->fc.high_water = 0x5C20;
 886                 hw->fc.low_water = 0x5048;
 887                 hw->fc.pause_time = 0x0650;
 888                 hw->fc.refresh_time = 0x0400;
 889         } else if (hw->mac.type == e1000_pch_lpt ||
 890                    hw->mac.type == e1000_pch_spt ||
 891                    hw->mac.type == e1000_pch_cnp) {
 892                 hw->fc.requested_mode = e1000_fc_full;
 893         }
 894
 895         diag = e1000_init_hw(hw);
 896         if (diag < 0)
 897                 return diag;
 898         e1000_check_for_link(hw);
 899         return 0;
 900 }
 901
 902 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
 903 static void
 904 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 905 {
 906         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 907         struct e1000_hw_stats *stats =
 908                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 909         int pause_frames;
 910
 911         if(hw->phy.media_type == e1000_media_type_copper ||
 912                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 913                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
 914                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 915         }
 916
 917         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 918         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 919         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 920         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 921
 922         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 923         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 924         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 925         stats->dc += E1000_READ_REG(hw, E1000_DC);
 926         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 927         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 928         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 929
 930         /*
 931          * For watchdog management we need to know if we have been
 932          * paused during the last interval, so capture that here.
 933          */
 934         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 935         stats->xoffrxc += pause_frames;
 936         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 937         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 938         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 939         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 940         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 941         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 942         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 943         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 944         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 945         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 946         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 947         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 948
 949         /*
 950          * For the 64-bit byte counters the low dword must be read first.
 951          * Both registers clear on the read of the high dword.
 952          */
 953
 954         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 955         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 956         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 957         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 958
 959         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 960         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 961         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 962         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 963         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 964
 965         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 966         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 967
 968         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 969         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 970         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 971         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 972         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 973         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 974         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 975         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 976         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 977         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 978
 979         /* Interrupt Counts */
 980
 981         if (hw->mac.type >= e1000_82571) {
 982                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
 983                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 984                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 985                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 986                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 987                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 988                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 989                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 990                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 991         }
 992
 993         if (hw->mac.type >= e1000_82543) {
 994                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 995                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 996                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 997                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 998                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 999                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1000         }
1001
1002         if (rte_stats == NULL)
1003                 return;
1004
1005         /* Rx Errors */
1006         rte_stats->imissed = stats->mpc;
1007         rte_stats->ierrors = stats->crcerrs +
1008                              stats->rlec + stats->ruc + stats->roc +
1009                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1010
1011         /* Tx Errors */
1012         rte_stats->oerrors = stats->ecol + stats->latecol;
1013
1014         rte_stats->ipackets = stats->gprc;
1015         rte_stats->opackets = stats->gptc;
1016         rte_stats->ibytes   = stats->gorc;
1017         rte_stats->obytes   = stats->gotc;
1018 }
1019
1020 static void
1021 eth_em_stats_reset(struct rte_eth_dev *dev)
1022 {
1023         struct e1000_hw_stats *hw_stats =
1024                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1025
1026         /* HW registers are cleared on read */
1027         eth_em_stats_get(dev, NULL);
1028
1029         /* Reset software totals */
1030         memset(hw_stats, 0, sizeof(*hw_stats));
1031 }
1032
1033 static int
1034 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1035 {
1036         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1037         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1038         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1039
1040         em_rxq_intr_enable(hw);
1041         rte_intr_enable(intr_handle);
1042
1043         return 0;
1044 }
1045
1046 static int
1047 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1048 {
1049         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1050
1051         em_rxq_intr_disable(hw);
1052
1053         return 0;
1054 }
1055
1056 static uint32_t
1057 em_get_max_pktlen(const struct e1000_hw *hw)
1058 {
1059         switch (hw->mac.type) {
1060         case e1000_82571:
1061         case e1000_82572:
1062         case e1000_ich9lan:
1063         case e1000_ich10lan:
1064         case e1000_pch2lan:
1065         case e1000_pch_lpt:
1066         case e1000_pch_spt:
1067         case e1000_pch_cnp:
1068         case e1000_82574:
1069         case e1000_80003es2lan: /* 9K Jumbo Frame size */
1070         case e1000_82583:
1071                 return 0x2412;
1072         case e1000_pchlan:
1073                 return 0x1000;
1074         /* Adapters that do not support jumbo frames */
1075         case e1000_ich8lan:
1076                 return ETHER_MAX_LEN;
1077         default:
1078                 return MAX_JUMBO_FRAME_SIZE;
1079         }
1080 }
1081
1082 static void
1083 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1084 {
1085         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1086
1087         dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
1088         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1089         dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
1090         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1091
1092         /*
1093          * Starting with 631xESB hw supports 2 TX/RX queues per port.
1094          * Unfortunatelly, all these nics have just one TX context.
1095          * So we have few choises for TX:
1096          * - Use just one TX queue.
1097          * - Allow cksum offload only for one TX queue.
1098          * - Don't allow TX cksum offload at all.
1099          * For now, option #1 was chosen.
1100          * To use second RX queue we have to use extended RX descriptor
1101          * (Multiple Receive Queues are mutually exclusive with UDP
1102          * fragmentation and are not supported when a legacy receive
1103          * descriptor format is used).
1104          * Which means separate RX routinies - as legacy nics (82540, 82545)
1105          * don't support extended RXD.
1106          * To avoid it we support just one RX queue for now (no RSS).
1107          */
1108
1109         dev_info->max_rx_queues = 1;
1110         dev_info->max_tx_queues = 1;
1111
1112         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1113                 .nb_max = E1000_MAX_RING_DESC,
1114                 .nb_min = E1000_MIN_RING_DESC,
1115                 .nb_align = EM_RXD_ALIGN,
1116         };
1117
1118         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1119                 .nb_max = E1000_MAX_RING_DESC,
1120                 .nb_min = E1000_MIN_RING_DESC,
1121                 .nb_align = EM_TXD_ALIGN,
1122                 .nb_seg_max = EM_TX_MAX_SEG,
1123                 .nb_mtu_seg_max = EM_TX_MAX_MTU_SEG,
1124         };
1125
1126         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1127                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1128                         ETH_LINK_SPEED_1G;
1129 }
1130
1131 /* return 0 means link status changed, -1 means not changed */
1132 static int
1133 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1134 {
1135         struct e1000_hw *hw =
1136                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1137         struct rte_eth_link link, old;
1138         int link_check, count;
1139
1140         link_check = 0;
1141         hw->mac.get_link_status = 1;
1142
1143         /* possible wait-to-complete in up to 9 seconds */
1144         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1145                 /* Read the real link status */
1146                 switch (hw->phy.media_type) {
1147                 case e1000_media_type_copper:
1148                         /* Do the work to read phy */
1149                         e1000_check_for_link(hw);
1150                         link_check = !hw->mac.get_link_status;
1151                         break;
1152
1153                 case e1000_media_type_fiber:
1154                         e1000_check_for_link(hw);
1155                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1156                                         E1000_STATUS_LU);
1157                         break;
1158
1159                 case e1000_media_type_internal_serdes:
1160                         e1000_check_for_link(hw);
1161                         link_check = hw->mac.serdes_has_link;
1162                         break;
1163
1164                 default:
1165                         break;
1166                 }
1167                 if (link_check || wait_to_complete == 0)
1168                         break;
1169                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1170         }
1171         memset(&link, 0, sizeof(link));
1172         rte_em_dev_atomic_read_link_status(dev, &link);
1173         old = link;
1174
1175         /* Now we check if a transition has happened */
1176         if (link_check && (link.link_status == ETH_LINK_DOWN)) {
1177                 uint16_t duplex, speed;
1178                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1179                 link.link_duplex = (duplex == FULL_DUPLEX) ?
1180                                 ETH_LINK_FULL_DUPLEX :
1181                                 ETH_LINK_HALF_DUPLEX;
1182                 link.link_speed = speed;
1183                 link.link_status = ETH_LINK_UP;
1184                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1185                                 ETH_LINK_SPEED_FIXED);
1186         } else if (!link_check && (link.link_status == ETH_LINK_UP)) {
1187                 link.link_speed = 0;
1188                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1189                 link.link_status = ETH_LINK_DOWN;
1190                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
1191         }
1192         rte_em_dev_atomic_write_link_status(dev, &link);
1193
1194         /* not changed */
1195         if (old.link_status == link.link_status)
1196                 return -1;
1197
1198         /* changed */
1199         return 0;
1200 }
1201
1202 /*
1203  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1204  * For ASF and Pass Through versions of f/w this means
1205  * that the driver is loaded. For AMT version type f/w
1206  * this means that the network i/f is open.
1207  */
1208 static void
1209 em_hw_control_acquire(struct e1000_hw *hw)
1210 {
1211         uint32_t ctrl_ext, swsm;
1212
1213         /* Let firmware know the driver has taken over */
1214         if (hw->mac.type == e1000_82573) {
1215                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1216                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1217
1218         } else {
1219                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1220                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1221                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1222         }
1223 }
1224
1225 /*
1226  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1227  * For ASF and Pass Through versions of f/w this means that the
1228  * driver is no longer loaded. For AMT versions of the
1229  * f/w this means that the network i/f is closed.
1230  */
1231 static void
1232 em_hw_control_release(struct e1000_hw *hw)
1233 {
1234         uint32_t ctrl_ext, swsm;
1235
1236         /* Let firmware taken over control of h/w */
1237         if (hw->mac.type == e1000_82573) {
1238                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1239                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1240         } else {
1241                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1242                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1243                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1244         }
1245 }
1246
1247 /*
1248  * Bit of a misnomer, what this really means is
1249  * to enable OS management of the system... aka
1250  * to disable special hardware management features.
1251  */
1252 static void
1253 em_init_manageability(struct e1000_hw *hw)
1254 {
1255         if (e1000_enable_mng_pass_thru(hw)) {
1256                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1257                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1258
1259                 /* disable hardware interception of ARP */
1260                 manc &= ~(E1000_MANC_ARP_EN);
1261
1262                 /* enable receiving management packets to the host */
1263                 manc |= E1000_MANC_EN_MNG2HOST;
1264                 manc2h |= 1 << 5;  /* Mng Port 623 */
1265                 manc2h |= 1 << 6;  /* Mng Port 664 */
1266                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1267                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1268         }
1269 }
1270
1271 /*
1272  * Give control back to hardware management
1273  * controller if there is one.
1274  */
1275 static void
1276 em_release_manageability(struct e1000_hw *hw)
1277 {
1278         uint32_t manc;
1279
1280         if (e1000_enable_mng_pass_thru(hw)) {
1281                 manc = E1000_READ_REG(hw, E1000_MANC);
1282
1283                 /* re-enable hardware interception of ARP */
1284                 manc |= E1000_MANC_ARP_EN;
1285                 manc &= ~E1000_MANC_EN_MNG2HOST;
1286
1287                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1288         }
1289 }
1290
1291 static void
1292 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1293 {
1294         struct e1000_hw *hw =
1295                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1296         uint32_t rctl;
1297
1298         rctl = E1000_READ_REG(hw, E1000_RCTL);
1299         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1300         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1301 }
1302
1303 static void
1304 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1305 {
1306         struct e1000_hw *hw =
1307                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1308         uint32_t rctl;
1309
1310         rctl = E1000_READ_REG(hw, E1000_RCTL);
1311         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1312         if (dev->data->all_multicast == 1)
1313                 rctl |= E1000_RCTL_MPE;
1314         else
1315                 rctl &= (~E1000_RCTL_MPE);
1316         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1317 }
1318
1319 static void
1320 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1321 {
1322         struct e1000_hw *hw =
1323                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1324         uint32_t rctl;
1325
1326         rctl = E1000_READ_REG(hw, E1000_RCTL);
1327         rctl |= E1000_RCTL_MPE;
1328         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1329 }
1330
1331 static void
1332 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1333 {
1334         struct e1000_hw *hw =
1335                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1336         uint32_t rctl;
1337
1338         if (dev->data->promiscuous == 1)
1339                 return; /* must remain in all_multicast mode */
1340         rctl = E1000_READ_REG(hw, E1000_RCTL);
1341         rctl &= (~E1000_RCTL_MPE);
1342         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1343 }
1344
1345 static int
1346 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1347 {
1348         struct e1000_hw *hw =
1349                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1350         struct e1000_vfta * shadow_vfta =
1351                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1352         uint32_t vfta;
1353         uint32_t vid_idx;
1354         uint32_t vid_bit;
1355
1356         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1357                               E1000_VFTA_ENTRY_MASK);
1358         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1359         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1360         if (on)
1361                 vfta |= vid_bit;
1362         else
1363                 vfta &= ~vid_bit;
1364         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1365
1366         /* update local VFTA copy */
1367         shadow_vfta->vfta[vid_idx] = vfta;
1368
1369         return 0;
1370 }
1371
1372 static void
1373 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1374 {
1375         struct e1000_hw *hw =
1376                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1377         uint32_t reg;
1378
1379         /* Filter Table Disable */
1380         reg = E1000_READ_REG(hw, E1000_RCTL);
1381         reg &= ~E1000_RCTL_CFIEN;
1382         reg &= ~E1000_RCTL_VFE;
1383         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1384 }
1385
1386 static void
1387 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1388 {
1389         struct e1000_hw *hw =
1390                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1391         struct e1000_vfta * shadow_vfta =
1392                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1393         uint32_t reg;
1394         int i;
1395
1396         /* Filter Table Enable, CFI not used for packet acceptance */
1397         reg = E1000_READ_REG(hw, E1000_RCTL);
1398         reg &= ~E1000_RCTL_CFIEN;
1399         reg |= E1000_RCTL_VFE;
1400         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1401
1402         /* restore vfta from local copy */
1403         for (i = 0; i < IGB_VFTA_SIZE; i++)
1404                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1405 }
1406
1407 static void
1408 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1409 {
1410         struct e1000_hw *hw =
1411                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1412         uint32_t reg;
1413
1414         /* VLAN Mode Disable */
1415         reg = E1000_READ_REG(hw, E1000_CTRL);
1416         reg &= ~E1000_CTRL_VME;
1417         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1418
1419 }
1420
1421 static void
1422 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1423 {
1424         struct e1000_hw *hw =
1425                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1426         uint32_t reg;
1427
1428         /* VLAN Mode Enable */
1429         reg = E1000_READ_REG(hw, E1000_CTRL);
1430         reg |= E1000_CTRL_VME;
1431         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1432 }
1433
1434 static void
1435 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1436 {
1437         if(mask & ETH_VLAN_STRIP_MASK){
1438                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1439                         em_vlan_hw_strip_enable(dev);
1440                 else
1441                         em_vlan_hw_strip_disable(dev);
1442         }
1443
1444         if(mask & ETH_VLAN_FILTER_MASK){
1445                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1446                         em_vlan_hw_filter_enable(dev);
1447                 else
1448                         em_vlan_hw_filter_disable(dev);
1449         }
1450 }
1451
1452 /*
1453  * It enables the interrupt mask and then enable the interrupt.
1454  *
1455  * @param dev
1456  *  Pointer to struct rte_eth_dev.
1457  *
1458  * @return
1459  *  - On success, zero.
1460  *  - On failure, a negative value.
1461  */
1462 static int
1463 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1464 {
1465         uint32_t regval;
1466         struct e1000_hw *hw =
1467                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1468
1469         /* clear interrupt */
1470         E1000_READ_REG(hw, E1000_ICR);
1471         regval = E1000_READ_REG(hw, E1000_IMS);
1472         E1000_WRITE_REG(hw, E1000_IMS, regval | E1000_ICR_LSC);
1473         return 0;
1474 }
1475
1476 /*
1477  * It clears the interrupt causes and enables the interrupt.
1478  * It will be called once only during nic initialized.
1479  *
1480  * @param dev
1481  *  Pointer to struct rte_eth_dev.
1482  *
1483  * @return
1484  *  - On success, zero.
1485  *  - On failure, a negative value.
1486  */
1487 static int
1488 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1489 {
1490         struct e1000_hw *hw =
1491         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1492
1493         E1000_READ_REG(hw, E1000_ICR);
1494         em_rxq_intr_enable(hw);
1495         return 0;
1496 }
1497
1498 /*
1499  * It enable receive packet interrupt.
1500  * @param hw
1501  * Pointer to struct e1000_hw
1502  *
1503  * @return
1504  */
1505 static void
1506 em_rxq_intr_enable(struct e1000_hw *hw)
1507 {
1508         E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1509         E1000_WRITE_FLUSH(hw);
1510 }
1511
1512 /*
1513  * It disabled lsc interrupt.
1514  * @param hw
1515  * Pointer to struct e1000_hw
1516  *
1517  * @return
1518  */
1519 static void
1520 em_lsc_intr_disable(struct e1000_hw *hw)
1521 {
1522         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC);
1523         E1000_WRITE_FLUSH(hw);
1524 }
1525
1526 /*
1527  * It disabled receive packet interrupt.
1528  * @param hw
1529  * Pointer to struct e1000_hw
1530  *
1531  * @return
1532  */
1533 static void
1534 em_rxq_intr_disable(struct e1000_hw *hw)
1535 {
1536         E1000_READ_REG(hw, E1000_ICR);
1537         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1538         E1000_WRITE_FLUSH(hw);
1539 }
1540
1541 /*
1542  * It reads ICR and gets interrupt causes, check it and set a bit flag
1543  * to update link status.
1544  *
1545  * @param dev
1546  *  Pointer to struct rte_eth_dev.
1547  *
1548  * @return
1549  *  - On success, zero.
1550  *  - On failure, a negative value.
1551  */
1552 static int
1553 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1554 {
1555         uint32_t icr;
1556         struct e1000_hw *hw =
1557                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1558         struct e1000_interrupt *intr =
1559                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1560
1561         /* read-on-clear nic registers here */
1562         icr = E1000_READ_REG(hw, E1000_ICR);
1563         if (icr & E1000_ICR_LSC) {
1564                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1565         }
1566
1567         return 0;
1568 }
1569
1570 /*
1571  * It executes link_update after knowing an interrupt is prsent.
1572  *
1573  * @param dev
1574  *  Pointer to struct rte_eth_dev.
1575  *
1576  * @return
1577  *  - On success, zero.
1578  *  - On failure, a negative value.
1579  */
1580 static int
1581 eth_em_interrupt_action(struct rte_eth_dev *dev,
1582                         struct rte_intr_handle *intr_handle)
1583 {
1584         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1585         struct e1000_hw *hw =
1586                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1587         struct e1000_interrupt *intr =
1588                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1589         uint32_t tctl, rctl;
1590         struct rte_eth_link link;
1591         int ret;
1592
1593         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1594                 return -1;
1595
1596         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1597         rte_intr_enable(intr_handle);
1598
1599         /* set get_link_status to check register later */
1600         hw->mac.get_link_status = 1;
1601         ret = eth_em_link_update(dev, 0);
1602
1603         /* check if link has changed */
1604         if (ret < 0)
1605                 return 0;
1606
1607         memset(&link, 0, sizeof(link));
1608         rte_em_dev_atomic_read_link_status(dev, &link);
1609         if (link.link_status) {
1610                 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1611                              dev->data->port_id, (unsigned)link.link_speed,
1612                              link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1613                              "full-duplex" : "half-duplex");
1614         } else {
1615                 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1616         }
1617         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1618                      pci_dev->addr.domain, pci_dev->addr.bus,
1619                      pci_dev->addr.devid, pci_dev->addr.function);
1620
1621         tctl = E1000_READ_REG(hw, E1000_TCTL);
1622         rctl = E1000_READ_REG(hw, E1000_RCTL);
1623         if (link.link_status) {
1624                 /* enable Tx/Rx */
1625                 tctl |= E1000_TCTL_EN;
1626                 rctl |= E1000_RCTL_EN;
1627         } else {
1628                 /* disable Tx/Rx */
1629                 tctl &= ~E1000_TCTL_EN;
1630                 rctl &= ~E1000_RCTL_EN;
1631         }
1632         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1633         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1634         E1000_WRITE_FLUSH(hw);
1635
1636         return 0;
1637 }
1638
1639 /**
1640  * Interrupt handler which shall be registered at first.
1641  *
1642  * @param handle
1643  *  Pointer to interrupt handle.
1644  * @param param
1645  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1646  *
1647  * @return
1648  *  void
1649  */
1650 static void
1651 eth_em_interrupt_handler(struct rte_intr_handle *handle,
1652                          void *param)
1653 {
1654         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1655
1656         eth_em_interrupt_get_status(dev);
1657         eth_em_interrupt_action(dev, handle);
1658         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1659 }
1660
1661 static int
1662 eth_em_led_on(struct rte_eth_dev *dev)
1663 {
1664         struct e1000_hw *hw;
1665
1666         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1667         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1668 }
1669
1670 static int
1671 eth_em_led_off(struct rte_eth_dev *dev)
1672 {
1673         struct e1000_hw *hw;
1674
1675         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1676         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1677 }
1678
1679 static int
1680 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1681 {
1682         struct e1000_hw *hw;
1683         uint32_t ctrl;
1684         int tx_pause;
1685         int rx_pause;
1686
1687         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1688         fc_conf->pause_time = hw->fc.pause_time;
1689         fc_conf->high_water = hw->fc.high_water;
1690         fc_conf->low_water = hw->fc.low_water;
1691         fc_conf->send_xon = hw->fc.send_xon;
1692         fc_conf->autoneg = hw->mac.autoneg;
1693
1694         /*
1695          * Return rx_pause and tx_pause status according to actual setting of
1696          * the TFCE and RFCE bits in the CTRL register.
1697          */
1698         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1699         if (ctrl & E1000_CTRL_TFCE)
1700                 tx_pause = 1;
1701         else
1702                 tx_pause = 0;
1703
1704         if (ctrl & E1000_CTRL_RFCE)
1705                 rx_pause = 1;
1706         else
1707                 rx_pause = 0;
1708
1709         if (rx_pause && tx_pause)
1710                 fc_conf->mode = RTE_FC_FULL;
1711         else if (rx_pause)
1712                 fc_conf->mode = RTE_FC_RX_PAUSE;
1713         else if (tx_pause)
1714                 fc_conf->mode = RTE_FC_TX_PAUSE;
1715         else
1716                 fc_conf->mode = RTE_FC_NONE;
1717
1718         return 0;
1719 }
1720
1721 static int
1722 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1723 {
1724         struct e1000_hw *hw;
1725         int err;
1726         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1727                 e1000_fc_none,
1728                 e1000_fc_rx_pause,
1729                 e1000_fc_tx_pause,
1730                 e1000_fc_full
1731         };
1732         uint32_t rx_buf_size;
1733         uint32_t max_high_water;
1734         uint32_t rctl;
1735
1736         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1737         if (fc_conf->autoneg != hw->mac.autoneg)
1738                 return -ENOTSUP;
1739         rx_buf_size = em_get_rx_buffer_size(hw);
1740         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1741
1742         /* At least reserve one Ethernet frame for watermark */
1743         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1744         if ((fc_conf->high_water > max_high_water) ||
1745             (fc_conf->high_water < fc_conf->low_water)) {
1746                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1747                 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1748                 return -EINVAL;
1749         }
1750
1751         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1752         hw->fc.pause_time     = fc_conf->pause_time;
1753         hw->fc.high_water     = fc_conf->high_water;
1754         hw->fc.low_water      = fc_conf->low_water;
1755         hw->fc.send_xon       = fc_conf->send_xon;
1756
1757         err = e1000_setup_link_generic(hw);
1758         if (err == E1000_SUCCESS) {
1759
1760                 /* check if we want to forward MAC frames - driver doesn't have native
1761                  * capability to do that, so we'll write the registers ourselves */
1762
1763                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1764
1765                 /* set or clear MFLCN.PMCF bit depending on configuration */
1766                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1767                         rctl |= E1000_RCTL_PMCF;
1768                 else
1769                         rctl &= ~E1000_RCTL_PMCF;
1770
1771                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1772                 E1000_WRITE_FLUSH(hw);
1773
1774                 return 0;
1775         }
1776
1777         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1778         return -EIO;
1779 }
1780
1781 static void
1782 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1783                 uint32_t index, __rte_unused uint32_t pool)
1784 {
1785         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1786
1787         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1788 }
1789
1790 static void
1791 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1792 {
1793         uint8_t addr[ETHER_ADDR_LEN];
1794         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1795
1796         memset(addr, 0, sizeof(addr));
1797
1798         e1000_rar_set(hw, addr, index);
1799 }
1800
1801 static int
1802 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1803 {
1804         struct rte_eth_dev_info dev_info;
1805         struct e1000_hw *hw;
1806         uint32_t frame_size;
1807         uint32_t rctl;
1808
1809         eth_em_infos_get(dev, &dev_info);
1810         frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1811
1812         /* check that mtu is within the allowed range */
1813         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1814                 return -EINVAL;
1815
1816         /* refuse mtu that requires the support of scattered packets when this
1817          * feature has not been enabled before. */
1818         if (!dev->data->scattered_rx &&
1819             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1820                 return -EINVAL;
1821
1822         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1823         rctl = E1000_READ_REG(hw, E1000_RCTL);
1824
1825         /* switch to jumbo mode if needed */
1826         if (frame_size > ETHER_MAX_LEN) {
1827                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1828                 rctl |= E1000_RCTL_LPE;
1829         } else {
1830                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1831                 rctl &= ~E1000_RCTL_LPE;
1832         }
1833         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1834
1835         /* update max frame size */
1836         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1837         return 0;
1838 }
1839
1840 static int
1841 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1842                         struct ether_addr *mc_addr_set,
1843                         uint32_t nb_mc_addr)
1844 {
1845         struct e1000_hw *hw;
1846
1847         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1848         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1849         return 0;
1850 }
1851
1852 RTE_PMD_REGISTER_PCI(net_e1000_em, rte_em_pmd.pci_drv);
1853 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_em, pci_id_em_map);
1854 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_em, "* igb_uio | uio_pci_generic | vfio");