drivers/net/e1000/em_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <stdarg.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_interrupts.h>
  13 #include <rte_byteorder.h>
  14 #include <rte_log.h>
  15 #include <rte_debug.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_memory.h>
  22 #include <rte_eal.h>
  23 #include <rte_malloc.h>
  24 #include <rte_dev.h>
  25
  26 #include "e1000_logs.h"
  27 #include "base/e1000_api.h"
  28 #include "e1000_ethdev.h"
  29
  30 #define EM_EIAC                 0x000DC
  31
  32 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
  33
  34
  35 static int eth_em_configure(struct rte_eth_dev *dev);
  36 static int eth_em_start(struct rte_eth_dev *dev);
  37 static void eth_em_stop(struct rte_eth_dev *dev);
  38 static void eth_em_close(struct rte_eth_dev *dev);
  39 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
  40 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
  41 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
  42 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
  43 static int eth_em_link_update(struct rte_eth_dev *dev,
  44                                 int wait_to_complete);
  45 static int eth_em_stats_get(struct rte_eth_dev *dev,
  46                                 struct rte_eth_stats *rte_stats);
  47 static void eth_em_stats_reset(struct rte_eth_dev *dev);
  48 static void eth_em_infos_get(struct rte_eth_dev *dev,
  49                                 struct rte_eth_dev_info *dev_info);
  50 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
  51                                 struct rte_eth_fc_conf *fc_conf);
  52 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
  53                                 struct rte_eth_fc_conf *fc_conf);
  54 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
  55 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
  56 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
  57 static int eth_em_interrupt_action(struct rte_eth_dev *dev,
  58                                    struct rte_intr_handle *handle);
  59 static void eth_em_interrupt_handler(void *param);
  60
  61 static int em_hw_init(struct e1000_hw *hw);
  62 static int em_hardware_init(struct e1000_hw *hw);
  63 static void em_hw_control_acquire(struct e1000_hw *hw);
  64 static void em_hw_control_release(struct e1000_hw *hw);
  65 static void em_init_manageability(struct e1000_hw *hw);
  66 static void em_release_manageability(struct e1000_hw *hw);
  67
  68 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  69
  70 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
  71                 uint16_t vlan_id, int on);
  72 static int eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  73 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
  74 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
  75 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
  76 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
  77
  78 /*
  79 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
  80                                         uint16_t vlan_id, int on);
  81 */
  82
  83 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
  84 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
  85 static void em_lsc_intr_disable(struct e1000_hw *hw);
  86 static void em_rxq_intr_enable(struct e1000_hw *hw);
  87 static void em_rxq_intr_disable(struct e1000_hw *hw);
  88
  89 static int eth_em_led_on(struct rte_eth_dev *dev);
  90 static int eth_em_led_off(struct rte_eth_dev *dev);
  91
  92 static int em_get_rx_buffer_size(struct e1000_hw *hw);
  93 static int eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
  94                           uint32_t index, uint32_t pool);
  95 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
  96
  97 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
  98                                    struct ether_addr *mc_addr_set,
  99                                    uint32_t nb_mc_addr);
 100
 101 #define EM_FC_PAUSE_TIME 0x0680
 102 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 103 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 104
 105 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
 106
 107 int e1000_logtype_init;
 108 int e1000_logtype_driver;
 109
 110 /*
 111  * The set of PCI devices this driver supports
 112  */
 113 static const struct rte_pci_id pci_id_em_map[] = {
 114         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
 115         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
 116         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
 117         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
 118         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
 119         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
 120         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
 121         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
 122         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
 123         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
 124         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
 125         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
 126         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
 127         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
 128         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
 129         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
 130         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
 131         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
 132         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
 133         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
 134         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
 135         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
 136         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
 137         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH2_LV_LM) },
 138         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
 139         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
 140         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
 141         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
 142         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
 143         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
 144         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
 145         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
 146         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM) },
 147         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V) },
 148         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM2) },
 149         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V2) },
 150         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LBG_I219_LM3) },
 151         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM4) },
 152         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V4) },
 153         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM5) },
 154         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V5) },
 155         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM6) },
 156         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V6) },
 157         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM7) },
 158         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V7) },
 159         { .vendor_id = 0, /* sentinel */ },
 160 };
 161
 162 static const struct eth_dev_ops eth_em_ops = {
 163         .dev_configure        = eth_em_configure,
 164         .dev_start            = eth_em_start,
 165         .dev_stop             = eth_em_stop,
 166         .dev_close            = eth_em_close,
 167         .promiscuous_enable   = eth_em_promiscuous_enable,
 168         .promiscuous_disable  = eth_em_promiscuous_disable,
 169         .allmulticast_enable  = eth_em_allmulticast_enable,
 170         .allmulticast_disable = eth_em_allmulticast_disable,
 171         .link_update          = eth_em_link_update,
 172         .stats_get            = eth_em_stats_get,
 173         .stats_reset          = eth_em_stats_reset,
 174         .dev_infos_get        = eth_em_infos_get,
 175         .mtu_set              = eth_em_mtu_set,
 176         .vlan_filter_set      = eth_em_vlan_filter_set,
 177         .vlan_offload_set     = eth_em_vlan_offload_set,
 178         .rx_queue_setup       = eth_em_rx_queue_setup,
 179         .rx_queue_release     = eth_em_rx_queue_release,
 180         .rx_queue_count       = eth_em_rx_queue_count,
 181         .rx_descriptor_done   = eth_em_rx_descriptor_done,
 182         .rx_descriptor_status = eth_em_rx_descriptor_status,
 183         .tx_descriptor_status = eth_em_tx_descriptor_status,
 184         .tx_queue_setup       = eth_em_tx_queue_setup,
 185         .tx_queue_release     = eth_em_tx_queue_release,
 186         .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
 187         .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
 188         .dev_led_on           = eth_em_led_on,
 189         .dev_led_off          = eth_em_led_off,
 190         .flow_ctrl_get        = eth_em_flow_ctrl_get,
 191         .flow_ctrl_set        = eth_em_flow_ctrl_set,
 192         .mac_addr_add         = eth_em_rar_set,
 193         .mac_addr_remove      = eth_em_rar_clear,
 194         .set_mc_addr_list     = eth_em_set_mc_addr_list,
 195         .rxq_info_get         = em_rxq_info_get,
 196         .txq_info_get         = em_txq_info_get,
 197 };
 198
 199
 200 /**
 201  *  eth_em_dev_is_ich8 - Check for ICH8 device
 202  *  @hw: pointer to the HW structure
 203  *
 204  *  return TRUE for ICH8, otherwise FALSE
 205  **/
 206 static bool
 207 eth_em_dev_is_ich8(struct e1000_hw *hw)
 208 {
 209         DEBUGFUNC("eth_em_dev_is_ich8");
 210
 211         switch (hw->device_id) {
 212         case E1000_DEV_ID_PCH2_LV_LM:
 213         case E1000_DEV_ID_PCH_LPT_I217_LM:
 214         case E1000_DEV_ID_PCH_LPT_I217_V:
 215         case E1000_DEV_ID_PCH_LPTLP_I218_LM:
 216         case E1000_DEV_ID_PCH_LPTLP_I218_V:
 217         case E1000_DEV_ID_PCH_I218_V2:
 218         case E1000_DEV_ID_PCH_I218_LM2:
 219         case E1000_DEV_ID_PCH_I218_V3:
 220         case E1000_DEV_ID_PCH_I218_LM3:
 221         case E1000_DEV_ID_PCH_SPT_I219_LM:
 222         case E1000_DEV_ID_PCH_SPT_I219_V:
 223         case E1000_DEV_ID_PCH_SPT_I219_LM2:
 224         case E1000_DEV_ID_PCH_SPT_I219_V2:
 225         case E1000_DEV_ID_PCH_LBG_I219_LM3:
 226         case E1000_DEV_ID_PCH_SPT_I219_LM4:
 227         case E1000_DEV_ID_PCH_SPT_I219_V4:
 228         case E1000_DEV_ID_PCH_SPT_I219_LM5:
 229         case E1000_DEV_ID_PCH_SPT_I219_V5:
 230         case E1000_DEV_ID_PCH_CNP_I219_LM6:
 231         case E1000_DEV_ID_PCH_CNP_I219_V6:
 232         case E1000_DEV_ID_PCH_CNP_I219_LM7:
 233         case E1000_DEV_ID_PCH_CNP_I219_V7:
 234                 return 1;
 235         default:
 236                 return 0;
 237         }
 238 }
 239
 240 static int
 241 eth_em_dev_init(struct rte_eth_dev *eth_dev)
 242 {
 243         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 244         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 245         struct e1000_adapter *adapter =
 246                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 247         struct e1000_hw *hw =
 248                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 249         struct e1000_vfta * shadow_vfta =
 250                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 251
 252         eth_dev->dev_ops = &eth_em_ops;
 253         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
 254         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
 255         eth_dev->tx_pkt_prepare = (eth_tx_prep_t)&eth_em_prep_pkts;
 256
 257         /* for secondary processes, we don't initialise any further as primary
 258          * has already done this work. Only check we don't need a different
 259          * RX function */
 260         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 261                 if (eth_dev->data->scattered_rx)
 262                         eth_dev->rx_pkt_burst =
 263                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
 264                 return 0;
 265         }
 266
 267         rte_eth_copy_pci_info(eth_dev, pci_dev);
 268
 269         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 270         hw->device_id = pci_dev->id.device_id;
 271         adapter->stopped = 0;
 272
 273         /* For ICH8 support we'll need to map the flash memory BAR */
 274         if (eth_em_dev_is_ich8(hw))
 275                 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
 276
 277         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
 278                         em_hw_init(hw) != 0) {
 279                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
 280                         "failed to init HW",
 281                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 282                         pci_dev->id.device_id);
 283                 return -ENODEV;
 284         }
 285
 286         /* Allocate memory for storing MAC addresses */
 287         eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
 288                         hw->mac.rar_entry_count, 0);
 289         if (eth_dev->data->mac_addrs == NULL) {
 290                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 291                         "store MAC addresses",
 292                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 293                 return -ENOMEM;
 294         }
 295
 296         /* Copy the permanent MAC address */
 297         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 298                 eth_dev->data->mac_addrs);
 299
 300         /* initialize the vfta */
 301         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 302
 303         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 304                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 305                      pci_dev->id.device_id);
 306
 307         rte_intr_callback_register(intr_handle,
 308                                    eth_em_interrupt_handler, eth_dev);
 309
 310         return 0;
 311 }
 312
 313 static int
 314 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
 315 {
 316         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 317         struct e1000_adapter *adapter =
 318                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 319         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 320
 321         PMD_INIT_FUNC_TRACE();
 322
 323         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 324                 return -EPERM;
 325
 326         if (adapter->stopped == 0)
 327                 eth_em_close(eth_dev);
 328
 329         eth_dev->dev_ops = NULL;
 330         eth_dev->rx_pkt_burst = NULL;
 331         eth_dev->tx_pkt_burst = NULL;
 332
 333         rte_free(eth_dev->data->mac_addrs);
 334         eth_dev->data->mac_addrs = NULL;
 335
 336         /* disable uio intr before callback unregister */
 337         rte_intr_disable(intr_handle);
 338         rte_intr_callback_unregister(intr_handle,
 339                                      eth_em_interrupt_handler, eth_dev);
 340
 341         return 0;
 342 }
 343
 344 static int eth_em_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 345         struct rte_pci_device *pci_dev)
 346 {
 347         return rte_eth_dev_pci_generic_probe(pci_dev,
 348                 sizeof(struct e1000_adapter), eth_em_dev_init);
 349 }
 350
 351 static int eth_em_pci_remove(struct rte_pci_device *pci_dev)
 352 {
 353         return rte_eth_dev_pci_generic_remove(pci_dev, eth_em_dev_uninit);
 354 }
 355
 356 static struct rte_pci_driver rte_em_pmd = {
 357         .id_table = pci_id_em_map,
 358         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 359                      RTE_PCI_DRV_IOVA_AS_VA,
 360         .probe = eth_em_pci_probe,
 361         .remove = eth_em_pci_remove,
 362 };
 363
 364 static int
 365 em_hw_init(struct e1000_hw *hw)
 366 {
 367         int diag;
 368
 369         diag = hw->mac.ops.init_params(hw);
 370         if (diag != 0) {
 371                 PMD_INIT_LOG(ERR, "MAC Initialization Error");
 372                 return diag;
 373         }
 374         diag = hw->nvm.ops.init_params(hw);
 375         if (diag != 0) {
 376                 PMD_INIT_LOG(ERR, "NVM Initialization Error");
 377                 return diag;
 378         }
 379         diag = hw->phy.ops.init_params(hw);
 380         if (diag != 0) {
 381                 PMD_INIT_LOG(ERR, "PHY Initialization Error");
 382                 return diag;
 383         }
 384         (void) e1000_get_bus_info(hw);
 385
 386         hw->mac.autoneg = 1;
 387         hw->phy.autoneg_wait_to_complete = 0;
 388         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 389
 390         e1000_init_script_state_82541(hw, TRUE);
 391         e1000_set_tbi_compatibility_82543(hw, TRUE);
 392
 393         /* Copper options */
 394         if (hw->phy.media_type == e1000_media_type_copper) {
 395                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 396                 hw->phy.disable_polarity_correction = 0;
 397                 hw->phy.ms_type = e1000_ms_hw_default;
 398         }
 399
 400         /*
 401          * Start from a known state, this is important in reading the nvm
 402          * and mac from that.
 403          */
 404         e1000_reset_hw(hw);
 405
 406         /* Make sure we have a good EEPROM before we read from it */
 407         if (e1000_validate_nvm_checksum(hw) < 0) {
 408                 /*
 409                  * Some PCI-E parts fail the first check due to
 410                  * the link being in sleep state, call it again,
 411                  * if it fails a second time its a real issue.
 412                  */
 413                 diag = e1000_validate_nvm_checksum(hw);
 414                 if (diag < 0) {
 415                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 416                         goto error;
 417                 }
 418         }
 419
 420         /* Read the permanent MAC address out of the EEPROM */
 421         diag = e1000_read_mac_addr(hw);
 422         if (diag != 0) {
 423                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 424                 goto error;
 425         }
 426
 427         /* Now initialize the hardware */
 428         diag = em_hardware_init(hw);
 429         if (diag != 0) {
 430                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 431                 goto error;
 432         }
 433
 434         hw->mac.get_link_status = 1;
 435
 436         /* Indicate SOL/IDER usage */
 437         diag = e1000_check_reset_block(hw);
 438         if (diag < 0) {
 439                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
 440                         "SOL/IDER session");
 441         }
 442         return 0;
 443
 444 error:
 445         em_hw_control_release(hw);
 446         return diag;
 447 }
 448
 449 static int
 450 eth_em_configure(struct rte_eth_dev *dev)
 451 {
 452         struct e1000_interrupt *intr =
 453                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 454         struct rte_eth_dev_info dev_info;
 455         uint64_t rx_offloads;
 456         uint64_t tx_offloads;
 457
 458         PMD_INIT_FUNC_TRACE();
 459         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 460
 461         eth_em_infos_get(dev, &dev_info);
 462         rx_offloads = dev->data->dev_conf.rxmode.offloads;
 463         if ((rx_offloads & dev_info.rx_offload_capa) != rx_offloads) {
 464                 PMD_DRV_LOG(ERR, "Some Rx offloads are not supported "
 465                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
 466                             rx_offloads, dev_info.rx_offload_capa);
 467                 return -ENOTSUP;
 468         }
 469         tx_offloads = dev->data->dev_conf.txmode.offloads;
 470         if ((tx_offloads & dev_info.tx_offload_capa) != tx_offloads) {
 471                 PMD_DRV_LOG(ERR, "Some Tx offloads are not supported "
 472                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
 473                             tx_offloads, dev_info.tx_offload_capa);
 474                 return -ENOTSUP;
 475         }
 476
 477         PMD_INIT_FUNC_TRACE();
 478
 479         return 0;
 480 }
 481
 482 static void
 483 em_set_pba(struct e1000_hw *hw)
 484 {
 485         uint32_t pba;
 486
 487         /*
 488          * Packet Buffer Allocation (PBA)
 489          * Writing PBA sets the receive portion of the buffer
 490          * the remainder is used for the transmit buffer.
 491          * Devices before the 82547 had a Packet Buffer of 64K.
 492          * After the 82547 the buffer was reduced to 40K.
 493          */
 494         switch (hw->mac.type) {
 495                 case e1000_82547:
 496                 case e1000_82547_rev_2:
 497                 /* 82547: Total Packet Buffer is 40K */
 498                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
 499                         break;
 500                 case e1000_82571:
 501                 case e1000_82572:
 502                 case e1000_80003es2lan:
 503                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 504                         break;
 505                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
 506                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
 507                         break;
 508                 case e1000_82574:
 509                 case e1000_82583:
 510                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
 511                         break;
 512                 case e1000_ich8lan:
 513                         pba = E1000_PBA_8K;
 514                         break;
 515                 case e1000_ich9lan:
 516                 case e1000_ich10lan:
 517                         pba = E1000_PBA_10K;
 518                         break;
 519                 case e1000_pchlan:
 520                 case e1000_pch2lan:
 521                 case e1000_pch_lpt:
 522                 case e1000_pch_spt:
 523                 case e1000_pch_cnp:
 524                         pba = E1000_PBA_26K;
 525                         break;
 526                 default:
 527                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
 528         }
 529
 530         E1000_WRITE_REG(hw, E1000_PBA, pba);
 531 }
 532
 533 static void
 534 eth_em_rxtx_control(struct rte_eth_dev *dev,
 535                     bool enable)
 536 {
 537         struct e1000_hw *hw =
 538                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 539         uint32_t tctl, rctl;
 540
 541         tctl = E1000_READ_REG(hw, E1000_TCTL);
 542         rctl = E1000_READ_REG(hw, E1000_RCTL);
 543         if (enable) {
 544                 /* enable Tx/Rx */
 545                 tctl |= E1000_TCTL_EN;
 546                 rctl |= E1000_RCTL_EN;
 547         } else {
 548                 /* disable Tx/Rx */
 549                 tctl &= ~E1000_TCTL_EN;
 550                 rctl &= ~E1000_RCTL_EN;
 551         }
 552         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
 553         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
 554         E1000_WRITE_FLUSH(hw);
 555 }
 556
 557 static int
 558 eth_em_start(struct rte_eth_dev *dev)
 559 {
 560         struct e1000_adapter *adapter =
 561                 E1000_DEV_PRIVATE(dev->data->dev_private);
 562         struct e1000_hw *hw =
 563                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 564         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 565         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 566         int ret, mask;
 567         uint32_t intr_vector = 0;
 568         uint32_t *speeds;
 569         int num_speeds;
 570         bool autoneg;
 571
 572         PMD_INIT_FUNC_TRACE();
 573
 574         eth_em_stop(dev);
 575
 576         e1000_power_up_phy(hw);
 577
 578         /* Set default PBA value */
 579         em_set_pba(hw);
 580
 581         /* Put the address into the Receive Address Array */
 582         e1000_rar_set(hw, hw->mac.addr, 0);
 583
 584         /*
 585          * With the 82571 adapter, RAR[0] may be overwritten
 586          * when the other port is reset, we make a duplicate
 587          * in RAR[14] for that eventuality, this assures
 588          * the interface continues to function.
 589          */
 590         if (hw->mac.type == e1000_82571) {
 591                 e1000_set_laa_state_82571(hw, TRUE);
 592                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
 593         }
 594
 595         /* Initialize the hardware */
 596         if (em_hardware_init(hw)) {
 597                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 598                 return -EIO;
 599         }
 600
 601         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 602
 603         /* Configure for OS presence */
 604         em_init_manageability(hw);
 605
 606         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 607                 intr_vector = dev->data->nb_rx_queues;
 608                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 609                         return -1;
 610         }
 611
 612         if (rte_intr_dp_is_en(intr_handle)) {
 613                 intr_handle->intr_vec =
 614                         rte_zmalloc("intr_vec",
 615                                         dev->data->nb_rx_queues * sizeof(int), 0);
 616                 if (intr_handle->intr_vec == NULL) {
 617                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 618                                                 " intr_vec", dev->data->nb_rx_queues);
 619                         return -ENOMEM;
 620                 }
 621
 622                 /* enable rx interrupt */
 623                 em_rxq_intr_enable(hw);
 624         }
 625
 626         eth_em_tx_init(dev);
 627
 628         ret = eth_em_rx_init(dev);
 629         if (ret) {
 630                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 631                 em_dev_clear_queues(dev);
 632                 return ret;
 633         }
 634
 635         e1000_clear_hw_cntrs_base_generic(hw);
 636
 637         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 638                         ETH_VLAN_EXTEND_MASK;
 639         ret = eth_em_vlan_offload_set(dev, mask);
 640         if (ret) {
 641                 PMD_INIT_LOG(ERR, "Unable to update vlan offload");
 642                 em_dev_clear_queues(dev);
 643                 return ret;
 644         }
 645
 646         /* Set Interrupt Throttling Rate to maximum allowed value. */
 647         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
 648
 649         /* Setup link speed and duplex */
 650         speeds = &dev->data->dev_conf.link_speeds;
 651         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
 652                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 653                 hw->mac.autoneg = 1;
 654         } else {
 655                 num_speeds = 0;
 656                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
 657
 658                 /* Reset */
 659                 hw->phy.autoneg_advertised = 0;
 660
 661                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
 662                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
 663                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
 664                         num_speeds = -1;
 665                         goto error_invalid_config;
 666                 }
 667                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
 668                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
 669                         num_speeds++;
 670                 }
 671                 if (*speeds & ETH_LINK_SPEED_10M) {
 672                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
 673                         num_speeds++;
 674                 }
 675                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
 676                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
 677                         num_speeds++;
 678                 }
 679                 if (*speeds & ETH_LINK_SPEED_100M) {
 680                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
 681                         num_speeds++;
 682                 }
 683                 if (*speeds & ETH_LINK_SPEED_1G) {
 684                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
 685                         num_speeds++;
 686                 }
 687                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
 688                         goto error_invalid_config;
 689
 690                 /* Set/reset the mac.autoneg based on the link speed,
 691                  * fixed or not
 692                  */
 693                 if (!autoneg) {
 694                         hw->mac.autoneg = 0;
 695                         hw->mac.forced_speed_duplex =
 696                                         hw->phy.autoneg_advertised;
 697                 } else {
 698                         hw->mac.autoneg = 1;
 699                 }
 700         }
 701
 702         e1000_setup_link(hw);
 703
 704         if (rte_intr_allow_others(intr_handle)) {
 705                 /* check if lsc interrupt is enabled */
 706                 if (dev->data->dev_conf.intr_conf.lsc != 0) {
 707                         ret = eth_em_interrupt_setup(dev);
 708                         if (ret) {
 709                                 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
 710                                 em_dev_clear_queues(dev);
 711                                 return ret;
 712                         }
 713                 }
 714         } else {
 715                 rte_intr_callback_unregister(intr_handle,
 716                                                 eth_em_interrupt_handler,
 717                                                 (void *)dev);
 718                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 719                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
 720                                      " no intr multiplexn");
 721         }
 722         /* check if rxq interrupt is enabled */
 723         if (dev->data->dev_conf.intr_conf.rxq != 0)
 724                 eth_em_rxq_interrupt_setup(dev);
 725
 726         rte_intr_enable(intr_handle);
 727
 728         adapter->stopped = 0;
 729
 730         eth_em_rxtx_control(dev, true);
 731         eth_em_link_update(dev, 0);
 732
 733         PMD_INIT_LOG(DEBUG, "<<");
 734
 735         return 0;
 736
 737 error_invalid_config:
 738         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
 739                      dev->data->dev_conf.link_speeds, dev->data->port_id);
 740         em_dev_clear_queues(dev);
 741         return -EINVAL;
 742 }
 743
 744 /*********************************************************************
 745  *
 746  *  This routine disables all traffic on the adapter by issuing a
 747  *  global reset on the MAC.
 748  *
 749  **********************************************************************/
 750 static void
 751 eth_em_stop(struct rte_eth_dev *dev)
 752 {
 753         struct rte_eth_link link;
 754         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 755         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 756         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 757
 758         eth_em_rxtx_control(dev, false);
 759         em_rxq_intr_disable(hw);
 760         em_lsc_intr_disable(hw);
 761
 762         e1000_reset_hw(hw);
 763         if (hw->mac.type >= e1000_82544)
 764                 E1000_WRITE_REG(hw, E1000_WUC, 0);
 765
 766         /* Power down the phy. Needed to make the link go down */
 767         e1000_power_down_phy(hw);
 768
 769         em_dev_clear_queues(dev);
 770
 771         /* clear the recorded link status */
 772         memset(&link, 0, sizeof(link));
 773         rte_eth_linkstatus_set(dev, &link);
 774
 775         if (!rte_intr_allow_others(intr_handle))
 776                 /* resume to the default handler */
 777                 rte_intr_callback_register(intr_handle,
 778                                            eth_em_interrupt_handler,
 779                                            (void *)dev);
 780
 781         /* Clean datapath event and queue/vec mapping */
 782         rte_intr_efd_disable(intr_handle);
 783         if (intr_handle->intr_vec != NULL) {
 784                 rte_free(intr_handle->intr_vec);
 785                 intr_handle->intr_vec = NULL;
 786         }
 787 }
 788
 789 static void
 790 eth_em_close(struct rte_eth_dev *dev)
 791 {
 792         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 793         struct e1000_adapter *adapter =
 794                 E1000_DEV_PRIVATE(dev->data->dev_private);
 795
 796         eth_em_stop(dev);
 797         adapter->stopped = 1;
 798         em_dev_free_queues(dev);
 799         e1000_phy_hw_reset(hw);
 800         em_release_manageability(hw);
 801         em_hw_control_release(hw);
 802 }
 803
 804 static int
 805 em_get_rx_buffer_size(struct e1000_hw *hw)
 806 {
 807         uint32_t rx_buf_size;
 808
 809         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
 810         return rx_buf_size;
 811 }
 812
 813 /*********************************************************************
 814  *
 815  *  Initialize the hardware
 816  *
 817  **********************************************************************/
 818 static int
 819 em_hardware_init(struct e1000_hw *hw)
 820 {
 821         uint32_t rx_buf_size;
 822         int diag;
 823
 824         /* Issue a global reset */
 825         e1000_reset_hw(hw);
 826
 827         /* Let the firmware know the OS is in control */
 828         em_hw_control_acquire(hw);
 829
 830         /*
 831          * These parameters control the automatic generation (Tx) and
 832          * response (Rx) to Ethernet PAUSE frames.
 833          * - High water mark should allow for at least two standard size (1518)
 834          *   frames to be received after sending an XOFF.
 835          * - Low water mark works best when it is very near the high water mark.
 836          *   This allows the receiver to restart by sending XON when it has
 837          *   drained a bit. Here we use an arbitrary value of 1500 which will
 838          *   restart after one full frame is pulled from the buffer. There
 839          *   could be several smaller frames in the buffer and if so they will
 840          *   not trigger the XON until their total number reduces the buffer
 841          *   by 1500.
 842          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 843          */
 844         rx_buf_size = em_get_rx_buffer_size(hw);
 845
 846         hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
 847         hw->fc.low_water = hw->fc.high_water - 1500;
 848
 849         if (hw->mac.type == e1000_80003es2lan)
 850                 hw->fc.pause_time = UINT16_MAX;
 851         else
 852                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
 853
 854         hw->fc.send_xon = 1;
 855
 856         /* Set Flow control, use the tunable location if sane */
 857         if (em_fc_setting <= e1000_fc_full)
 858                 hw->fc.requested_mode = em_fc_setting;
 859         else
 860                 hw->fc.requested_mode = e1000_fc_none;
 861
 862         /* Workaround: no TX flow ctrl for PCH */
 863         if (hw->mac.type == e1000_pchlan)
 864                 hw->fc.requested_mode = e1000_fc_rx_pause;
 865
 866         /* Override - settings for PCH2LAN, ya its magic :) */
 867         if (hw->mac.type == e1000_pch2lan) {
 868                 hw->fc.high_water = 0x5C20;
 869                 hw->fc.low_water = 0x5048;
 870                 hw->fc.pause_time = 0x0650;
 871                 hw->fc.refresh_time = 0x0400;
 872         } else if (hw->mac.type == e1000_pch_lpt ||
 873                    hw->mac.type == e1000_pch_spt ||
 874                    hw->mac.type == e1000_pch_cnp) {
 875                 hw->fc.requested_mode = e1000_fc_full;
 876         }
 877
 878         diag = e1000_init_hw(hw);
 879         if (diag < 0)
 880                 return diag;
 881         e1000_check_for_link(hw);
 882         return 0;
 883 }
 884
 885 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
 886 static int
 887 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 888 {
 889         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 890         struct e1000_hw_stats *stats =
 891                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 892         int pause_frames;
 893
 894         if(hw->phy.media_type == e1000_media_type_copper ||
 895                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 896                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
 897                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 898         }
 899
 900         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 901         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 902         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 903         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 904
 905         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 906         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 907         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 908         stats->dc += E1000_READ_REG(hw, E1000_DC);
 909         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 910         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 911         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 912
 913         /*
 914          * For watchdog management we need to know if we have been
 915          * paused during the last interval, so capture that here.
 916          */
 917         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 918         stats->xoffrxc += pause_frames;
 919         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 920         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 921         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 922         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 923         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 924         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 925         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 926         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 927         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 928         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 929         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 930         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 931
 932         /*
 933          * For the 64-bit byte counters the low dword must be read first.
 934          * Both registers clear on the read of the high dword.
 935          */
 936
 937         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 938         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 939         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 940         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 941
 942         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 943         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 944         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 945         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 946         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 947
 948         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 949         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 950
 951         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 952         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 953         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 954         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 955         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 956         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 957         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 958         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 959         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 960         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 961
 962         /* Interrupt Counts */
 963
 964         if (hw->mac.type >= e1000_82571) {
 965                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
 966                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 967                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 968                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 969                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 970                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 971                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 972                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 973                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 974         }
 975
 976         if (hw->mac.type >= e1000_82543) {
 977                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 978                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 979                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 980                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 981                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 982                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 983         }
 984
 985         if (rte_stats == NULL)
 986                 return -EINVAL;
 987
 988         /* Rx Errors */
 989         rte_stats->imissed = stats->mpc;
 990         rte_stats->ierrors = stats->crcerrs +
 991                              stats->rlec + stats->ruc + stats->roc +
 992                              stats->rxerrc + stats->algnerrc + stats->cexterr;
 993
 994         /* Tx Errors */
 995         rte_stats->oerrors = stats->ecol + stats->latecol;
 996
 997         rte_stats->ipackets = stats->gprc;
 998         rte_stats->opackets = stats->gptc;
 999         rte_stats->ibytes   = stats->gorc;
1000         rte_stats->obytes   = stats->gotc;
1001         return 0;
1002 }
1003
1004 static void
1005 eth_em_stats_reset(struct rte_eth_dev *dev)
1006 {
1007         struct e1000_hw_stats *hw_stats =
1008                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1009
1010         /* HW registers are cleared on read */
1011         eth_em_stats_get(dev, NULL);
1012
1013         /* Reset software totals */
1014         memset(hw_stats, 0, sizeof(*hw_stats));
1015 }
1016
1017 static int
1018 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1019 {
1020         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1021         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1022         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1023
1024         em_rxq_intr_enable(hw);
1025         rte_intr_enable(intr_handle);
1026
1027         return 0;
1028 }
1029
1030 static int
1031 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1032 {
1033         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1034
1035         em_rxq_intr_disable(hw);
1036
1037         return 0;
1038 }
1039
1040 uint32_t
1041 em_get_max_pktlen(struct rte_eth_dev *dev)
1042 {
1043         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1044
1045         switch (hw->mac.type) {
1046         case e1000_82571:
1047         case e1000_82572:
1048         case e1000_ich9lan:
1049         case e1000_ich10lan:
1050         case e1000_pch2lan:
1051         case e1000_pch_lpt:
1052         case e1000_pch_spt:
1053         case e1000_pch_cnp:
1054         case e1000_82574:
1055         case e1000_80003es2lan: /* 9K Jumbo Frame size */
1056         case e1000_82583:
1057                 return 0x2412;
1058         case e1000_pchlan:
1059                 return 0x1000;
1060         /* Adapters that do not support jumbo frames */
1061         case e1000_ich8lan:
1062                 return ETHER_MAX_LEN;
1063         default:
1064                 return MAX_JUMBO_FRAME_SIZE;
1065         }
1066 }
1067
1068 static void
1069 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1070 {
1071         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1072
1073         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1074         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1075         dev_info->max_rx_pktlen = em_get_max_pktlen(dev);
1076         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1077
1078         /*
1079          * Starting with 631xESB hw supports 2 TX/RX queues per port.
1080          * Unfortunatelly, all these nics have just one TX context.
1081          * So we have few choises for TX:
1082          * - Use just one TX queue.
1083          * - Allow cksum offload only for one TX queue.
1084          * - Don't allow TX cksum offload at all.
1085          * For now, option #1 was chosen.
1086          * To use second RX queue we have to use extended RX descriptor
1087          * (Multiple Receive Queues are mutually exclusive with UDP
1088          * fragmentation and are not supported when a legacy receive
1089          * descriptor format is used).
1090          * Which means separate RX routinies - as legacy nics (82540, 82545)
1091          * don't support extended RXD.
1092          * To avoid it we support just one RX queue for now (no RSS).
1093          */
1094
1095         dev_info->max_rx_queues = 1;
1096         dev_info->max_tx_queues = 1;
1097
1098         dev_info->rx_queue_offload_capa = em_get_rx_queue_offloads_capa(dev);
1099         dev_info->rx_offload_capa = em_get_rx_port_offloads_capa(dev) |
1100                                     dev_info->rx_queue_offload_capa;
1101         dev_info->tx_queue_offload_capa = em_get_tx_queue_offloads_capa(dev);
1102         dev_info->tx_offload_capa = em_get_tx_port_offloads_capa(dev) |
1103                                     dev_info->tx_queue_offload_capa;
1104
1105         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1106                 .nb_max = E1000_MAX_RING_DESC,
1107                 .nb_min = E1000_MIN_RING_DESC,
1108                 .nb_align = EM_RXD_ALIGN,
1109         };
1110
1111         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1112                 .nb_max = E1000_MAX_RING_DESC,
1113                 .nb_min = E1000_MIN_RING_DESC,
1114                 .nb_align = EM_TXD_ALIGN,
1115                 .nb_seg_max = EM_TX_MAX_SEG,
1116                 .nb_mtu_seg_max = EM_TX_MAX_MTU_SEG,
1117         };
1118
1119         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1120                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1121                         ETH_LINK_SPEED_1G;
1122 }
1123
1124 /* return 0 means link status changed, -1 means not changed */
1125 static int
1126 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1127 {
1128         struct e1000_hw *hw =
1129                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1130         struct rte_eth_link link;
1131         int link_check, count;
1132
1133         link_check = 0;
1134         hw->mac.get_link_status = 1;
1135
1136         /* possible wait-to-complete in up to 9 seconds */
1137         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1138                 /* Read the real link status */
1139                 switch (hw->phy.media_type) {
1140                 case e1000_media_type_copper:
1141                         /* Do the work to read phy */
1142                         e1000_check_for_link(hw);
1143                         link_check = !hw->mac.get_link_status;
1144                         break;
1145
1146                 case e1000_media_type_fiber:
1147                         e1000_check_for_link(hw);
1148                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1149                                         E1000_STATUS_LU);
1150                         break;
1151
1152                 case e1000_media_type_internal_serdes:
1153                         e1000_check_for_link(hw);
1154                         link_check = hw->mac.serdes_has_link;
1155                         break;
1156
1157                 default:
1158                         break;
1159                 }
1160                 if (link_check || wait_to_complete == 0)
1161                         break;
1162                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1163         }
1164         memset(&link, 0, sizeof(link));
1165
1166         /* Now we check if a transition has happened */
1167         if (link_check && (link.link_status == ETH_LINK_DOWN)) {
1168                 uint16_t duplex, speed;
1169                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1170                 link.link_duplex = (duplex == FULL_DUPLEX) ?
1171                                 ETH_LINK_FULL_DUPLEX :
1172                                 ETH_LINK_HALF_DUPLEX;
1173                 link.link_speed = speed;
1174                 link.link_status = ETH_LINK_UP;
1175                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1176                                 ETH_LINK_SPEED_FIXED);
1177         } else if (!link_check && (link.link_status == ETH_LINK_UP)) {
1178                 link.link_speed = 0;
1179                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1180                 link.link_status = ETH_LINK_DOWN;
1181                 link.link_autoneg = ETH_LINK_FIXED;
1182         }
1183
1184         return rte_eth_linkstatus_set(dev, &link);
1185 }
1186
1187 /*
1188  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1189  * For ASF and Pass Through versions of f/w this means
1190  * that the driver is loaded. For AMT version type f/w
1191  * this means that the network i/f is open.
1192  */
1193 static void
1194 em_hw_control_acquire(struct e1000_hw *hw)
1195 {
1196         uint32_t ctrl_ext, swsm;
1197
1198         /* Let firmware know the driver has taken over */
1199         if (hw->mac.type == e1000_82573) {
1200                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1201                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1202
1203         } else {
1204                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1205                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1206                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1207         }
1208 }
1209
1210 /*
1211  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1212  * For ASF and Pass Through versions of f/w this means that the
1213  * driver is no longer loaded. For AMT versions of the
1214  * f/w this means that the network i/f is closed.
1215  */
1216 static void
1217 em_hw_control_release(struct e1000_hw *hw)
1218 {
1219         uint32_t ctrl_ext, swsm;
1220
1221         /* Let firmware taken over control of h/w */
1222         if (hw->mac.type == e1000_82573) {
1223                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1224                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1225         } else {
1226                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1227                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1228                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1229         }
1230 }
1231
1232 /*
1233  * Bit of a misnomer, what this really means is
1234  * to enable OS management of the system... aka
1235  * to disable special hardware management features.
1236  */
1237 static void
1238 em_init_manageability(struct e1000_hw *hw)
1239 {
1240         if (e1000_enable_mng_pass_thru(hw)) {
1241                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1242                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1243
1244                 /* disable hardware interception of ARP */
1245                 manc &= ~(E1000_MANC_ARP_EN);
1246
1247                 /* enable receiving management packets to the host */
1248                 manc |= E1000_MANC_EN_MNG2HOST;
1249                 manc2h |= 1 << 5;  /* Mng Port 623 */
1250                 manc2h |= 1 << 6;  /* Mng Port 664 */
1251                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1252                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1253         }
1254 }
1255
1256 /*
1257  * Give control back to hardware management
1258  * controller if there is one.
1259  */
1260 static void
1261 em_release_manageability(struct e1000_hw *hw)
1262 {
1263         uint32_t manc;
1264
1265         if (e1000_enable_mng_pass_thru(hw)) {
1266                 manc = E1000_READ_REG(hw, E1000_MANC);
1267
1268                 /* re-enable hardware interception of ARP */
1269                 manc |= E1000_MANC_ARP_EN;
1270                 manc &= ~E1000_MANC_EN_MNG2HOST;
1271
1272                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1273         }
1274 }
1275
1276 static void
1277 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1278 {
1279         struct e1000_hw *hw =
1280                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1281         uint32_t rctl;
1282
1283         rctl = E1000_READ_REG(hw, E1000_RCTL);
1284         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1285         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1286 }
1287
1288 static void
1289 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1290 {
1291         struct e1000_hw *hw =
1292                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1293         uint32_t rctl;
1294
1295         rctl = E1000_READ_REG(hw, E1000_RCTL);
1296         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1297         if (dev->data->all_multicast == 1)
1298                 rctl |= E1000_RCTL_MPE;
1299         else
1300                 rctl &= (~E1000_RCTL_MPE);
1301         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1302 }
1303
1304 static void
1305 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1306 {
1307         struct e1000_hw *hw =
1308                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1309         uint32_t rctl;
1310
1311         rctl = E1000_READ_REG(hw, E1000_RCTL);
1312         rctl |= E1000_RCTL_MPE;
1313         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1314 }
1315
1316 static void
1317 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1318 {
1319         struct e1000_hw *hw =
1320                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1321         uint32_t rctl;
1322
1323         if (dev->data->promiscuous == 1)
1324                 return; /* must remain in all_multicast mode */
1325         rctl = E1000_READ_REG(hw, E1000_RCTL);
1326         rctl &= (~E1000_RCTL_MPE);
1327         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1328 }
1329
1330 static int
1331 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1332 {
1333         struct e1000_hw *hw =
1334                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1335         struct e1000_vfta * shadow_vfta =
1336                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1337         uint32_t vfta;
1338         uint32_t vid_idx;
1339         uint32_t vid_bit;
1340
1341         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1342                               E1000_VFTA_ENTRY_MASK);
1343         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1344         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1345         if (on)
1346                 vfta |= vid_bit;
1347         else
1348                 vfta &= ~vid_bit;
1349         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1350
1351         /* update local VFTA copy */
1352         shadow_vfta->vfta[vid_idx] = vfta;
1353
1354         return 0;
1355 }
1356
1357 static void
1358 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1359 {
1360         struct e1000_hw *hw =
1361                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1362         uint32_t reg;
1363
1364         /* Filter Table Disable */
1365         reg = E1000_READ_REG(hw, E1000_RCTL);
1366         reg &= ~E1000_RCTL_CFIEN;
1367         reg &= ~E1000_RCTL_VFE;
1368         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1369 }
1370
1371 static void
1372 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1373 {
1374         struct e1000_hw *hw =
1375                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1376         struct e1000_vfta * shadow_vfta =
1377                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1378         uint32_t reg;
1379         int i;
1380
1381         /* Filter Table Enable, CFI not used for packet acceptance */
1382         reg = E1000_READ_REG(hw, E1000_RCTL);
1383         reg &= ~E1000_RCTL_CFIEN;
1384         reg |= E1000_RCTL_VFE;
1385         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1386
1387         /* restore vfta from local copy */
1388         for (i = 0; i < IGB_VFTA_SIZE; i++)
1389                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1390 }
1391
1392 static void
1393 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1394 {
1395         struct e1000_hw *hw =
1396                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1397         uint32_t reg;
1398
1399         /* VLAN Mode Disable */
1400         reg = E1000_READ_REG(hw, E1000_CTRL);
1401         reg &= ~E1000_CTRL_VME;
1402         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1403
1404 }
1405
1406 static void
1407 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1408 {
1409         struct e1000_hw *hw =
1410                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1411         uint32_t reg;
1412
1413         /* VLAN Mode Enable */
1414         reg = E1000_READ_REG(hw, E1000_CTRL);
1415         reg |= E1000_CTRL_VME;
1416         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1417 }
1418
1419 static int
1420 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1421 {
1422         struct rte_eth_rxmode *rxmode;
1423
1424         rxmode = &dev->data->dev_conf.rxmode;
1425         if(mask & ETH_VLAN_STRIP_MASK){
1426                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1427                         em_vlan_hw_strip_enable(dev);
1428                 else
1429                         em_vlan_hw_strip_disable(dev);
1430         }
1431
1432         if(mask & ETH_VLAN_FILTER_MASK){
1433                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1434                         em_vlan_hw_filter_enable(dev);
1435                 else
1436                         em_vlan_hw_filter_disable(dev);
1437         }
1438
1439         return 0;
1440 }
1441
1442 /*
1443  * It enables the interrupt mask and then enable the interrupt.
1444  *
1445  * @param dev
1446  *  Pointer to struct rte_eth_dev.
1447  *
1448  * @return
1449  *  - On success, zero.
1450  *  - On failure, a negative value.
1451  */
1452 static int
1453 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1454 {
1455         uint32_t regval;
1456         struct e1000_hw *hw =
1457                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1458
1459         /* clear interrupt */
1460         E1000_READ_REG(hw, E1000_ICR);
1461         regval = E1000_READ_REG(hw, E1000_IMS);
1462         E1000_WRITE_REG(hw, E1000_IMS, regval | E1000_ICR_LSC);
1463         return 0;
1464 }
1465
1466 /*
1467  * It clears the interrupt causes and enables the interrupt.
1468  * It will be called once only during nic initialized.
1469  *
1470  * @param dev
1471  *  Pointer to struct rte_eth_dev.
1472  *
1473  * @return
1474  *  - On success, zero.
1475  *  - On failure, a negative value.
1476  */
1477 static int
1478 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1479 {
1480         struct e1000_hw *hw =
1481         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1482
1483         E1000_READ_REG(hw, E1000_ICR);
1484         em_rxq_intr_enable(hw);
1485         return 0;
1486 }
1487
1488 /*
1489  * It enable receive packet interrupt.
1490  * @param hw
1491  * Pointer to struct e1000_hw
1492  *
1493  * @return
1494  */
1495 static void
1496 em_rxq_intr_enable(struct e1000_hw *hw)
1497 {
1498         E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1499         E1000_WRITE_FLUSH(hw);
1500 }
1501
1502 /*
1503  * It disabled lsc interrupt.
1504  * @param hw
1505  * Pointer to struct e1000_hw
1506  *
1507  * @return
1508  */
1509 static void
1510 em_lsc_intr_disable(struct e1000_hw *hw)
1511 {
1512         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC);
1513         E1000_WRITE_FLUSH(hw);
1514 }
1515
1516 /*
1517  * It disabled receive packet interrupt.
1518  * @param hw
1519  * Pointer to struct e1000_hw
1520  *
1521  * @return
1522  */
1523 static void
1524 em_rxq_intr_disable(struct e1000_hw *hw)
1525 {
1526         E1000_READ_REG(hw, E1000_ICR);
1527         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1528         E1000_WRITE_FLUSH(hw);
1529 }
1530
1531 /*
1532  * It reads ICR and gets interrupt causes, check it and set a bit flag
1533  * to update link status.
1534  *
1535  * @param dev
1536  *  Pointer to struct rte_eth_dev.
1537  *
1538  * @return
1539  *  - On success, zero.
1540  *  - On failure, a negative value.
1541  */
1542 static int
1543 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1544 {
1545         uint32_t icr;
1546         struct e1000_hw *hw =
1547                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1548         struct e1000_interrupt *intr =
1549                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1550
1551         /* read-on-clear nic registers here */
1552         icr = E1000_READ_REG(hw, E1000_ICR);
1553         if (icr & E1000_ICR_LSC) {
1554                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1555         }
1556
1557         return 0;
1558 }
1559
1560 /*
1561  * It executes link_update after knowing an interrupt is prsent.
1562  *
1563  * @param dev
1564  *  Pointer to struct rte_eth_dev.
1565  *
1566  * @return
1567  *  - On success, zero.
1568  *  - On failure, a negative value.
1569  */
1570 static int
1571 eth_em_interrupt_action(struct rte_eth_dev *dev,
1572                         struct rte_intr_handle *intr_handle)
1573 {
1574         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1575         struct e1000_hw *hw =
1576                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1577         struct e1000_interrupt *intr =
1578                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1579         struct rte_eth_link link;
1580         int ret;
1581
1582         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1583                 return -1;
1584
1585         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1586         rte_intr_enable(intr_handle);
1587
1588         /* set get_link_status to check register later */
1589         hw->mac.get_link_status = 1;
1590         ret = eth_em_link_update(dev, 0);
1591
1592         /* check if link has changed */
1593         if (ret < 0)
1594                 return 0;
1595
1596         rte_eth_linkstatus_get(dev, &link);
1597
1598         if (link.link_status) {
1599                 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1600                              dev->data->port_id, link.link_speed,
1601                              link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1602                              "full-duplex" : "half-duplex");
1603         } else {
1604                 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1605         }
1606         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1607                      pci_dev->addr.domain, pci_dev->addr.bus,
1608                      pci_dev->addr.devid, pci_dev->addr.function);
1609
1610         return 0;
1611 }
1612
1613 /**
1614  * Interrupt handler which shall be registered at first.
1615  *
1616  * @param handle
1617  *  Pointer to interrupt handle.
1618  * @param param
1619  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1620  *
1621  * @return
1622  *  void
1623  */
1624 static void
1625 eth_em_interrupt_handler(void *param)
1626 {
1627         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1628
1629         eth_em_interrupt_get_status(dev);
1630         eth_em_interrupt_action(dev, dev->intr_handle);
1631         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1632 }
1633
1634 static int
1635 eth_em_led_on(struct rte_eth_dev *dev)
1636 {
1637         struct e1000_hw *hw;
1638
1639         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1640         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1641 }
1642
1643 static int
1644 eth_em_led_off(struct rte_eth_dev *dev)
1645 {
1646         struct e1000_hw *hw;
1647
1648         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1649         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1650 }
1651
1652 static int
1653 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1654 {
1655         struct e1000_hw *hw;
1656         uint32_t ctrl;
1657         int tx_pause;
1658         int rx_pause;
1659
1660         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1661         fc_conf->pause_time = hw->fc.pause_time;
1662         fc_conf->high_water = hw->fc.high_water;
1663         fc_conf->low_water = hw->fc.low_water;
1664         fc_conf->send_xon = hw->fc.send_xon;
1665         fc_conf->autoneg = hw->mac.autoneg;
1666
1667         /*
1668          * Return rx_pause and tx_pause status according to actual setting of
1669          * the TFCE and RFCE bits in the CTRL register.
1670          */
1671         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1672         if (ctrl & E1000_CTRL_TFCE)
1673                 tx_pause = 1;
1674         else
1675                 tx_pause = 0;
1676
1677         if (ctrl & E1000_CTRL_RFCE)
1678                 rx_pause = 1;
1679         else
1680                 rx_pause = 0;
1681
1682         if (rx_pause && tx_pause)
1683                 fc_conf->mode = RTE_FC_FULL;
1684         else if (rx_pause)
1685                 fc_conf->mode = RTE_FC_RX_PAUSE;
1686         else if (tx_pause)
1687                 fc_conf->mode = RTE_FC_TX_PAUSE;
1688         else
1689                 fc_conf->mode = RTE_FC_NONE;
1690
1691         return 0;
1692 }
1693
1694 static int
1695 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1696 {
1697         struct e1000_hw *hw;
1698         int err;
1699         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1700                 e1000_fc_none,
1701                 e1000_fc_rx_pause,
1702                 e1000_fc_tx_pause,
1703                 e1000_fc_full
1704         };
1705         uint32_t rx_buf_size;
1706         uint32_t max_high_water;
1707         uint32_t rctl;
1708
1709         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1710         if (fc_conf->autoneg != hw->mac.autoneg)
1711                 return -ENOTSUP;
1712         rx_buf_size = em_get_rx_buffer_size(hw);
1713         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1714
1715         /* At least reserve one Ethernet frame for watermark */
1716         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1717         if ((fc_conf->high_water > max_high_water) ||
1718             (fc_conf->high_water < fc_conf->low_water)) {
1719                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1720                 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1721                 return -EINVAL;
1722         }
1723
1724         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1725         hw->fc.pause_time     = fc_conf->pause_time;
1726         hw->fc.high_water     = fc_conf->high_water;
1727         hw->fc.low_water      = fc_conf->low_water;
1728         hw->fc.send_xon       = fc_conf->send_xon;
1729
1730         err = e1000_setup_link_generic(hw);
1731         if (err == E1000_SUCCESS) {
1732
1733                 /* check if we want to forward MAC frames - driver doesn't have native
1734                  * capability to do that, so we'll write the registers ourselves */
1735
1736                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1737
1738                 /* set or clear MFLCN.PMCF bit depending on configuration */
1739                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1740                         rctl |= E1000_RCTL_PMCF;
1741                 else
1742                         rctl &= ~E1000_RCTL_PMCF;
1743
1744                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1745                 E1000_WRITE_FLUSH(hw);
1746
1747                 return 0;
1748         }
1749
1750         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1751         return -EIO;
1752 }
1753
1754 static int
1755 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1756                 uint32_t index, __rte_unused uint32_t pool)
1757 {
1758         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1759
1760         return e1000_rar_set(hw, mac_addr->addr_bytes, index);
1761 }
1762
1763 static void
1764 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1765 {
1766         uint8_t addr[ETHER_ADDR_LEN];
1767         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1768
1769         memset(addr, 0, sizeof(addr));
1770
1771         e1000_rar_set(hw, addr, index);
1772 }
1773
1774 static int
1775 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1776 {
1777         struct rte_eth_dev_info dev_info;
1778         struct e1000_hw *hw;
1779         uint32_t frame_size;
1780         uint32_t rctl;
1781
1782         eth_em_infos_get(dev, &dev_info);
1783         frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1784
1785         /* check that mtu is within the allowed range */
1786         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1787                 return -EINVAL;
1788
1789         /* refuse mtu that requires the support of scattered packets when this
1790          * feature has not been enabled before. */
1791         if (!dev->data->scattered_rx &&
1792             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1793                 return -EINVAL;
1794
1795         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1796         rctl = E1000_READ_REG(hw, E1000_RCTL);
1797
1798         /* switch to jumbo mode if needed */
1799         if (frame_size > ETHER_MAX_LEN) {
1800                 dev->data->dev_conf.rxmode.offloads |=
1801                         DEV_RX_OFFLOAD_JUMBO_FRAME;
1802                 rctl |= E1000_RCTL_LPE;
1803         } else {
1804                 dev->data->dev_conf.rxmode.offloads &=
1805                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1806                 rctl &= ~E1000_RCTL_LPE;
1807         }
1808         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1809
1810         /* update max frame size */
1811         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1812         return 0;
1813 }
1814
1815 static int
1816 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1817                         struct ether_addr *mc_addr_set,
1818                         uint32_t nb_mc_addr)
1819 {
1820         struct e1000_hw *hw;
1821
1822         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1823         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1824         return 0;
1825 }
1826
1827 RTE_PMD_REGISTER_PCI(net_e1000_em, rte_em_pmd);
1828 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_em, pci_id_em_map);
1829 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_em, "* igb_uio | uio_pci_generic | vfio-pci");
1830
1831 RTE_INIT(e1000_init_log);
1832 static void
1833 e1000_init_log(void)
1834 {
1835         e1000_logtype_init = rte_log_register("pmd.net.e1000.init");
1836         if (e1000_logtype_init >= 0)
1837                 rte_log_set_level(e1000_logtype_init, RTE_LOG_NOTICE);
1838         e1000_logtype_driver = rte_log_register("pmd.net.e1000.driver");
1839         if (e1000_logtype_driver >= 0)
1840                 rte_log_set_level(e1000_logtype_driver, RTE_LOG_NOTICE);
1841 }