drivers/net/e1000/em_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <stdarg.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_interrupts.h>
  13 #include <rte_byteorder.h>
  14 #include <rte_log.h>
  15 #include <rte_debug.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_memory.h>
  22 #include <rte_eal.h>
  23 #include <rte_atomic.h>
  24 #include <rte_malloc.h>
  25 #include <rte_dev.h>
  26
  27 #include "e1000_logs.h"
  28 #include "base/e1000_api.h"
  29 #include "e1000_ethdev.h"
  30
  31 #define EM_EIAC                 0x000DC
  32
  33 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
  34
  35
  36 static int eth_em_configure(struct rte_eth_dev *dev);
  37 static int eth_em_start(struct rte_eth_dev *dev);
  38 static void eth_em_stop(struct rte_eth_dev *dev);
  39 static void eth_em_close(struct rte_eth_dev *dev);
  40 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
  41 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
  42 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
  43 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
  44 static int eth_em_link_update(struct rte_eth_dev *dev,
  45                                 int wait_to_complete);
  46 static int eth_em_stats_get(struct rte_eth_dev *dev,
  47                                 struct rte_eth_stats *rte_stats);
  48 static void eth_em_stats_reset(struct rte_eth_dev *dev);
  49 static void eth_em_infos_get(struct rte_eth_dev *dev,
  50                                 struct rte_eth_dev_info *dev_info);
  51 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
  52                                 struct rte_eth_fc_conf *fc_conf);
  53 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
  54                                 struct rte_eth_fc_conf *fc_conf);
  55 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
  56 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
  57 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
  58 static int eth_em_interrupt_action(struct rte_eth_dev *dev,
  59                                    struct rte_intr_handle *handle);
  60 static void eth_em_interrupt_handler(void *param);
  61
  62 static int em_hw_init(struct e1000_hw *hw);
  63 static int em_hardware_init(struct e1000_hw *hw);
  64 static void em_hw_control_acquire(struct e1000_hw *hw);
  65 static void em_hw_control_release(struct e1000_hw *hw);
  66 static void em_init_manageability(struct e1000_hw *hw);
  67 static void em_release_manageability(struct e1000_hw *hw);
  68
  69 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  70
  71 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
  72                 uint16_t vlan_id, int on);
  73 static int eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  74 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
  75 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
  76 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
  77 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
  78
  79 /*
  80 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
  81                                         uint16_t vlan_id, int on);
  82 */
  83
  84 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
  85 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
  86 static void em_lsc_intr_disable(struct e1000_hw *hw);
  87 static void em_rxq_intr_enable(struct e1000_hw *hw);
  88 static void em_rxq_intr_disable(struct e1000_hw *hw);
  89
  90 static int eth_em_led_on(struct rte_eth_dev *dev);
  91 static int eth_em_led_off(struct rte_eth_dev *dev);
  92
  93 static int em_get_rx_buffer_size(struct e1000_hw *hw);
  94 static int eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
  95                           uint32_t index, uint32_t pool);
  96 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
  97
  98 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
  99                                    struct ether_addr *mc_addr_set,
 100                                    uint32_t nb_mc_addr);
 101
 102 #define EM_FC_PAUSE_TIME 0x0680
 103 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 104 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 105
 106 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
 107
 108 int e1000_logtype_init;
 109 int e1000_logtype_driver;
 110
 111 /*
 112  * The set of PCI devices this driver supports
 113  */
 114 static const struct rte_pci_id pci_id_em_map[] = {
 115         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
 116         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
 117         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
 118         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
 119         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
 120         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
 121         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
 122         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
 123         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
 124         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
 125         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
 126         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
 127         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
 128         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
 129         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
 130         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
 131         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
 132         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
 133         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
 134         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
 135         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
 136         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
 137         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
 138         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
 139         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
 140         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
 141         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
 142         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
 143         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
 144         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
 145         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
 146         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM) },
 147         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V) },
 148         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM2) },
 149         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V2) },
 150         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LBG_I219_LM3) },
 151         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM4) },
 152         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V4) },
 153         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM5) },
 154         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V5) },
 155         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM6) },
 156         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V6) },
 157         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM7) },
 158         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V7) },
 159         { .vendor_id = 0, /* sentinel */ },
 160 };
 161
 162 static const struct eth_dev_ops eth_em_ops = {
 163         .dev_configure        = eth_em_configure,
 164         .dev_start            = eth_em_start,
 165         .dev_stop             = eth_em_stop,
 166         .dev_close            = eth_em_close,
 167         .promiscuous_enable   = eth_em_promiscuous_enable,
 168         .promiscuous_disable  = eth_em_promiscuous_disable,
 169         .allmulticast_enable  = eth_em_allmulticast_enable,
 170         .allmulticast_disable = eth_em_allmulticast_disable,
 171         .link_update          = eth_em_link_update,
 172         .stats_get            = eth_em_stats_get,
 173         .stats_reset          = eth_em_stats_reset,
 174         .dev_infos_get        = eth_em_infos_get,
 175         .mtu_set              = eth_em_mtu_set,
 176         .vlan_filter_set      = eth_em_vlan_filter_set,
 177         .vlan_offload_set     = eth_em_vlan_offload_set,
 178         .rx_queue_setup       = eth_em_rx_queue_setup,
 179         .rx_queue_release     = eth_em_rx_queue_release,
 180         .rx_queue_count       = eth_em_rx_queue_count,
 181         .rx_descriptor_done   = eth_em_rx_descriptor_done,
 182         .rx_descriptor_status = eth_em_rx_descriptor_status,
 183         .tx_descriptor_status = eth_em_tx_descriptor_status,
 184         .tx_queue_setup       = eth_em_tx_queue_setup,
 185         .tx_queue_release     = eth_em_tx_queue_release,
 186         .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
 187         .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
 188         .dev_led_on           = eth_em_led_on,
 189         .dev_led_off          = eth_em_led_off,
 190         .flow_ctrl_get        = eth_em_flow_ctrl_get,
 191         .flow_ctrl_set        = eth_em_flow_ctrl_set,
 192         .mac_addr_add         = eth_em_rar_set,
 193         .mac_addr_remove      = eth_em_rar_clear,
 194         .set_mc_addr_list     = eth_em_set_mc_addr_list,
 195         .rxq_info_get         = em_rxq_info_get,
 196         .txq_info_get         = em_txq_info_get,
 197 };
 198
 199 /**
 200  * Atomically reads the link status information from global
 201  * structure rte_eth_dev.
 202  *
 203  * @param dev
 204  *   - Pointer to the structure rte_eth_dev to read from.
 205  *   - Pointer to the buffer to be saved with the link status.
 206  *
 207  * @return
 208  *   - On success, zero.
 209  *   - On failure, negative value.
 210  */
 211 static inline int
 212 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 213                                 struct rte_eth_link *link)
 214 {
 215         struct rte_eth_link *dst = link;
 216         struct rte_eth_link *src = &(dev->data->dev_link);
 217
 218         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 219                                         *(uint64_t *)src) == 0)
 220                 return -1;
 221
 222         return 0;
 223 }
 224
 225 /**
 226  * Atomically writes the link status information into global
 227  * structure rte_eth_dev.
 228  *
 229  * @param dev
 230  *   - Pointer to the structure rte_eth_dev to read from.
 231  *   - Pointer to the buffer to be saved with the link status.
 232  *
 233  * @return
 234  *   - On success, zero.
 235  *   - On failure, negative value.
 236  */
 237 static inline int
 238 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 239                                 struct rte_eth_link *link)
 240 {
 241         struct rte_eth_link *dst = &(dev->data->dev_link);
 242         struct rte_eth_link *src = link;
 243
 244         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 245                                         *(uint64_t *)src) == 0)
 246                 return -1;
 247
 248         return 0;
 249 }
 250
 251 /**
 252  *  eth_em_dev_is_ich8 - Check for ICH8 device
 253  *  @hw: pointer to the HW structure
 254  *
 255  *  return TRUE for ICH8, otherwise FALSE
 256  **/
 257 static bool
 258 eth_em_dev_is_ich8(struct e1000_hw *hw)
 259 {
 260         DEBUGFUNC("eth_em_dev_is_ich8");
 261
 262         switch (hw->device_id) {
 263         case E1000_DEV_ID_PCH_LPT_I217_LM:
 264         case E1000_DEV_ID_PCH_LPT_I217_V:
 265         case E1000_DEV_ID_PCH_LPTLP_I218_LM:
 266         case E1000_DEV_ID_PCH_LPTLP_I218_V:
 267         case E1000_DEV_ID_PCH_I218_V2:
 268         case E1000_DEV_ID_PCH_I218_LM2:
 269         case E1000_DEV_ID_PCH_I218_V3:
 270         case E1000_DEV_ID_PCH_I218_LM3:
 271         case E1000_DEV_ID_PCH_SPT_I219_LM:
 272         case E1000_DEV_ID_PCH_SPT_I219_V:
 273         case E1000_DEV_ID_PCH_SPT_I219_LM2:
 274         case E1000_DEV_ID_PCH_SPT_I219_V2:
 275         case E1000_DEV_ID_PCH_LBG_I219_LM3:
 276         case E1000_DEV_ID_PCH_SPT_I219_LM4:
 277         case E1000_DEV_ID_PCH_SPT_I219_V4:
 278         case E1000_DEV_ID_PCH_SPT_I219_LM5:
 279         case E1000_DEV_ID_PCH_SPT_I219_V5:
 280         case E1000_DEV_ID_PCH_CNP_I219_LM6:
 281         case E1000_DEV_ID_PCH_CNP_I219_V6:
 282         case E1000_DEV_ID_PCH_CNP_I219_LM7:
 283         case E1000_DEV_ID_PCH_CNP_I219_V7:
 284                 return 1;
 285         default:
 286                 return 0;
 287         }
 288 }
 289
 290 static int
 291 eth_em_dev_init(struct rte_eth_dev *eth_dev)
 292 {
 293         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 294         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 295         struct e1000_adapter *adapter =
 296                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 297         struct e1000_hw *hw =
 298                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 299         struct e1000_vfta * shadow_vfta =
 300                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 301
 302         eth_dev->dev_ops = &eth_em_ops;
 303         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
 304         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
 305         eth_dev->tx_pkt_prepare = (eth_tx_prep_t)&eth_em_prep_pkts;
 306
 307         /* for secondary processes, we don't initialise any further as primary
 308          * has already done this work. Only check we don't need a different
 309          * RX function */
 310         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 311                 if (eth_dev->data->scattered_rx)
 312                         eth_dev->rx_pkt_burst =
 313                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
 314                 return 0;
 315         }
 316
 317         rte_eth_copy_pci_info(eth_dev, pci_dev);
 318
 319         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 320         hw->device_id = pci_dev->id.device_id;
 321         adapter->stopped = 0;
 322
 323         /* For ICH8 support we'll need to map the flash memory BAR */
 324         if (eth_em_dev_is_ich8(hw))
 325                 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
 326
 327         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
 328                         em_hw_init(hw) != 0) {
 329                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
 330                         "failed to init HW",
 331                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 332                         pci_dev->id.device_id);
 333                 return -ENODEV;
 334         }
 335
 336         /* Allocate memory for storing MAC addresses */
 337         eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
 338                         hw->mac.rar_entry_count, 0);
 339         if (eth_dev->data->mac_addrs == NULL) {
 340                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 341                         "store MAC addresses",
 342                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 343                 return -ENOMEM;
 344         }
 345
 346         /* Copy the permanent MAC address */
 347         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 348                 eth_dev->data->mac_addrs);
 349
 350         /* initialize the vfta */
 351         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 352
 353         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 354                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 355                      pci_dev->id.device_id);
 356
 357         rte_intr_callback_register(intr_handle,
 358                                    eth_em_interrupt_handler, eth_dev);
 359
 360         return 0;
 361 }
 362
 363 static int
 364 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
 365 {
 366         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 367         struct e1000_adapter *adapter =
 368                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 369         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 370
 371         PMD_INIT_FUNC_TRACE();
 372
 373         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 374                 return -EPERM;
 375
 376         if (adapter->stopped == 0)
 377                 eth_em_close(eth_dev);
 378
 379         eth_dev->dev_ops = NULL;
 380         eth_dev->rx_pkt_burst = NULL;
 381         eth_dev->tx_pkt_burst = NULL;
 382
 383         rte_free(eth_dev->data->mac_addrs);
 384         eth_dev->data->mac_addrs = NULL;
 385
 386         /* disable uio intr before callback unregister */
 387         rte_intr_disable(intr_handle);
 388         rte_intr_callback_unregister(intr_handle,
 389                                      eth_em_interrupt_handler, eth_dev);
 390
 391         return 0;
 392 }
 393
 394 static int eth_em_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 395         struct rte_pci_device *pci_dev)
 396 {
 397         return rte_eth_dev_pci_generic_probe(pci_dev,
 398                 sizeof(struct e1000_adapter), eth_em_dev_init);
 399 }
 400
 401 static int eth_em_pci_remove(struct rte_pci_device *pci_dev)
 402 {
 403         return rte_eth_dev_pci_generic_remove(pci_dev, eth_em_dev_uninit);
 404 }
 405
 406 static struct rte_pci_driver rte_em_pmd = {
 407         .id_table = pci_id_em_map,
 408         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 409                      RTE_PCI_DRV_IOVA_AS_VA,
 410         .probe = eth_em_pci_probe,
 411         .remove = eth_em_pci_remove,
 412 };
 413
 414 static int
 415 em_hw_init(struct e1000_hw *hw)
 416 {
 417         int diag;
 418
 419         diag = hw->mac.ops.init_params(hw);
 420         if (diag != 0) {
 421                 PMD_INIT_LOG(ERR, "MAC Initialization Error");
 422                 return diag;
 423         }
 424         diag = hw->nvm.ops.init_params(hw);
 425         if (diag != 0) {
 426                 PMD_INIT_LOG(ERR, "NVM Initialization Error");
 427                 return diag;
 428         }
 429         diag = hw->phy.ops.init_params(hw);
 430         if (diag != 0) {
 431                 PMD_INIT_LOG(ERR, "PHY Initialization Error");
 432                 return diag;
 433         }
 434         (void) e1000_get_bus_info(hw);
 435
 436         hw->mac.autoneg = 1;
 437         hw->phy.autoneg_wait_to_complete = 0;
 438         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 439
 440         e1000_init_script_state_82541(hw, TRUE);
 441         e1000_set_tbi_compatibility_82543(hw, TRUE);
 442
 443         /* Copper options */
 444         if (hw->phy.media_type == e1000_media_type_copper) {
 445                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 446                 hw->phy.disable_polarity_correction = 0;
 447                 hw->phy.ms_type = e1000_ms_hw_default;
 448         }
 449
 450         /*
 451          * Start from a known state, this is important in reading the nvm
 452          * and mac from that.
 453          */
 454         e1000_reset_hw(hw);
 455
 456         /* Make sure we have a good EEPROM before we read from it */
 457         if (e1000_validate_nvm_checksum(hw) < 0) {
 458                 /*
 459                  * Some PCI-E parts fail the first check due to
 460                  * the link being in sleep state, call it again,
 461                  * if it fails a second time its a real issue.
 462                  */
 463                 diag = e1000_validate_nvm_checksum(hw);
 464                 if (diag < 0) {
 465                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 466                         goto error;
 467                 }
 468         }
 469
 470         /* Read the permanent MAC address out of the EEPROM */
 471         diag = e1000_read_mac_addr(hw);
 472         if (diag != 0) {
 473                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 474                 goto error;
 475         }
 476
 477         /* Now initialize the hardware */
 478         diag = em_hardware_init(hw);
 479         if (diag != 0) {
 480                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 481                 goto error;
 482         }
 483
 484         hw->mac.get_link_status = 1;
 485
 486         /* Indicate SOL/IDER usage */
 487         diag = e1000_check_reset_block(hw);
 488         if (diag < 0) {
 489                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
 490                         "SOL/IDER session");
 491         }
 492         return 0;
 493
 494 error:
 495         em_hw_control_release(hw);
 496         return diag;
 497 }
 498
 499 static int
 500 eth_em_configure(struct rte_eth_dev *dev)
 501 {
 502         struct e1000_interrupt *intr =
 503                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 504
 505         PMD_INIT_FUNC_TRACE();
 506         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 507         PMD_INIT_FUNC_TRACE();
 508
 509         return 0;
 510 }
 511
 512 static void
 513 em_set_pba(struct e1000_hw *hw)
 514 {
 515         uint32_t pba;
 516
 517         /*
 518          * Packet Buffer Allocation (PBA)
 519          * Writing PBA sets the receive portion of the buffer
 520          * the remainder is used for the transmit buffer.
 521          * Devices before the 82547 had a Packet Buffer of 64K.
 522          * After the 82547 the buffer was reduced to 40K.
 523          */
 524         switch (hw->mac.type) {
 525                 case e1000_82547:
 526                 case e1000_82547_rev_2:
 527                 /* 82547: Total Packet Buffer is 40K */
 528                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
 529                         break;
 530                 case e1000_82571:
 531                 case e1000_82572:
 532                 case e1000_80003es2lan:
 533                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 534                         break;
 535                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
 536                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
 537                         break;
 538                 case e1000_82574:
 539                 case e1000_82583:
 540                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
 541                         break;
 542                 case e1000_ich8lan:
 543                         pba = E1000_PBA_8K;
 544                         break;
 545                 case e1000_ich9lan:
 546                 case e1000_ich10lan:
 547                         pba = E1000_PBA_10K;
 548                         break;
 549                 case e1000_pchlan:
 550                 case e1000_pch2lan:
 551                 case e1000_pch_lpt:
 552                 case e1000_pch_spt:
 553                 case e1000_pch_cnp:
 554                         pba = E1000_PBA_26K;
 555                         break;
 556                 default:
 557                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
 558         }
 559
 560         E1000_WRITE_REG(hw, E1000_PBA, pba);
 561 }
 562
 563 static int
 564 eth_em_start(struct rte_eth_dev *dev)
 565 {
 566         struct e1000_adapter *adapter =
 567                 E1000_DEV_PRIVATE(dev->data->dev_private);
 568         struct e1000_hw *hw =
 569                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 570         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 571         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 572         int ret, mask;
 573         uint32_t intr_vector = 0;
 574         uint32_t *speeds;
 575         int num_speeds;
 576         bool autoneg;
 577
 578         PMD_INIT_FUNC_TRACE();
 579
 580         eth_em_stop(dev);
 581
 582         e1000_power_up_phy(hw);
 583
 584         /* Set default PBA value */
 585         em_set_pba(hw);
 586
 587         /* Put the address into the Receive Address Array */
 588         e1000_rar_set(hw, hw->mac.addr, 0);
 589
 590         /*
 591          * With the 82571 adapter, RAR[0] may be overwritten
 592          * when the other port is reset, we make a duplicate
 593          * in RAR[14] for that eventuality, this assures
 594          * the interface continues to function.
 595          */
 596         if (hw->mac.type == e1000_82571) {
 597                 e1000_set_laa_state_82571(hw, TRUE);
 598                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
 599         }
 600
 601         /* Initialize the hardware */
 602         if (em_hardware_init(hw)) {
 603                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 604                 return -EIO;
 605         }
 606
 607         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 608
 609         /* Configure for OS presence */
 610         em_init_manageability(hw);
 611
 612         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 613                 intr_vector = dev->data->nb_rx_queues;
 614                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 615                         return -1;
 616         }
 617
 618         if (rte_intr_dp_is_en(intr_handle)) {
 619                 intr_handle->intr_vec =
 620                         rte_zmalloc("intr_vec",
 621                                         dev->data->nb_rx_queues * sizeof(int), 0);
 622                 if (intr_handle->intr_vec == NULL) {
 623                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 624                                                 " intr_vec", dev->data->nb_rx_queues);
 625                         return -ENOMEM;
 626                 }
 627
 628                 /* enable rx interrupt */
 629                 em_rxq_intr_enable(hw);
 630         }
 631
 632         eth_em_tx_init(dev);
 633
 634         ret = eth_em_rx_init(dev);
 635         if (ret) {
 636                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 637                 em_dev_clear_queues(dev);
 638                 return ret;
 639         }
 640
 641         e1000_clear_hw_cntrs_base_generic(hw);
 642
 643         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 644                         ETH_VLAN_EXTEND_MASK;
 645         ret = eth_em_vlan_offload_set(dev, mask);
 646         if (ret) {
 647                 PMD_INIT_LOG(ERR, "Unable to update vlan offload");
 648                 em_dev_clear_queues(dev);
 649                 return ret;
 650         }
 651
 652         /* Set Interrupt Throttling Rate to maximum allowed value. */
 653         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
 654
 655         /* Setup link speed and duplex */
 656         speeds = &dev->data->dev_conf.link_speeds;
 657         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
 658                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 659                 hw->mac.autoneg = 1;
 660         } else {
 661                 num_speeds = 0;
 662                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
 663
 664                 /* Reset */
 665                 hw->phy.autoneg_advertised = 0;
 666
 667                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
 668                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
 669                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
 670                         num_speeds = -1;
 671                         goto error_invalid_config;
 672                 }
 673                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
 674                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
 675                         num_speeds++;
 676                 }
 677                 if (*speeds & ETH_LINK_SPEED_10M) {
 678                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
 679                         num_speeds++;
 680                 }
 681                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
 682                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
 683                         num_speeds++;
 684                 }
 685                 if (*speeds & ETH_LINK_SPEED_100M) {
 686                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
 687                         num_speeds++;
 688                 }
 689                 if (*speeds & ETH_LINK_SPEED_1G) {
 690                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
 691                         num_speeds++;
 692                 }
 693                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
 694                         goto error_invalid_config;
 695
 696                 /* Set/reset the mac.autoneg based on the link speed,
 697                  * fixed or not
 698                  */
 699                 if (!autoneg) {
 700                         hw->mac.autoneg = 0;
 701                         hw->mac.forced_speed_duplex =
 702                                         hw->phy.autoneg_advertised;
 703                 } else {
 704                         hw->mac.autoneg = 1;
 705                 }
 706         }
 707
 708         e1000_setup_link(hw);
 709
 710         if (rte_intr_allow_others(intr_handle)) {
 711                 /* check if lsc interrupt is enabled */
 712                 if (dev->data->dev_conf.intr_conf.lsc != 0) {
 713                         ret = eth_em_interrupt_setup(dev);
 714                         if (ret) {
 715                                 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
 716                                 em_dev_clear_queues(dev);
 717                                 return ret;
 718                         }
 719                 }
 720         } else {
 721                 rte_intr_callback_unregister(intr_handle,
 722                                                 eth_em_interrupt_handler,
 723                                                 (void *)dev);
 724                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 725                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
 726                                      " no intr multiplexn");
 727         }
 728         /* check if rxq interrupt is enabled */
 729         if (dev->data->dev_conf.intr_conf.rxq != 0)
 730                 eth_em_rxq_interrupt_setup(dev);
 731
 732         rte_intr_enable(intr_handle);
 733
 734         adapter->stopped = 0;
 735
 736         PMD_INIT_LOG(DEBUG, "<<");
 737
 738         return 0;
 739
 740 error_invalid_config:
 741         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
 742                      dev->data->dev_conf.link_speeds, dev->data->port_id);
 743         em_dev_clear_queues(dev);
 744         return -EINVAL;
 745 }
 746
 747 /*********************************************************************
 748  *
 749  *  This routine disables all traffic on the adapter by issuing a
 750  *  global reset on the MAC.
 751  *
 752  **********************************************************************/
 753 static void
 754 eth_em_stop(struct rte_eth_dev *dev)
 755 {
 756         struct rte_eth_link link;
 757         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 758         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 759         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 760
 761         em_rxq_intr_disable(hw);
 762         em_lsc_intr_disable(hw);
 763
 764         e1000_reset_hw(hw);
 765         if (hw->mac.type >= e1000_82544)
 766                 E1000_WRITE_REG(hw, E1000_WUC, 0);
 767
 768         /* Power down the phy. Needed to make the link go down */
 769         e1000_power_down_phy(hw);
 770
 771         em_dev_clear_queues(dev);
 772
 773         /* clear the recorded link status */
 774         memset(&link, 0, sizeof(link));
 775         rte_em_dev_atomic_write_link_status(dev, &link);
 776
 777         if (!rte_intr_allow_others(intr_handle))
 778                 /* resume to the default handler */
 779                 rte_intr_callback_register(intr_handle,
 780                                            eth_em_interrupt_handler,
 781                                            (void *)dev);
 782
 783         /* Clean datapath event and queue/vec mapping */
 784         rte_intr_efd_disable(intr_handle);
 785         if (intr_handle->intr_vec != NULL) {
 786                 rte_free(intr_handle->intr_vec);
 787                 intr_handle->intr_vec = NULL;
 788         }
 789 }
 790
 791 static void
 792 eth_em_close(struct rte_eth_dev *dev)
 793 {
 794         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 795         struct e1000_adapter *adapter =
 796                 E1000_DEV_PRIVATE(dev->data->dev_private);
 797
 798         eth_em_stop(dev);
 799         adapter->stopped = 1;
 800         em_dev_free_queues(dev);
 801         e1000_phy_hw_reset(hw);
 802         em_release_manageability(hw);
 803         em_hw_control_release(hw);
 804 }
 805
 806 static int
 807 em_get_rx_buffer_size(struct e1000_hw *hw)
 808 {
 809         uint32_t rx_buf_size;
 810
 811         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
 812         return rx_buf_size;
 813 }
 814
 815 /*********************************************************************
 816  *
 817  *  Initialize the hardware
 818  *
 819  **********************************************************************/
 820 static int
 821 em_hardware_init(struct e1000_hw *hw)
 822 {
 823         uint32_t rx_buf_size;
 824         int diag;
 825
 826         /* Issue a global reset */
 827         e1000_reset_hw(hw);
 828
 829         /* Let the firmware know the OS is in control */
 830         em_hw_control_acquire(hw);
 831
 832         /*
 833          * These parameters control the automatic generation (Tx) and
 834          * response (Rx) to Ethernet PAUSE frames.
 835          * - High water mark should allow for at least two standard size (1518)
 836          *   frames to be received after sending an XOFF.
 837          * - Low water mark works best when it is very near the high water mark.
 838          *   This allows the receiver to restart by sending XON when it has
 839          *   drained a bit. Here we use an arbitrary value of 1500 which will
 840          *   restart after one full frame is pulled from the buffer. There
 841          *   could be several smaller frames in the buffer and if so they will
 842          *   not trigger the XON until their total number reduces the buffer
 843          *   by 1500.
 844          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 845          */
 846         rx_buf_size = em_get_rx_buffer_size(hw);
 847
 848         hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
 849         hw->fc.low_water = hw->fc.high_water - 1500;
 850
 851         if (hw->mac.type == e1000_80003es2lan)
 852                 hw->fc.pause_time = UINT16_MAX;
 853         else
 854                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
 855
 856         hw->fc.send_xon = 1;
 857
 858         /* Set Flow control, use the tunable location if sane */
 859         if (em_fc_setting <= e1000_fc_full)
 860                 hw->fc.requested_mode = em_fc_setting;
 861         else
 862                 hw->fc.requested_mode = e1000_fc_none;
 863
 864         /* Workaround: no TX flow ctrl for PCH */
 865         if (hw->mac.type == e1000_pchlan)
 866                 hw->fc.requested_mode = e1000_fc_rx_pause;
 867
 868         /* Override - settings for PCH2LAN, ya its magic :) */
 869         if (hw->mac.type == e1000_pch2lan) {
 870                 hw->fc.high_water = 0x5C20;
 871                 hw->fc.low_water = 0x5048;
 872                 hw->fc.pause_time = 0x0650;
 873                 hw->fc.refresh_time = 0x0400;
 874         } else if (hw->mac.type == e1000_pch_lpt ||
 875                    hw->mac.type == e1000_pch_spt ||
 876                    hw->mac.type == e1000_pch_cnp) {
 877                 hw->fc.requested_mode = e1000_fc_full;
 878         }
 879
 880         diag = e1000_init_hw(hw);
 881         if (diag < 0)
 882                 return diag;
 883         e1000_check_for_link(hw);
 884         return 0;
 885 }
 886
 887 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
 888 static int
 889 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 890 {
 891         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 892         struct e1000_hw_stats *stats =
 893                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 894         int pause_frames;
 895
 896         if(hw->phy.media_type == e1000_media_type_copper ||
 897                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 898                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
 899                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 900         }
 901
 902         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 903         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 904         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 905         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 906
 907         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 908         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 909         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 910         stats->dc += E1000_READ_REG(hw, E1000_DC);
 911         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 912         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 913         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 914
 915         /*
 916          * For watchdog management we need to know if we have been
 917          * paused during the last interval, so capture that here.
 918          */
 919         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 920         stats->xoffrxc += pause_frames;
 921         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 922         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 923         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 924         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 925         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 926         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 927         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 928         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 929         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 930         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 931         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 932         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 933
 934         /*
 935          * For the 64-bit byte counters the low dword must be read first.
 936          * Both registers clear on the read of the high dword.
 937          */
 938
 939         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 940         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 941         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 942         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 943
 944         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 945         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 946         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 947         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 948         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 949
 950         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 951         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 952
 953         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 954         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 955         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 956         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 957         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 958         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 959         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 960         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 961         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 962         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 963
 964         /* Interrupt Counts */
 965
 966         if (hw->mac.type >= e1000_82571) {
 967                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
 968                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 969                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 970                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 971                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 972                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 973                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 974                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 975                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 976         }
 977
 978         if (hw->mac.type >= e1000_82543) {
 979                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 980                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 981                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 982                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 983                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 984                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 985         }
 986
 987         if (rte_stats == NULL)
 988                 return -EINVAL;
 989
 990         /* Rx Errors */
 991         rte_stats->imissed = stats->mpc;
 992         rte_stats->ierrors = stats->crcerrs +
 993                              stats->rlec + stats->ruc + stats->roc +
 994                              stats->rxerrc + stats->algnerrc + stats->cexterr;
 995
 996         /* Tx Errors */
 997         rte_stats->oerrors = stats->ecol + stats->latecol;
 998
 999         rte_stats->ipackets = stats->gprc;
1000         rte_stats->opackets = stats->gptc;
1001         rte_stats->ibytes   = stats->gorc;
1002         rte_stats->obytes   = stats->gotc;
1003         return 0;
1004 }
1005
1006 static void
1007 eth_em_stats_reset(struct rte_eth_dev *dev)
1008 {
1009         struct e1000_hw_stats *hw_stats =
1010                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1011
1012         /* HW registers are cleared on read */
1013         eth_em_stats_get(dev, NULL);
1014
1015         /* Reset software totals */
1016         memset(hw_stats, 0, sizeof(*hw_stats));
1017 }
1018
1019 static int
1020 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1021 {
1022         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1023         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1024         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1025
1026         em_rxq_intr_enable(hw);
1027         rte_intr_enable(intr_handle);
1028
1029         return 0;
1030 }
1031
1032 static int
1033 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1034 {
1035         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1036
1037         em_rxq_intr_disable(hw);
1038
1039         return 0;
1040 }
1041
1042 static uint32_t
1043 em_get_max_pktlen(const struct e1000_hw *hw)
1044 {
1045         switch (hw->mac.type) {
1046         case e1000_82571:
1047         case e1000_82572:
1048         case e1000_ich9lan:
1049         case e1000_ich10lan:
1050         case e1000_pch2lan:
1051         case e1000_pch_lpt:
1052         case e1000_pch_spt:
1053         case e1000_pch_cnp:
1054         case e1000_82574:
1055         case e1000_80003es2lan: /* 9K Jumbo Frame size */
1056         case e1000_82583:
1057                 return 0x2412;
1058         case e1000_pchlan:
1059                 return 0x1000;
1060         /* Adapters that do not support jumbo frames */
1061         case e1000_ich8lan:
1062                 return ETHER_MAX_LEN;
1063         default:
1064                 return MAX_JUMBO_FRAME_SIZE;
1065         }
1066 }
1067
1068 static void
1069 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1070 {
1071         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1072
1073         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1074         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1075         dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
1076         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1077         dev_info->rx_offload_capa =
1078                 DEV_RX_OFFLOAD_VLAN_STRIP |
1079                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1080                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1081                 DEV_RX_OFFLOAD_TCP_CKSUM;
1082         dev_info->tx_offload_capa =
1083                 DEV_TX_OFFLOAD_VLAN_INSERT |
1084                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1085                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1086                 DEV_TX_OFFLOAD_TCP_CKSUM;
1087
1088         /*
1089          * Starting with 631xESB hw supports 2 TX/RX queues per port.
1090          * Unfortunatelly, all these nics have just one TX context.
1091          * So we have few choises for TX:
1092          * - Use just one TX queue.
1093          * - Allow cksum offload only for one TX queue.
1094          * - Don't allow TX cksum offload at all.
1095          * For now, option #1 was chosen.
1096          * To use second RX queue we have to use extended RX descriptor
1097          * (Multiple Receive Queues are mutually exclusive with UDP
1098          * fragmentation and are not supported when a legacy receive
1099          * descriptor format is used).
1100          * Which means separate RX routinies - as legacy nics (82540, 82545)
1101          * don't support extended RXD.
1102          * To avoid it we support just one RX queue for now (no RSS).
1103          */
1104
1105         dev_info->max_rx_queues = 1;
1106         dev_info->max_tx_queues = 1;
1107
1108         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1109                 .nb_max = E1000_MAX_RING_DESC,
1110                 .nb_min = E1000_MIN_RING_DESC,
1111                 .nb_align = EM_RXD_ALIGN,
1112         };
1113
1114         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1115                 .nb_max = E1000_MAX_RING_DESC,
1116                 .nb_min = E1000_MIN_RING_DESC,
1117                 .nb_align = EM_TXD_ALIGN,
1118                 .nb_seg_max = EM_TX_MAX_SEG,
1119                 .nb_mtu_seg_max = EM_TX_MAX_MTU_SEG,
1120         };
1121
1122         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1123                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1124                         ETH_LINK_SPEED_1G;
1125 }
1126
1127 /* return 0 means link status changed, -1 means not changed */
1128 static int
1129 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1130 {
1131         struct e1000_hw *hw =
1132                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1133         struct rte_eth_link link, old;
1134         int link_check, count;
1135
1136         link_check = 0;
1137         hw->mac.get_link_status = 1;
1138
1139         /* possible wait-to-complete in up to 9 seconds */
1140         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1141                 /* Read the real link status */
1142                 switch (hw->phy.media_type) {
1143                 case e1000_media_type_copper:
1144                         /* Do the work to read phy */
1145                         e1000_check_for_link(hw);
1146                         link_check = !hw->mac.get_link_status;
1147                         break;
1148
1149                 case e1000_media_type_fiber:
1150                         e1000_check_for_link(hw);
1151                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1152                                         E1000_STATUS_LU);
1153                         break;
1154
1155                 case e1000_media_type_internal_serdes:
1156                         e1000_check_for_link(hw);
1157                         link_check = hw->mac.serdes_has_link;
1158                         break;
1159
1160                 default:
1161                         break;
1162                 }
1163                 if (link_check || wait_to_complete == 0)
1164                         break;
1165                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1166         }
1167         memset(&link, 0, sizeof(link));
1168         rte_em_dev_atomic_read_link_status(dev, &link);
1169         old = link;
1170
1171         /* Now we check if a transition has happened */
1172         if (link_check && (link.link_status == ETH_LINK_DOWN)) {
1173                 uint16_t duplex, speed;
1174                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1175                 link.link_duplex = (duplex == FULL_DUPLEX) ?
1176                                 ETH_LINK_FULL_DUPLEX :
1177                                 ETH_LINK_HALF_DUPLEX;
1178                 link.link_speed = speed;
1179                 link.link_status = ETH_LINK_UP;
1180                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1181                                 ETH_LINK_SPEED_FIXED);
1182         } else if (!link_check && (link.link_status == ETH_LINK_UP)) {
1183                 link.link_speed = 0;
1184                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1185                 link.link_status = ETH_LINK_DOWN;
1186                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
1187         }
1188         rte_em_dev_atomic_write_link_status(dev, &link);
1189
1190         /* not changed */
1191         if (old.link_status == link.link_status)
1192                 return -1;
1193
1194         /* changed */
1195         return 0;
1196 }
1197
1198 /*
1199  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1200  * For ASF and Pass Through versions of f/w this means
1201  * that the driver is loaded. For AMT version type f/w
1202  * this means that the network i/f is open.
1203  */
1204 static void
1205 em_hw_control_acquire(struct e1000_hw *hw)
1206 {
1207         uint32_t ctrl_ext, swsm;
1208
1209         /* Let firmware know the driver has taken over */
1210         if (hw->mac.type == e1000_82573) {
1211                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1212                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1213
1214         } else {
1215                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1216                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1217                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1218         }
1219 }
1220
1221 /*
1222  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1223  * For ASF and Pass Through versions of f/w this means that the
1224  * driver is no longer loaded. For AMT versions of the
1225  * f/w this means that the network i/f is closed.
1226  */
1227 static void
1228 em_hw_control_release(struct e1000_hw *hw)
1229 {
1230         uint32_t ctrl_ext, swsm;
1231
1232         /* Let firmware taken over control of h/w */
1233         if (hw->mac.type == e1000_82573) {
1234                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1235                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1236         } else {
1237                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1238                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1239                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1240         }
1241 }
1242
1243 /*
1244  * Bit of a misnomer, what this really means is
1245  * to enable OS management of the system... aka
1246  * to disable special hardware management features.
1247  */
1248 static void
1249 em_init_manageability(struct e1000_hw *hw)
1250 {
1251         if (e1000_enable_mng_pass_thru(hw)) {
1252                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1253                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1254
1255                 /* disable hardware interception of ARP */
1256                 manc &= ~(E1000_MANC_ARP_EN);
1257
1258                 /* enable receiving management packets to the host */
1259                 manc |= E1000_MANC_EN_MNG2HOST;
1260                 manc2h |= 1 << 5;  /* Mng Port 623 */
1261                 manc2h |= 1 << 6;  /* Mng Port 664 */
1262                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1263                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1264         }
1265 }
1266
1267 /*
1268  * Give control back to hardware management
1269  * controller if there is one.
1270  */
1271 static void
1272 em_release_manageability(struct e1000_hw *hw)
1273 {
1274         uint32_t manc;
1275
1276         if (e1000_enable_mng_pass_thru(hw)) {
1277                 manc = E1000_READ_REG(hw, E1000_MANC);
1278
1279                 /* re-enable hardware interception of ARP */
1280                 manc |= E1000_MANC_ARP_EN;
1281                 manc &= ~E1000_MANC_EN_MNG2HOST;
1282
1283                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1284         }
1285 }
1286
1287 static void
1288 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1289 {
1290         struct e1000_hw *hw =
1291                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1292         uint32_t rctl;
1293
1294         rctl = E1000_READ_REG(hw, E1000_RCTL);
1295         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1296         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1297 }
1298
1299 static void
1300 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1301 {
1302         struct e1000_hw *hw =
1303                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1304         uint32_t rctl;
1305
1306         rctl = E1000_READ_REG(hw, E1000_RCTL);
1307         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1308         if (dev->data->all_multicast == 1)
1309                 rctl |= E1000_RCTL_MPE;
1310         else
1311                 rctl &= (~E1000_RCTL_MPE);
1312         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1313 }
1314
1315 static void
1316 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1317 {
1318         struct e1000_hw *hw =
1319                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1320         uint32_t rctl;
1321
1322         rctl = E1000_READ_REG(hw, E1000_RCTL);
1323         rctl |= E1000_RCTL_MPE;
1324         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1325 }
1326
1327 static void
1328 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1329 {
1330         struct e1000_hw *hw =
1331                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1332         uint32_t rctl;
1333
1334         if (dev->data->promiscuous == 1)
1335                 return; /* must remain in all_multicast mode */
1336         rctl = E1000_READ_REG(hw, E1000_RCTL);
1337         rctl &= (~E1000_RCTL_MPE);
1338         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1339 }
1340
1341 static int
1342 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1343 {
1344         struct e1000_hw *hw =
1345                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1346         struct e1000_vfta * shadow_vfta =
1347                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1348         uint32_t vfta;
1349         uint32_t vid_idx;
1350         uint32_t vid_bit;
1351
1352         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1353                               E1000_VFTA_ENTRY_MASK);
1354         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1355         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1356         if (on)
1357                 vfta |= vid_bit;
1358         else
1359                 vfta &= ~vid_bit;
1360         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1361
1362         /* update local VFTA copy */
1363         shadow_vfta->vfta[vid_idx] = vfta;
1364
1365         return 0;
1366 }
1367
1368 static void
1369 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1370 {
1371         struct e1000_hw *hw =
1372                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1373         uint32_t reg;
1374
1375         /* Filter Table Disable */
1376         reg = E1000_READ_REG(hw, E1000_RCTL);
1377         reg &= ~E1000_RCTL_CFIEN;
1378         reg &= ~E1000_RCTL_VFE;
1379         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1380 }
1381
1382 static void
1383 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1384 {
1385         struct e1000_hw *hw =
1386                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1387         struct e1000_vfta * shadow_vfta =
1388                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1389         uint32_t reg;
1390         int i;
1391
1392         /* Filter Table Enable, CFI not used for packet acceptance */
1393         reg = E1000_READ_REG(hw, E1000_RCTL);
1394         reg &= ~E1000_RCTL_CFIEN;
1395         reg |= E1000_RCTL_VFE;
1396         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1397
1398         /* restore vfta from local copy */
1399         for (i = 0; i < IGB_VFTA_SIZE; i++)
1400                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1401 }
1402
1403 static void
1404 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1405 {
1406         struct e1000_hw *hw =
1407                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1408         uint32_t reg;
1409
1410         /* VLAN Mode Disable */
1411         reg = E1000_READ_REG(hw, E1000_CTRL);
1412         reg &= ~E1000_CTRL_VME;
1413         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1414
1415 }
1416
1417 static void
1418 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1419 {
1420         struct e1000_hw *hw =
1421                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1422         uint32_t reg;
1423
1424         /* VLAN Mode Enable */
1425         reg = E1000_READ_REG(hw, E1000_CTRL);
1426         reg |= E1000_CTRL_VME;
1427         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1428 }
1429
1430 static int
1431 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1432 {
1433         if(mask & ETH_VLAN_STRIP_MASK){
1434                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1435                         em_vlan_hw_strip_enable(dev);
1436                 else
1437                         em_vlan_hw_strip_disable(dev);
1438         }
1439
1440         if(mask & ETH_VLAN_FILTER_MASK){
1441                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1442                         em_vlan_hw_filter_enable(dev);
1443                 else
1444                         em_vlan_hw_filter_disable(dev);
1445         }
1446
1447         return 0;
1448 }
1449
1450 /*
1451  * It enables the interrupt mask and then enable the interrupt.
1452  *
1453  * @param dev
1454  *  Pointer to struct rte_eth_dev.
1455  *
1456  * @return
1457  *  - On success, zero.
1458  *  - On failure, a negative value.
1459  */
1460 static int
1461 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1462 {
1463         uint32_t regval;
1464         struct e1000_hw *hw =
1465                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1466
1467         /* clear interrupt */
1468         E1000_READ_REG(hw, E1000_ICR);
1469         regval = E1000_READ_REG(hw, E1000_IMS);
1470         E1000_WRITE_REG(hw, E1000_IMS, regval | E1000_ICR_LSC);
1471         return 0;
1472 }
1473
1474 /*
1475  * It clears the interrupt causes and enables the interrupt.
1476  * It will be called once only during nic initialized.
1477  *
1478  * @param dev
1479  *  Pointer to struct rte_eth_dev.
1480  *
1481  * @return
1482  *  - On success, zero.
1483  *  - On failure, a negative value.
1484  */
1485 static int
1486 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1487 {
1488         struct e1000_hw *hw =
1489         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1490
1491         E1000_READ_REG(hw, E1000_ICR);
1492         em_rxq_intr_enable(hw);
1493         return 0;
1494 }
1495
1496 /*
1497  * It enable receive packet interrupt.
1498  * @param hw
1499  * Pointer to struct e1000_hw
1500  *
1501  * @return
1502  */
1503 static void
1504 em_rxq_intr_enable(struct e1000_hw *hw)
1505 {
1506         E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1507         E1000_WRITE_FLUSH(hw);
1508 }
1509
1510 /*
1511  * It disabled lsc interrupt.
1512  * @param hw
1513  * Pointer to struct e1000_hw
1514  *
1515  * @return
1516  */
1517 static void
1518 em_lsc_intr_disable(struct e1000_hw *hw)
1519 {
1520         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC);
1521         E1000_WRITE_FLUSH(hw);
1522 }
1523
1524 /*
1525  * It disabled receive packet interrupt.
1526  * @param hw
1527  * Pointer to struct e1000_hw
1528  *
1529  * @return
1530  */
1531 static void
1532 em_rxq_intr_disable(struct e1000_hw *hw)
1533 {
1534         E1000_READ_REG(hw, E1000_ICR);
1535         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1536         E1000_WRITE_FLUSH(hw);
1537 }
1538
1539 /*
1540  * It reads ICR and gets interrupt causes, check it and set a bit flag
1541  * to update link status.
1542  *
1543  * @param dev
1544  *  Pointer to struct rte_eth_dev.
1545  *
1546  * @return
1547  *  - On success, zero.
1548  *  - On failure, a negative value.
1549  */
1550 static int
1551 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1552 {
1553         uint32_t icr;
1554         struct e1000_hw *hw =
1555                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1556         struct e1000_interrupt *intr =
1557                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1558
1559         /* read-on-clear nic registers here */
1560         icr = E1000_READ_REG(hw, E1000_ICR);
1561         if (icr & E1000_ICR_LSC) {
1562                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1563         }
1564
1565         return 0;
1566 }
1567
1568 /*
1569  * It executes link_update after knowing an interrupt is prsent.
1570  *
1571  * @param dev
1572  *  Pointer to struct rte_eth_dev.
1573  *
1574  * @return
1575  *  - On success, zero.
1576  *  - On failure, a negative value.
1577  */
1578 static int
1579 eth_em_interrupt_action(struct rte_eth_dev *dev,
1580                         struct rte_intr_handle *intr_handle)
1581 {
1582         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1583         struct e1000_hw *hw =
1584                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1585         struct e1000_interrupt *intr =
1586                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1587         uint32_t tctl, rctl;
1588         struct rte_eth_link link;
1589         int ret;
1590
1591         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1592                 return -1;
1593
1594         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1595         rte_intr_enable(intr_handle);
1596
1597         /* set get_link_status to check register later */
1598         hw->mac.get_link_status = 1;
1599         ret = eth_em_link_update(dev, 0);
1600
1601         /* check if link has changed */
1602         if (ret < 0)
1603                 return 0;
1604
1605         memset(&link, 0, sizeof(link));
1606         rte_em_dev_atomic_read_link_status(dev, &link);
1607         if (link.link_status) {
1608                 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1609                              dev->data->port_id, link.link_speed,
1610                              link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1611                              "full-duplex" : "half-duplex");
1612         } else {
1613                 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1614         }
1615         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1616                      pci_dev->addr.domain, pci_dev->addr.bus,
1617                      pci_dev->addr.devid, pci_dev->addr.function);
1618
1619         tctl = E1000_READ_REG(hw, E1000_TCTL);
1620         rctl = E1000_READ_REG(hw, E1000_RCTL);
1621         if (link.link_status) {
1622                 /* enable Tx/Rx */
1623                 tctl |= E1000_TCTL_EN;
1624                 rctl |= E1000_RCTL_EN;
1625         } else {
1626                 /* disable Tx/Rx */
1627                 tctl &= ~E1000_TCTL_EN;
1628                 rctl &= ~E1000_RCTL_EN;
1629         }
1630         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1631         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1632         E1000_WRITE_FLUSH(hw);
1633
1634         return 0;
1635 }
1636
1637 /**
1638  * Interrupt handler which shall be registered at first.
1639  *
1640  * @param handle
1641  *  Pointer to interrupt handle.
1642  * @param param
1643  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1644  *
1645  * @return
1646  *  void
1647  */
1648 static void
1649 eth_em_interrupt_handler(void *param)
1650 {
1651         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1652
1653         eth_em_interrupt_get_status(dev);
1654         eth_em_interrupt_action(dev, dev->intr_handle);
1655         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
1656 }
1657
1658 static int
1659 eth_em_led_on(struct rte_eth_dev *dev)
1660 {
1661         struct e1000_hw *hw;
1662
1663         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1664         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1665 }
1666
1667 static int
1668 eth_em_led_off(struct rte_eth_dev *dev)
1669 {
1670         struct e1000_hw *hw;
1671
1672         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1673         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1674 }
1675
1676 static int
1677 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1678 {
1679         struct e1000_hw *hw;
1680         uint32_t ctrl;
1681         int tx_pause;
1682         int rx_pause;
1683
1684         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1685         fc_conf->pause_time = hw->fc.pause_time;
1686         fc_conf->high_water = hw->fc.high_water;
1687         fc_conf->low_water = hw->fc.low_water;
1688         fc_conf->send_xon = hw->fc.send_xon;
1689         fc_conf->autoneg = hw->mac.autoneg;
1690
1691         /*
1692          * Return rx_pause and tx_pause status according to actual setting of
1693          * the TFCE and RFCE bits in the CTRL register.
1694          */
1695         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1696         if (ctrl & E1000_CTRL_TFCE)
1697                 tx_pause = 1;
1698         else
1699                 tx_pause = 0;
1700
1701         if (ctrl & E1000_CTRL_RFCE)
1702                 rx_pause = 1;
1703         else
1704                 rx_pause = 0;
1705
1706         if (rx_pause && tx_pause)
1707                 fc_conf->mode = RTE_FC_FULL;
1708         else if (rx_pause)
1709                 fc_conf->mode = RTE_FC_RX_PAUSE;
1710         else if (tx_pause)
1711                 fc_conf->mode = RTE_FC_TX_PAUSE;
1712         else
1713                 fc_conf->mode = RTE_FC_NONE;
1714
1715         return 0;
1716 }
1717
1718 static int
1719 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1720 {
1721         struct e1000_hw *hw;
1722         int err;
1723         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1724                 e1000_fc_none,
1725                 e1000_fc_rx_pause,
1726                 e1000_fc_tx_pause,
1727                 e1000_fc_full
1728         };
1729         uint32_t rx_buf_size;
1730         uint32_t max_high_water;
1731         uint32_t rctl;
1732
1733         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1734         if (fc_conf->autoneg != hw->mac.autoneg)
1735                 return -ENOTSUP;
1736         rx_buf_size = em_get_rx_buffer_size(hw);
1737         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1738
1739         /* At least reserve one Ethernet frame for watermark */
1740         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1741         if ((fc_conf->high_water > max_high_water) ||
1742             (fc_conf->high_water < fc_conf->low_water)) {
1743                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1744                 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1745                 return -EINVAL;
1746         }
1747
1748         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1749         hw->fc.pause_time     = fc_conf->pause_time;
1750         hw->fc.high_water     = fc_conf->high_water;
1751         hw->fc.low_water      = fc_conf->low_water;
1752         hw->fc.send_xon       = fc_conf->send_xon;
1753
1754         err = e1000_setup_link_generic(hw);
1755         if (err == E1000_SUCCESS) {
1756
1757                 /* check if we want to forward MAC frames - driver doesn't have native
1758                  * capability to do that, so we'll write the registers ourselves */
1759
1760                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1761
1762                 /* set or clear MFLCN.PMCF bit depending on configuration */
1763                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1764                         rctl |= E1000_RCTL_PMCF;
1765                 else
1766                         rctl &= ~E1000_RCTL_PMCF;
1767
1768                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1769                 E1000_WRITE_FLUSH(hw);
1770
1771                 return 0;
1772         }
1773
1774         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1775         return -EIO;
1776 }
1777
1778 static int
1779 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1780                 uint32_t index, __rte_unused uint32_t pool)
1781 {
1782         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1783
1784         return e1000_rar_set(hw, mac_addr->addr_bytes, index);
1785 }
1786
1787 static void
1788 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1789 {
1790         uint8_t addr[ETHER_ADDR_LEN];
1791         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1792
1793         memset(addr, 0, sizeof(addr));
1794
1795         e1000_rar_set(hw, addr, index);
1796 }
1797
1798 static int
1799 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1800 {
1801         struct rte_eth_dev_info dev_info;
1802         struct e1000_hw *hw;
1803         uint32_t frame_size;
1804         uint32_t rctl;
1805
1806         eth_em_infos_get(dev, &dev_info);
1807         frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1808
1809         /* check that mtu is within the allowed range */
1810         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1811                 return -EINVAL;
1812
1813         /* refuse mtu that requires the support of scattered packets when this
1814          * feature has not been enabled before. */
1815         if (!dev->data->scattered_rx &&
1816             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1817                 return -EINVAL;
1818
1819         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1820         rctl = E1000_READ_REG(hw, E1000_RCTL);
1821
1822         /* switch to jumbo mode if needed */
1823         if (frame_size > ETHER_MAX_LEN) {
1824                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1825                 rctl |= E1000_RCTL_LPE;
1826         } else {
1827                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1828                 rctl &= ~E1000_RCTL_LPE;
1829         }
1830         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1831
1832         /* update max frame size */
1833         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1834         return 0;
1835 }
1836
1837 static int
1838 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1839                         struct ether_addr *mc_addr_set,
1840                         uint32_t nb_mc_addr)
1841 {
1842         struct e1000_hw *hw;
1843
1844         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1845         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1846         return 0;
1847 }
1848
1849 RTE_PMD_REGISTER_PCI(net_e1000_em, rte_em_pmd);
1850 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_em, pci_id_em_map);
1851 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_em, "* igb_uio | uio_pci_generic | vfio-pci");
1852
1853 RTE_INIT(e1000_init_log);
1854 static void
1855 e1000_init_log(void)
1856 {
1857         e1000_logtype_init = rte_log_register("pmd.e1000.init");
1858         if (e1000_logtype_init >= 0)
1859                 rte_log_set_level(e1000_logtype_init, RTE_LOG_NOTICE);
1860         e1000_logtype_driver = rte_log_register("pmd.e1000.driver");
1861         if (e1000_logtype_driver >= 0)
1862                 rte_log_set_level(e1000_logtype_driver, RTE_LOG_NOTICE);
1863 }