drivers/net/e1000/igb_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <stdarg.h>
  10
  11 #include <rte_string_fns.h>
  12 #include <rte_common.h>
  13 #include <rte_interrupts.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_log.h>
  16 #include <rte_debug.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memory.h>
  23 #include <rte_eal.h>
  24 #include <rte_malloc.h>
  25 #include <rte_dev.h>
  26
  27 #include "e1000_logs.h"
  28 #include "base/e1000_api.h"
  29 #include "e1000_ethdev.h"
  30 #include "igb_regs.h"
  31
  32 /*
  33  * Default values for port configuration
  34  */
  35 #define IGB_DEFAULT_RX_FREE_THRESH  32
  36
  37 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  38 #define IGB_DEFAULT_RX_HTHRESH      8
  39 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  40
  41 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  42 #define IGB_DEFAULT_TX_HTHRESH      1
  43 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  44
  45 /* Bit shift and mask */
  46 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  47 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  48 #define IGB_8_BIT_WIDTH  CHAR_BIT
  49 #define IGB_8_BIT_MASK   UINT8_MAX
  50
  51 /* Additional timesync values. */
  52 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  53 #define E1000_ETQF_FILTER_1588       3
  54 #define IGB_82576_TSYNC_SHIFT        16
  55 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  56 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  57 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  58
  59 #define E1000_VTIVAR_MISC                0x01740
  60 #define E1000_VTIVAR_MISC_MASK           0xFF
  61 #define E1000_VTIVAR_VALID               0x80
  62 #define E1000_VTIVAR_MISC_MAILBOX        0
  63 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  64
  65 /* External VLAN Enable bit mask */
  66 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  67
  68 /* External VLAN Ether Type bit mask and shift */
  69 #define E1000_VET_VET_EXT            0xFFFF0000
  70 #define E1000_VET_VET_EXT_SHIFT      16
  71
  72 /* MSI-X other interrupt vector */
  73 #define IGB_MSIX_OTHER_INTR_VEC      0
  74
  75 static int  eth_igb_configure(struct rte_eth_dev *dev);
  76 static int  eth_igb_start(struct rte_eth_dev *dev);
  77 static void eth_igb_stop(struct rte_eth_dev *dev);
  78 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
  79 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
  80 static void eth_igb_close(struct rte_eth_dev *dev);
  81 static int eth_igb_reset(struct rte_eth_dev *dev);
  82 static int  eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  83 static int  eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  84 static int  eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  85 static int  eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  86 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  87                                 int wait_to_complete);
  88 static int eth_igb_stats_get(struct rte_eth_dev *dev,
  89                                 struct rte_eth_stats *rte_stats);
  90 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
  91                               struct rte_eth_xstat *xstats, unsigned n);
  92 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
  93                 const uint64_t *ids,
  94                 uint64_t *values, unsigned int n);
  95 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
  96                                     struct rte_eth_xstat_name *xstats_names,
  97                                     unsigned int size);
  98 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
  99                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
 100                 unsigned int limit);
 101 static int eth_igb_stats_reset(struct rte_eth_dev *dev);
 102 static int eth_igb_xstats_reset(struct rte_eth_dev *dev);
 103 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
 104                                    char *fw_version, size_t fw_size);
 105 static int eth_igb_infos_get(struct rte_eth_dev *dev,
 106                               struct rte_eth_dev_info *dev_info);
 107 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 108 static int eth_igbvf_infos_get(struct rte_eth_dev *dev,
 109                                 struct rte_eth_dev_info *dev_info);
 110 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 111                                 struct rte_eth_fc_conf *fc_conf);
 112 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 113                                 struct rte_eth_fc_conf *fc_conf);
 114 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 115 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 116 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 117 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 118                                     struct rte_intr_handle *handle);
 119 static void eth_igb_interrupt_handler(void *param);
 120 static int  igb_hardware_init(struct e1000_hw *hw);
 121 static void igb_hw_control_acquire(struct e1000_hw *hw);
 122 static void igb_hw_control_release(struct e1000_hw *hw);
 123 static void igb_init_manageability(struct e1000_hw *hw);
 124 static void igb_release_manageability(struct e1000_hw *hw);
 125
 126 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 127
 128 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 129                 uint16_t vlan_id, int on);
 130 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 131                                  enum rte_vlan_type vlan_type,
 132                                  uint16_t tpid_id);
 133 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 134
 135 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 136 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 137 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 138 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 139 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 140 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 141
 142 static int eth_igb_led_on(struct rte_eth_dev *dev);
 143 static int eth_igb_led_off(struct rte_eth_dev *dev);
 144
 145 static void igb_intr_disable(struct rte_eth_dev *dev);
 146 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 147 static int eth_igb_rar_set(struct rte_eth_dev *dev,
 148                            struct rte_ether_addr *mac_addr,
 149                            uint32_t index, uint32_t pool);
 150 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 151 static int eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 152                 struct rte_ether_addr *addr);
 153
 154 static void igbvf_intr_disable(struct e1000_hw *hw);
 155 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 156 static int igbvf_dev_start(struct rte_eth_dev *dev);
 157 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 158 static void igbvf_dev_close(struct rte_eth_dev *dev);
 159 static int igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 160 static int igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 161 static int igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 162 static int igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 163 static int eth_igbvf_link_update(struct e1000_hw *hw);
 164 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
 165                                 struct rte_eth_stats *rte_stats);
 166 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 167                                 struct rte_eth_xstat *xstats, unsigned n);
 168 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 169                                       struct rte_eth_xstat_name *xstats_names,
 170                                       unsigned limit);
 171 static int eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 172 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 173                 uint16_t vlan_id, int on);
 174 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 175 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 176 static int igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 177                 struct rte_ether_addr *addr);
 178 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 179 static int igbvf_get_regs(struct rte_eth_dev *dev,
 180                 struct rte_dev_reg_info *regs);
 181
 182 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 183                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 184                                    uint16_t reta_size);
 185 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 186                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 187                                   uint16_t reta_size);
 188
 189 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 190                         struct rte_eth_syn_filter *filter);
 191 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 192                         enum rte_filter_op filter_op,
 193                         void *arg);
 194 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 195                         struct rte_eth_ntuple_filter *ntuple_filter);
 196 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 197                         struct rte_eth_ntuple_filter *ntuple_filter);
 198 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 199                         struct rte_eth_flex_filter *filter);
 200 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 201                         enum rte_filter_op filter_op,
 202                         void *arg);
 203 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 204                         struct rte_eth_ntuple_filter *ntuple_filter);
 205 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 206                         struct rte_eth_ntuple_filter *ntuple_filter);
 207 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 208                         struct rte_eth_ntuple_filter *filter);
 209 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 210                                 enum rte_filter_op filter_op,
 211                                 void *arg);
 212 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 213                                 enum rte_filter_op filter_op,
 214                                 void *arg);
 215 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 216                         struct rte_eth_ethertype_filter *filter);
 217 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 218                      enum rte_filter_type filter_type,
 219                      enum rte_filter_op filter_op,
 220                      void *arg);
 221 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 222 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 223                 struct rte_dev_reg_info *regs);
 224 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 225 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 226                 struct rte_dev_eeprom_info *eeprom);
 227 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 228                 struct rte_dev_eeprom_info *eeprom);
 229 static int eth_igb_get_module_info(struct rte_eth_dev *dev,
 230                                    struct rte_eth_dev_module_info *modinfo);
 231 static int eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
 232                                      struct rte_dev_eeprom_info *info);
 233 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 234                                     struct rte_ether_addr *mc_addr_set,
 235                                     uint32_t nb_mc_addr);
 236 static int igb_timesync_enable(struct rte_eth_dev *dev);
 237 static int igb_timesync_disable(struct rte_eth_dev *dev);
 238 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 239                                           struct timespec *timestamp,
 240                                           uint32_t flags);
 241 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 242                                           struct timespec *timestamp);
 243 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 244 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 245                                   struct timespec *timestamp);
 246 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 247                                    const struct timespec *timestamp);
 248 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 249                                         uint16_t queue_id);
 250 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 251                                          uint16_t queue_id);
 252 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 253                                        uint8_t queue, uint8_t msix_vector);
 254 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 255                                uint8_t index, uint8_t offset);
 256 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 257 static void eth_igbvf_interrupt_handler(void *param);
 258 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 259 static int igb_filter_restore(struct rte_eth_dev *dev);
 260
 261 /*
 262  * Define VF Stats MACRO for Non "cleared on read" register
 263  */
 264 #define UPDATE_VF_STAT(reg, last, cur)            \
 265 {                                                 \
 266         u32 latest = E1000_READ_REG(hw, reg);     \
 267         cur += (latest - last) & UINT_MAX;        \
 268         last = latest;                            \
 269 }
 270
 271 #define IGB_FC_PAUSE_TIME 0x0680
 272 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 273 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 274
 275 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 276
 277 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 278
 279 /*
 280  * The set of PCI devices this driver supports
 281  */
 282 static const struct rte_pci_id pci_id_igb_map[] = {
 283         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 284         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 285         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 286         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 287         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 288         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 289         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 290         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 291
 292         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 293         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 294         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 295
 296         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 297         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 298         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 299         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 300         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 301         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 302
 303         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 304         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 305         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 306         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 307         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 308         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 309         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 310         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 311         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 312         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 313         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 314         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
 315         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
 316         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 317         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 318         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 319         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 320         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 321         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 322         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 323         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 324         { .vendor_id = 0, /* sentinel */ },
 325 };
 326
 327 /*
 328  * The set of PCI devices this driver supports (for 82576&I350 VF)
 329  */
 330 static const struct rte_pci_id pci_id_igbvf_map[] = {
 331         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 332         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 333         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 334         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 335         { .vendor_id = 0, /* sentinel */ },
 336 };
 337
 338 static const struct rte_eth_desc_lim rx_desc_lim = {
 339         .nb_max = E1000_MAX_RING_DESC,
 340         .nb_min = E1000_MIN_RING_DESC,
 341         .nb_align = IGB_RXD_ALIGN,
 342 };
 343
 344 static const struct rte_eth_desc_lim tx_desc_lim = {
 345         .nb_max = E1000_MAX_RING_DESC,
 346         .nb_min = E1000_MIN_RING_DESC,
 347         .nb_align = IGB_RXD_ALIGN,
 348         .nb_seg_max = IGB_TX_MAX_SEG,
 349         .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
 350 };
 351
 352 static const struct eth_dev_ops eth_igb_ops = {
 353         .dev_configure        = eth_igb_configure,
 354         .dev_start            = eth_igb_start,
 355         .dev_stop             = eth_igb_stop,
 356         .dev_set_link_up      = eth_igb_dev_set_link_up,
 357         .dev_set_link_down    = eth_igb_dev_set_link_down,
 358         .dev_close            = eth_igb_close,
 359         .dev_reset            = eth_igb_reset,
 360         .promiscuous_enable   = eth_igb_promiscuous_enable,
 361         .promiscuous_disable  = eth_igb_promiscuous_disable,
 362         .allmulticast_enable  = eth_igb_allmulticast_enable,
 363         .allmulticast_disable = eth_igb_allmulticast_disable,
 364         .link_update          = eth_igb_link_update,
 365         .stats_get            = eth_igb_stats_get,
 366         .xstats_get           = eth_igb_xstats_get,
 367         .xstats_get_by_id     = eth_igb_xstats_get_by_id,
 368         .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
 369         .xstats_get_names     = eth_igb_xstats_get_names,
 370         .stats_reset          = eth_igb_stats_reset,
 371         .xstats_reset         = eth_igb_xstats_reset,
 372         .fw_version_get       = eth_igb_fw_version_get,
 373         .dev_infos_get        = eth_igb_infos_get,
 374         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 375         .mtu_set              = eth_igb_mtu_set,
 376         .vlan_filter_set      = eth_igb_vlan_filter_set,
 377         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 378         .vlan_offload_set     = eth_igb_vlan_offload_set,
 379         .rx_queue_setup       = eth_igb_rx_queue_setup,
 380         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 381         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 382         .rx_queue_release     = eth_igb_rx_queue_release,
 383         .rx_queue_count       = eth_igb_rx_queue_count,
 384         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 385         .rx_descriptor_status = eth_igb_rx_descriptor_status,
 386         .tx_descriptor_status = eth_igb_tx_descriptor_status,
 387         .tx_queue_setup       = eth_igb_tx_queue_setup,
 388         .tx_queue_release     = eth_igb_tx_queue_release,
 389         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 390         .dev_led_on           = eth_igb_led_on,
 391         .dev_led_off          = eth_igb_led_off,
 392         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 393         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 394         .mac_addr_add         = eth_igb_rar_set,
 395         .mac_addr_remove      = eth_igb_rar_clear,
 396         .mac_addr_set         = eth_igb_default_mac_addr_set,
 397         .reta_update          = eth_igb_rss_reta_update,
 398         .reta_query           = eth_igb_rss_reta_query,
 399         .rss_hash_update      = eth_igb_rss_hash_update,
 400         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 401         .filter_ctrl          = eth_igb_filter_ctrl,
 402         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 403         .rxq_info_get         = igb_rxq_info_get,
 404         .txq_info_get         = igb_txq_info_get,
 405         .timesync_enable      = igb_timesync_enable,
 406         .timesync_disable     = igb_timesync_disable,
 407         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 408         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 409         .get_reg              = eth_igb_get_regs,
 410         .get_eeprom_length    = eth_igb_get_eeprom_length,
 411         .get_eeprom           = eth_igb_get_eeprom,
 412         .set_eeprom           = eth_igb_set_eeprom,
 413         .get_module_info      = eth_igb_get_module_info,
 414         .get_module_eeprom    = eth_igb_get_module_eeprom,
 415         .timesync_adjust_time = igb_timesync_adjust_time,
 416         .timesync_read_time   = igb_timesync_read_time,
 417         .timesync_write_time  = igb_timesync_write_time,
 418 };
 419
 420 /*
 421  * dev_ops for virtual function, bare necessities for basic vf
 422  * operation have been implemented
 423  */
 424 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 425         .dev_configure        = igbvf_dev_configure,
 426         .dev_start            = igbvf_dev_start,
 427         .dev_stop             = igbvf_dev_stop,
 428         .dev_close            = igbvf_dev_close,
 429         .promiscuous_enable   = igbvf_promiscuous_enable,
 430         .promiscuous_disable  = igbvf_promiscuous_disable,
 431         .allmulticast_enable  = igbvf_allmulticast_enable,
 432         .allmulticast_disable = igbvf_allmulticast_disable,
 433         .link_update          = eth_igb_link_update,
 434         .stats_get            = eth_igbvf_stats_get,
 435         .xstats_get           = eth_igbvf_xstats_get,
 436         .xstats_get_names     = eth_igbvf_xstats_get_names,
 437         .stats_reset          = eth_igbvf_stats_reset,
 438         .xstats_reset         = eth_igbvf_stats_reset,
 439         .vlan_filter_set      = igbvf_vlan_filter_set,
 440         .dev_infos_get        = eth_igbvf_infos_get,
 441         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 442         .rx_queue_setup       = eth_igb_rx_queue_setup,
 443         .rx_queue_release     = eth_igb_rx_queue_release,
 444         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 445         .rx_descriptor_status = eth_igb_rx_descriptor_status,
 446         .tx_descriptor_status = eth_igb_tx_descriptor_status,
 447         .tx_queue_setup       = eth_igb_tx_queue_setup,
 448         .tx_queue_release     = eth_igb_tx_queue_release,
 449         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 450         .rxq_info_get         = igb_rxq_info_get,
 451         .txq_info_get         = igb_txq_info_get,
 452         .mac_addr_set         = igbvf_default_mac_addr_set,
 453         .get_reg              = igbvf_get_regs,
 454 };
 455
 456 /* store statistics names and its offset in stats structure */
 457 struct rte_igb_xstats_name_off {
 458         char name[RTE_ETH_XSTATS_NAME_SIZE];
 459         unsigned offset;
 460 };
 461
 462 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 463         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 464         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 465         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 466         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 467         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 468         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 469         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 470                 ecol)},
 471         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 472         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 473         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 474         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 475         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 476         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 477         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 478         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 479         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 480         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 481         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 482                 fcruc)},
 483         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 484         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 485         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 486         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 487         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 488                 prc1023)},
 489         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 490                 prc1522)},
 491         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 492         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 493         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 494         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 495         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 496         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 497         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 498         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 499         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 500         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 501         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 502         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 503         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 504         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 505         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 506         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 507         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 508         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 509                 ptc1023)},
 510         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 511                 ptc1522)},
 512         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 513         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 514         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 515         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 516         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 517         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 518         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 519
 520         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 521 };
 522
 523 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 524                 sizeof(rte_igb_stats_strings[0]))
 525
 526 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 527         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 528         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 529         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 530         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 531         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 532 };
 533
 534 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 535                 sizeof(rte_igbvf_stats_strings[0]))
 536
 537
 538 static inline void
 539 igb_intr_enable(struct rte_eth_dev *dev)
 540 {
 541         struct e1000_interrupt *intr =
 542                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 543         struct e1000_hw *hw =
 544                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 545         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 546         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 547
 548         if (rte_intr_allow_others(intr_handle) &&
 549                 dev->data->dev_conf.intr_conf.lsc != 0) {
 550                 E1000_WRITE_REG(hw, E1000_EIMS, 1 << IGB_MSIX_OTHER_INTR_VEC);
 551         }
 552
 553         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 554         E1000_WRITE_FLUSH(hw);
 555 }
 556
 557 static void
 558 igb_intr_disable(struct rte_eth_dev *dev)
 559 {
 560         struct e1000_hw *hw =
 561                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 562         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 563         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 564
 565         if (rte_intr_allow_others(intr_handle) &&
 566                 dev->data->dev_conf.intr_conf.lsc != 0) {
 567                 E1000_WRITE_REG(hw, E1000_EIMC, 1 << IGB_MSIX_OTHER_INTR_VEC);
 568         }
 569
 570         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 571         E1000_WRITE_FLUSH(hw);
 572 }
 573
 574 static inline void
 575 igbvf_intr_enable(struct rte_eth_dev *dev)
 576 {
 577         struct e1000_hw *hw =
 578                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 579
 580         /* only for mailbox */
 581         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 582         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 583         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 584         E1000_WRITE_FLUSH(hw);
 585 }
 586
 587 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 588 static void
 589 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 590 {
 591         uint32_t tmp = 0;
 592
 593         /* mailbox */
 594         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 595         tmp |= E1000_VTIVAR_VALID;
 596         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 597 }
 598
 599 static void
 600 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 601 {
 602         struct e1000_hw *hw =
 603                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 604
 605         /* Configure VF other cause ivar */
 606         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 607 }
 608
 609 static inline int32_t
 610 igb_pf_reset_hw(struct e1000_hw *hw)
 611 {
 612         uint32_t ctrl_ext;
 613         int32_t status;
 614
 615         status = e1000_reset_hw(hw);
 616
 617         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 618         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 619         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 620         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 621         E1000_WRITE_FLUSH(hw);
 622
 623         return status;
 624 }
 625
 626 static void
 627 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 628 {
 629         struct e1000_hw *hw =
 630                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 631
 632
 633         hw->vendor_id = pci_dev->id.vendor_id;
 634         hw->device_id = pci_dev->id.device_id;
 635         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 636         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 637
 638         e1000_set_mac_type(hw);
 639
 640         /* need to check if it is a vf device below */
 641 }
 642
 643 static int
 644 igb_reset_swfw_lock(struct e1000_hw *hw)
 645 {
 646         int ret_val;
 647
 648         /*
 649          * Do mac ops initialization manually here, since we will need
 650          * some function pointers set by this call.
 651          */
 652         ret_val = e1000_init_mac_params(hw);
 653         if (ret_val)
 654                 return ret_val;
 655
 656         /*
 657          * SMBI lock should not fail in this early stage. If this is the case,
 658          * it is due to an improper exit of the application.
 659          * So force the release of the faulty lock.
 660          */
 661         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 662                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 663         }
 664         e1000_put_hw_semaphore_generic(hw);
 665
 666         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 667                 uint16_t mask;
 668
 669                 /*
 670                  * Phy lock should not fail in this early stage. If this is the case,
 671                  * it is due to an improper exit of the application.
 672                  * So force the release of the faulty lock.
 673                  */
 674                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 675                 if (hw->bus.func > E1000_FUNC_1)
 676                         mask <<= 2;
 677                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 678                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 679                                     hw->bus.func);
 680                 }
 681                 hw->mac.ops.release_swfw_sync(hw, mask);
 682
 683                 /*
 684                  * This one is more tricky since it is common to all ports; but
 685                  * swfw_sync retries last long enough (1s) to be almost sure that if
 686                  * lock can not be taken it is due to an improper lock of the
 687                  * semaphore.
 688                  */
 689                 mask = E1000_SWFW_EEP_SM;
 690                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 691                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 692                 }
 693                 hw->mac.ops.release_swfw_sync(hw, mask);
 694         }
 695
 696         return E1000_SUCCESS;
 697 }
 698
 699 /* Remove all ntuple filters of the device */
 700 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 701 {
 702         struct e1000_filter_info *filter_info =
 703                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 704         struct e1000_5tuple_filter *p_5tuple;
 705         struct e1000_2tuple_filter *p_2tuple;
 706
 707         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 708                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 709                         p_5tuple, entries);
 710                         rte_free(p_5tuple);
 711         }
 712         filter_info->fivetuple_mask = 0;
 713         while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
 714                 TAILQ_REMOVE(&filter_info->twotuple_list,
 715                         p_2tuple, entries);
 716                         rte_free(p_2tuple);
 717         }
 718         filter_info->twotuple_mask = 0;
 719
 720         return 0;
 721 }
 722
 723 /* Remove all flex filters of the device */
 724 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
 725 {
 726         struct e1000_filter_info *filter_info =
 727                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 728         struct e1000_flex_filter *p_flex;
 729
 730         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
 731                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
 732                 rte_free(p_flex);
 733         }
 734         filter_info->flex_mask = 0;
 735
 736         return 0;
 737 }
 738
 739 static int
 740 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 741 {
 742         int error = 0;
 743         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 744         struct e1000_hw *hw =
 745                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 746         struct e1000_vfta * shadow_vfta =
 747                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 748         struct e1000_filter_info *filter_info =
 749                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 750         struct e1000_adapter *adapter =
 751                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 752
 753         uint32_t ctrl_ext;
 754
 755         eth_dev->dev_ops = &eth_igb_ops;
 756         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 757         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 758         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 759
 760         /* for secondary processes, we don't initialise any further as primary
 761          * has already done this work. Only check we don't need a different
 762          * RX function */
 763         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 764                 if (eth_dev->data->scattered_rx)
 765                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 766                 return 0;
 767         }
 768
 769         rte_eth_copy_pci_info(eth_dev, pci_dev);
 770
 771         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 772
 773         igb_identify_hardware(eth_dev, pci_dev);
 774         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 775                 error = -EIO;
 776                 goto err_late;
 777         }
 778
 779         e1000_get_bus_info(hw);
 780
 781         /* Reset any pending lock */
 782         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 783                 error = -EIO;
 784                 goto err_late;
 785         }
 786
 787         /* Finish initialization */
 788         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 789                 error = -EIO;
 790                 goto err_late;
 791         }
 792
 793         hw->mac.autoneg = 1;
 794         hw->phy.autoneg_wait_to_complete = 0;
 795         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 796
 797         /* Copper options */
 798         if (hw->phy.media_type == e1000_media_type_copper) {
 799                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 800                 hw->phy.disable_polarity_correction = 0;
 801                 hw->phy.ms_type = e1000_ms_hw_default;
 802         }
 803
 804         /*
 805          * Start from a known state, this is important in reading the nvm
 806          * and mac from that.
 807          */
 808         igb_pf_reset_hw(hw);
 809
 810         /* Make sure we have a good EEPROM before we read from it */
 811         if (e1000_validate_nvm_checksum(hw) < 0) {
 812                 /*
 813                  * Some PCI-E parts fail the first check due to
 814                  * the link being in sleep state, call it again,
 815                  * if it fails a second time its a real issue.
 816                  */
 817                 if (e1000_validate_nvm_checksum(hw) < 0) {
 818                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 819                         error = -EIO;
 820                         goto err_late;
 821                 }
 822         }
 823
 824         /* Read the permanent MAC address out of the EEPROM */
 825         if (e1000_read_mac_addr(hw) != 0) {
 826                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 827                 error = -EIO;
 828                 goto err_late;
 829         }
 830
 831         /* Allocate memory for storing MAC addresses */
 832         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 833                 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 834         if (eth_dev->data->mac_addrs == NULL) {
 835                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 836                                                 "store MAC addresses",
 837                                 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 838                 error = -ENOMEM;
 839                 goto err_late;
 840         }
 841
 842         /* Copy the permanent MAC address */
 843         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
 844                         &eth_dev->data->mac_addrs[0]);
 845
 846         /* Pass the information to the rte_eth_dev_close() that it should also
 847          * release the private port resources.
 848          */
 849         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
 850
 851         /* initialize the vfta */
 852         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 853
 854         /* Now initialize the hardware */
 855         if (igb_hardware_init(hw) != 0) {
 856                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 857                 rte_free(eth_dev->data->mac_addrs);
 858                 eth_dev->data->mac_addrs = NULL;
 859                 error = -ENODEV;
 860                 goto err_late;
 861         }
 862         hw->mac.get_link_status = 1;
 863         adapter->stopped = 0;
 864
 865         /* Indicate SOL/IDER usage */
 866         if (e1000_check_reset_block(hw) < 0) {
 867                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 868                                         "SOL/IDER session");
 869         }
 870
 871         /* initialize PF if max_vfs not zero */
 872         igb_pf_host_init(eth_dev);
 873
 874         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 875         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 876         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 877         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 878         E1000_WRITE_FLUSH(hw);
 879
 880         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 881                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 882                      pci_dev->id.device_id);
 883
 884         rte_intr_callback_register(&pci_dev->intr_handle,
 885                                    eth_igb_interrupt_handler,
 886                                    (void *)eth_dev);
 887
 888         /* enable uio/vfio intr/eventfd mapping */
 889         rte_intr_enable(&pci_dev->intr_handle);
 890
 891         /* enable support intr */
 892         igb_intr_enable(eth_dev);
 893
 894         /* initialize filter info */
 895         memset(filter_info, 0,
 896                sizeof(struct e1000_filter_info));
 897
 898         TAILQ_INIT(&filter_info->flex_list);
 899         TAILQ_INIT(&filter_info->twotuple_list);
 900         TAILQ_INIT(&filter_info->fivetuple_list);
 901
 902         TAILQ_INIT(&igb_filter_ntuple_list);
 903         TAILQ_INIT(&igb_filter_ethertype_list);
 904         TAILQ_INIT(&igb_filter_syn_list);
 905         TAILQ_INIT(&igb_filter_flex_list);
 906         TAILQ_INIT(&igb_filter_rss_list);
 907         TAILQ_INIT(&igb_flow_list);
 908
 909         return 0;
 910
 911 err_late:
 912         igb_hw_control_release(hw);
 913
 914         return error;
 915 }
 916
 917 static int
 918 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 919 {
 920         PMD_INIT_FUNC_TRACE();
 921
 922         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 923                 return -EPERM;
 924
 925         eth_igb_close(eth_dev);
 926
 927         return 0;
 928 }
 929
 930 /*
 931  * Virtual Function device init
 932  */
 933 static int
 934 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 935 {
 936         struct rte_pci_device *pci_dev;
 937         struct rte_intr_handle *intr_handle;
 938         struct e1000_adapter *adapter =
 939                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 940         struct e1000_hw *hw =
 941                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 942         int diag;
 943         struct rte_ether_addr *perm_addr =
 944                 (struct rte_ether_addr *)hw->mac.perm_addr;
 945
 946         PMD_INIT_FUNC_TRACE();
 947
 948         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 949         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 950         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 951         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 952
 953         /* for secondary processes, we don't initialise any further as primary
 954          * has already done this work. Only check we don't need a different
 955          * RX function */
 956         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 957                 if (eth_dev->data->scattered_rx)
 958                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 959                 return 0;
 960         }
 961
 962         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 963         rte_eth_copy_pci_info(eth_dev, pci_dev);
 964
 965         hw->device_id = pci_dev->id.device_id;
 966         hw->vendor_id = pci_dev->id.vendor_id;
 967         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 968         adapter->stopped = 0;
 969
 970         /* Initialize the shared code (base driver) */
 971         diag = e1000_setup_init_funcs(hw, TRUE);
 972         if (diag != 0) {
 973                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 974                         diag);
 975                 return -EIO;
 976         }
 977
 978         /* init_mailbox_params */
 979         hw->mbx.ops.init_params(hw);
 980
 981         /* Disable the interrupts for VF */
 982         igbvf_intr_disable(hw);
 983
 984         diag = hw->mac.ops.reset_hw(hw);
 985
 986         /* Allocate memory for storing MAC addresses */
 987         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", RTE_ETHER_ADDR_LEN *
 988                 hw->mac.rar_entry_count, 0);
 989         if (eth_dev->data->mac_addrs == NULL) {
 990                 PMD_INIT_LOG(ERR,
 991                         "Failed to allocate %d bytes needed to store MAC "
 992                         "addresses",
 993                         RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 994                 return -ENOMEM;
 995         }
 996
 997         /* Pass the information to the rte_eth_dev_close() that it should also
 998          * release the private port resources.
 999          */
1000         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1001
1002         /* Generate a random MAC address, if none was assigned by PF. */
1003         if (rte_is_zero_ether_addr(perm_addr)) {
1004                 rte_eth_random_addr(perm_addr->addr_bytes);
1005                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1006                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1007                              "%02x:%02x:%02x:%02x:%02x:%02x",
1008                              perm_addr->addr_bytes[0],
1009                              perm_addr->addr_bytes[1],
1010                              perm_addr->addr_bytes[2],
1011                              perm_addr->addr_bytes[3],
1012                              perm_addr->addr_bytes[4],
1013                              perm_addr->addr_bytes[5]);
1014         }
1015
1016         diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1017         if (diag) {
1018                 rte_free(eth_dev->data->mac_addrs);
1019                 eth_dev->data->mac_addrs = NULL;
1020                 return diag;
1021         }
1022         /* Copy the permanent MAC address */
1023         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1024                         &eth_dev->data->mac_addrs[0]);
1025
1026         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1027                      "mac.type=%s",
1028                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1029                      pci_dev->id.device_id, "igb_mac_82576_vf");
1030
1031         intr_handle = &pci_dev->intr_handle;
1032         rte_intr_callback_register(intr_handle,
1033                                    eth_igbvf_interrupt_handler, eth_dev);
1034
1035         return 0;
1036 }
1037
1038 static int
1039 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1040 {
1041         PMD_INIT_FUNC_TRACE();
1042
1043         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1044                 return -EPERM;
1045
1046         igbvf_dev_close(eth_dev);
1047
1048         return 0;
1049 }
1050
1051 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1052         struct rte_pci_device *pci_dev)
1053 {
1054         return rte_eth_dev_pci_generic_probe(pci_dev,
1055                 sizeof(struct e1000_adapter), eth_igb_dev_init);
1056 }
1057
1058 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1059 {
1060         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1061 }
1062
1063 static struct rte_pci_driver rte_igb_pmd = {
1064         .id_table = pci_id_igb_map,
1065         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1066         .probe = eth_igb_pci_probe,
1067         .remove = eth_igb_pci_remove,
1068 };
1069
1070
1071 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1072         struct rte_pci_device *pci_dev)
1073 {
1074         return rte_eth_dev_pci_generic_probe(pci_dev,
1075                 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1076 }
1077
1078 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1079 {
1080         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1081 }
1082
1083 /*
1084  * virtual function driver struct
1085  */
1086 static struct rte_pci_driver rte_igbvf_pmd = {
1087         .id_table = pci_id_igbvf_map,
1088         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1089         .probe = eth_igbvf_pci_probe,
1090         .remove = eth_igbvf_pci_remove,
1091 };
1092
1093 static void
1094 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1095 {
1096         struct e1000_hw *hw =
1097                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1098         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1099         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1100         rctl |= E1000_RCTL_VFE;
1101         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1102 }
1103
1104 static int
1105 igb_check_mq_mode(struct rte_eth_dev *dev)
1106 {
1107         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1108         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1109         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1110         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1111
1112         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1113             tx_mq_mode == ETH_MQ_TX_DCB ||
1114             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1115                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1116                 return -EINVAL;
1117         }
1118         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1119                 /* Check multi-queue mode.
1120                  * To no break software we accept ETH_MQ_RX_NONE as this might
1121                  * be used to turn off VLAN filter.
1122                  */
1123
1124                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1125                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1126                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1127                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1128                 } else {
1129                         /* Only support one queue on VFs.
1130                          * RSS together with SRIOV is not supported.
1131                          */
1132                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1133                                         " wrong mq_mode rx %d.",
1134                                         rx_mq_mode);
1135                         return -EINVAL;
1136                 }
1137                 /* TX mode is not used here, so mode might be ignored.*/
1138                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1139                         /* SRIOV only works in VMDq enable mode */
1140                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1141                                         " TX mode %d is not supported. "
1142                                         " Driver will behave as %d mode.",
1143                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1144                 }
1145
1146                 /* check valid queue number */
1147                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1148                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1149                                         " only support one queue on VFs.");
1150                         return -EINVAL;
1151                 }
1152         } else {
1153                 /* To no break software that set invalid mode, only display
1154                  * warning if invalid mode is used.
1155                  */
1156                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1157                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1158                     rx_mq_mode != ETH_MQ_RX_RSS) {
1159                         /* RSS together with VMDq not supported*/
1160                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1161                                      rx_mq_mode);
1162                         return -EINVAL;
1163                 }
1164
1165                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1166                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1167                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1168                                         " Due to txmode is meaningless in this"
1169                                         " driver, just ignore.",
1170                                         tx_mq_mode);
1171                 }
1172         }
1173         return 0;
1174 }
1175
1176 static int
1177 eth_igb_configure(struct rte_eth_dev *dev)
1178 {
1179         struct e1000_interrupt *intr =
1180                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1181         int ret;
1182
1183         PMD_INIT_FUNC_TRACE();
1184
1185         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1186                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1187
1188         /* multipe queue mode checking */
1189         ret  = igb_check_mq_mode(dev);
1190         if (ret != 0) {
1191                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1192                             ret);
1193                 return ret;
1194         }
1195
1196         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1197         PMD_INIT_FUNC_TRACE();
1198
1199         return 0;
1200 }
1201
1202 static void
1203 eth_igb_rxtx_control(struct rte_eth_dev *dev,
1204                      bool enable)
1205 {
1206         struct e1000_hw *hw =
1207                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1208         uint32_t tctl, rctl;
1209
1210         tctl = E1000_READ_REG(hw, E1000_TCTL);
1211         rctl = E1000_READ_REG(hw, E1000_RCTL);
1212
1213         if (enable) {
1214                 /* enable Tx/Rx */
1215                 tctl |= E1000_TCTL_EN;
1216                 rctl |= E1000_RCTL_EN;
1217         } else {
1218                 /* disable Tx/Rx */
1219                 tctl &= ~E1000_TCTL_EN;
1220                 rctl &= ~E1000_RCTL_EN;
1221         }
1222         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1223         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1224         E1000_WRITE_FLUSH(hw);
1225 }
1226
1227 static int
1228 eth_igb_start(struct rte_eth_dev *dev)
1229 {
1230         struct e1000_hw *hw =
1231                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1232         struct e1000_adapter *adapter =
1233                 E1000_DEV_PRIVATE(dev->data->dev_private);
1234         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1235         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1236         int ret, mask;
1237         uint32_t intr_vector = 0;
1238         uint32_t ctrl_ext;
1239         uint32_t *speeds;
1240         int num_speeds;
1241         bool autoneg;
1242
1243         PMD_INIT_FUNC_TRACE();
1244
1245         /* disable uio/vfio intr/eventfd mapping */
1246         rte_intr_disable(intr_handle);
1247
1248         /* Power up the phy. Needed to make the link go Up */
1249         eth_igb_dev_set_link_up(dev);
1250
1251         /*
1252          * Packet Buffer Allocation (PBA)
1253          * Writing PBA sets the receive portion of the buffer
1254          * the remainder is used for the transmit buffer.
1255          */
1256         if (hw->mac.type == e1000_82575) {
1257                 uint32_t pba;
1258
1259                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1260                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1261         }
1262
1263         /* Put the address into the Receive Address Array */
1264         e1000_rar_set(hw, hw->mac.addr, 0);
1265
1266         /* Initialize the hardware */
1267         if (igb_hardware_init(hw)) {
1268                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1269                 return -EIO;
1270         }
1271         adapter->stopped = 0;
1272
1273         E1000_WRITE_REG(hw, E1000_VET,
1274                         RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1275
1276         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1277         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1278         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1279         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1280         E1000_WRITE_FLUSH(hw);
1281
1282         /* configure PF module if SRIOV enabled */
1283         igb_pf_host_configure(dev);
1284
1285         /* check and configure queue intr-vector mapping */
1286         if ((rte_intr_cap_multiple(intr_handle) ||
1287              !RTE_ETH_DEV_SRIOV(dev).active) &&
1288             dev->data->dev_conf.intr_conf.rxq != 0) {
1289                 intr_vector = dev->data->nb_rx_queues;
1290                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1291                         return -1;
1292         }
1293
1294         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1295                 intr_handle->intr_vec =
1296                         rte_zmalloc("intr_vec",
1297                                     dev->data->nb_rx_queues * sizeof(int), 0);
1298                 if (intr_handle->intr_vec == NULL) {
1299                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1300                                      " intr_vec", dev->data->nb_rx_queues);
1301                         return -ENOMEM;
1302                 }
1303         }
1304
1305         /* confiugre msix for rx interrupt */
1306         eth_igb_configure_msix_intr(dev);
1307
1308         /* Configure for OS presence */
1309         igb_init_manageability(hw);
1310
1311         eth_igb_tx_init(dev);
1312
1313         /* This can fail when allocating mbufs for descriptor rings */
1314         ret = eth_igb_rx_init(dev);
1315         if (ret) {
1316                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1317                 igb_dev_clear_queues(dev);
1318                 return ret;
1319         }
1320
1321         e1000_clear_hw_cntrs_base_generic(hw);
1322
1323         /*
1324          * VLAN Offload Settings
1325          */
1326         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1327                         ETH_VLAN_EXTEND_MASK;
1328         ret = eth_igb_vlan_offload_set(dev, mask);
1329         if (ret) {
1330                 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1331                 igb_dev_clear_queues(dev);
1332                 return ret;
1333         }
1334
1335         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1336                 /* Enable VLAN filter since VMDq always use VLAN filter */
1337                 igb_vmdq_vlan_hw_filter_enable(dev);
1338         }
1339
1340         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1341                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1342                 (hw->mac.type == e1000_i211)) {
1343                 /* Configure EITR with the maximum possible value (0xFFFF) */
1344                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1345         }
1346
1347         /* Setup link speed and duplex */
1348         speeds = &dev->data->dev_conf.link_speeds;
1349         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1350                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1351                 hw->mac.autoneg = 1;
1352         } else {
1353                 num_speeds = 0;
1354                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1355
1356                 /* Reset */
1357                 hw->phy.autoneg_advertised = 0;
1358
1359                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1360                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1361                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1362                         num_speeds = -1;
1363                         goto error_invalid_config;
1364                 }
1365                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1366                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1367                         num_speeds++;
1368                 }
1369                 if (*speeds & ETH_LINK_SPEED_10M) {
1370                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1371                         num_speeds++;
1372                 }
1373                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1374                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1375                         num_speeds++;
1376                 }
1377                 if (*speeds & ETH_LINK_SPEED_100M) {
1378                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1379                         num_speeds++;
1380                 }
1381                 if (*speeds & ETH_LINK_SPEED_1G) {
1382                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1383                         num_speeds++;
1384                 }
1385                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1386                         goto error_invalid_config;
1387
1388                 /* Set/reset the mac.autoneg based on the link speed,
1389                  * fixed or not
1390                  */
1391                 if (!autoneg) {
1392                         hw->mac.autoneg = 0;
1393                         hw->mac.forced_speed_duplex =
1394                                         hw->phy.autoneg_advertised;
1395                 } else {
1396                         hw->mac.autoneg = 1;
1397                 }
1398         }
1399
1400         e1000_setup_link(hw);
1401
1402         if (rte_intr_allow_others(intr_handle)) {
1403                 /* check if lsc interrupt is enabled */
1404                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1405                         eth_igb_lsc_interrupt_setup(dev, TRUE);
1406                 else
1407                         eth_igb_lsc_interrupt_setup(dev, FALSE);
1408         } else {
1409                 rte_intr_callback_unregister(intr_handle,
1410                                              eth_igb_interrupt_handler,
1411                                              (void *)dev);
1412                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1413                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1414                                      " no intr multiplex");
1415         }
1416
1417         /* check if rxq interrupt is enabled */
1418         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1419             rte_intr_dp_is_en(intr_handle))
1420                 eth_igb_rxq_interrupt_setup(dev);
1421
1422         /* enable uio/vfio intr/eventfd mapping */
1423         rte_intr_enable(intr_handle);
1424
1425         /* resume enabled intr since hw reset */
1426         igb_intr_enable(dev);
1427
1428         /* restore all types filter */
1429         igb_filter_restore(dev);
1430
1431         eth_igb_rxtx_control(dev, true);
1432         eth_igb_link_update(dev, 0);
1433
1434         PMD_INIT_LOG(DEBUG, "<<");
1435
1436         return 0;
1437
1438 error_invalid_config:
1439         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1440                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1441         igb_dev_clear_queues(dev);
1442         return -EINVAL;
1443 }
1444
1445 /*********************************************************************
1446  *
1447  *  This routine disables all traffic on the adapter by issuing a
1448  *  global reset on the MAC.
1449  *
1450  **********************************************************************/
1451 static void
1452 eth_igb_stop(struct rte_eth_dev *dev)
1453 {
1454         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1455         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1456         struct rte_eth_link link;
1457         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1458         struct e1000_adapter *adapter =
1459                 E1000_DEV_PRIVATE(dev->data->dev_private);
1460
1461         if (adapter->stopped)
1462                 return;
1463
1464         eth_igb_rxtx_control(dev, false);
1465
1466         igb_intr_disable(dev);
1467
1468         /* disable intr eventfd mapping */
1469         rte_intr_disable(intr_handle);
1470
1471         igb_pf_reset_hw(hw);
1472         E1000_WRITE_REG(hw, E1000_WUC, 0);
1473
1474         /* Set bit for Go Link disconnect if PHY reset is not blocked */
1475         if (hw->mac.type >= e1000_82580 &&
1476             (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1477                 uint32_t phpm_reg;
1478
1479                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1480                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1481                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1482         }
1483
1484         /* Power down the phy. Needed to make the link go Down */
1485         eth_igb_dev_set_link_down(dev);
1486
1487         igb_dev_clear_queues(dev);
1488
1489         /* clear the recorded link status */
1490         memset(&link, 0, sizeof(link));
1491         rte_eth_linkstatus_set(dev, &link);
1492
1493         if (!rte_intr_allow_others(intr_handle))
1494                 /* resume to the default handler */
1495                 rte_intr_callback_register(intr_handle,
1496                                            eth_igb_interrupt_handler,
1497                                            (void *)dev);
1498
1499         /* Clean datapath event and queue/vec mapping */
1500         rte_intr_efd_disable(intr_handle);
1501         if (intr_handle->intr_vec != NULL) {
1502                 rte_free(intr_handle->intr_vec);
1503                 intr_handle->intr_vec = NULL;
1504         }
1505
1506         adapter->stopped = true;
1507 }
1508
1509 static int
1510 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1511 {
1512         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1513
1514         if (hw->phy.media_type == e1000_media_type_copper)
1515                 e1000_power_up_phy(hw);
1516         else
1517                 e1000_power_up_fiber_serdes_link(hw);
1518
1519         return 0;
1520 }
1521
1522 static int
1523 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1524 {
1525         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1526
1527         if (hw->phy.media_type == e1000_media_type_copper)
1528                 e1000_power_down_phy(hw);
1529         else
1530                 e1000_shutdown_fiber_serdes_link(hw);
1531
1532         return 0;
1533 }
1534
1535 static void
1536 eth_igb_close(struct rte_eth_dev *dev)
1537 {
1538         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1539         struct rte_eth_link link;
1540         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1541         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1542         struct e1000_filter_info *filter_info =
1543                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1544
1545         eth_igb_stop(dev);
1546
1547         e1000_phy_hw_reset(hw);
1548         igb_release_manageability(hw);
1549         igb_hw_control_release(hw);
1550
1551         /* Clear bit for Go Link disconnect if PHY reset is not blocked */
1552         if (hw->mac.type >= e1000_82580 &&
1553             (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1554                 uint32_t phpm_reg;
1555
1556                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1557                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1558                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1559         }
1560
1561         igb_dev_free_queues(dev);
1562
1563         if (intr_handle->intr_vec) {
1564                 rte_free(intr_handle->intr_vec);
1565                 intr_handle->intr_vec = NULL;
1566         }
1567
1568         memset(&link, 0, sizeof(link));
1569         rte_eth_linkstatus_set(dev, &link);
1570
1571         dev->dev_ops = NULL;
1572         dev->rx_pkt_burst = NULL;
1573         dev->tx_pkt_burst = NULL;
1574
1575         /* Reset any pending lock */
1576         igb_reset_swfw_lock(hw);
1577
1578         /* uninitialize PF if max_vfs not zero */
1579         igb_pf_host_uninit(dev);
1580
1581         rte_intr_callback_unregister(intr_handle,
1582                                      eth_igb_interrupt_handler, dev);
1583
1584         /* clear the SYN filter info */
1585         filter_info->syn_info = 0;
1586
1587         /* clear the ethertype filters info */
1588         filter_info->ethertype_mask = 0;
1589         memset(filter_info->ethertype_filters, 0,
1590                 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
1591
1592         /* clear the rss filter info */
1593         memset(&filter_info->rss_info, 0,
1594                 sizeof(struct igb_rte_flow_rss_conf));
1595
1596         /* remove all ntuple filters of the device */
1597         igb_ntuple_filter_uninit(dev);
1598
1599         /* remove all flex filters of the device */
1600         igb_flex_filter_uninit(dev);
1601
1602         /* clear all the filters list */
1603         igb_filterlist_flush(dev);
1604 }
1605
1606 /*
1607  * Reset PF device.
1608  */
1609 static int
1610 eth_igb_reset(struct rte_eth_dev *dev)
1611 {
1612         int ret;
1613
1614         /* When a DPDK PMD PF begin to reset PF port, it should notify all
1615          * its VF to make them align with it. The detailed notification
1616          * mechanism is PMD specific and is currently not implemented.
1617          * To avoid unexpected behavior in VF, currently reset of PF with
1618          * SR-IOV activation is not supported. It might be supported later.
1619          */
1620         if (dev->data->sriov.active)
1621                 return -ENOTSUP;
1622
1623         ret = eth_igb_dev_uninit(dev);
1624         if (ret)
1625                 return ret;
1626
1627         ret = eth_igb_dev_init(dev);
1628
1629         return ret;
1630 }
1631
1632
1633 static int
1634 igb_get_rx_buffer_size(struct e1000_hw *hw)
1635 {
1636         uint32_t rx_buf_size;
1637         if (hw->mac.type == e1000_82576) {
1638                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1639         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1640                 /* PBS needs to be translated according to a lookup table */
1641                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1642                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1643                 rx_buf_size = (rx_buf_size << 10);
1644         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1645                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1646         } else {
1647                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1648         }
1649
1650         return rx_buf_size;
1651 }
1652
1653 /*********************************************************************
1654  *
1655  *  Initialize the hardware
1656  *
1657  **********************************************************************/
1658 static int
1659 igb_hardware_init(struct e1000_hw *hw)
1660 {
1661         uint32_t rx_buf_size;
1662         int diag;
1663
1664         /* Let the firmware know the OS is in control */
1665         igb_hw_control_acquire(hw);
1666
1667         /*
1668          * These parameters control the automatic generation (Tx) and
1669          * response (Rx) to Ethernet PAUSE frames.
1670          * - High water mark should allow for at least two standard size (1518)
1671          *   frames to be received after sending an XOFF.
1672          * - Low water mark works best when it is very near the high water mark.
1673          *   This allows the receiver to restart by sending XON when it has
1674          *   drained a bit. Here we use an arbitrary value of 1500 which will
1675          *   restart after one full frame is pulled from the buffer. There
1676          *   could be several smaller frames in the buffer and if so they will
1677          *   not trigger the XON until their total number reduces the buffer
1678          *   by 1500.
1679          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1680          */
1681         rx_buf_size = igb_get_rx_buffer_size(hw);
1682
1683         hw->fc.high_water = rx_buf_size - (RTE_ETHER_MAX_LEN * 2);
1684         hw->fc.low_water = hw->fc.high_water - 1500;
1685         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1686         hw->fc.send_xon = 1;
1687
1688         /* Set Flow control, use the tunable location if sane */
1689         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1690                 hw->fc.requested_mode = igb_fc_setting;
1691         else
1692                 hw->fc.requested_mode = e1000_fc_none;
1693
1694         /* Issue a global reset */
1695         igb_pf_reset_hw(hw);
1696         E1000_WRITE_REG(hw, E1000_WUC, 0);
1697
1698         diag = e1000_init_hw(hw);
1699         if (diag < 0)
1700                 return diag;
1701
1702         E1000_WRITE_REG(hw, E1000_VET,
1703                         RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1704         e1000_get_phy_info(hw);
1705         e1000_check_for_link(hw);
1706
1707         return 0;
1708 }
1709
1710 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1711 static void
1712 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1713 {
1714         int pause_frames;
1715
1716         uint64_t old_gprc  = stats->gprc;
1717         uint64_t old_gptc  = stats->gptc;
1718         uint64_t old_tpr   = stats->tpr;
1719         uint64_t old_tpt   = stats->tpt;
1720         uint64_t old_rpthc = stats->rpthc;
1721         uint64_t old_hgptc = stats->hgptc;
1722
1723         if(hw->phy.media_type == e1000_media_type_copper ||
1724             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1725                 stats->symerrs +=
1726                     E1000_READ_REG(hw,E1000_SYMERRS);
1727                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1728         }
1729
1730         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1731         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1732         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1733         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1734
1735         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1736         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1737         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1738         stats->dc += E1000_READ_REG(hw, E1000_DC);
1739         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1740         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1741         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1742         /*
1743         ** For watchdog management we need to know if we have been
1744         ** paused during the last interval, so capture that here.
1745         */
1746         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1747         stats->xoffrxc += pause_frames;
1748         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1749         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1750         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1751         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1752         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1753         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1754         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1755         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1756         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1757         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1758         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1759         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1760
1761         /* For the 64-bit byte counters the low dword must be read first. */
1762         /* Both registers clear on the read of the high dword */
1763
1764         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1765         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1766         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1767         stats->gorc -= (stats->gprc - old_gprc) * RTE_ETHER_CRC_LEN;
1768         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1769         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1770         stats->gotc -= (stats->gptc - old_gptc) * RTE_ETHER_CRC_LEN;
1771
1772         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1773         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1774         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1775         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1776         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1777
1778         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1779         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1780
1781         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1782         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1783         stats->tor -= (stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
1784         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1785         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1786         stats->tot -= (stats->tpt - old_tpt) * RTE_ETHER_CRC_LEN;
1787
1788         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1789         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1790         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1791         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1792         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1793         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1794         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1795         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1796
1797         /* Interrupt Counts */
1798
1799         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1800         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1801         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1802         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1803         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1804         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1805         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1806         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1807         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1808
1809         /* Host to Card Statistics */
1810
1811         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1812         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1813         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1814         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1815         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1816         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1817         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1818         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1819         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1820         stats->hgorc -= (stats->rpthc - old_rpthc) * RTE_ETHER_CRC_LEN;
1821         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1822         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1823         stats->hgotc -= (stats->hgptc - old_hgptc) * RTE_ETHER_CRC_LEN;
1824         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1825         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1826         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1827
1828         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1829         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1830         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1831         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1832         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1833         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1834 }
1835
1836 static int
1837 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1838 {
1839         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1840         struct e1000_hw_stats *stats =
1841                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1842
1843         igb_read_stats_registers(hw, stats);
1844
1845         if (rte_stats == NULL)
1846                 return -EINVAL;
1847
1848         /* Rx Errors */
1849         rte_stats->imissed = stats->mpc;
1850         rte_stats->ierrors = stats->crcerrs +
1851                              stats->rlec + stats->ruc + stats->roc +
1852                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1853
1854         /* Tx Errors */
1855         rte_stats->oerrors = stats->ecol + stats->latecol;
1856
1857         rte_stats->ipackets = stats->gprc;
1858         rte_stats->opackets = stats->gptc;
1859         rte_stats->ibytes   = stats->gorc;
1860         rte_stats->obytes   = stats->gotc;
1861         return 0;
1862 }
1863
1864 static int
1865 eth_igb_stats_reset(struct rte_eth_dev *dev)
1866 {
1867         struct e1000_hw_stats *hw_stats =
1868                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1869
1870         /* HW registers are cleared on read */
1871         eth_igb_stats_get(dev, NULL);
1872
1873         /* Reset software totals */
1874         memset(hw_stats, 0, sizeof(*hw_stats));
1875
1876         return 0;
1877 }
1878
1879 static int
1880 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1881 {
1882         struct e1000_hw_stats *stats =
1883                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1884
1885         /* HW registers are cleared on read */
1886         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1887
1888         /* Reset software totals */
1889         memset(stats, 0, sizeof(*stats));
1890
1891         return 0;
1892 }
1893
1894 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1895         struct rte_eth_xstat_name *xstats_names,
1896         __rte_unused unsigned int size)
1897 {
1898         unsigned i;
1899
1900         if (xstats_names == NULL)
1901                 return IGB_NB_XSTATS;
1902
1903         /* Note: limit checked in rte_eth_xstats_names() */
1904
1905         for (i = 0; i < IGB_NB_XSTATS; i++) {
1906                 strlcpy(xstats_names[i].name, rte_igb_stats_strings[i].name,
1907                         sizeof(xstats_names[i].name));
1908         }
1909
1910         return IGB_NB_XSTATS;
1911 }
1912
1913 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1914                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1915                 unsigned int limit)
1916 {
1917         unsigned int i;
1918
1919         if (!ids) {
1920                 if (xstats_names == NULL)
1921                         return IGB_NB_XSTATS;
1922
1923                 for (i = 0; i < IGB_NB_XSTATS; i++)
1924                         strlcpy(xstats_names[i].name,
1925                                 rte_igb_stats_strings[i].name,
1926                                 sizeof(xstats_names[i].name));
1927
1928                 return IGB_NB_XSTATS;
1929
1930         } else {
1931                 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1932
1933                 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1934                                 IGB_NB_XSTATS);
1935
1936                 for (i = 0; i < limit; i++) {
1937                         if (ids[i] >= IGB_NB_XSTATS) {
1938                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1939                                 return -1;
1940                         }
1941                         strcpy(xstats_names[i].name,
1942                                         xstats_names_copy[ids[i]].name);
1943                 }
1944                 return limit;
1945         }
1946 }
1947
1948 static int
1949 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1950                    unsigned n)
1951 {
1952         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1953         struct e1000_hw_stats *hw_stats =
1954                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1955         unsigned i;
1956
1957         if (n < IGB_NB_XSTATS)
1958                 return IGB_NB_XSTATS;
1959
1960         igb_read_stats_registers(hw, hw_stats);
1961
1962         /* If this is a reset xstats is NULL, and we have cleared the
1963          * registers by reading them.
1964          */
1965         if (!xstats)
1966                 return 0;
1967
1968         /* Extended stats */
1969         for (i = 0; i < IGB_NB_XSTATS; i++) {
1970                 xstats[i].id = i;
1971                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1972                         rte_igb_stats_strings[i].offset);
1973         }
1974
1975         return IGB_NB_XSTATS;
1976 }
1977
1978 static int
1979 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1980                 uint64_t *values, unsigned int n)
1981 {
1982         unsigned int i;
1983
1984         if (!ids) {
1985                 struct e1000_hw *hw =
1986                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1987                 struct e1000_hw_stats *hw_stats =
1988                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1989
1990                 if (n < IGB_NB_XSTATS)
1991                         return IGB_NB_XSTATS;
1992
1993                 igb_read_stats_registers(hw, hw_stats);
1994
1995                 /* If this is a reset xstats is NULL, and we have cleared the
1996                  * registers by reading them.
1997                  */
1998                 if (!values)
1999                         return 0;
2000
2001                 /* Extended stats */
2002                 for (i = 0; i < IGB_NB_XSTATS; i++)
2003                         values[i] = *(uint64_t *)(((char *)hw_stats) +
2004                                         rte_igb_stats_strings[i].offset);
2005
2006                 return IGB_NB_XSTATS;
2007
2008         } else {
2009                 uint64_t values_copy[IGB_NB_XSTATS];
2010
2011                 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
2012                                 IGB_NB_XSTATS);
2013
2014                 for (i = 0; i < n; i++) {
2015                         if (ids[i] >= IGB_NB_XSTATS) {
2016                                 PMD_INIT_LOG(ERR, "id value isn't valid");
2017                                 return -1;
2018                         }
2019                         values[i] = values_copy[ids[i]];
2020                 }
2021                 return n;
2022         }
2023 }
2024
2025 static void
2026 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2027 {
2028         /* Good Rx packets, include VF loopback */
2029         UPDATE_VF_STAT(E1000_VFGPRC,
2030             hw_stats->last_gprc, hw_stats->gprc);
2031
2032         /* Good Rx octets, include VF loopback */
2033         UPDATE_VF_STAT(E1000_VFGORC,
2034             hw_stats->last_gorc, hw_stats->gorc);
2035
2036         /* Good Tx packets, include VF loopback */
2037         UPDATE_VF_STAT(E1000_VFGPTC,
2038             hw_stats->last_gptc, hw_stats->gptc);
2039
2040         /* Good Tx octets, include VF loopback */
2041         UPDATE_VF_STAT(E1000_VFGOTC,
2042             hw_stats->last_gotc, hw_stats->gotc);
2043
2044         /* Rx Multicst packets */
2045         UPDATE_VF_STAT(E1000_VFMPRC,
2046             hw_stats->last_mprc, hw_stats->mprc);
2047
2048         /* Good Rx loopback packets */
2049         UPDATE_VF_STAT(E1000_VFGPRLBC,
2050             hw_stats->last_gprlbc, hw_stats->gprlbc);
2051
2052         /* Good Rx loopback octets */
2053         UPDATE_VF_STAT(E1000_VFGORLBC,
2054             hw_stats->last_gorlbc, hw_stats->gorlbc);
2055
2056         /* Good Tx loopback packets */
2057         UPDATE_VF_STAT(E1000_VFGPTLBC,
2058             hw_stats->last_gptlbc, hw_stats->gptlbc);
2059
2060         /* Good Tx loopback octets */
2061         UPDATE_VF_STAT(E1000_VFGOTLBC,
2062             hw_stats->last_gotlbc, hw_stats->gotlbc);
2063 }
2064
2065 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2066                                      struct rte_eth_xstat_name *xstats_names,
2067                                      __rte_unused unsigned limit)
2068 {
2069         unsigned i;
2070
2071         if (xstats_names != NULL)
2072                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2073                         strlcpy(xstats_names[i].name,
2074                                 rte_igbvf_stats_strings[i].name,
2075                                 sizeof(xstats_names[i].name));
2076                 }
2077         return IGBVF_NB_XSTATS;
2078 }
2079
2080 static int
2081 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2082                      unsigned n)
2083 {
2084         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2085         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2086                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2087         unsigned i;
2088
2089         if (n < IGBVF_NB_XSTATS)
2090                 return IGBVF_NB_XSTATS;
2091
2092         igbvf_read_stats_registers(hw, hw_stats);
2093
2094         if (!xstats)
2095                 return 0;
2096
2097         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2098                 xstats[i].id = i;
2099                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2100                         rte_igbvf_stats_strings[i].offset);
2101         }
2102
2103         return IGBVF_NB_XSTATS;
2104 }
2105
2106 static int
2107 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2108 {
2109         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2110         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2111                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2112
2113         igbvf_read_stats_registers(hw, hw_stats);
2114
2115         if (rte_stats == NULL)
2116                 return -EINVAL;
2117
2118         rte_stats->ipackets = hw_stats->gprc;
2119         rte_stats->ibytes = hw_stats->gorc;
2120         rte_stats->opackets = hw_stats->gptc;
2121         rte_stats->obytes = hw_stats->gotc;
2122         return 0;
2123 }
2124
2125 static int
2126 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2127 {
2128         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2129                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2130
2131         /* Sync HW register to the last stats */
2132         eth_igbvf_stats_get(dev, NULL);
2133
2134         /* reset HW current stats*/
2135         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2136                offsetof(struct e1000_vf_stats, gprc));
2137
2138         return 0;
2139 }
2140
2141 static int
2142 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2143                        size_t fw_size)
2144 {
2145         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2146         struct e1000_fw_version fw;
2147         int ret;
2148
2149         e1000_get_fw_version(hw, &fw);
2150
2151         switch (hw->mac.type) {
2152         case e1000_i210:
2153         case e1000_i211:
2154                 if (!(e1000_get_flash_presence_i210(hw))) {
2155                         ret = snprintf(fw_version, fw_size,
2156                                  "%2d.%2d-%d",
2157                                  fw.invm_major, fw.invm_minor,
2158                                  fw.invm_img_type);
2159                         break;
2160                 }
2161                 /* fall through */
2162         default:
2163                 /* if option rom is valid, display its version too */
2164                 if (fw.or_valid) {
2165                         ret = snprintf(fw_version, fw_size,
2166                                  "%d.%d, 0x%08x, %d.%d.%d",
2167                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2168                                  fw.or_major, fw.or_build, fw.or_patch);
2169                 /* no option rom */
2170                 } else {
2171                         if (fw.etrack_id != 0X0000) {
2172                                 ret = snprintf(fw_version, fw_size,
2173                                          "%d.%d, 0x%08x",
2174                                          fw.eep_major, fw.eep_minor,
2175                                          fw.etrack_id);
2176                         } else {
2177                                 ret = snprintf(fw_version, fw_size,
2178                                          "%d.%d.%d",
2179                                          fw.eep_major, fw.eep_minor,
2180                                          fw.eep_build);
2181                         }
2182                 }
2183                 break;
2184         }
2185
2186         ret += 1; /* add the size of '\0' */
2187         if (fw_size < (u32)ret)
2188                 return ret;
2189         else
2190                 return 0;
2191 }
2192
2193 static int
2194 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2195 {
2196         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2197
2198         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2199         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2200         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2201         dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2202         dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2203                                     dev_info->rx_queue_offload_capa;
2204         dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2205         dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2206                                     dev_info->tx_queue_offload_capa;
2207
2208         switch (hw->mac.type) {
2209         case e1000_82575:
2210                 dev_info->max_rx_queues = 4;
2211                 dev_info->max_tx_queues = 4;
2212                 dev_info->max_vmdq_pools = 0;
2213                 break;
2214
2215         case e1000_82576:
2216                 dev_info->max_rx_queues = 16;
2217                 dev_info->max_tx_queues = 16;
2218                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2219                 dev_info->vmdq_queue_num = 16;
2220                 break;
2221
2222         case e1000_82580:
2223                 dev_info->max_rx_queues = 8;
2224                 dev_info->max_tx_queues = 8;
2225                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2226                 dev_info->vmdq_queue_num = 8;
2227                 break;
2228
2229         case e1000_i350:
2230                 dev_info->max_rx_queues = 8;
2231                 dev_info->max_tx_queues = 8;
2232                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2233                 dev_info->vmdq_queue_num = 8;
2234                 break;
2235
2236         case e1000_i354:
2237                 dev_info->max_rx_queues = 8;
2238                 dev_info->max_tx_queues = 8;
2239                 break;
2240
2241         case e1000_i210:
2242                 dev_info->max_rx_queues = 4;
2243                 dev_info->max_tx_queues = 4;
2244                 dev_info->max_vmdq_pools = 0;
2245                 break;
2246
2247         case e1000_i211:
2248                 dev_info->max_rx_queues = 2;
2249                 dev_info->max_tx_queues = 2;
2250                 dev_info->max_vmdq_pools = 0;
2251                 break;
2252
2253         default:
2254                 /* Should not happen */
2255                 return -EINVAL;
2256         }
2257         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2258         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2259         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2260
2261         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2262                 .rx_thresh = {
2263                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2264                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2265                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2266                 },
2267                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2268                 .rx_drop_en = 0,
2269                 .offloads = 0,
2270         };
2271
2272         dev_info->default_txconf = (struct rte_eth_txconf) {
2273                 .tx_thresh = {
2274                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2275                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2276                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2277                 },
2278                 .offloads = 0,
2279         };
2280
2281         dev_info->rx_desc_lim = rx_desc_lim;
2282         dev_info->tx_desc_lim = tx_desc_lim;
2283
2284         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2285                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2286                         ETH_LINK_SPEED_1G;
2287
2288         dev_info->max_mtu = dev_info->max_rx_pktlen - E1000_ETH_OVERHEAD;
2289         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2290
2291         return 0;
2292 }
2293
2294 static const uint32_t *
2295 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2296 {
2297         static const uint32_t ptypes[] = {
2298                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2299                 RTE_PTYPE_L2_ETHER,
2300                 RTE_PTYPE_L3_IPV4,
2301                 RTE_PTYPE_L3_IPV4_EXT,
2302                 RTE_PTYPE_L3_IPV6,
2303                 RTE_PTYPE_L3_IPV6_EXT,
2304                 RTE_PTYPE_L4_TCP,
2305                 RTE_PTYPE_L4_UDP,
2306                 RTE_PTYPE_L4_SCTP,
2307                 RTE_PTYPE_TUNNEL_IP,
2308                 RTE_PTYPE_INNER_L3_IPV6,
2309                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2310                 RTE_PTYPE_INNER_L4_TCP,
2311                 RTE_PTYPE_INNER_L4_UDP,
2312                 RTE_PTYPE_UNKNOWN
2313         };
2314
2315         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2316             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2317                 return ptypes;
2318         return NULL;
2319 }
2320
2321 static int
2322 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2323 {
2324         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2325
2326         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2327         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2328         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2329         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2330                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2331                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2332                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2333                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2334                                 DEV_TX_OFFLOAD_TCP_TSO;
2335         switch (hw->mac.type) {
2336         case e1000_vfadapt:
2337                 dev_info->max_rx_queues = 2;
2338                 dev_info->max_tx_queues = 2;
2339                 break;
2340         case e1000_vfadapt_i350:
2341                 dev_info->max_rx_queues = 1;
2342                 dev_info->max_tx_queues = 1;
2343                 break;
2344         default:
2345                 /* Should not happen */
2346                 return -EINVAL;
2347         }
2348
2349         dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2350         dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2351                                     dev_info->rx_queue_offload_capa;
2352         dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2353         dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2354                                     dev_info->tx_queue_offload_capa;
2355
2356         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2357                 .rx_thresh = {
2358                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2359                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2360                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2361                 },
2362                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2363                 .rx_drop_en = 0,
2364                 .offloads = 0,
2365         };
2366
2367         dev_info->default_txconf = (struct rte_eth_txconf) {
2368                 .tx_thresh = {
2369                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2370                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2371                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2372                 },
2373                 .offloads = 0,
2374         };
2375
2376         dev_info->rx_desc_lim = rx_desc_lim;
2377         dev_info->tx_desc_lim = tx_desc_lim;
2378
2379         return 0;
2380 }
2381
2382 /* return 0 means link status changed, -1 means not changed */
2383 static int
2384 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2385 {
2386         struct e1000_hw *hw =
2387                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2388         struct rte_eth_link link;
2389         int link_check, count;
2390
2391         link_check = 0;
2392         hw->mac.get_link_status = 1;
2393
2394         /* possible wait-to-complete in up to 9 seconds */
2395         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2396                 /* Read the real link status */
2397                 switch (hw->phy.media_type) {
2398                 case e1000_media_type_copper:
2399                         /* Do the work to read phy */
2400                         e1000_check_for_link(hw);
2401                         link_check = !hw->mac.get_link_status;
2402                         break;
2403
2404                 case e1000_media_type_fiber:
2405                         e1000_check_for_link(hw);
2406                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2407                                       E1000_STATUS_LU);
2408                         break;
2409
2410                 case e1000_media_type_internal_serdes:
2411                         e1000_check_for_link(hw);
2412                         link_check = hw->mac.serdes_has_link;
2413                         break;
2414
2415                 /* VF device is type_unknown */
2416                 case e1000_media_type_unknown:
2417                         eth_igbvf_link_update(hw);
2418                         link_check = !hw->mac.get_link_status;
2419                         break;
2420
2421                 default:
2422                         break;
2423                 }
2424                 if (link_check || wait_to_complete == 0)
2425                         break;
2426                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2427         }
2428         memset(&link, 0, sizeof(link));
2429
2430         /* Now we check if a transition has happened */
2431         if (link_check) {
2432                 uint16_t duplex, speed;
2433                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2434                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2435                                 ETH_LINK_FULL_DUPLEX :
2436                                 ETH_LINK_HALF_DUPLEX;
2437                 link.link_speed = speed;
2438                 link.link_status = ETH_LINK_UP;
2439                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2440                                 ETH_LINK_SPEED_FIXED);
2441         } else if (!link_check) {
2442                 link.link_speed = 0;
2443                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2444                 link.link_status = ETH_LINK_DOWN;
2445                 link.link_autoneg = ETH_LINK_FIXED;
2446         }
2447
2448         return rte_eth_linkstatus_set(dev, &link);
2449 }
2450
2451 /*
2452  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2453  * For ASF and Pass Through versions of f/w this means
2454  * that the driver is loaded.
2455  */
2456 static void
2457 igb_hw_control_acquire(struct e1000_hw *hw)
2458 {
2459         uint32_t ctrl_ext;
2460
2461         /* Let firmware know the driver has taken over */
2462         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2463         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2464 }
2465
2466 /*
2467  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2468  * For ASF and Pass Through versions of f/w this means that the
2469  * driver is no longer loaded.
2470  */
2471 static void
2472 igb_hw_control_release(struct e1000_hw *hw)
2473 {
2474         uint32_t ctrl_ext;
2475
2476         /* Let firmware taken over control of h/w */
2477         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2478         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2479                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2480 }
2481
2482 /*
2483  * Bit of a misnomer, what this really means is
2484  * to enable OS management of the system... aka
2485  * to disable special hardware management features.
2486  */
2487 static void
2488 igb_init_manageability(struct e1000_hw *hw)
2489 {
2490         if (e1000_enable_mng_pass_thru(hw)) {
2491                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2492                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2493
2494                 /* disable hardware interception of ARP */
2495                 manc &= ~(E1000_MANC_ARP_EN);
2496
2497                 /* enable receiving management packets to the host */
2498                 manc |= E1000_MANC_EN_MNG2HOST;
2499                 manc2h |= 1 << 5;  /* Mng Port 623 */
2500                 manc2h |= 1 << 6;  /* Mng Port 664 */
2501                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2502                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2503         }
2504 }
2505
2506 static void
2507 igb_release_manageability(struct e1000_hw *hw)
2508 {
2509         if (e1000_enable_mng_pass_thru(hw)) {
2510                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2511
2512                 manc |= E1000_MANC_ARP_EN;
2513                 manc &= ~E1000_MANC_EN_MNG2HOST;
2514
2515                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2516         }
2517 }
2518
2519 static int
2520 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2521 {
2522         struct e1000_hw *hw =
2523                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2524         uint32_t rctl;
2525
2526         rctl = E1000_READ_REG(hw, E1000_RCTL);
2527         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2528         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2529
2530         return 0;
2531 }
2532
2533 static int
2534 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2535 {
2536         struct e1000_hw *hw =
2537                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2538         uint32_t rctl;
2539
2540         rctl = E1000_READ_REG(hw, E1000_RCTL);
2541         rctl &= (~E1000_RCTL_UPE);
2542         if (dev->data->all_multicast == 1)
2543                 rctl |= E1000_RCTL_MPE;
2544         else
2545                 rctl &= (~E1000_RCTL_MPE);
2546         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2547
2548         return 0;
2549 }
2550
2551 static int
2552 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2553 {
2554         struct e1000_hw *hw =
2555                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2556         uint32_t rctl;
2557
2558         rctl = E1000_READ_REG(hw, E1000_RCTL);
2559         rctl |= E1000_RCTL_MPE;
2560         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2561
2562         return 0;
2563 }
2564
2565 static int
2566 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2567 {
2568         struct e1000_hw *hw =
2569                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2570         uint32_t rctl;
2571
2572         if (dev->data->promiscuous == 1)
2573                 return 0; /* must remain in all_multicast mode */
2574         rctl = E1000_READ_REG(hw, E1000_RCTL);
2575         rctl &= (~E1000_RCTL_MPE);
2576         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2577
2578         return 0;
2579 }
2580
2581 static int
2582 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2583 {
2584         struct e1000_hw *hw =
2585                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2586         struct e1000_vfta * shadow_vfta =
2587                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2588         uint32_t vfta;
2589         uint32_t vid_idx;
2590         uint32_t vid_bit;
2591
2592         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2593                               E1000_VFTA_ENTRY_MASK);
2594         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2595         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2596         if (on)
2597                 vfta |= vid_bit;
2598         else
2599                 vfta &= ~vid_bit;
2600         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2601
2602         /* update local VFTA copy */
2603         shadow_vfta->vfta[vid_idx] = vfta;
2604
2605         return 0;
2606 }
2607
2608 static int
2609 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2610                       enum rte_vlan_type vlan_type,
2611                       uint16_t tpid)
2612 {
2613         struct e1000_hw *hw =
2614                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2615         uint32_t reg, qinq;
2616
2617         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2618         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2619
2620         /* only outer TPID of double VLAN can be configured*/
2621         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2622                 reg = E1000_READ_REG(hw, E1000_VET);
2623                 reg = (reg & (~E1000_VET_VET_EXT)) |
2624                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2625                 E1000_WRITE_REG(hw, E1000_VET, reg);
2626
2627                 return 0;
2628         }
2629
2630         /* all other TPID values are read-only*/
2631         PMD_DRV_LOG(ERR, "Not supported");
2632
2633         return -ENOTSUP;
2634 }
2635
2636 static void
2637 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2638 {
2639         struct e1000_hw *hw =
2640                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2641         uint32_t reg;
2642
2643         /* Filter Table Disable */
2644         reg = E1000_READ_REG(hw, E1000_RCTL);
2645         reg &= ~E1000_RCTL_CFIEN;
2646         reg &= ~E1000_RCTL_VFE;
2647         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2648 }
2649
2650 static void
2651 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2652 {
2653         struct e1000_hw *hw =
2654                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2655         struct e1000_vfta * shadow_vfta =
2656                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2657         uint32_t reg;
2658         int i;
2659
2660         /* Filter Table Enable, CFI not used for packet acceptance */
2661         reg = E1000_READ_REG(hw, E1000_RCTL);
2662         reg &= ~E1000_RCTL_CFIEN;
2663         reg |= E1000_RCTL_VFE;
2664         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2665
2666         /* restore VFTA table */
2667         for (i = 0; i < IGB_VFTA_SIZE; i++)
2668                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2669 }
2670
2671 static void
2672 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2673 {
2674         struct e1000_hw *hw =
2675                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2676         uint32_t reg;
2677
2678         /* VLAN Mode Disable */
2679         reg = E1000_READ_REG(hw, E1000_CTRL);
2680         reg &= ~E1000_CTRL_VME;
2681         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2682 }
2683
2684 static void
2685 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2686 {
2687         struct e1000_hw *hw =
2688                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2689         uint32_t reg;
2690
2691         /* VLAN Mode Enable */
2692         reg = E1000_READ_REG(hw, E1000_CTRL);
2693         reg |= E1000_CTRL_VME;
2694         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2695 }
2696
2697 static void
2698 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2699 {
2700         struct e1000_hw *hw =
2701                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2702         uint32_t reg;
2703
2704         /* CTRL_EXT: Extended VLAN */
2705         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2706         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2707         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2708
2709         /* Update maximum packet length */
2710         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2711                 E1000_WRITE_REG(hw, E1000_RLPML,
2712                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2713                                                 VLAN_TAG_SIZE);
2714 }
2715
2716 static void
2717 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2718 {
2719         struct e1000_hw *hw =
2720                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2721         uint32_t reg;
2722
2723         /* CTRL_EXT: Extended VLAN */
2724         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2725         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2726         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2727
2728         /* Update maximum packet length */
2729         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2730                 E1000_WRITE_REG(hw, E1000_RLPML,
2731                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2732                                                 2 * VLAN_TAG_SIZE);
2733 }
2734
2735 static int
2736 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2737 {
2738         struct rte_eth_rxmode *rxmode;
2739
2740         rxmode = &dev->data->dev_conf.rxmode;
2741         if(mask & ETH_VLAN_STRIP_MASK){
2742                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2743                         igb_vlan_hw_strip_enable(dev);
2744                 else
2745                         igb_vlan_hw_strip_disable(dev);
2746         }
2747
2748         if(mask & ETH_VLAN_FILTER_MASK){
2749                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2750                         igb_vlan_hw_filter_enable(dev);
2751                 else
2752                         igb_vlan_hw_filter_disable(dev);
2753         }
2754
2755         if(mask & ETH_VLAN_EXTEND_MASK){
2756                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2757                         igb_vlan_hw_extend_enable(dev);
2758                 else
2759                         igb_vlan_hw_extend_disable(dev);
2760         }
2761
2762         return 0;
2763 }
2764
2765
2766 /**
2767  * It enables the interrupt mask and then enable the interrupt.
2768  *
2769  * @param dev
2770  *  Pointer to struct rte_eth_dev.
2771  * @param on
2772  *  Enable or Disable
2773  *
2774  * @return
2775  *  - On success, zero.
2776  *  - On failure, a negative value.
2777  */
2778 static int
2779 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2780 {
2781         struct e1000_interrupt *intr =
2782                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2783
2784         if (on)
2785                 intr->mask |= E1000_ICR_LSC;
2786         else
2787                 intr->mask &= ~E1000_ICR_LSC;
2788
2789         return 0;
2790 }
2791
2792 /* It clears the interrupt causes and enables the interrupt.
2793  * It will be called once only during nic initialized.
2794  *
2795  * @param dev
2796  *  Pointer to struct rte_eth_dev.
2797  *
2798  * @return
2799  *  - On success, zero.
2800  *  - On failure, a negative value.
2801  */
2802 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2803 {
2804         uint32_t mask, regval;
2805         int ret;
2806         struct e1000_hw *hw =
2807                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2808         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2809         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2810         int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0;
2811         struct rte_eth_dev_info dev_info;
2812
2813         memset(&dev_info, 0, sizeof(dev_info));
2814         ret = eth_igb_infos_get(dev, &dev_info);
2815         if (ret != 0)
2816                 return ret;
2817
2818         mask = (0xFFFFFFFF >> (32 - dev_info.max_rx_queues)) << misc_shift;
2819         regval = E1000_READ_REG(hw, E1000_EIMS);
2820         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2821
2822         return 0;
2823 }
2824
2825 /*
2826  * It reads ICR and gets interrupt causes, check it and set a bit flag
2827  * to update link status.
2828  *
2829  * @param dev
2830  *  Pointer to struct rte_eth_dev.
2831  *
2832  * @return
2833  *  - On success, zero.
2834  *  - On failure, a negative value.
2835  */
2836 static int
2837 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2838 {
2839         uint32_t icr;
2840         struct e1000_hw *hw =
2841                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2842         struct e1000_interrupt *intr =
2843                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2844
2845         igb_intr_disable(dev);
2846
2847         /* read-on-clear nic registers here */
2848         icr = E1000_READ_REG(hw, E1000_ICR);
2849
2850         intr->flags = 0;
2851         if (icr & E1000_ICR_LSC) {
2852                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2853         }
2854
2855         if (icr & E1000_ICR_VMMB)
2856                 intr->flags |= E1000_FLAG_MAILBOX;
2857
2858         return 0;
2859 }
2860
2861 /*
2862  * It executes link_update after knowing an interrupt is prsent.
2863  *
2864  * @param dev
2865  *  Pointer to struct rte_eth_dev.
2866  *
2867  * @return
2868  *  - On success, zero.
2869  *  - On failure, a negative value.
2870  */
2871 static int
2872 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2873                          struct rte_intr_handle *intr_handle)
2874 {
2875         struct e1000_hw *hw =
2876                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2877         struct e1000_interrupt *intr =
2878                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2879         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2880         struct rte_eth_link link;
2881         int ret;
2882
2883         if (intr->flags & E1000_FLAG_MAILBOX) {
2884                 igb_pf_mbx_process(dev);
2885                 intr->flags &= ~E1000_FLAG_MAILBOX;
2886         }
2887
2888         igb_intr_enable(dev);
2889         rte_intr_ack(intr_handle);
2890
2891         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2892                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2893
2894                 /* set get_link_status to check register later */
2895                 hw->mac.get_link_status = 1;
2896                 ret = eth_igb_link_update(dev, 0);
2897
2898                 /* check if link has changed */
2899                 if (ret < 0)
2900                         return 0;
2901
2902                 rte_eth_linkstatus_get(dev, &link);
2903                 if (link.link_status) {
2904                         PMD_INIT_LOG(INFO,
2905                                      " Port %d: Link Up - speed %u Mbps - %s",
2906                                      dev->data->port_id,
2907                                      (unsigned)link.link_speed,
2908                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2909                                      "full-duplex" : "half-duplex");
2910                 } else {
2911                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2912                                      dev->data->port_id);
2913                 }
2914
2915                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2916                              pci_dev->addr.domain,
2917                              pci_dev->addr.bus,
2918                              pci_dev->addr.devid,
2919                              pci_dev->addr.function);
2920                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2921                                               NULL);
2922         }
2923
2924         return 0;
2925 }
2926
2927 /**
2928  * Interrupt handler which shall be registered at first.
2929  *
2930  * @param handle
2931  *  Pointer to interrupt handle.
2932  * @param param
2933  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2934  *
2935  * @return
2936  *  void
2937  */
2938 static void
2939 eth_igb_interrupt_handler(void *param)
2940 {
2941         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2942
2943         eth_igb_interrupt_get_status(dev);
2944         eth_igb_interrupt_action(dev, dev->intr_handle);
2945 }
2946
2947 static int
2948 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2949 {
2950         uint32_t eicr;
2951         struct e1000_hw *hw =
2952                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2953         struct e1000_interrupt *intr =
2954                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2955
2956         igbvf_intr_disable(hw);
2957
2958         /* read-on-clear nic registers here */
2959         eicr = E1000_READ_REG(hw, E1000_EICR);
2960         intr->flags = 0;
2961
2962         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2963                 intr->flags |= E1000_FLAG_MAILBOX;
2964
2965         return 0;
2966 }
2967
2968 void igbvf_mbx_process(struct rte_eth_dev *dev)
2969 {
2970         struct e1000_hw *hw =
2971                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2972         struct e1000_mbx_info *mbx = &hw->mbx;
2973         u32 in_msg = 0;
2974
2975         /* peek the message first */
2976         in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2977
2978         /* PF reset VF event */
2979         if (in_msg == E1000_PF_CONTROL_MSG) {
2980                 /* dummy mbx read to ack pf */
2981                 if (mbx->ops.read(hw, &in_msg, 1, 0))
2982                         return;
2983                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2984                                               NULL);
2985         }
2986 }
2987
2988 static int
2989 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2990 {
2991         struct e1000_interrupt *intr =
2992                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2993
2994         if (intr->flags & E1000_FLAG_MAILBOX) {
2995                 igbvf_mbx_process(dev);
2996                 intr->flags &= ~E1000_FLAG_MAILBOX;
2997         }
2998
2999         igbvf_intr_enable(dev);
3000         rte_intr_ack(intr_handle);
3001
3002         return 0;
3003 }
3004
3005 static void
3006 eth_igbvf_interrupt_handler(void *param)
3007 {
3008         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3009
3010         eth_igbvf_interrupt_get_status(dev);
3011         eth_igbvf_interrupt_action(dev, dev->intr_handle);
3012 }
3013
3014 static int
3015 eth_igb_led_on(struct rte_eth_dev *dev)
3016 {
3017         struct e1000_hw *hw;
3018
3019         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3020         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3021 }
3022
3023 static int
3024 eth_igb_led_off(struct rte_eth_dev *dev)
3025 {
3026         struct e1000_hw *hw;
3027
3028         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3029         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3030 }
3031
3032 static int
3033 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3034 {
3035         struct e1000_hw *hw;
3036         uint32_t ctrl;
3037         int tx_pause;
3038         int rx_pause;
3039
3040         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3041         fc_conf->pause_time = hw->fc.pause_time;
3042         fc_conf->high_water = hw->fc.high_water;
3043         fc_conf->low_water = hw->fc.low_water;
3044         fc_conf->send_xon = hw->fc.send_xon;
3045         fc_conf->autoneg = hw->mac.autoneg;
3046
3047         /*
3048          * Return rx_pause and tx_pause status according to actual setting of
3049          * the TFCE and RFCE bits in the CTRL register.
3050          */
3051         ctrl = E1000_READ_REG(hw, E1000_CTRL);
3052         if (ctrl & E1000_CTRL_TFCE)
3053                 tx_pause = 1;
3054         else
3055                 tx_pause = 0;
3056
3057         if (ctrl & E1000_CTRL_RFCE)
3058                 rx_pause = 1;
3059         else
3060                 rx_pause = 0;
3061
3062         if (rx_pause && tx_pause)
3063                 fc_conf->mode = RTE_FC_FULL;
3064         else if (rx_pause)
3065                 fc_conf->mode = RTE_FC_RX_PAUSE;
3066         else if (tx_pause)
3067                 fc_conf->mode = RTE_FC_TX_PAUSE;
3068         else
3069                 fc_conf->mode = RTE_FC_NONE;
3070
3071         return 0;
3072 }
3073
3074 static int
3075 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3076 {
3077         struct e1000_hw *hw;
3078         int err;
3079         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3080                 e1000_fc_none,
3081                 e1000_fc_rx_pause,
3082                 e1000_fc_tx_pause,
3083                 e1000_fc_full
3084         };
3085         uint32_t rx_buf_size;
3086         uint32_t max_high_water;
3087         uint32_t rctl;
3088
3089         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3090         if (fc_conf->autoneg != hw->mac.autoneg)
3091                 return -ENOTSUP;
3092         rx_buf_size = igb_get_rx_buffer_size(hw);
3093         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3094
3095         /* At least reserve one Ethernet frame for watermark */
3096         max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
3097         if ((fc_conf->high_water > max_high_water) ||
3098             (fc_conf->high_water < fc_conf->low_water)) {
3099                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3100                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
3101                 return -EINVAL;
3102         }
3103
3104         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3105         hw->fc.pause_time     = fc_conf->pause_time;
3106         hw->fc.high_water     = fc_conf->high_water;
3107         hw->fc.low_water      = fc_conf->low_water;
3108         hw->fc.send_xon       = fc_conf->send_xon;
3109
3110         err = e1000_setup_link_generic(hw);
3111         if (err == E1000_SUCCESS) {
3112
3113                 /* check if we want to forward MAC frames - driver doesn't have native
3114                  * capability to do that, so we'll write the registers ourselves */
3115
3116                 rctl = E1000_READ_REG(hw, E1000_RCTL);
3117
3118                 /* set or clear MFLCN.PMCF bit depending on configuration */
3119                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3120                         rctl |= E1000_RCTL_PMCF;
3121                 else
3122                         rctl &= ~E1000_RCTL_PMCF;
3123
3124                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3125                 E1000_WRITE_FLUSH(hw);
3126
3127                 return 0;
3128         }
3129
3130         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3131         return -EIO;
3132 }
3133
3134 #define E1000_RAH_POOLSEL_SHIFT      (18)
3135 static int
3136 eth_igb_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3137                 uint32_t index, uint32_t pool)
3138 {
3139         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3140         uint32_t rah;
3141
3142         e1000_rar_set(hw, mac_addr->addr_bytes, index);
3143         rah = E1000_READ_REG(hw, E1000_RAH(index));
3144         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3145         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3146         return 0;
3147 }
3148
3149 static void
3150 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3151 {
3152         uint8_t addr[RTE_ETHER_ADDR_LEN];
3153         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3154
3155         memset(addr, 0, sizeof(addr));
3156
3157         e1000_rar_set(hw, addr, index);
3158 }
3159
3160 static int
3161 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3162                                 struct rte_ether_addr *addr)
3163 {
3164         eth_igb_rar_clear(dev, 0);
3165         eth_igb_rar_set(dev, (void *)addr, 0, 0);
3166
3167         return 0;
3168 }
3169 /*
3170  * Virtual Function operations
3171  */
3172 static void
3173 igbvf_intr_disable(struct e1000_hw *hw)
3174 {
3175         PMD_INIT_FUNC_TRACE();
3176
3177         /* Clear interrupt mask to stop from interrupts being generated */
3178         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3179
3180         E1000_WRITE_FLUSH(hw);
3181 }
3182
3183 static void
3184 igbvf_stop_adapter(struct rte_eth_dev *dev)
3185 {
3186         u32 reg_val;
3187         u16 i;
3188         struct rte_eth_dev_info dev_info;
3189         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3190         int ret;
3191
3192         memset(&dev_info, 0, sizeof(dev_info));
3193         ret = eth_igbvf_infos_get(dev, &dev_info);
3194         if (ret != 0)
3195                 return;
3196
3197         /* Clear interrupt mask to stop from interrupts being generated */
3198         igbvf_intr_disable(hw);
3199
3200         /* Clear any pending interrupts, flush previous writes */
3201         E1000_READ_REG(hw, E1000_EICR);
3202
3203         /* Disable the transmit unit.  Each queue must be disabled. */
3204         for (i = 0; i < dev_info.max_tx_queues; i++)
3205                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3206
3207         /* Disable the receive unit by stopping each queue */
3208         for (i = 0; i < dev_info.max_rx_queues; i++) {
3209                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3210                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3211                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3212                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3213                         ;
3214         }
3215
3216         /* flush all queues disables */
3217         E1000_WRITE_FLUSH(hw);
3218         msec_delay(2);
3219 }
3220
3221 static int eth_igbvf_link_update(struct e1000_hw *hw)
3222 {
3223         struct e1000_mbx_info *mbx = &hw->mbx;
3224         struct e1000_mac_info *mac = &hw->mac;
3225         int ret_val = E1000_SUCCESS;
3226
3227         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3228
3229         /*
3230          * We only want to run this if there has been a rst asserted.
3231          * in this case that could mean a link change, device reset,
3232          * or a virtual function reset
3233          */
3234
3235         /* If we were hit with a reset or timeout drop the link */
3236         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3237                 mac->get_link_status = TRUE;
3238
3239         if (!mac->get_link_status)
3240                 goto out;
3241
3242         /* if link status is down no point in checking to see if pf is up */
3243         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3244                 goto out;
3245
3246         /* if we passed all the tests above then the link is up and we no
3247          * longer need to check for link */
3248         mac->get_link_status = FALSE;
3249
3250 out:
3251         return ret_val;
3252 }
3253
3254
3255 static int
3256 igbvf_dev_configure(struct rte_eth_dev *dev)
3257 {
3258         struct rte_eth_conf* conf = &dev->data->dev_conf;
3259
3260         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3261                      dev->data->port_id);
3262
3263         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3264                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3265
3266         /*
3267          * VF has no ability to enable/disable HW CRC
3268          * Keep the persistent behavior the same as Host PF
3269          */
3270 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3271         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
3272                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3273                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
3274         }
3275 #else
3276         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
3277                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3278                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
3279         }
3280 #endif
3281
3282         return 0;
3283 }
3284
3285 static int
3286 igbvf_dev_start(struct rte_eth_dev *dev)
3287 {
3288         struct e1000_hw *hw =
3289                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3290         struct e1000_adapter *adapter =
3291                 E1000_DEV_PRIVATE(dev->data->dev_private);
3292         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3293         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3294         int ret;
3295         uint32_t intr_vector = 0;
3296
3297         PMD_INIT_FUNC_TRACE();
3298
3299         hw->mac.ops.reset_hw(hw);
3300         adapter->stopped = 0;
3301
3302         /* Set all vfta */
3303         igbvf_set_vfta_all(dev,1);
3304
3305         eth_igbvf_tx_init(dev);
3306
3307         /* This can fail when allocating mbufs for descriptor rings */
3308         ret = eth_igbvf_rx_init(dev);
3309         if (ret) {
3310                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3311                 igb_dev_clear_queues(dev);
3312                 return ret;
3313         }
3314
3315         /* check and configure queue intr-vector mapping */
3316         if (rte_intr_cap_multiple(intr_handle) &&
3317             dev->data->dev_conf.intr_conf.rxq) {
3318                 intr_vector = dev->data->nb_rx_queues;
3319                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3320                 if (ret)
3321                         return ret;
3322         }
3323
3324         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3325                 intr_handle->intr_vec =
3326                         rte_zmalloc("intr_vec",
3327                                     dev->data->nb_rx_queues * sizeof(int), 0);
3328                 if (!intr_handle->intr_vec) {
3329                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3330                                      " intr_vec", dev->data->nb_rx_queues);
3331                         return -ENOMEM;
3332                 }
3333         }
3334
3335         eth_igbvf_configure_msix_intr(dev);
3336
3337         /* enable uio/vfio intr/eventfd mapping */
3338         rte_intr_enable(intr_handle);
3339
3340         /* resume enabled intr since hw reset */
3341         igbvf_intr_enable(dev);
3342
3343         return 0;
3344 }
3345
3346 static void
3347 igbvf_dev_stop(struct rte_eth_dev *dev)
3348 {
3349         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3350         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3351         struct e1000_adapter *adapter =
3352                 E1000_DEV_PRIVATE(dev->data->dev_private);
3353
3354         if (adapter->stopped)
3355                 return;
3356
3357         PMD_INIT_FUNC_TRACE();
3358
3359         igbvf_stop_adapter(dev);
3360
3361         /*
3362           * Clear what we set, but we still keep shadow_vfta to
3363           * restore after device starts
3364           */
3365         igbvf_set_vfta_all(dev,0);
3366
3367         igb_dev_clear_queues(dev);
3368
3369         /* disable intr eventfd mapping */
3370         rte_intr_disable(intr_handle);
3371
3372         /* Clean datapath event and queue/vec mapping */
3373         rte_intr_efd_disable(intr_handle);
3374         if (intr_handle->intr_vec) {
3375                 rte_free(intr_handle->intr_vec);
3376                 intr_handle->intr_vec = NULL;
3377         }
3378
3379         adapter->stopped = true;
3380 }
3381
3382 static void
3383 igbvf_dev_close(struct rte_eth_dev *dev)
3384 {
3385         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3386         struct rte_ether_addr addr;
3387         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3388
3389         PMD_INIT_FUNC_TRACE();
3390
3391         e1000_reset_hw(hw);
3392
3393         igbvf_dev_stop(dev);
3394
3395         igb_dev_free_queues(dev);
3396
3397         /**
3398          * reprogram the RAR with a zero mac address,
3399          * to ensure that the VF traffic goes to the PF
3400          * after stop, close and detach of the VF.
3401          **/
3402
3403         memset(&addr, 0, sizeof(addr));
3404         igbvf_default_mac_addr_set(dev, &addr);
3405
3406         dev->dev_ops = NULL;
3407         dev->rx_pkt_burst = NULL;
3408         dev->tx_pkt_burst = NULL;
3409
3410         rte_intr_callback_unregister(&pci_dev->intr_handle,
3411                                      eth_igbvf_interrupt_handler,
3412                                      (void *)dev);
3413 }
3414
3415 static int
3416 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3417 {
3418         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3419
3420         /* Set both unicast and multicast promisc */
3421         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3422
3423         return 0;
3424 }
3425
3426 static int
3427 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3428 {
3429         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3430
3431         /* If in allmulticast mode leave multicast promisc */
3432         if (dev->data->all_multicast == 1)
3433                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3434         else
3435                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3436
3437         return 0;
3438 }
3439
3440 static int
3441 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3442 {
3443         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3444
3445         /* In promiscuous mode multicast promisc already set */
3446         if (dev->data->promiscuous == 0)
3447                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3448
3449         return 0;
3450 }
3451
3452 static int
3453 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3454 {
3455         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3456
3457         /* In promiscuous mode leave multicast promisc enabled */
3458         if (dev->data->promiscuous == 0)
3459                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3460
3461         return 0;
3462 }
3463
3464 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3465 {
3466         struct e1000_mbx_info *mbx = &hw->mbx;
3467         uint32_t msgbuf[2];
3468         s32 err;
3469
3470         /* After set vlan, vlan strip will also be enabled in igb driver*/
3471         msgbuf[0] = E1000_VF_SET_VLAN;
3472         msgbuf[1] = vid;
3473         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3474         if (on)
3475                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3476
3477         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3478         if (err)
3479                 goto mbx_err;
3480
3481         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3482         if (err)
3483                 goto mbx_err;
3484
3485         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3486         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3487                 err = -EINVAL;
3488
3489 mbx_err:
3490         return err;
3491 }
3492
3493 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3494 {
3495         struct e1000_hw *hw =
3496                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3497         struct e1000_vfta * shadow_vfta =
3498                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3499         int i = 0, j = 0, vfta = 0, mask = 1;
3500
3501         for (i = 0; i < IGB_VFTA_SIZE; i++){
3502                 vfta = shadow_vfta->vfta[i];
3503                 if(vfta){
3504                         mask = 1;
3505                         for (j = 0; j < 32; j++){
3506                                 if(vfta & mask)
3507                                         igbvf_set_vfta(hw,
3508                                                 (uint16_t)((i<<5)+j), on);
3509                                 mask<<=1;
3510                         }
3511                 }
3512         }
3513
3514 }
3515
3516 static int
3517 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3518 {
3519         struct e1000_hw *hw =
3520                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3521         struct e1000_vfta * shadow_vfta =
3522                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3523         uint32_t vid_idx = 0;
3524         uint32_t vid_bit = 0;
3525         int ret = 0;
3526
3527         PMD_INIT_FUNC_TRACE();
3528
3529         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3530         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3531         if(ret){
3532                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3533                 return ret;
3534         }
3535         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3536         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3537
3538         /*Save what we set and retore it after device reset*/
3539         if (on)
3540                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3541         else
3542                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3543
3544         return 0;
3545 }
3546
3547 static int
3548 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3549 {
3550         struct e1000_hw *hw =
3551                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3552
3553         /* index is not used by rar_set() */
3554         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3555         return 0;
3556 }
3557
3558
3559 static int
3560 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3561                         struct rte_eth_rss_reta_entry64 *reta_conf,
3562                         uint16_t reta_size)
3563 {
3564         uint8_t i, j, mask;
3565         uint32_t reta, r;
3566         uint16_t idx, shift;
3567         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3568
3569         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3570                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3571                         "(%d) doesn't match the number hardware can supported "
3572                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3573                 return -EINVAL;
3574         }
3575
3576         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3577                 idx = i / RTE_RETA_GROUP_SIZE;
3578                 shift = i % RTE_RETA_GROUP_SIZE;
3579                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3580                                                 IGB_4_BIT_MASK);
3581                 if (!mask)
3582                         continue;
3583                 if (mask == IGB_4_BIT_MASK)
3584                         r = 0;
3585                 else
3586                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3587                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3588                         if (mask & (0x1 << j))
3589                                 reta |= reta_conf[idx].reta[shift + j] <<
3590                                                         (CHAR_BIT * j);
3591                         else
3592                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3593                 }
3594                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3595         }
3596
3597         return 0;
3598 }
3599
3600 static int
3601 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3602                        struct rte_eth_rss_reta_entry64 *reta_conf,
3603                        uint16_t reta_size)
3604 {
3605         uint8_t i, j, mask;
3606         uint32_t reta;
3607         uint16_t idx, shift;
3608         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3609
3610         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3611                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3612                         "(%d) doesn't match the number hardware can supported "
3613                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3614                 return -EINVAL;
3615         }
3616
3617         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3618                 idx = i / RTE_RETA_GROUP_SIZE;
3619                 shift = i % RTE_RETA_GROUP_SIZE;
3620                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3621                                                 IGB_4_BIT_MASK);
3622                 if (!mask)
3623                         continue;
3624                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3625                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3626                         if (mask & (0x1 << j))
3627                                 reta_conf[idx].reta[shift + j] =
3628                                         ((reta >> (CHAR_BIT * j)) &
3629                                                 IGB_8_BIT_MASK);
3630                 }
3631         }
3632
3633         return 0;
3634 }
3635
3636 int
3637 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3638                         struct rte_eth_syn_filter *filter,
3639                         bool add)
3640 {
3641         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3642         struct e1000_filter_info *filter_info =
3643                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3644         uint32_t synqf, rfctl;
3645
3646         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3647                 return -EINVAL;
3648
3649         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3650
3651         if (add) {
3652                 if (synqf & E1000_SYN_FILTER_ENABLE)
3653                         return -EINVAL;
3654
3655                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3656                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3657
3658                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3659                 if (filter->hig_pri)
3660                         rfctl |= E1000_RFCTL_SYNQFP;
3661                 else
3662                         rfctl &= ~E1000_RFCTL_SYNQFP;
3663
3664                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3665         } else {
3666                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3667                         return -ENOENT;
3668                 synqf = 0;
3669         }
3670
3671         filter_info->syn_info = synqf;
3672         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3673         E1000_WRITE_FLUSH(hw);
3674         return 0;
3675 }
3676
3677 static int
3678 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3679                         struct rte_eth_syn_filter *filter)
3680 {
3681         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3682         uint32_t synqf, rfctl;
3683
3684         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3685         if (synqf & E1000_SYN_FILTER_ENABLE) {
3686                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3687                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3688                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3689                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3690                 return 0;
3691         }
3692
3693         return -ENOENT;
3694 }
3695
3696 static int
3697 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3698                         enum rte_filter_op filter_op,
3699                         void *arg)
3700 {
3701         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3702         int ret;
3703
3704         MAC_TYPE_FILTER_SUP(hw->mac.type);
3705
3706         if (filter_op == RTE_ETH_FILTER_NOP)
3707                 return 0;
3708
3709         if (arg == NULL) {
3710                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3711                             filter_op);
3712                 return -EINVAL;
3713         }
3714
3715         switch (filter_op) {
3716         case RTE_ETH_FILTER_ADD:
3717                 ret = eth_igb_syn_filter_set(dev,
3718                                 (struct rte_eth_syn_filter *)arg,
3719                                 TRUE);
3720                 break;
3721         case RTE_ETH_FILTER_DELETE:
3722                 ret = eth_igb_syn_filter_set(dev,
3723                                 (struct rte_eth_syn_filter *)arg,
3724                                 FALSE);
3725                 break;
3726         case RTE_ETH_FILTER_GET:
3727                 ret = eth_igb_syn_filter_get(dev,
3728                                 (struct rte_eth_syn_filter *)arg);
3729                 break;
3730         default:
3731                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3732                 ret = -EINVAL;
3733                 break;
3734         }
3735
3736         return ret;
3737 }
3738
3739 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3740 static inline int
3741 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3742                         struct e1000_2tuple_filter_info *filter_info)
3743 {
3744         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3745                 return -EINVAL;
3746         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3747                 return -EINVAL;  /* filter index is out of range. */
3748         if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
3749                 return -EINVAL;  /* flags is invalid. */
3750
3751         switch (filter->dst_port_mask) {
3752         case UINT16_MAX:
3753                 filter_info->dst_port_mask = 0;
3754                 filter_info->dst_port = filter->dst_port;
3755                 break;
3756         case 0:
3757                 filter_info->dst_port_mask = 1;
3758                 break;
3759         default:
3760                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3761                 return -EINVAL;
3762         }
3763
3764         switch (filter->proto_mask) {
3765         case UINT8_MAX:
3766                 filter_info->proto_mask = 0;
3767                 filter_info->proto = filter->proto;
3768                 break;
3769         case 0:
3770                 filter_info->proto_mask = 1;
3771                 break;
3772         default:
3773                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3774                 return -EINVAL;
3775         }
3776
3777         filter_info->priority = (uint8_t)filter->priority;
3778         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3779                 filter_info->tcp_flags = filter->tcp_flags;
3780         else
3781                 filter_info->tcp_flags = 0;
3782
3783         return 0;
3784 }
3785
3786 static inline struct e1000_2tuple_filter *
3787 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3788                         struct e1000_2tuple_filter_info *key)
3789 {
3790         struct e1000_2tuple_filter *it;
3791
3792         TAILQ_FOREACH(it, filter_list, entries) {
3793                 if (memcmp(key, &it->filter_info,
3794                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3795                         return it;
3796                 }
3797         }
3798         return NULL;
3799 }
3800
3801 /* inject a igb 2tuple filter to HW */
3802 static inline void
3803 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3804                            struct e1000_2tuple_filter *filter)
3805 {
3806         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3807         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3808         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3809         int i;
3810
3811         i = filter->index;
3812         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3813         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3814                 imir |= E1000_IMIR_PORT_BP;
3815         else
3816                 imir &= ~E1000_IMIR_PORT_BP;
3817
3818         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3819
3820         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3821         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3822         ttqf |= (uint32_t)(filter->filter_info.proto &
3823                                                 E1000_TTQF_PROTOCOL_MASK);
3824         if (filter->filter_info.proto_mask == 0)
3825                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3826
3827         /* tcp flags bits setting. */
3828         if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
3829                 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
3830                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3831                 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
3832                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3833                 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
3834                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3835                 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
3836                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3837                 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
3838                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3839                 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
3840                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3841         } else {
3842                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3843         }
3844         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3845         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3846         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3847 }
3848
3849 /*
3850  * igb_add_2tuple_filter - add a 2tuple filter
3851  *
3852  * @param
3853  * dev: Pointer to struct rte_eth_dev.
3854  * ntuple_filter: ponter to the filter that will be added.
3855  *
3856  * @return
3857  *    - On success, zero.
3858  *    - On failure, a negative value.
3859  */
3860 static int
3861 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3862                         struct rte_eth_ntuple_filter *ntuple_filter)
3863 {
3864         struct e1000_filter_info *filter_info =
3865                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3866         struct e1000_2tuple_filter *filter;
3867         int i, ret;
3868
3869         filter = rte_zmalloc("e1000_2tuple_filter",
3870                         sizeof(struct e1000_2tuple_filter), 0);
3871         if (filter == NULL)
3872                 return -ENOMEM;
3873
3874         ret = ntuple_filter_to_2tuple(ntuple_filter,
3875                                       &filter->filter_info);
3876         if (ret < 0) {
3877                 rte_free(filter);
3878                 return ret;
3879         }
3880         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3881                                          &filter->filter_info) != NULL) {
3882                 PMD_DRV_LOG(ERR, "filter exists.");
3883                 rte_free(filter);
3884                 return -EEXIST;
3885         }
3886         filter->queue = ntuple_filter->queue;
3887
3888         /*
3889          * look for an unused 2tuple filter index,
3890          * and insert the filter to list.
3891          */
3892         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3893                 if (!(filter_info->twotuple_mask & (1 << i))) {
3894                         filter_info->twotuple_mask |= 1 << i;
3895                         filter->index = i;
3896                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3897                                           filter,
3898                                           entries);
3899                         break;
3900                 }
3901         }
3902         if (i >= E1000_MAX_TTQF_FILTERS) {
3903                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3904                 rte_free(filter);
3905                 return -ENOSYS;
3906         }
3907
3908         igb_inject_2uple_filter(dev, filter);
3909         return 0;
3910 }
3911
3912 int
3913 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3914                         struct e1000_2tuple_filter *filter)
3915 {
3916         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3917         struct e1000_filter_info *filter_info =
3918                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3919
3920         filter_info->twotuple_mask &= ~(1 << filter->index);
3921         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3922         rte_free(filter);
3923
3924         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3925         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3926         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3927         return 0;
3928 }
3929
3930 /*
3931  * igb_remove_2tuple_filter - remove a 2tuple filter
3932  *
3933  * @param
3934  * dev: Pointer to struct rte_eth_dev.
3935  * ntuple_filter: ponter to the filter that will be removed.
3936  *
3937  * @return
3938  *    - On success, zero.
3939  *    - On failure, a negative value.
3940  */
3941 static int
3942 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3943                         struct rte_eth_ntuple_filter *ntuple_filter)
3944 {
3945         struct e1000_filter_info *filter_info =
3946                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3947         struct e1000_2tuple_filter_info filter_2tuple;
3948         struct e1000_2tuple_filter *filter;
3949         int ret;
3950
3951         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3952         ret = ntuple_filter_to_2tuple(ntuple_filter,
3953                                       &filter_2tuple);
3954         if (ret < 0)
3955                 return ret;
3956
3957         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3958                                          &filter_2tuple);
3959         if (filter == NULL) {
3960                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3961                 return -ENOENT;
3962         }
3963
3964         igb_delete_2tuple_filter(dev, filter);
3965
3966         return 0;
3967 }
3968
3969 /* inject a igb flex filter to HW */
3970 static inline void
3971 igb_inject_flex_filter(struct rte_eth_dev *dev,
3972                            struct e1000_flex_filter *filter)
3973 {
3974         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3975         uint32_t wufc, queueing;
3976         uint32_t reg_off;
3977         uint8_t i, j = 0;
3978
3979         wufc = E1000_READ_REG(hw, E1000_WUFC);
3980         if (filter->index < E1000_MAX_FHFT)
3981                 reg_off = E1000_FHFT(filter->index);
3982         else
3983                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3984
3985         E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3986                         (E1000_WUFC_FLX0 << filter->index));
3987         queueing = filter->filter_info.len |
3988                 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3989                 (filter->filter_info.priority <<
3990                         E1000_FHFT_QUEUEING_PRIO_SHIFT);
3991         E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3992                         queueing);
3993
3994         for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3995                 E1000_WRITE_REG(hw, reg_off,
3996                                 filter->filter_info.dwords[j]);
3997                 reg_off += sizeof(uint32_t);
3998                 E1000_WRITE_REG(hw, reg_off,
3999                                 filter->filter_info.dwords[++j]);
4000                 reg_off += sizeof(uint32_t);
4001                 E1000_WRITE_REG(hw, reg_off,
4002                         (uint32_t)filter->filter_info.mask[i]);
4003                 reg_off += sizeof(uint32_t) * 2;
4004                 ++j;
4005         }
4006 }
4007
4008 static inline struct e1000_flex_filter *
4009 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
4010                         struct e1000_flex_filter_info *key)
4011 {
4012         struct e1000_flex_filter *it;
4013
4014         TAILQ_FOREACH(it, filter_list, entries) {
4015                 if (memcmp(key, &it->filter_info,
4016                         sizeof(struct e1000_flex_filter_info)) == 0)
4017                         return it;
4018         }
4019
4020         return NULL;
4021 }
4022
4023 /* remove a flex byte filter
4024  * @param
4025  * dev: Pointer to struct rte_eth_dev.
4026  * filter: the pointer of the filter will be removed.
4027  */
4028 void
4029 igb_remove_flex_filter(struct rte_eth_dev *dev,
4030                         struct e1000_flex_filter *filter)
4031 {
4032         struct e1000_filter_info *filter_info =
4033                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4034         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4035         uint32_t wufc, i;
4036         uint32_t reg_off;
4037
4038         wufc = E1000_READ_REG(hw, E1000_WUFC);
4039         if (filter->index < E1000_MAX_FHFT)
4040                 reg_off = E1000_FHFT(filter->index);
4041         else
4042                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
4043
4044         for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
4045                 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
4046
4047         E1000_WRITE_REG(hw, E1000_WUFC, wufc &
4048                 (~(E1000_WUFC_FLX0 << filter->index)));
4049
4050         filter_info->flex_mask &= ~(1 << filter->index);
4051         TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
4052         rte_free(filter);
4053 }
4054
4055 int
4056 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
4057                         struct rte_eth_flex_filter *filter,
4058                         bool add)
4059 {
4060         struct e1000_filter_info *filter_info =
4061                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4062         struct e1000_flex_filter *flex_filter, *it;
4063         uint32_t mask;
4064         uint8_t shift, i;
4065
4066         flex_filter = rte_zmalloc("e1000_flex_filter",
4067                         sizeof(struct e1000_flex_filter), 0);
4068         if (flex_filter == NULL)
4069                 return -ENOMEM;
4070
4071         flex_filter->filter_info.len = filter->len;
4072         flex_filter->filter_info.priority = filter->priority;
4073         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4074         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4075                 mask = 0;
4076                 /* reverse bits in flex filter's mask*/
4077                 for (shift = 0; shift < CHAR_BIT; shift++) {
4078                         if (filter->mask[i] & (0x01 << shift))
4079                                 mask |= (0x80 >> shift);
4080                 }
4081                 flex_filter->filter_info.mask[i] = mask;
4082         }
4083
4084         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4085                                 &flex_filter->filter_info);
4086         if (it == NULL && !add) {
4087                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4088                 rte_free(flex_filter);
4089                 return -ENOENT;
4090         }
4091         if (it != NULL && add) {
4092                 PMD_DRV_LOG(ERR, "filter exists.");
4093                 rte_free(flex_filter);
4094                 return -EEXIST;
4095         }
4096
4097         if (add) {
4098                 flex_filter->queue = filter->queue;
4099                 /*
4100                  * look for an unused flex filter index
4101                  * and insert the filter into the list.
4102                  */
4103                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4104                         if (!(filter_info->flex_mask & (1 << i))) {
4105                                 filter_info->flex_mask |= 1 << i;
4106                                 flex_filter->index = i;
4107                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4108                                         flex_filter,
4109                                         entries);
4110                                 break;
4111                         }
4112                 }
4113                 if (i >= E1000_MAX_FLEX_FILTERS) {
4114                         PMD_DRV_LOG(ERR, "flex filters are full.");
4115                         rte_free(flex_filter);
4116                         return -ENOSYS;
4117                 }
4118
4119                 igb_inject_flex_filter(dev, flex_filter);
4120
4121         } else {
4122                 igb_remove_flex_filter(dev, it);
4123                 rte_free(flex_filter);
4124         }
4125
4126         return 0;
4127 }
4128
4129 static int
4130 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4131                         struct rte_eth_flex_filter *filter)
4132 {
4133         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4134         struct e1000_filter_info *filter_info =
4135                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4136         struct e1000_flex_filter flex_filter, *it;
4137         uint32_t wufc, queueing, wufc_en = 0;
4138
4139         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4140         flex_filter.filter_info.len = filter->len;
4141         flex_filter.filter_info.priority = filter->priority;
4142         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4143         memcpy(flex_filter.filter_info.mask, filter->mask,
4144                         RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT);
4145
4146         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4147                                 &flex_filter.filter_info);
4148         if (it == NULL) {
4149                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4150                 return -ENOENT;
4151         }
4152
4153         wufc = E1000_READ_REG(hw, E1000_WUFC);
4154         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4155
4156         if ((wufc & wufc_en) == wufc_en) {
4157                 uint32_t reg_off = 0;
4158                 if (it->index < E1000_MAX_FHFT)
4159                         reg_off = E1000_FHFT(it->index);
4160                 else
4161                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4162
4163                 queueing = E1000_READ_REG(hw,
4164                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4165                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4166                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4167                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
4168                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4169                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4170                 return 0;
4171         }
4172         return -ENOENT;
4173 }
4174
4175 static int
4176 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4177                         enum rte_filter_op filter_op,
4178                         void *arg)
4179 {
4180         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4181         struct rte_eth_flex_filter *filter;
4182         int ret = 0;
4183
4184         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4185
4186         if (filter_op == RTE_ETH_FILTER_NOP)
4187                 return ret;
4188
4189         if (arg == NULL) {
4190                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4191                             filter_op);
4192                 return -EINVAL;
4193         }
4194
4195         filter = (struct rte_eth_flex_filter *)arg;
4196         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4197             || filter->len % sizeof(uint64_t) != 0) {
4198                 PMD_DRV_LOG(ERR, "filter's length is out of range");
4199                 return -EINVAL;
4200         }
4201         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4202                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4203                 return -EINVAL;
4204         }
4205
4206         switch (filter_op) {
4207         case RTE_ETH_FILTER_ADD:
4208                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4209                 break;
4210         case RTE_ETH_FILTER_DELETE:
4211                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4212                 break;
4213         case RTE_ETH_FILTER_GET:
4214                 ret = eth_igb_get_flex_filter(dev, filter);
4215                 break;
4216         default:
4217                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4218                 ret = -EINVAL;
4219                 break;
4220         }
4221
4222         return ret;
4223 }
4224
4225 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4226 static inline int
4227 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4228                         struct e1000_5tuple_filter_info *filter_info)
4229 {
4230         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4231                 return -EINVAL;
4232         if (filter->priority > E1000_2TUPLE_MAX_PRI)
4233                 return -EINVAL;  /* filter index is out of range. */
4234         if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
4235                 return -EINVAL;  /* flags is invalid. */
4236
4237         switch (filter->dst_ip_mask) {
4238         case UINT32_MAX:
4239                 filter_info->dst_ip_mask = 0;
4240                 filter_info->dst_ip = filter->dst_ip;
4241                 break;
4242         case 0:
4243                 filter_info->dst_ip_mask = 1;
4244                 break;
4245         default:
4246                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4247                 return -EINVAL;
4248         }
4249
4250         switch (filter->src_ip_mask) {
4251         case UINT32_MAX:
4252                 filter_info->src_ip_mask = 0;
4253                 filter_info->src_ip = filter->src_ip;
4254                 break;
4255         case 0:
4256                 filter_info->src_ip_mask = 1;
4257                 break;
4258         default:
4259                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4260                 return -EINVAL;
4261         }
4262
4263         switch (filter->dst_port_mask) {
4264         case UINT16_MAX:
4265                 filter_info->dst_port_mask = 0;
4266                 filter_info->dst_port = filter->dst_port;
4267                 break;
4268         case 0:
4269                 filter_info->dst_port_mask = 1;
4270                 break;
4271         default:
4272                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4273                 return -EINVAL;
4274         }
4275
4276         switch (filter->src_port_mask) {
4277         case UINT16_MAX:
4278                 filter_info->src_port_mask = 0;
4279                 filter_info->src_port = filter->src_port;
4280                 break;
4281         case 0:
4282                 filter_info->src_port_mask = 1;
4283                 break;
4284         default:
4285                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4286                 return -EINVAL;
4287         }
4288
4289         switch (filter->proto_mask) {
4290         case UINT8_MAX:
4291                 filter_info->proto_mask = 0;
4292                 filter_info->proto = filter->proto;
4293                 break;
4294         case 0:
4295                 filter_info->proto_mask = 1;
4296                 break;
4297         default:
4298                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4299                 return -EINVAL;
4300         }
4301
4302         filter_info->priority = (uint8_t)filter->priority;
4303         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4304                 filter_info->tcp_flags = filter->tcp_flags;
4305         else
4306                 filter_info->tcp_flags = 0;
4307
4308         return 0;
4309 }
4310
4311 static inline struct e1000_5tuple_filter *
4312 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4313                         struct e1000_5tuple_filter_info *key)
4314 {
4315         struct e1000_5tuple_filter *it;
4316
4317         TAILQ_FOREACH(it, filter_list, entries) {
4318                 if (memcmp(key, &it->filter_info,
4319                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4320                         return it;
4321                 }
4322         }
4323         return NULL;
4324 }
4325
4326 /* inject a igb 5-tuple filter to HW */
4327 static inline void
4328 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4329                            struct e1000_5tuple_filter *filter)
4330 {
4331         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4332         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4333         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4334         uint8_t i;
4335
4336         i = filter->index;
4337         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4338         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4339                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4340         if (filter->filter_info.dst_ip_mask == 0)
4341                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4342         if (filter->filter_info.src_port_mask == 0)
4343                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4344         if (filter->filter_info.proto_mask == 0)
4345                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4346         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4347                 E1000_FTQF_QUEUE_MASK;
4348         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4349         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4350         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4351         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4352
4353         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4354         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4355
4356         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4357         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4358                 imir |= E1000_IMIR_PORT_BP;
4359         else
4360                 imir &= ~E1000_IMIR_PORT_BP;
4361         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4362
4363         /* tcp flags bits setting. */
4364         if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
4365                 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
4366                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4367                 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
4368                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4369                 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
4370                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4371                 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
4372                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4373                 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
4374                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4375                 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
4376                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4377         } else {
4378                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4379         }
4380         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4381         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4382 }
4383
4384 /*
4385  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4386  *
4387  * @param
4388  * dev: Pointer to struct rte_eth_dev.
4389  * ntuple_filter: ponter to the filter that will be added.
4390  *
4391  * @return
4392  *    - On success, zero.
4393  *    - On failure, a negative value.
4394  */
4395 static int
4396 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4397                         struct rte_eth_ntuple_filter *ntuple_filter)
4398 {
4399         struct e1000_filter_info *filter_info =
4400                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4401         struct e1000_5tuple_filter *filter;
4402         uint8_t i;
4403         int ret;
4404
4405         filter = rte_zmalloc("e1000_5tuple_filter",
4406                         sizeof(struct e1000_5tuple_filter), 0);
4407         if (filter == NULL)
4408                 return -ENOMEM;
4409
4410         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4411                                             &filter->filter_info);
4412         if (ret < 0) {
4413                 rte_free(filter);
4414                 return ret;
4415         }
4416
4417         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4418                                          &filter->filter_info) != NULL) {
4419                 PMD_DRV_LOG(ERR, "filter exists.");
4420                 rte_free(filter);
4421                 return -EEXIST;
4422         }
4423         filter->queue = ntuple_filter->queue;
4424
4425         /*
4426          * look for an unused 5tuple filter index,
4427          * and insert the filter to list.
4428          */
4429         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4430                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4431                         filter_info->fivetuple_mask |= 1 << i;
4432                         filter->index = i;
4433                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4434                                           filter,
4435                                           entries);
4436                         break;
4437                 }
4438         }
4439         if (i >= E1000_MAX_FTQF_FILTERS) {
4440                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4441                 rte_free(filter);
4442                 return -ENOSYS;
4443         }
4444
4445         igb_inject_5tuple_filter_82576(dev, filter);
4446         return 0;
4447 }
4448
4449 int
4450 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4451                                 struct e1000_5tuple_filter *filter)
4452 {
4453         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4454         struct e1000_filter_info *filter_info =
4455                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4456
4457         filter_info->fivetuple_mask &= ~(1 << filter->index);
4458         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4459         rte_free(filter);
4460
4461         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4462                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4463         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4464         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4465         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4466         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4467         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4468         return 0;
4469 }
4470
4471 /*
4472  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4473  *
4474  * @param
4475  * dev: Pointer to struct rte_eth_dev.
4476  * ntuple_filter: ponter to the filter that will be removed.
4477  *
4478  * @return
4479  *    - On success, zero.
4480  *    - On failure, a negative value.
4481  */
4482 static int
4483 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4484                                 struct rte_eth_ntuple_filter *ntuple_filter)
4485 {
4486         struct e1000_filter_info *filter_info =
4487                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4488         struct e1000_5tuple_filter_info filter_5tuple;
4489         struct e1000_5tuple_filter *filter;
4490         int ret;
4491
4492         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4493         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4494                                             &filter_5tuple);
4495         if (ret < 0)
4496                 return ret;
4497
4498         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4499                                          &filter_5tuple);
4500         if (filter == NULL) {
4501                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4502                 return -ENOENT;
4503         }
4504
4505         igb_delete_5tuple_filter_82576(dev, filter);
4506
4507         return 0;
4508 }
4509
4510 static int
4511 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4512 {
4513         uint32_t rctl;
4514         struct e1000_hw *hw;
4515         struct rte_eth_dev_info dev_info;
4516         uint32_t frame_size = mtu + E1000_ETH_OVERHEAD;
4517         int ret;
4518
4519         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4520
4521 #ifdef RTE_LIBRTE_82571_SUPPORT
4522         /* XXX: not bigger than max_rx_pktlen */
4523         if (hw->mac.type == e1000_82571)
4524                 return -ENOTSUP;
4525 #endif
4526         ret = eth_igb_infos_get(dev, &dev_info);
4527         if (ret != 0)
4528                 return ret;
4529
4530         /* check that mtu is within the allowed range */
4531         if (mtu < RTE_ETHER_MIN_MTU ||
4532                         frame_size > dev_info.max_rx_pktlen)
4533                 return -EINVAL;
4534
4535         /* refuse mtu that requires the support of scattered packets when this
4536          * feature has not been enabled before. */
4537         if (!dev->data->scattered_rx &&
4538             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4539                 return -EINVAL;
4540
4541         rctl = E1000_READ_REG(hw, E1000_RCTL);
4542
4543         /* switch to jumbo mode if needed */
4544         if (frame_size > RTE_ETHER_MAX_LEN) {
4545                 dev->data->dev_conf.rxmode.offloads |=
4546                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4547                 rctl |= E1000_RCTL_LPE;
4548         } else {
4549                 dev->data->dev_conf.rxmode.offloads &=
4550                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4551                 rctl &= ~E1000_RCTL_LPE;
4552         }
4553         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4554
4555         /* update max frame size */
4556         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4557
4558         E1000_WRITE_REG(hw, E1000_RLPML,
4559                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4560
4561         return 0;
4562 }
4563
4564 /*
4565  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4566  *
4567  * @param
4568  * dev: Pointer to struct rte_eth_dev.
4569  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4570  * add: if true, add filter, if false, remove filter
4571  *
4572  * @return
4573  *    - On success, zero.
4574  *    - On failure, a negative value.
4575  */
4576 int
4577 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4578                         struct rte_eth_ntuple_filter *ntuple_filter,
4579                         bool add)
4580 {
4581         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4582         int ret;
4583
4584         switch (ntuple_filter->flags) {
4585         case RTE_5TUPLE_FLAGS:
4586         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4587                 if (hw->mac.type != e1000_82576)
4588                         return -ENOTSUP;
4589                 if (add)
4590                         ret = igb_add_5tuple_filter_82576(dev,
4591                                                           ntuple_filter);
4592                 else
4593                         ret = igb_remove_5tuple_filter_82576(dev,
4594                                                              ntuple_filter);
4595                 break;
4596         case RTE_2TUPLE_FLAGS:
4597         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4598                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4599                         hw->mac.type != e1000_i210 &&
4600                         hw->mac.type != e1000_i211)
4601                         return -ENOTSUP;
4602                 if (add)
4603                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4604                 else
4605                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4606                 break;
4607         default:
4608                 ret = -EINVAL;
4609                 break;
4610         }
4611
4612         return ret;
4613 }
4614
4615 /*
4616  * igb_get_ntuple_filter - get a ntuple filter
4617  *
4618  * @param
4619  * dev: Pointer to struct rte_eth_dev.
4620  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4621  *
4622  * @return
4623  *    - On success, zero.
4624  *    - On failure, a negative value.
4625  */
4626 static int
4627 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4628                         struct rte_eth_ntuple_filter *ntuple_filter)
4629 {
4630         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4631         struct e1000_filter_info *filter_info =
4632                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4633         struct e1000_5tuple_filter_info filter_5tuple;
4634         struct e1000_2tuple_filter_info filter_2tuple;
4635         struct e1000_5tuple_filter *p_5tuple_filter;
4636         struct e1000_2tuple_filter *p_2tuple_filter;
4637         int ret;
4638
4639         switch (ntuple_filter->flags) {
4640         case RTE_5TUPLE_FLAGS:
4641         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4642                 if (hw->mac.type != e1000_82576)
4643                         return -ENOTSUP;
4644                 memset(&filter_5tuple,
4645                         0,
4646                         sizeof(struct e1000_5tuple_filter_info));
4647                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4648                                                     &filter_5tuple);
4649                 if (ret < 0)
4650                         return ret;
4651                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4652                                         &filter_info->fivetuple_list,
4653                                         &filter_5tuple);
4654                 if (p_5tuple_filter == NULL) {
4655                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4656                         return -ENOENT;
4657                 }
4658                 ntuple_filter->queue = p_5tuple_filter->queue;
4659                 break;
4660         case RTE_2TUPLE_FLAGS:
4661         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4662                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4663                         return -ENOTSUP;
4664                 memset(&filter_2tuple,
4665                         0,
4666                         sizeof(struct e1000_2tuple_filter_info));
4667                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4668                 if (ret < 0)
4669                         return ret;
4670                 p_2tuple_filter = igb_2tuple_filter_lookup(
4671                                         &filter_info->twotuple_list,
4672                                         &filter_2tuple);
4673                 if (p_2tuple_filter == NULL) {
4674                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4675                         return -ENOENT;
4676                 }
4677                 ntuple_filter->queue = p_2tuple_filter->queue;
4678                 break;
4679         default:
4680                 ret = -EINVAL;
4681                 break;
4682         }
4683
4684         return 0;
4685 }
4686
4687 /*
4688  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4689  * @dev: pointer to rte_eth_dev structure
4690  * @filter_op:operation will be taken.
4691  * @arg: a pointer to specific structure corresponding to the filter_op
4692  */
4693 static int
4694 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4695                                 enum rte_filter_op filter_op,
4696                                 void *arg)
4697 {
4698         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4699         int ret;
4700
4701         MAC_TYPE_FILTER_SUP(hw->mac.type);
4702
4703         if (filter_op == RTE_ETH_FILTER_NOP)
4704                 return 0;
4705
4706         if (arg == NULL) {
4707                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4708                             filter_op);
4709                 return -EINVAL;
4710         }
4711
4712         switch (filter_op) {
4713         case RTE_ETH_FILTER_ADD:
4714                 ret = igb_add_del_ntuple_filter(dev,
4715                         (struct rte_eth_ntuple_filter *)arg,
4716                         TRUE);
4717                 break;
4718         case RTE_ETH_FILTER_DELETE:
4719                 ret = igb_add_del_ntuple_filter(dev,
4720                         (struct rte_eth_ntuple_filter *)arg,
4721                         FALSE);
4722                 break;
4723         case RTE_ETH_FILTER_GET:
4724                 ret = igb_get_ntuple_filter(dev,
4725                         (struct rte_eth_ntuple_filter *)arg);
4726                 break;
4727         default:
4728                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4729                 ret = -EINVAL;
4730                 break;
4731         }
4732         return ret;
4733 }
4734
4735 static inline int
4736 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4737                         uint16_t ethertype)
4738 {
4739         int i;
4740
4741         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4742                 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4743                     (filter_info->ethertype_mask & (1 << i)))
4744                         return i;
4745         }
4746         return -1;
4747 }
4748
4749 static inline int
4750 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4751                         uint16_t ethertype, uint32_t etqf)
4752 {
4753         int i;
4754
4755         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4756                 if (!(filter_info->ethertype_mask & (1 << i))) {
4757                         filter_info->ethertype_mask |= 1 << i;
4758                         filter_info->ethertype_filters[i].ethertype = ethertype;
4759                         filter_info->ethertype_filters[i].etqf = etqf;
4760                         return i;
4761                 }
4762         }
4763         return -1;
4764 }
4765
4766 int
4767 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4768                         uint8_t idx)
4769 {
4770         if (idx >= E1000_MAX_ETQF_FILTERS)
4771                 return -1;
4772         filter_info->ethertype_mask &= ~(1 << idx);
4773         filter_info->ethertype_filters[idx].ethertype = 0;
4774         filter_info->ethertype_filters[idx].etqf = 0;
4775         return idx;
4776 }
4777
4778
4779 int
4780 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4781                         struct rte_eth_ethertype_filter *filter,
4782                         bool add)
4783 {
4784         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4785         struct e1000_filter_info *filter_info =
4786                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4787         uint32_t etqf = 0;
4788         int ret;
4789
4790         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
4791                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
4792                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4793                         " ethertype filter.", filter->ether_type);
4794                 return -EINVAL;
4795         }
4796
4797         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4798                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4799                 return -EINVAL;
4800         }
4801         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4802                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4803                 return -EINVAL;
4804         }
4805
4806         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4807         if (ret >= 0 && add) {
4808                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4809                             filter->ether_type);
4810                 return -EEXIST;
4811         }
4812         if (ret < 0 && !add) {
4813                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4814                             filter->ether_type);
4815                 return -ENOENT;
4816         }
4817
4818         if (add) {
4819                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4820                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4821                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4822                 ret = igb_ethertype_filter_insert(filter_info,
4823                                 filter->ether_type, etqf);
4824                 if (ret < 0) {
4825                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4826                         return -ENOSYS;
4827                 }
4828         } else {
4829                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4830                 if (ret < 0)
4831                         return -ENOSYS;
4832         }
4833         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4834         E1000_WRITE_FLUSH(hw);
4835
4836         return 0;
4837 }
4838
4839 static int
4840 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4841                         struct rte_eth_ethertype_filter *filter)
4842 {
4843         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4844         struct e1000_filter_info *filter_info =
4845                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4846         uint32_t etqf;
4847         int ret;
4848
4849         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4850         if (ret < 0) {
4851                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4852                             filter->ether_type);
4853                 return -ENOENT;
4854         }
4855
4856         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4857         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4858                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4859                 filter->flags = 0;
4860                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4861                                 E1000_ETQF_QUEUE_SHIFT;
4862                 return 0;
4863         }
4864
4865         return -ENOENT;
4866 }
4867
4868 /*
4869  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4870  * @dev: pointer to rte_eth_dev structure
4871  * @filter_op:operation will be taken.
4872  * @arg: a pointer to specific structure corresponding to the filter_op
4873  */
4874 static int
4875 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4876                                 enum rte_filter_op filter_op,
4877                                 void *arg)
4878 {
4879         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4880         int ret;
4881
4882         MAC_TYPE_FILTER_SUP(hw->mac.type);
4883
4884         if (filter_op == RTE_ETH_FILTER_NOP)
4885                 return 0;
4886
4887         if (arg == NULL) {
4888                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4889                             filter_op);
4890                 return -EINVAL;
4891         }
4892
4893         switch (filter_op) {
4894         case RTE_ETH_FILTER_ADD:
4895                 ret = igb_add_del_ethertype_filter(dev,
4896                         (struct rte_eth_ethertype_filter *)arg,
4897                         TRUE);
4898                 break;
4899         case RTE_ETH_FILTER_DELETE:
4900                 ret = igb_add_del_ethertype_filter(dev,
4901                         (struct rte_eth_ethertype_filter *)arg,
4902                         FALSE);
4903                 break;
4904         case RTE_ETH_FILTER_GET:
4905                 ret = igb_get_ethertype_filter(dev,
4906                         (struct rte_eth_ethertype_filter *)arg);
4907                 break;
4908         default:
4909                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4910                 ret = -EINVAL;
4911                 break;
4912         }
4913         return ret;
4914 }
4915
4916 static int
4917 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4918                      enum rte_filter_type filter_type,
4919                      enum rte_filter_op filter_op,
4920                      void *arg)
4921 {
4922         int ret = 0;
4923
4924         switch (filter_type) {
4925         case RTE_ETH_FILTER_NTUPLE:
4926                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4927                 break;
4928         case RTE_ETH_FILTER_ETHERTYPE:
4929                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4930                 break;
4931         case RTE_ETH_FILTER_SYN:
4932                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4933                 break;
4934         case RTE_ETH_FILTER_FLEXIBLE:
4935                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4936                 break;
4937         case RTE_ETH_FILTER_GENERIC:
4938                 if (filter_op != RTE_ETH_FILTER_GET)
4939                         return -EINVAL;
4940                 *(const void **)arg = &igb_flow_ops;
4941                 break;
4942         default:
4943                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4944                                                         filter_type);
4945                 break;
4946         }
4947
4948         return ret;
4949 }
4950
4951 static int
4952 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4953                          struct rte_ether_addr *mc_addr_set,
4954                          uint32_t nb_mc_addr)
4955 {
4956         struct e1000_hw *hw;
4957
4958         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4959         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4960         return 0;
4961 }
4962
4963 static uint64_t
4964 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4965 {
4966         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4967         uint64_t systime_cycles;
4968
4969         switch (hw->mac.type) {
4970         case e1000_i210:
4971         case e1000_i211:
4972                 /*
4973                  * Need to read System Time Residue Register to be able
4974                  * to read the other two registers.
4975                  */
4976                 E1000_READ_REG(hw, E1000_SYSTIMR);
4977                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4978                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4979                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4980                                 * NSEC_PER_SEC;
4981                 break;
4982         case e1000_82580:
4983         case e1000_i350:
4984         case e1000_i354:
4985                 /*
4986                  * Need to read System Time Residue Register to be able
4987                  * to read the other two registers.
4988                  */
4989                 E1000_READ_REG(hw, E1000_SYSTIMR);
4990                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4991                 /* Only the 8 LSB are valid. */
4992                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4993                                 & 0xff) << 32;
4994                 break;
4995         default:
4996                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4997                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4998                                 << 32;
4999                 break;
5000         }
5001
5002         return systime_cycles;
5003 }
5004
5005 static uint64_t
5006 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5007 {
5008         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5009         uint64_t rx_tstamp_cycles;
5010
5011         switch (hw->mac.type) {
5012         case e1000_i210:
5013         case e1000_i211:
5014                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5015                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
5016                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
5017                                 * NSEC_PER_SEC;
5018                 break;
5019         case e1000_82580:
5020         case e1000_i350:
5021         case e1000_i354:
5022                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
5023                 /* Only the 8 LSB are valid. */
5024                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
5025                                 & 0xff) << 32;
5026                 break;
5027         default:
5028                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
5029                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
5030                                 << 32;
5031                 break;
5032         }
5033
5034         return rx_tstamp_cycles;
5035 }
5036
5037 static uint64_t
5038 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5039 {
5040         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5041         uint64_t tx_tstamp_cycles;
5042
5043         switch (hw->mac.type) {
5044         case e1000_i210:
5045         case e1000_i211:
5046                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5047                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5048                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5049                                 * NSEC_PER_SEC;
5050                 break;
5051         case e1000_82580:
5052         case e1000_i350:
5053         case e1000_i354:
5054                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5055                 /* Only the 8 LSB are valid. */
5056                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
5057                                 & 0xff) << 32;
5058                 break;
5059         default:
5060                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5061                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5062                                 << 32;
5063                 break;
5064         }
5065
5066         return tx_tstamp_cycles;
5067 }
5068
5069 static void
5070 igb_start_timecounters(struct rte_eth_dev *dev)
5071 {
5072         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5073         struct e1000_adapter *adapter = dev->data->dev_private;
5074         uint32_t incval = 1;
5075         uint32_t shift = 0;
5076         uint64_t mask = E1000_CYCLECOUNTER_MASK;
5077
5078         switch (hw->mac.type) {
5079         case e1000_82580:
5080         case e1000_i350:
5081         case e1000_i354:
5082                 /* 32 LSB bits + 8 MSB bits = 40 bits */
5083                 mask = (1ULL << 40) - 1;
5084                 /* fall-through */
5085         case e1000_i210:
5086         case e1000_i211:
5087                 /*
5088                  * Start incrementing the register
5089                  * used to timestamp PTP packets.
5090                  */
5091                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
5092                 break;
5093         case e1000_82576:
5094                 incval = E1000_INCVALUE_82576;
5095                 shift = IGB_82576_TSYNC_SHIFT;
5096                 E1000_WRITE_REG(hw, E1000_TIMINCA,
5097                                 E1000_INCPERIOD_82576 | incval);
5098                 break;
5099         default:
5100                 /* Not supported */
5101                 return;
5102         }
5103
5104         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5105         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5106         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5107
5108         adapter->systime_tc.cc_mask = mask;
5109         adapter->systime_tc.cc_shift = shift;
5110         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5111
5112         adapter->rx_tstamp_tc.cc_mask = mask;
5113         adapter->rx_tstamp_tc.cc_shift = shift;
5114         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5115
5116         adapter->tx_tstamp_tc.cc_mask = mask;
5117         adapter->tx_tstamp_tc.cc_shift = shift;
5118         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5119 }
5120
5121 static int
5122 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5123 {
5124         struct e1000_adapter *adapter = dev->data->dev_private;
5125
5126         adapter->systime_tc.nsec += delta;
5127         adapter->rx_tstamp_tc.nsec += delta;
5128         adapter->tx_tstamp_tc.nsec += delta;
5129
5130         return 0;
5131 }
5132
5133 static int
5134 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5135 {
5136         uint64_t ns;
5137         struct e1000_adapter *adapter = dev->data->dev_private;
5138
5139         ns = rte_timespec_to_ns(ts);
5140
5141         /* Set the timecounters to a new value. */
5142         adapter->systime_tc.nsec = ns;
5143         adapter->rx_tstamp_tc.nsec = ns;
5144         adapter->tx_tstamp_tc.nsec = ns;
5145
5146         return 0;
5147 }
5148
5149 static int
5150 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5151 {
5152         uint64_t ns, systime_cycles;
5153         struct e1000_adapter *adapter = dev->data->dev_private;
5154
5155         systime_cycles = igb_read_systime_cyclecounter(dev);
5156         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5157         *ts = rte_ns_to_timespec(ns);
5158
5159         return 0;
5160 }
5161
5162 static int
5163 igb_timesync_enable(struct rte_eth_dev *dev)
5164 {
5165         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5166         uint32_t tsync_ctl;
5167         uint32_t tsauxc;
5168
5169         /* Stop the timesync system time. */
5170         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5171         /* Reset the timesync system time value. */
5172         switch (hw->mac.type) {
5173         case e1000_82580:
5174         case e1000_i350:
5175         case e1000_i354:
5176         case e1000_i210:
5177         case e1000_i211:
5178                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5179                 /* fall-through */
5180         case e1000_82576:
5181                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5182                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5183                 break;
5184         default:
5185                 /* Not supported. */
5186                 return -ENOTSUP;
5187         }
5188
5189         /* Enable system time for it isn't on by default. */
5190         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5191         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5192         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5193
5194         igb_start_timecounters(dev);
5195
5196         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5197         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5198                         (RTE_ETHER_TYPE_1588 |
5199                          E1000_ETQF_FILTER_ENABLE |
5200                          E1000_ETQF_1588));
5201
5202         /* Enable timestamping of received PTP packets. */
5203         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5204         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5205         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5206
5207         /* Enable Timestamping of transmitted PTP packets. */
5208         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5209         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5210         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5211
5212         return 0;
5213 }
5214
5215 static int
5216 igb_timesync_disable(struct rte_eth_dev *dev)
5217 {
5218         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5219         uint32_t tsync_ctl;
5220
5221         /* Disable timestamping of transmitted PTP packets. */
5222         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5223         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5224         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5225
5226         /* Disable timestamping of received PTP packets. */
5227         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5228         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5229         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5230
5231         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5232         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5233
5234         /* Stop incrementating the System Time registers. */
5235         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5236
5237         return 0;
5238 }
5239
5240 static int
5241 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5242                                struct timespec *timestamp,
5243                                uint32_t flags __rte_unused)
5244 {
5245         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5246         struct e1000_adapter *adapter = dev->data->dev_private;
5247         uint32_t tsync_rxctl;
5248         uint64_t rx_tstamp_cycles;
5249         uint64_t ns;
5250
5251         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5252         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5253                 return -EINVAL;
5254
5255         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5256         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5257         *timestamp = rte_ns_to_timespec(ns);
5258
5259         return  0;
5260 }
5261
5262 static int
5263 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5264                                struct timespec *timestamp)
5265 {
5266         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5267         struct e1000_adapter *adapter = dev->data->dev_private;
5268         uint32_t tsync_txctl;
5269         uint64_t tx_tstamp_cycles;
5270         uint64_t ns;
5271
5272         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5273         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5274                 return -EINVAL;
5275
5276         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5277         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5278         *timestamp = rte_ns_to_timespec(ns);
5279
5280         return  0;
5281 }
5282
5283 static int
5284 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5285 {
5286         int count = 0;
5287         int g_ind = 0;
5288         const struct reg_info *reg_group;
5289
5290         while ((reg_group = igb_regs[g_ind++]))
5291                 count += igb_reg_group_count(reg_group);
5292
5293         return count;
5294 }
5295
5296 static int
5297 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5298 {
5299         int count = 0;
5300         int g_ind = 0;
5301         const struct reg_info *reg_group;
5302
5303         while ((reg_group = igbvf_regs[g_ind++]))
5304                 count += igb_reg_group_count(reg_group);
5305
5306         return count;
5307 }
5308
5309 static int
5310 eth_igb_get_regs(struct rte_eth_dev *dev,
5311         struct rte_dev_reg_info *regs)
5312 {
5313         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5314         uint32_t *data = regs->data;
5315         int g_ind = 0;
5316         int count = 0;
5317         const struct reg_info *reg_group;
5318
5319         if (data == NULL) {
5320                 regs->length = eth_igb_get_reg_length(dev);
5321                 regs->width = sizeof(uint32_t);
5322                 return 0;
5323         }
5324
5325         /* Support only full register dump */
5326         if ((regs->length == 0) ||
5327             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5328                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5329                         hw->device_id;
5330                 while ((reg_group = igb_regs[g_ind++]))
5331                         count += igb_read_regs_group(dev, &data[count],
5332                                                         reg_group);
5333                 return 0;
5334         }
5335
5336         return -ENOTSUP;
5337 }
5338
5339 static int
5340 igbvf_get_regs(struct rte_eth_dev *dev,
5341         struct rte_dev_reg_info *regs)
5342 {
5343         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5344         uint32_t *data = regs->data;
5345         int g_ind = 0;
5346         int count = 0;
5347         const struct reg_info *reg_group;
5348
5349         if (data == NULL) {
5350                 regs->length = igbvf_get_reg_length(dev);
5351                 regs->width = sizeof(uint32_t);
5352                 return 0;
5353         }
5354
5355         /* Support only full register dump */
5356         if ((regs->length == 0) ||
5357             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5358                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5359                         hw->device_id;
5360                 while ((reg_group = igbvf_regs[g_ind++]))
5361                         count += igb_read_regs_group(dev, &data[count],
5362                                                         reg_group);
5363                 return 0;
5364         }
5365
5366         return -ENOTSUP;
5367 }
5368
5369 static int
5370 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5371 {
5372         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5373
5374         /* Return unit is byte count */
5375         return hw->nvm.word_size * 2;
5376 }
5377
5378 static int
5379 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5380         struct rte_dev_eeprom_info *in_eeprom)
5381 {
5382         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5383         struct e1000_nvm_info *nvm = &hw->nvm;
5384         uint16_t *data = in_eeprom->data;
5385         int first, length;
5386
5387         first = in_eeprom->offset >> 1;
5388         length = in_eeprom->length >> 1;
5389         if ((first >= hw->nvm.word_size) ||
5390             ((first + length) >= hw->nvm.word_size))
5391                 return -EINVAL;
5392
5393         in_eeprom->magic = hw->vendor_id |
5394                 ((uint32_t)hw->device_id << 16);
5395
5396         if ((nvm->ops.read) == NULL)
5397                 return -ENOTSUP;
5398
5399         return nvm->ops.read(hw, first, length, data);
5400 }
5401
5402 static int
5403 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5404         struct rte_dev_eeprom_info *in_eeprom)
5405 {
5406         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5407         struct e1000_nvm_info *nvm = &hw->nvm;
5408         uint16_t *data = in_eeprom->data;
5409         int first, length;
5410
5411         first = in_eeprom->offset >> 1;
5412         length = in_eeprom->length >> 1;
5413         if ((first >= hw->nvm.word_size) ||
5414             ((first + length) >= hw->nvm.word_size))
5415                 return -EINVAL;
5416
5417         in_eeprom->magic = (uint32_t)hw->vendor_id |
5418                 ((uint32_t)hw->device_id << 16);
5419
5420         if ((nvm->ops.write) == NULL)
5421                 return -ENOTSUP;
5422         return nvm->ops.write(hw,  first, length, data);
5423 }
5424
5425 static int
5426 eth_igb_get_module_info(struct rte_eth_dev *dev,
5427                         struct rte_eth_dev_module_info *modinfo)
5428 {
5429         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5430
5431         uint32_t status = 0;
5432         uint16_t sff8472_rev, addr_mode;
5433         bool page_swap = false;
5434
5435         if (hw->phy.media_type == e1000_media_type_copper ||
5436             hw->phy.media_type == e1000_media_type_unknown)
5437                 return -EOPNOTSUPP;
5438
5439         /* Check whether we support SFF-8472 or not */
5440         status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
5441         if (status)
5442                 return -EIO;
5443
5444         /* addressing mode is not supported */
5445         status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
5446         if (status)
5447                 return -EIO;
5448
5449         /* addressing mode is not supported */
5450         if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
5451                 PMD_DRV_LOG(ERR,
5452                             "Address change required to access page 0xA2, "
5453                             "but not supported. Please report the module "
5454                             "type to the driver maintainers.\n");
5455                 page_swap = true;
5456         }
5457
5458         if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
5459                 /* We have an SFP, but it does not support SFF-8472 */
5460                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
5461                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
5462         } else {
5463                 /* We have an SFP which supports a revision of SFF-8472 */
5464                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
5465                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
5466         }
5467
5468         return 0;
5469 }
5470
5471 static int
5472 eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
5473                           struct rte_dev_eeprom_info *info)
5474 {
5475         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5476
5477         uint32_t status = 0;
5478         uint16_t dataword[RTE_ETH_MODULE_SFF_8472_LEN / 2 + 1];
5479         u16 first_word, last_word;
5480         int i = 0;
5481
5482         if (info->length == 0)
5483                 return -EINVAL;
5484
5485         first_word = info->offset >> 1;
5486         last_word = (info->offset + info->length - 1) >> 1;
5487
5488         /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
5489         for (i = 0; i < last_word - first_word + 1; i++) {
5490                 status = e1000_read_phy_reg_i2c(hw, (first_word + i) * 2,
5491                                                 &dataword[i]);
5492                 if (status) {
5493                         /* Error occurred while reading module */
5494                         return -EIO;
5495                 }
5496
5497                 dataword[i] = rte_be_to_cpu_16(dataword[i]);
5498         }
5499
5500         memcpy(info->data, (u8 *)dataword + (info->offset & 1), info->length);
5501
5502         return 0;
5503 }
5504
5505 static int
5506 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5507 {
5508         struct e1000_hw *hw =
5509                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5510         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5511         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5512         uint32_t vec = E1000_MISC_VEC_ID;
5513
5514         if (rte_intr_allow_others(intr_handle))
5515                 vec = E1000_RX_VEC_START;
5516
5517         uint32_t mask = 1 << (queue_id + vec);
5518
5519         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5520         E1000_WRITE_FLUSH(hw);
5521
5522         return 0;
5523 }
5524
5525 static int
5526 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5527 {
5528         struct e1000_hw *hw =
5529                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5530         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5531         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5532         uint32_t vec = E1000_MISC_VEC_ID;
5533
5534         if (rte_intr_allow_others(intr_handle))
5535                 vec = E1000_RX_VEC_START;
5536
5537         uint32_t mask = 1 << (queue_id + vec);
5538         uint32_t regval;
5539
5540         regval = E1000_READ_REG(hw, E1000_EIMS);
5541         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5542         E1000_WRITE_FLUSH(hw);
5543
5544         rte_intr_ack(intr_handle);
5545
5546         return 0;
5547 }
5548
5549 static void
5550 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5551                    uint8_t index, uint8_t offset)
5552 {
5553         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5554
5555         /* clear bits */
5556         val &= ~((uint32_t)0xFF << offset);
5557
5558         /* write vector and valid bit */
5559         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5560
5561         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5562 }
5563
5564 static void
5565 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5566                            uint8_t queue, uint8_t msix_vector)
5567 {
5568         uint32_t tmp = 0;
5569
5570         if (hw->mac.type == e1000_82575) {
5571                 if (direction == 0)
5572                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5573                 else if (direction == 1)
5574                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5575                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5576         } else if (hw->mac.type == e1000_82576) {
5577                 if ((direction == 0) || (direction == 1))
5578                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5579                                            ((queue & 0x8) << 1) +
5580                                            8 * direction);
5581         } else if ((hw->mac.type == e1000_82580) ||
5582                         (hw->mac.type == e1000_i350) ||
5583                         (hw->mac.type == e1000_i354) ||
5584                         (hw->mac.type == e1000_i210) ||
5585                         (hw->mac.type == e1000_i211)) {
5586                 if ((direction == 0) || (direction == 1))
5587                         eth_igb_write_ivar(hw, msix_vector,
5588                                            queue >> 1,
5589                                            ((queue & 0x1) << 4) +
5590                                            8 * direction);
5591         }
5592 }
5593
5594 /* Sets up the hardware to generate MSI-X interrupts properly
5595  * @hw
5596  *  board private structure
5597  */
5598 static void
5599 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5600 {
5601         int queue_id;
5602         uint32_t tmpval, regval, intr_mask;
5603         struct e1000_hw *hw =
5604                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5605         uint32_t vec = E1000_MISC_VEC_ID;
5606         uint32_t base = E1000_MISC_VEC_ID;
5607         uint32_t misc_shift = 0;
5608         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5609         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5610
5611         /* won't configure msix register if no mapping is done
5612          * between intr vector and event fd
5613          */
5614         if (!rte_intr_dp_is_en(intr_handle))
5615                 return;
5616
5617         if (rte_intr_allow_others(intr_handle)) {
5618                 vec = base = E1000_RX_VEC_START;
5619                 misc_shift = 1;
5620         }
5621
5622         /* set interrupt vector for other causes */
5623         if (hw->mac.type == e1000_82575) {
5624                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5625                 /* enable MSI-X PBA support */
5626                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5627
5628                 /* Auto-Mask interrupts upon ICR read */
5629                 tmpval |= E1000_CTRL_EXT_EIAME;
5630                 tmpval |= E1000_CTRL_EXT_IRCA;
5631
5632                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5633
5634                 /* enable msix_other interrupt */
5635                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5636                 regval = E1000_READ_REG(hw, E1000_EIAC);
5637                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5638                 regval = E1000_READ_REG(hw, E1000_EIAM);
5639                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5640         } else if ((hw->mac.type == e1000_82576) ||
5641                         (hw->mac.type == e1000_82580) ||
5642                         (hw->mac.type == e1000_i350) ||
5643                         (hw->mac.type == e1000_i354) ||
5644                         (hw->mac.type == e1000_i210) ||
5645                         (hw->mac.type == e1000_i211)) {
5646                 /* turn on MSI-X capability first */
5647                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5648                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5649                                         E1000_GPIE_NSICR);
5650                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5651                         misc_shift;
5652
5653                 if (dev->data->dev_conf.intr_conf.lsc != 0)
5654                         intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5655
5656                 regval = E1000_READ_REG(hw, E1000_EIAC);
5657                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5658
5659                 /* enable msix_other interrupt */
5660                 regval = E1000_READ_REG(hw, E1000_EIMS);
5661                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5662                 tmpval = (IGB_MSIX_OTHER_INTR_VEC | E1000_IVAR_VALID) << 8;
5663                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5664         }
5665
5666         /* use EIAM to auto-mask when MSI-X interrupt
5667          * is asserted, this saves a register write for every interrupt
5668          */
5669         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5670                 misc_shift;
5671
5672         if (dev->data->dev_conf.intr_conf.lsc != 0)
5673                 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5674
5675         regval = E1000_READ_REG(hw, E1000_EIAM);
5676         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5677
5678         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5679                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5680                 intr_handle->intr_vec[queue_id] = vec;
5681                 if (vec < base + intr_handle->nb_efd - 1)
5682                         vec++;
5683         }
5684
5685         E1000_WRITE_FLUSH(hw);
5686 }
5687
5688 /* restore n-tuple filter */
5689 static inline void
5690 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5691 {
5692         struct e1000_filter_info *filter_info =
5693                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5694         struct e1000_5tuple_filter *p_5tuple;
5695         struct e1000_2tuple_filter *p_2tuple;
5696
5697         TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5698                 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5699         }
5700
5701         TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5702                 igb_inject_2uple_filter(dev, p_2tuple);
5703         }
5704 }
5705
5706 /* restore SYN filter */
5707 static inline void
5708 igb_syn_filter_restore(struct rte_eth_dev *dev)
5709 {
5710         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5711         struct e1000_filter_info *filter_info =
5712                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5713         uint32_t synqf;
5714
5715         synqf = filter_info->syn_info;
5716
5717         if (synqf & E1000_SYN_FILTER_ENABLE) {
5718                 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5719                 E1000_WRITE_FLUSH(hw);
5720         }
5721 }
5722
5723 /* restore ethernet type filter */
5724 static inline void
5725 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5726 {
5727         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5728         struct e1000_filter_info *filter_info =
5729                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5730         int i;
5731
5732         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5733                 if (filter_info->ethertype_mask & (1 << i)) {
5734                         E1000_WRITE_REG(hw, E1000_ETQF(i),
5735                                 filter_info->ethertype_filters[i].etqf);
5736                         E1000_WRITE_FLUSH(hw);
5737                 }
5738         }
5739 }
5740
5741 /* restore flex byte filter */
5742 static inline void
5743 igb_flex_filter_restore(struct rte_eth_dev *dev)
5744 {
5745         struct e1000_filter_info *filter_info =
5746                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5747         struct e1000_flex_filter *flex_filter;
5748
5749         TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5750                 igb_inject_flex_filter(dev, flex_filter);
5751         }
5752 }
5753
5754 /* restore rss filter */
5755 static inline void
5756 igb_rss_filter_restore(struct rte_eth_dev *dev)
5757 {
5758         struct e1000_filter_info *filter_info =
5759                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5760
5761         if (filter_info->rss_info.conf.queue_num)
5762                 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5763 }
5764
5765 /* restore all types filter */
5766 static int
5767 igb_filter_restore(struct rte_eth_dev *dev)
5768 {
5769         igb_ntuple_filter_restore(dev);
5770         igb_ethertype_filter_restore(dev);
5771         igb_syn_filter_restore(dev);
5772         igb_flex_filter_restore(dev);
5773         igb_rss_filter_restore(dev);
5774
5775         return 0;
5776 }
5777
5778 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5779 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5780 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5781 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5782 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5783 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");
5784
5785 /* see e1000_logs.c */
5786 RTE_INIT(e1000_init_log)
5787 {
5788         e1000_igb_init_log();
5789 }