drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58 #include "igb_regs.h"
  59
  60 /*
  61  * Default values for port configuration
  62  */
  63 #define IGB_DEFAULT_RX_FREE_THRESH  32
  64 #define IGB_DEFAULT_RX_PTHRESH      8
  65 #define IGB_DEFAULT_RX_HTHRESH      8
  66 #define IGB_DEFAULT_RX_WTHRESH      0
  67
  68 #define IGB_DEFAULT_TX_PTHRESH      32
  69 #define IGB_DEFAULT_TX_HTHRESH      0
  70 #define IGB_DEFAULT_TX_WTHRESH      0
  71
  72 #define IGB_HKEY_MAX_INDEX 10
  73
  74 /* Bit shift and mask */
  75 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  76 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  77 #define IGB_8_BIT_WIDTH  CHAR_BIT
  78 #define IGB_8_BIT_MASK   UINT8_MAX
  79
  80 /* Additional timesync values. */
  81 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  82 #define E1000_ETQF_FILTER_1588       3
  83 #define IGB_82576_TSYNC_SHIFT        16
  84 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  85 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  86 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  87
  88 static int  eth_igb_configure(struct rte_eth_dev *dev);
  89 static int  eth_igb_start(struct rte_eth_dev *dev);
  90 static void eth_igb_stop(struct rte_eth_dev *dev);
  91 static void eth_igb_close(struct rte_eth_dev *dev);
  92 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  93 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  94 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  95 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  96 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  97                                 int wait_to_complete);
  98 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  99                                 struct rte_eth_stats *rte_stats);
 100 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 101                               struct rte_eth_xstats *xstats, unsigned n);
 102 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 103 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 104 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 105                               struct rte_eth_dev_info *dev_info);
 106 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 107                                 struct rte_eth_dev_info *dev_info);
 108 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 109                                 struct rte_eth_fc_conf *fc_conf);
 110 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 111                                 struct rte_eth_fc_conf *fc_conf);
 112 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 113 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 114 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 115 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
 116 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 117                                                         void *param);
 118 static int  igb_hardware_init(struct e1000_hw *hw);
 119 static void igb_hw_control_acquire(struct e1000_hw *hw);
 120 static void igb_hw_control_release(struct e1000_hw *hw);
 121 static void igb_init_manageability(struct e1000_hw *hw);
 122 static void igb_release_manageability(struct e1000_hw *hw);
 123
 124 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 125
 126 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 127                 uint16_t vlan_id, int on);
 128 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 129 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 130
 131 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 132 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 133 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 134 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 135 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 136 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 137
 138 static int eth_igb_led_on(struct rte_eth_dev *dev);
 139 static int eth_igb_led_off(struct rte_eth_dev *dev);
 140
 141 static void igb_intr_disable(struct e1000_hw *hw);
 142 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 143 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 144                 struct ether_addr *mac_addr,
 145                 uint32_t index, uint32_t pool);
 146 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 147 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 148                 struct ether_addr *addr);
 149
 150 static void igbvf_intr_disable(struct e1000_hw *hw);
 151 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 152 static int igbvf_dev_start(struct rte_eth_dev *dev);
 153 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 154 static void igbvf_dev_close(struct rte_eth_dev *dev);
 155 static int eth_igbvf_link_update(struct e1000_hw *hw);
 156 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
 157                                 struct rte_eth_stats *rte_stats);
 158 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 159                                 struct rte_eth_xstats *xstats, unsigned n);
 160 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 161 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 162                 uint16_t vlan_id, int on);
 163 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 164 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 165 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 166                 struct ether_addr *addr);
 167 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 168 static int igbvf_get_regs(struct rte_eth_dev *dev,
 169                 struct rte_dev_reg_info *regs);
 170
 171 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 172                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 173                                    uint16_t reta_size);
 174 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 175                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 176                                   uint16_t reta_size);
 177
 178 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 179                         struct rte_eth_syn_filter *filter,
 180                         bool add);
 181 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 182                         struct rte_eth_syn_filter *filter);
 183 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 184                         enum rte_filter_op filter_op,
 185                         void *arg);
 186 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 187                         struct rte_eth_ntuple_filter *ntuple_filter);
 188 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 189                         struct rte_eth_ntuple_filter *ntuple_filter);
 190 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 191                         struct rte_eth_flex_filter *filter,
 192                         bool add);
 193 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 194                         struct rte_eth_flex_filter *filter);
 195 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 196                         enum rte_filter_op filter_op,
 197                         void *arg);
 198 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 199                         struct rte_eth_ntuple_filter *ntuple_filter);
 200 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 201                         struct rte_eth_ntuple_filter *ntuple_filter);
 202 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 203                         struct rte_eth_ntuple_filter *filter,
 204                         bool add);
 205 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 206                         struct rte_eth_ntuple_filter *filter);
 207 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 208                                 enum rte_filter_op filter_op,
 209                                 void *arg);
 210 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 211                         struct rte_eth_ethertype_filter *filter,
 212                         bool add);
 213 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 214                                 enum rte_filter_op filter_op,
 215                                 void *arg);
 216 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 217                         struct rte_eth_ethertype_filter *filter);
 218 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 219                      enum rte_filter_type filter_type,
 220                      enum rte_filter_op filter_op,
 221                      void *arg);
 222 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 223 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 224                 struct rte_dev_reg_info *regs);
 225 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 226 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 227                 struct rte_dev_eeprom_info *eeprom);
 228 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 229                 struct rte_dev_eeprom_info *eeprom);
 230 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 231                                     struct ether_addr *mc_addr_set,
 232                                     uint32_t nb_mc_addr);
 233 static int igb_timesync_enable(struct rte_eth_dev *dev);
 234 static int igb_timesync_disable(struct rte_eth_dev *dev);
 235 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 236                                           struct timespec *timestamp,
 237                                           uint32_t flags);
 238 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 239                                           struct timespec *timestamp);
 240 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 241 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 242                                   struct timespec *timestamp);
 243 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 244                                    const struct timespec *timestamp);
 245 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 246                                         uint16_t queue_id);
 247 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 248                                          uint16_t queue_id);
 249 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 250                                        uint8_t queue, uint8_t msix_vector);
 251 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 252                                uint8_t index, uint8_t offset);
 253 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 254
 255 /*
 256  * Define VF Stats MACRO for Non "cleared on read" register
 257  */
 258 #define UPDATE_VF_STAT(reg, last, cur)            \
 259 {                                                 \
 260         u32 latest = E1000_READ_REG(hw, reg);     \
 261         cur += (latest - last) & UINT_MAX;        \
 262         last = latest;                            \
 263 }
 264
 265 #define IGB_FC_PAUSE_TIME 0x0680
 266 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 267 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 268
 269 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 270
 271 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 272
 273 /*
 274  * The set of PCI devices this driver supports
 275  */
 276 static const struct rte_pci_id pci_id_igb_map[] = {
 277
 278 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 279 #include "rte_pci_dev_ids.h"
 280
 281 {0},
 282 };
 283
 284 /*
 285  * The set of PCI devices this driver supports (for 82576&I350 VF)
 286  */
 287 static const struct rte_pci_id pci_id_igbvf_map[] = {
 288
 289 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 290 #include "rte_pci_dev_ids.h"
 291
 292 {0},
 293 };
 294
 295 static const struct rte_eth_desc_lim rx_desc_lim = {
 296         .nb_max = E1000_MAX_RING_DESC,
 297         .nb_min = E1000_MIN_RING_DESC,
 298         .nb_align = IGB_RXD_ALIGN,
 299 };
 300
 301 static const struct rte_eth_desc_lim tx_desc_lim = {
 302         .nb_max = E1000_MAX_RING_DESC,
 303         .nb_min = E1000_MIN_RING_DESC,
 304         .nb_align = IGB_RXD_ALIGN,
 305 };
 306
 307 static const struct eth_dev_ops eth_igb_ops = {
 308         .dev_configure        = eth_igb_configure,
 309         .dev_start            = eth_igb_start,
 310         .dev_stop             = eth_igb_stop,
 311         .dev_close            = eth_igb_close,
 312         .promiscuous_enable   = eth_igb_promiscuous_enable,
 313         .promiscuous_disable  = eth_igb_promiscuous_disable,
 314         .allmulticast_enable  = eth_igb_allmulticast_enable,
 315         .allmulticast_disable = eth_igb_allmulticast_disable,
 316         .link_update          = eth_igb_link_update,
 317         .stats_get            = eth_igb_stats_get,
 318         .xstats_get           = eth_igb_xstats_get,
 319         .stats_reset          = eth_igb_stats_reset,
 320         .xstats_reset         = eth_igb_xstats_reset,
 321         .dev_infos_get        = eth_igb_infos_get,
 322         .mtu_set              = eth_igb_mtu_set,
 323         .vlan_filter_set      = eth_igb_vlan_filter_set,
 324         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 325         .vlan_offload_set     = eth_igb_vlan_offload_set,
 326         .rx_queue_setup       = eth_igb_rx_queue_setup,
 327         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 328         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 329         .rx_queue_release     = eth_igb_rx_queue_release,
 330         .rx_queue_count       = eth_igb_rx_queue_count,
 331         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 332         .tx_queue_setup       = eth_igb_tx_queue_setup,
 333         .tx_queue_release     = eth_igb_tx_queue_release,
 334         .dev_led_on           = eth_igb_led_on,
 335         .dev_led_off          = eth_igb_led_off,
 336         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 337         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 338         .mac_addr_add         = eth_igb_rar_set,
 339         .mac_addr_remove      = eth_igb_rar_clear,
 340         .mac_addr_set         = eth_igb_default_mac_addr_set,
 341         .reta_update          = eth_igb_rss_reta_update,
 342         .reta_query           = eth_igb_rss_reta_query,
 343         .rss_hash_update      = eth_igb_rss_hash_update,
 344         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 345         .filter_ctrl          = eth_igb_filter_ctrl,
 346         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 347         .rxq_info_get         = igb_rxq_info_get,
 348         .txq_info_get         = igb_txq_info_get,
 349         .timesync_enable      = igb_timesync_enable,
 350         .timesync_disable     = igb_timesync_disable,
 351         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 352         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 353         .get_reg_length       = eth_igb_get_reg_length,
 354         .get_reg              = eth_igb_get_regs,
 355         .get_eeprom_length    = eth_igb_get_eeprom_length,
 356         .get_eeprom           = eth_igb_get_eeprom,
 357         .set_eeprom           = eth_igb_set_eeprom,
 358         .timesync_adjust_time = igb_timesync_adjust_time,
 359         .timesync_read_time   = igb_timesync_read_time,
 360         .timesync_write_time  = igb_timesync_write_time,
 361 };
 362
 363 /*
 364  * dev_ops for virtual function, bare necessities for basic vf
 365  * operation have been implemented
 366  */
 367 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 368         .dev_configure        = igbvf_dev_configure,
 369         .dev_start            = igbvf_dev_start,
 370         .dev_stop             = igbvf_dev_stop,
 371         .dev_close            = igbvf_dev_close,
 372         .link_update          = eth_igb_link_update,
 373         .stats_get            = eth_igbvf_stats_get,
 374         .xstats_get           = eth_igbvf_xstats_get,
 375         .stats_reset          = eth_igbvf_stats_reset,
 376         .xstats_reset         = eth_igbvf_stats_reset,
 377         .vlan_filter_set      = igbvf_vlan_filter_set,
 378         .dev_infos_get        = eth_igbvf_infos_get,
 379         .rx_queue_setup       = eth_igb_rx_queue_setup,
 380         .rx_queue_release     = eth_igb_rx_queue_release,
 381         .tx_queue_setup       = eth_igb_tx_queue_setup,
 382         .tx_queue_release     = eth_igb_tx_queue_release,
 383         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 384         .rxq_info_get         = igb_rxq_info_get,
 385         .txq_info_get         = igb_txq_info_get,
 386         .mac_addr_set         = igbvf_default_mac_addr_set,
 387         .get_reg_length       = igbvf_get_reg_length,
 388         .get_reg              = igbvf_get_regs,
 389 };
 390
 391 /* store statistics names and its offset in stats structure */
 392 struct rte_igb_xstats_name_off {
 393         char name[RTE_ETH_XSTATS_NAME_SIZE];
 394         unsigned offset;
 395 };
 396
 397 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 398         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 399         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 400         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 401         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 402         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 403         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 404         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 405                 ecol)},
 406         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 407         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 408         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 409         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 410         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 411         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 412         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 413         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 414         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 415         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 416         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 417                 fcruc)},
 418         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 419         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 420         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 421         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 422         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 423                 prc1023)},
 424         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 425                 prc1522)},
 426         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 427         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 428         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 429         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 430         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 431         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 432         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 433         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 434         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 435         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 436         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 437         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 438         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 439         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 440         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 441         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 442         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 443         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 444                 ptc1023)},
 445         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 446                 ptc1522)},
 447         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 448         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 449         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 450         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 451         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 452         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 453         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 454
 455         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 456 };
 457
 458 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 459                 sizeof(rte_igb_stats_strings[0]))
 460
 461 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 462         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 463         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 464         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 465         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 466         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 467 };
 468
 469 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 470                 sizeof(rte_igbvf_stats_strings[0]))
 471
 472 /**
 473  * Atomically reads the link status information from global
 474  * structure rte_eth_dev.
 475  *
 476  * @param dev
 477  *   - Pointer to the structure rte_eth_dev to read from.
 478  *   - Pointer to the buffer to be saved with the link status.
 479  *
 480  * @return
 481  *   - On success, zero.
 482  *   - On failure, negative value.
 483  */
 484 static inline int
 485 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 486                                 struct rte_eth_link *link)
 487 {
 488         struct rte_eth_link *dst = link;
 489         struct rte_eth_link *src = &(dev->data->dev_link);
 490
 491         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 492                                         *(uint64_t *)src) == 0)
 493                 return -1;
 494
 495         return 0;
 496 }
 497
 498 /**
 499  * Atomically writes the link status information into global
 500  * structure rte_eth_dev.
 501  *
 502  * @param dev
 503  *   - Pointer to the structure rte_eth_dev to read from.
 504  *   - Pointer to the buffer to be saved with the link status.
 505  *
 506  * @return
 507  *   - On success, zero.
 508  *   - On failure, negative value.
 509  */
 510 static inline int
 511 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 512                                 struct rte_eth_link *link)
 513 {
 514         struct rte_eth_link *dst = &(dev->data->dev_link);
 515         struct rte_eth_link *src = link;
 516
 517         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 518                                         *(uint64_t *)src) == 0)
 519                 return -1;
 520
 521         return 0;
 522 }
 523
 524 static inline void
 525 igb_intr_enable(struct rte_eth_dev *dev)
 526 {
 527         struct e1000_interrupt *intr =
 528                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 529         struct e1000_hw *hw =
 530                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 531
 532         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 533         E1000_WRITE_FLUSH(hw);
 534 }
 535
 536 static void
 537 igb_intr_disable(struct e1000_hw *hw)
 538 {
 539         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 540         E1000_WRITE_FLUSH(hw);
 541 }
 542
 543 static inline int32_t
 544 igb_pf_reset_hw(struct e1000_hw *hw)
 545 {
 546         uint32_t ctrl_ext;
 547         int32_t status;
 548
 549         status = e1000_reset_hw(hw);
 550
 551         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 552         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 553         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 554         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 555         E1000_WRITE_FLUSH(hw);
 556
 557         return status;
 558 }
 559
 560 static void
 561 igb_identify_hardware(struct rte_eth_dev *dev)
 562 {
 563         struct e1000_hw *hw =
 564                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 565
 566         hw->vendor_id = dev->pci_dev->id.vendor_id;
 567         hw->device_id = dev->pci_dev->id.device_id;
 568         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 569         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 570
 571         e1000_set_mac_type(hw);
 572
 573         /* need to check if it is a vf device below */
 574 }
 575
 576 static int
 577 igb_reset_swfw_lock(struct e1000_hw *hw)
 578 {
 579         int ret_val;
 580
 581         /*
 582          * Do mac ops initialization manually here, since we will need
 583          * some function pointers set by this call.
 584          */
 585         ret_val = e1000_init_mac_params(hw);
 586         if (ret_val)
 587                 return ret_val;
 588
 589         /*
 590          * SMBI lock should not fail in this early stage. If this is the case,
 591          * it is due to an improper exit of the application.
 592          * So force the release of the faulty lock.
 593          */
 594         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 595                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 596         }
 597         e1000_put_hw_semaphore_generic(hw);
 598
 599         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 600                 uint16_t mask;
 601
 602                 /*
 603                  * Phy lock should not fail in this early stage. If this is the case,
 604                  * it is due to an improper exit of the application.
 605                  * So force the release of the faulty lock.
 606                  */
 607                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 608                 if (hw->bus.func > E1000_FUNC_1)
 609                         mask <<= 2;
 610                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 611                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 612                                     hw->bus.func);
 613                 }
 614                 hw->mac.ops.release_swfw_sync(hw, mask);
 615
 616                 /*
 617                  * This one is more tricky since it is common to all ports; but
 618                  * swfw_sync retries last long enough (1s) to be almost sure that if
 619                  * lock can not be taken it is due to an improper lock of the
 620                  * semaphore.
 621                  */
 622                 mask = E1000_SWFW_EEP_SM;
 623                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 624                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 625                 }
 626                 hw->mac.ops.release_swfw_sync(hw, mask);
 627         }
 628
 629         return E1000_SUCCESS;
 630 }
 631
 632 static int
 633 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 634 {
 635         int error = 0;
 636         struct rte_pci_device *pci_dev;
 637         struct e1000_hw *hw =
 638                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 639         struct e1000_vfta * shadow_vfta =
 640                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 641         struct e1000_filter_info *filter_info =
 642                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 643         struct e1000_adapter *adapter =
 644                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 645
 646         uint32_t ctrl_ext;
 647
 648         pci_dev = eth_dev->pci_dev;
 649
 650         eth_dev->dev_ops = &eth_igb_ops;
 651         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 652         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 653
 654         /* for secondary processes, we don't initialise any further as primary
 655          * has already done this work. Only check we don't need a different
 656          * RX function */
 657         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 658                 if (eth_dev->data->scattered_rx)
 659                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 660                 return 0;
 661         }
 662
 663         rte_eth_copy_pci_info(eth_dev, pci_dev);
 664
 665         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 666
 667         igb_identify_hardware(eth_dev);
 668         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 669                 error = -EIO;
 670                 goto err_late;
 671         }
 672
 673         e1000_get_bus_info(hw);
 674
 675         /* Reset any pending lock */
 676         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 677                 error = -EIO;
 678                 goto err_late;
 679         }
 680
 681         /* Finish initialization */
 682         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 683                 error = -EIO;
 684                 goto err_late;
 685         }
 686
 687         hw->mac.autoneg = 1;
 688         hw->phy.autoneg_wait_to_complete = 0;
 689         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 690
 691         /* Copper options */
 692         if (hw->phy.media_type == e1000_media_type_copper) {
 693                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 694                 hw->phy.disable_polarity_correction = 0;
 695                 hw->phy.ms_type = e1000_ms_hw_default;
 696         }
 697
 698         /*
 699          * Start from a known state, this is important in reading the nvm
 700          * and mac from that.
 701          */
 702         igb_pf_reset_hw(hw);
 703
 704         /* Make sure we have a good EEPROM before we read from it */
 705         if (e1000_validate_nvm_checksum(hw) < 0) {
 706                 /*
 707                  * Some PCI-E parts fail the first check due to
 708                  * the link being in sleep state, call it again,
 709                  * if it fails a second time its a real issue.
 710                  */
 711                 if (e1000_validate_nvm_checksum(hw) < 0) {
 712                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 713                         error = -EIO;
 714                         goto err_late;
 715                 }
 716         }
 717
 718         /* Read the permanent MAC address out of the EEPROM */
 719         if (e1000_read_mac_addr(hw) != 0) {
 720                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 721                 error = -EIO;
 722                 goto err_late;
 723         }
 724
 725         /* Allocate memory for storing MAC addresses */
 726         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 727                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 728         if (eth_dev->data->mac_addrs == NULL) {
 729                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 730                                                 "store MAC addresses",
 731                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 732                 error = -ENOMEM;
 733                 goto err_late;
 734         }
 735
 736         /* Copy the permanent MAC address */
 737         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 738
 739         /* initialize the vfta */
 740         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 741
 742         /* Now initialize the hardware */
 743         if (igb_hardware_init(hw) != 0) {
 744                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 745                 rte_free(eth_dev->data->mac_addrs);
 746                 eth_dev->data->mac_addrs = NULL;
 747                 error = -ENODEV;
 748                 goto err_late;
 749         }
 750         hw->mac.get_link_status = 1;
 751         adapter->stopped = 0;
 752
 753         /* Indicate SOL/IDER usage */
 754         if (e1000_check_reset_block(hw) < 0) {
 755                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 756                                         "SOL/IDER session");
 757         }
 758
 759         /* initialize PF if max_vfs not zero */
 760         igb_pf_host_init(eth_dev);
 761
 762         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 763         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 764         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 765         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 766         E1000_WRITE_FLUSH(hw);
 767
 768         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 769                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 770                      pci_dev->id.device_id);
 771
 772         rte_intr_callback_register(&pci_dev->intr_handle,
 773                                    eth_igb_interrupt_handler,
 774                                    (void *)eth_dev);
 775
 776         /* enable uio/vfio intr/eventfd mapping */
 777         rte_intr_enable(&pci_dev->intr_handle);
 778
 779         /* enable support intr */
 780         igb_intr_enable(eth_dev);
 781
 782         TAILQ_INIT(&filter_info->flex_list);
 783         filter_info->flex_mask = 0;
 784         TAILQ_INIT(&filter_info->twotuple_list);
 785         filter_info->twotuple_mask = 0;
 786         TAILQ_INIT(&filter_info->fivetuple_list);
 787         filter_info->fivetuple_mask = 0;
 788
 789         return 0;
 790
 791 err_late:
 792         igb_hw_control_release(hw);
 793
 794         return error;
 795 }
 796
 797 static int
 798 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 799 {
 800         struct rte_pci_device *pci_dev;
 801         struct e1000_hw *hw;
 802         struct e1000_adapter *adapter =
 803                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 804
 805         PMD_INIT_FUNC_TRACE();
 806
 807         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 808                 return -EPERM;
 809
 810         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 811         pci_dev = eth_dev->pci_dev;
 812
 813         if (adapter->stopped == 0)
 814                 eth_igb_close(eth_dev);
 815
 816         eth_dev->dev_ops = NULL;
 817         eth_dev->rx_pkt_burst = NULL;
 818         eth_dev->tx_pkt_burst = NULL;
 819
 820         /* Reset any pending lock */
 821         igb_reset_swfw_lock(hw);
 822
 823         rte_free(eth_dev->data->mac_addrs);
 824         eth_dev->data->mac_addrs = NULL;
 825
 826         /* uninitialize PF if max_vfs not zero */
 827         igb_pf_host_uninit(eth_dev);
 828
 829         /* disable uio intr before callback unregister */
 830         rte_intr_disable(&(pci_dev->intr_handle));
 831         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 832                 eth_igb_interrupt_handler, (void *)eth_dev);
 833
 834         return 0;
 835 }
 836
 837 /*
 838  * Virtual Function device init
 839  */
 840 static int
 841 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 842 {
 843         struct rte_pci_device *pci_dev;
 844         struct e1000_adapter *adapter =
 845                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 846         struct e1000_hw *hw =
 847                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 848         int diag;
 849         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
 850
 851         PMD_INIT_FUNC_TRACE();
 852
 853         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 854         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 855         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 856
 857         /* for secondary processes, we don't initialise any further as primary
 858          * has already done this work. Only check we don't need a different
 859          * RX function */
 860         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 861                 if (eth_dev->data->scattered_rx)
 862                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 863                 return 0;
 864         }
 865
 866         pci_dev = eth_dev->pci_dev;
 867
 868         rte_eth_copy_pci_info(eth_dev, pci_dev);
 869
 870         hw->device_id = pci_dev->id.device_id;
 871         hw->vendor_id = pci_dev->id.vendor_id;
 872         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 873         adapter->stopped = 0;
 874
 875         /* Initialize the shared code (base driver) */
 876         diag = e1000_setup_init_funcs(hw, TRUE);
 877         if (diag != 0) {
 878                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 879                         diag);
 880                 return -EIO;
 881         }
 882
 883         /* init_mailbox_params */
 884         hw->mbx.ops.init_params(hw);
 885
 886         /* Disable the interrupts for VF */
 887         igbvf_intr_disable(hw);
 888
 889         diag = hw->mac.ops.reset_hw(hw);
 890
 891         /* Allocate memory for storing MAC addresses */
 892         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 893                 hw->mac.rar_entry_count, 0);
 894         if (eth_dev->data->mac_addrs == NULL) {
 895                 PMD_INIT_LOG(ERR,
 896                         "Failed to allocate %d bytes needed to store MAC "
 897                         "addresses",
 898                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 899                 return -ENOMEM;
 900         }
 901
 902         /* Generate a random MAC address, if none was assigned by PF. */
 903         if (is_zero_ether_addr(perm_addr)) {
 904                 eth_random_addr(perm_addr->addr_bytes);
 905                 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
 906                 if (diag) {
 907                         rte_free(eth_dev->data->mac_addrs);
 908                         eth_dev->data->mac_addrs = NULL;
 909                         return diag;
 910                 }
 911                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
 912                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
 913                              "%02x:%02x:%02x:%02x:%02x:%02x",
 914                              perm_addr->addr_bytes[0],
 915                              perm_addr->addr_bytes[1],
 916                              perm_addr->addr_bytes[2],
 917                              perm_addr->addr_bytes[3],
 918                              perm_addr->addr_bytes[4],
 919                              perm_addr->addr_bytes[5]);
 920         }
 921
 922         /* Copy the permanent MAC address */
 923         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 924                         &eth_dev->data->mac_addrs[0]);
 925
 926         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
 927                      "mac.type=%s",
 928                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 929                      pci_dev->id.device_id, "igb_mac_82576_vf");
 930
 931         return 0;
 932 }
 933
 934 static int
 935 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
 936 {
 937         struct e1000_adapter *adapter =
 938                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 939
 940         PMD_INIT_FUNC_TRACE();
 941
 942         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 943                 return -EPERM;
 944
 945         if (adapter->stopped == 0)
 946                 igbvf_dev_close(eth_dev);
 947
 948         eth_dev->dev_ops = NULL;
 949         eth_dev->rx_pkt_burst = NULL;
 950         eth_dev->tx_pkt_burst = NULL;
 951
 952         rte_free(eth_dev->data->mac_addrs);
 953         eth_dev->data->mac_addrs = NULL;
 954
 955         return 0;
 956 }
 957
 958 static struct eth_driver rte_igb_pmd = {
 959         .pci_drv = {
 960                 .name = "rte_igb_pmd",
 961                 .id_table = pci_id_igb_map,
 962                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 963                         RTE_PCI_DRV_DETACHABLE,
 964         },
 965         .eth_dev_init = eth_igb_dev_init,
 966         .eth_dev_uninit = eth_igb_dev_uninit,
 967         .dev_private_size = sizeof(struct e1000_adapter),
 968 };
 969
 970 /*
 971  * virtual function driver struct
 972  */
 973 static struct eth_driver rte_igbvf_pmd = {
 974         .pci_drv = {
 975                 .name = "rte_igbvf_pmd",
 976                 .id_table = pci_id_igbvf_map,
 977                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
 978         },
 979         .eth_dev_init = eth_igbvf_dev_init,
 980         .eth_dev_uninit = eth_igbvf_dev_uninit,
 981         .dev_private_size = sizeof(struct e1000_adapter),
 982 };
 983
 984 static int
 985 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 986 {
 987         rte_eth_driver_register(&rte_igb_pmd);
 988         return 0;
 989 }
 990
 991 static void
 992 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
 993 {
 994         struct e1000_hw *hw =
 995                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 996         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
 997         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
 998         rctl |= E1000_RCTL_VFE;
 999         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1000 }
1001
1002 /*
1003  * VF Driver initialization routine.
1004  * Invoked one at EAL init time.
1005  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
1006  */
1007 static int
1008 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1009 {
1010         PMD_INIT_FUNC_TRACE();
1011
1012         rte_eth_driver_register(&rte_igbvf_pmd);
1013         return 0;
1014 }
1015
1016 static int
1017 igb_check_mq_mode(struct rte_eth_dev *dev)
1018 {
1019         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1020         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1021         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1022         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1023
1024         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1025             tx_mq_mode == ETH_MQ_TX_DCB ||
1026             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1027                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1028                 return -EINVAL;
1029         }
1030         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1031                 /* Check multi-queue mode.
1032                  * To no break software we accept ETH_MQ_RX_NONE as this might
1033                  * be used to turn off VLAN filter.
1034                  */
1035
1036                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1037                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1038                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1039                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1040                 } else {
1041                         /* Only support one queue on VFs.
1042                          * RSS together with SRIOV is not supported.
1043                          */
1044                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1045                                         " wrong mq_mode rx %d.",
1046                                         rx_mq_mode);
1047                         return -EINVAL;
1048                 }
1049                 /* TX mode is not used here, so mode might be ignored.*/
1050                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1051                         /* SRIOV only works in VMDq enable mode */
1052                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1053                                         " TX mode %d is not supported. "
1054                                         " Driver will behave as %d mode.",
1055                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1056                 }
1057
1058                 /* check valid queue number */
1059                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1060                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1061                                         " only support one queue on VFs.");
1062                         return -EINVAL;
1063                 }
1064         } else {
1065                 /* To no break software that set invalid mode, only display
1066                  * warning if invalid mode is used.
1067                  */
1068                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1069                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1070                     rx_mq_mode != ETH_MQ_RX_RSS) {
1071                         /* RSS together with VMDq not supported*/
1072                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1073                                      rx_mq_mode);
1074                         return -EINVAL;
1075                 }
1076
1077                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1078                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1079                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1080                                         " Due to txmode is meaningless in this"
1081                                         " driver, just ignore.",
1082                                         tx_mq_mode);
1083                 }
1084         }
1085         return 0;
1086 }
1087
1088 static int
1089 eth_igb_configure(struct rte_eth_dev *dev)
1090 {
1091         struct e1000_interrupt *intr =
1092                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1093         int ret;
1094
1095         PMD_INIT_FUNC_TRACE();
1096
1097         /* multipe queue mode checking */
1098         ret  = igb_check_mq_mode(dev);
1099         if (ret != 0) {
1100                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1101                             ret);
1102                 return ret;
1103         }
1104
1105         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1106         PMD_INIT_FUNC_TRACE();
1107
1108         return 0;
1109 }
1110
1111 static int
1112 eth_igb_start(struct rte_eth_dev *dev)
1113 {
1114         struct e1000_hw *hw =
1115                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1116         struct e1000_adapter *adapter =
1117                 E1000_DEV_PRIVATE(dev->data->dev_private);
1118         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1119         int ret, mask;
1120         uint32_t intr_vector = 0;
1121         uint32_t ctrl_ext;
1122
1123         PMD_INIT_FUNC_TRACE();
1124
1125         /* disable uio/vfio intr/eventfd mapping */
1126         rte_intr_disable(intr_handle);
1127
1128         /* Power up the phy. Needed to make the link go Up */
1129         e1000_power_up_phy(hw);
1130
1131         /*
1132          * Packet Buffer Allocation (PBA)
1133          * Writing PBA sets the receive portion of the buffer
1134          * the remainder is used for the transmit buffer.
1135          */
1136         if (hw->mac.type == e1000_82575) {
1137                 uint32_t pba;
1138
1139                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1140                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1141         }
1142
1143         /* Put the address into the Receive Address Array */
1144         e1000_rar_set(hw, hw->mac.addr, 0);
1145
1146         /* Initialize the hardware */
1147         if (igb_hardware_init(hw)) {
1148                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1149                 return -EIO;
1150         }
1151         adapter->stopped = 0;
1152
1153         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1154
1155         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1156         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1157         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1158         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1159         E1000_WRITE_FLUSH(hw);
1160
1161         /* configure PF module if SRIOV enabled */
1162         igb_pf_host_configure(dev);
1163
1164         /* check and configure queue intr-vector mapping */
1165         if ((rte_intr_cap_multiple(intr_handle) ||
1166              !RTE_ETH_DEV_SRIOV(dev).active) &&
1167             dev->data->dev_conf.intr_conf.rxq != 0) {
1168                 intr_vector = dev->data->nb_rx_queues;
1169                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1170                         return -1;
1171         }
1172
1173         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1174                 intr_handle->intr_vec =
1175                         rte_zmalloc("intr_vec",
1176                                     dev->data->nb_rx_queues * sizeof(int), 0);
1177                 if (intr_handle->intr_vec == NULL) {
1178                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1179                                      " intr_vec\n", dev->data->nb_rx_queues);
1180                         return -ENOMEM;
1181                 }
1182         }
1183
1184         /* confiugre msix for rx interrupt */
1185         eth_igb_configure_msix_intr(dev);
1186
1187         /* Configure for OS presence */
1188         igb_init_manageability(hw);
1189
1190         eth_igb_tx_init(dev);
1191
1192         /* This can fail when allocating mbufs for descriptor rings */
1193         ret = eth_igb_rx_init(dev);
1194         if (ret) {
1195                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1196                 igb_dev_clear_queues(dev);
1197                 return ret;
1198         }
1199
1200         e1000_clear_hw_cntrs_base_generic(hw);
1201
1202         /*
1203          * VLAN Offload Settings
1204          */
1205         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1206                         ETH_VLAN_EXTEND_MASK;
1207         eth_igb_vlan_offload_set(dev, mask);
1208
1209         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1210                 /* Enable VLAN filter since VMDq always use VLAN filter */
1211                 igb_vmdq_vlan_hw_filter_enable(dev);
1212         }
1213
1214         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1215                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1216                 (hw->mac.type == e1000_i211)) {
1217                 /* Configure EITR with the maximum possible value (0xFFFF) */
1218                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1219         }
1220
1221         /* Setup link speed and duplex */
1222         switch (dev->data->dev_conf.link_speed) {
1223         case ETH_LINK_SPEED_AUTONEG:
1224                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1225                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1226                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1227                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
1228                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1229                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
1230                 else
1231                         goto error_invalid_config;
1232                 break;
1233         case ETH_LINK_SPEED_10:
1234                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1235                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
1236                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1237                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
1238                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1239                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
1240                 else
1241                         goto error_invalid_config;
1242                 break;
1243         case ETH_LINK_SPEED_100:
1244                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1245                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
1246                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1247                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
1248                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1249                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
1250                 else
1251                         goto error_invalid_config;
1252                 break;
1253         case ETH_LINK_SPEED_1000:
1254                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
1255                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
1256                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
1257                 else
1258                         goto error_invalid_config;
1259                 break;
1260         case ETH_LINK_SPEED_10000:
1261         default:
1262                 goto error_invalid_config;
1263         }
1264         e1000_setup_link(hw);
1265
1266         if (rte_intr_allow_others(intr_handle)) {
1267                 /* check if lsc interrupt is enabled */
1268                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1269                         eth_igb_lsc_interrupt_setup(dev);
1270         } else {
1271                 rte_intr_callback_unregister(intr_handle,
1272                                              eth_igb_interrupt_handler,
1273                                              (void *)dev);
1274                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1275                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1276                                      " no intr multiplex\n");
1277         }
1278
1279         /* check if rxq interrupt is enabled */
1280         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1281             rte_intr_dp_is_en(intr_handle))
1282                 eth_igb_rxq_interrupt_setup(dev);
1283
1284         /* enable uio/vfio intr/eventfd mapping */
1285         rte_intr_enable(intr_handle);
1286
1287         /* resume enabled intr since hw reset */
1288         igb_intr_enable(dev);
1289
1290         PMD_INIT_LOG(DEBUG, "<<");
1291
1292         return 0;
1293
1294 error_invalid_config:
1295         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
1296                      dev->data->dev_conf.link_speed,
1297                      dev->data->dev_conf.link_duplex, dev->data->port_id);
1298         igb_dev_clear_queues(dev);
1299         return -EINVAL;
1300 }
1301
1302 /*********************************************************************
1303  *
1304  *  This routine disables all traffic on the adapter by issuing a
1305  *  global reset on the MAC.
1306  *
1307  **********************************************************************/
1308 static void
1309 eth_igb_stop(struct rte_eth_dev *dev)
1310 {
1311         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1312         struct e1000_filter_info *filter_info =
1313                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1314         struct rte_eth_link link;
1315         struct e1000_flex_filter *p_flex;
1316         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1317         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1318         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1319
1320         igb_intr_disable(hw);
1321
1322         /* disable intr eventfd mapping */
1323         rte_intr_disable(intr_handle);
1324
1325         igb_pf_reset_hw(hw);
1326         E1000_WRITE_REG(hw, E1000_WUC, 0);
1327
1328         /* Set bit for Go Link disconnect */
1329         if (hw->mac.type >= e1000_82580) {
1330                 uint32_t phpm_reg;
1331
1332                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1333                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1334                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1335         }
1336
1337         /* Power down the phy. Needed to make the link go Down */
1338         if (hw->phy.media_type == e1000_media_type_copper)
1339                 e1000_power_down_phy(hw);
1340         else
1341                 e1000_shutdown_fiber_serdes_link(hw);
1342
1343         igb_dev_clear_queues(dev);
1344
1345         /* clear the recorded link status */
1346         memset(&link, 0, sizeof(link));
1347         rte_igb_dev_atomic_write_link_status(dev, &link);
1348
1349         /* Remove all flex filters of the device */
1350         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1351                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1352                 rte_free(p_flex);
1353         }
1354         filter_info->flex_mask = 0;
1355
1356         /* Remove all ntuple filters of the device */
1357         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1358              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1359                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1360                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1361                              p_5tuple, entries);
1362                 rte_free(p_5tuple);
1363         }
1364         filter_info->fivetuple_mask = 0;
1365         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1366              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1367                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1368                 TAILQ_REMOVE(&filter_info->twotuple_list,
1369                              p_2tuple, entries);
1370                 rte_free(p_2tuple);
1371         }
1372         filter_info->twotuple_mask = 0;
1373
1374         if (!rte_intr_allow_others(intr_handle))
1375                 /* resume to the default handler */
1376                 rte_intr_callback_register(intr_handle,
1377                                            eth_igb_interrupt_handler,
1378                                            (void *)dev);
1379
1380         /* Clean datapath event and queue/vec mapping */
1381         rte_intr_efd_disable(intr_handle);
1382         if (intr_handle->intr_vec != NULL) {
1383                 rte_free(intr_handle->intr_vec);
1384                 intr_handle->intr_vec = NULL;
1385         }
1386 }
1387
1388 static void
1389 eth_igb_close(struct rte_eth_dev *dev)
1390 {
1391         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1392         struct e1000_adapter *adapter =
1393                 E1000_DEV_PRIVATE(dev->data->dev_private);
1394         struct rte_eth_link link;
1395         struct rte_pci_device *pci_dev;
1396
1397         eth_igb_stop(dev);
1398         adapter->stopped = 1;
1399
1400         e1000_phy_hw_reset(hw);
1401         igb_release_manageability(hw);
1402         igb_hw_control_release(hw);
1403
1404         /* Clear bit for Go Link disconnect */
1405         if (hw->mac.type >= e1000_82580) {
1406                 uint32_t phpm_reg;
1407
1408                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1409                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1410                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1411         }
1412
1413         igb_dev_free_queues(dev);
1414
1415         pci_dev = dev->pci_dev;
1416         if (pci_dev->intr_handle.intr_vec) {
1417                 rte_free(pci_dev->intr_handle.intr_vec);
1418                 pci_dev->intr_handle.intr_vec = NULL;
1419         }
1420
1421         memset(&link, 0, sizeof(link));
1422         rte_igb_dev_atomic_write_link_status(dev, &link);
1423 }
1424
1425 static int
1426 igb_get_rx_buffer_size(struct e1000_hw *hw)
1427 {
1428         uint32_t rx_buf_size;
1429         if (hw->mac.type == e1000_82576) {
1430                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1431         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1432                 /* PBS needs to be translated according to a lookup table */
1433                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1434                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1435                 rx_buf_size = (rx_buf_size << 10);
1436         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1437                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1438         } else {
1439                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1440         }
1441
1442         return rx_buf_size;
1443 }
1444
1445 /*********************************************************************
1446  *
1447  *  Initialize the hardware
1448  *
1449  **********************************************************************/
1450 static int
1451 igb_hardware_init(struct e1000_hw *hw)
1452 {
1453         uint32_t rx_buf_size;
1454         int diag;
1455
1456         /* Let the firmware know the OS is in control */
1457         igb_hw_control_acquire(hw);
1458
1459         /*
1460          * These parameters control the automatic generation (Tx) and
1461          * response (Rx) to Ethernet PAUSE frames.
1462          * - High water mark should allow for at least two standard size (1518)
1463          *   frames to be received after sending an XOFF.
1464          * - Low water mark works best when it is very near the high water mark.
1465          *   This allows the receiver to restart by sending XON when it has
1466          *   drained a bit. Here we use an arbitrary value of 1500 which will
1467          *   restart after one full frame is pulled from the buffer. There
1468          *   could be several smaller frames in the buffer and if so they will
1469          *   not trigger the XON until their total number reduces the buffer
1470          *   by 1500.
1471          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1472          */
1473         rx_buf_size = igb_get_rx_buffer_size(hw);
1474
1475         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1476         hw->fc.low_water = hw->fc.high_water - 1500;
1477         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1478         hw->fc.send_xon = 1;
1479
1480         /* Set Flow control, use the tunable location if sane */
1481         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1482                 hw->fc.requested_mode = igb_fc_setting;
1483         else
1484                 hw->fc.requested_mode = e1000_fc_none;
1485
1486         /* Issue a global reset */
1487         igb_pf_reset_hw(hw);
1488         E1000_WRITE_REG(hw, E1000_WUC, 0);
1489
1490         diag = e1000_init_hw(hw);
1491         if (diag < 0)
1492                 return diag;
1493
1494         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1495         e1000_get_phy_info(hw);
1496         e1000_check_for_link(hw);
1497
1498         return 0;
1499 }
1500
1501 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1502 static void
1503 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1504 {
1505         int pause_frames;
1506
1507         uint64_t old_gprc  = stats->gprc;
1508         uint64_t old_gptc  = stats->gptc;
1509         uint64_t old_tpr   = stats->tpr;
1510         uint64_t old_tpt   = stats->tpt;
1511         uint64_t old_rpthc = stats->rpthc;
1512         uint64_t old_hgptc = stats->hgptc;
1513
1514         if(hw->phy.media_type == e1000_media_type_copper ||
1515             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1516                 stats->symerrs +=
1517                     E1000_READ_REG(hw,E1000_SYMERRS);
1518                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1519         }
1520
1521         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1522         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1523         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1524         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1525
1526         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1527         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1528         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1529         stats->dc += E1000_READ_REG(hw, E1000_DC);
1530         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1531         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1532         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1533         /*
1534         ** For watchdog management we need to know if we have been
1535         ** paused during the last interval, so capture that here.
1536         */
1537         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1538         stats->xoffrxc += pause_frames;
1539         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1540         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1541         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1542         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1543         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1544         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1545         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1546         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1547         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1548         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1549         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1550         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1551
1552         /* For the 64-bit byte counters the low dword must be read first. */
1553         /* Both registers clear on the read of the high dword */
1554
1555         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1556         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1557         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1558         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1559         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1560         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1561         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1562
1563         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1564         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1565         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1566         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1567         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1568
1569         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1570         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1571
1572         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1573         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1574         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1575         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1576         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1577         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1578
1579         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1580         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1581         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1582         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1583         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1584         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1585         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1586         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1587
1588         /* Interrupt Counts */
1589
1590         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1591         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1592         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1593         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1594         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1595         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1596         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1597         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1598         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1599
1600         /* Host to Card Statistics */
1601
1602         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1603         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1604         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1605         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1606         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1607         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1608         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1609         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1610         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1611         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1612         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1613         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1614         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1615         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1616         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1617         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1618
1619         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1620         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1621         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1622         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1623         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1624         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1625 }
1626
1627 static void
1628 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1629 {
1630         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1631         struct e1000_hw_stats *stats =
1632                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1633
1634         igb_read_stats_registers(hw, stats);
1635
1636         if (rte_stats == NULL)
1637                 return;
1638
1639         /* Rx Errors */
1640         rte_stats->imissed = stats->mpc;
1641         rte_stats->ierrors = stats->crcerrs +
1642                              stats->rlec + stats->ruc + stats->roc +
1643                              rte_stats->imissed +
1644                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1645
1646         /* Tx Errors */
1647         rte_stats->oerrors = stats->ecol + stats->latecol;
1648
1649         rte_stats->ipackets = stats->gprc;
1650         rte_stats->opackets = stats->gptc;
1651         rte_stats->ibytes   = stats->gorc;
1652         rte_stats->obytes   = stats->gotc;
1653 }
1654
1655 static void
1656 eth_igb_stats_reset(struct rte_eth_dev *dev)
1657 {
1658         struct e1000_hw_stats *hw_stats =
1659                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1660
1661         /* HW registers are cleared on read */
1662         eth_igb_stats_get(dev, NULL);
1663
1664         /* Reset software totals */
1665         memset(hw_stats, 0, sizeof(*hw_stats));
1666 }
1667
1668 static void
1669 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1670 {
1671         struct e1000_hw_stats *stats =
1672                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1673
1674         /* HW registers are cleared on read */
1675         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1676
1677         /* Reset software totals */
1678         memset(stats, 0, sizeof(*stats));
1679 }
1680
1681 static int
1682 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1683                    unsigned n)
1684 {
1685         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1686         struct e1000_hw_stats *hw_stats =
1687                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1688         unsigned i;
1689
1690         if (n < IGB_NB_XSTATS)
1691                 return IGB_NB_XSTATS;
1692
1693         igb_read_stats_registers(hw, hw_stats);
1694
1695         /* If this is a reset xstats is NULL, and we have cleared the
1696          * registers by reading them.
1697          */
1698         if (!xstats)
1699                 return 0;
1700
1701         /* Extended stats */
1702         for (i = 0; i < IGB_NB_XSTATS; i++) {
1703                 snprintf(xstats[i].name, sizeof(xstats[i].name),
1704                          "%s", rte_igb_stats_strings[i].name);
1705                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1706                         rte_igb_stats_strings[i].offset);
1707         }
1708
1709         return IGB_NB_XSTATS;
1710 }
1711
1712 static void
1713 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1714 {
1715         /* Good Rx packets, include VF loopback */
1716         UPDATE_VF_STAT(E1000_VFGPRC,
1717             hw_stats->last_gprc, hw_stats->gprc);
1718
1719         /* Good Rx octets, include VF loopback */
1720         UPDATE_VF_STAT(E1000_VFGORC,
1721             hw_stats->last_gorc, hw_stats->gorc);
1722
1723         /* Good Tx packets, include VF loopback */
1724         UPDATE_VF_STAT(E1000_VFGPTC,
1725             hw_stats->last_gptc, hw_stats->gptc);
1726
1727         /* Good Tx octets, include VF loopback */
1728         UPDATE_VF_STAT(E1000_VFGOTC,
1729             hw_stats->last_gotc, hw_stats->gotc);
1730
1731         /* Rx Multicst packets */
1732         UPDATE_VF_STAT(E1000_VFMPRC,
1733             hw_stats->last_mprc, hw_stats->mprc);
1734
1735         /* Good Rx loopback packets */
1736         UPDATE_VF_STAT(E1000_VFGPRLBC,
1737             hw_stats->last_gprlbc, hw_stats->gprlbc);
1738
1739         /* Good Rx loopback octets */
1740         UPDATE_VF_STAT(E1000_VFGORLBC,
1741             hw_stats->last_gorlbc, hw_stats->gorlbc);
1742
1743         /* Good Tx loopback packets */
1744         UPDATE_VF_STAT(E1000_VFGPTLBC,
1745             hw_stats->last_gptlbc, hw_stats->gptlbc);
1746
1747         /* Good Tx loopback octets */
1748         UPDATE_VF_STAT(E1000_VFGOTLBC,
1749             hw_stats->last_gotlbc, hw_stats->gotlbc);
1750 }
1751
1752 static int
1753 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1754                      unsigned n)
1755 {
1756         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1757         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1758                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1759         unsigned i;
1760
1761         if (n < IGBVF_NB_XSTATS)
1762                 return IGBVF_NB_XSTATS;
1763
1764         igbvf_read_stats_registers(hw, hw_stats);
1765
1766         if (!xstats)
1767                 return 0;
1768
1769         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1770                 snprintf(xstats[i].name, sizeof(xstats[i].name), "%s",
1771                          rte_igbvf_stats_strings[i].name);
1772                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1773                         rte_igbvf_stats_strings[i].offset);
1774         }
1775
1776         return IGBVF_NB_XSTATS;
1777 }
1778
1779 static void
1780 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1781 {
1782         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1783         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1784                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1785
1786         igbvf_read_stats_registers(hw, hw_stats);
1787
1788         if (rte_stats == NULL)
1789                 return;
1790
1791         rte_stats->ipackets = hw_stats->gprc;
1792         rte_stats->ibytes = hw_stats->gorc;
1793         rte_stats->opackets = hw_stats->gptc;
1794         rte_stats->obytes = hw_stats->gotc;
1795         rte_stats->imcasts = hw_stats->mprc;
1796         rte_stats->ilbpackets = hw_stats->gprlbc;
1797         rte_stats->ilbbytes = hw_stats->gorlbc;
1798         rte_stats->olbpackets = hw_stats->gptlbc;
1799         rte_stats->olbbytes = hw_stats->gotlbc;
1800 }
1801
1802 static void
1803 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1804 {
1805         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1806                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1807
1808         /* Sync HW register to the last stats */
1809         eth_igbvf_stats_get(dev, NULL);
1810
1811         /* reset HW current stats*/
1812         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1813                offsetof(struct e1000_vf_stats, gprc));
1814 }
1815
1816 static void
1817 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1818 {
1819         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1820
1821         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1822         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1823         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1824         dev_info->rx_offload_capa =
1825                 DEV_RX_OFFLOAD_VLAN_STRIP |
1826                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1827                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1828                 DEV_RX_OFFLOAD_TCP_CKSUM;
1829         dev_info->tx_offload_capa =
1830                 DEV_TX_OFFLOAD_VLAN_INSERT |
1831                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1832                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1833                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1834                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1835                 DEV_TX_OFFLOAD_TCP_TSO;
1836
1837         switch (hw->mac.type) {
1838         case e1000_82575:
1839                 dev_info->max_rx_queues = 4;
1840                 dev_info->max_tx_queues = 4;
1841                 dev_info->max_vmdq_pools = 0;
1842                 break;
1843
1844         case e1000_82576:
1845                 dev_info->max_rx_queues = 16;
1846                 dev_info->max_tx_queues = 16;
1847                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1848                 dev_info->vmdq_queue_num = 16;
1849                 break;
1850
1851         case e1000_82580:
1852                 dev_info->max_rx_queues = 8;
1853                 dev_info->max_tx_queues = 8;
1854                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1855                 dev_info->vmdq_queue_num = 8;
1856                 break;
1857
1858         case e1000_i350:
1859                 dev_info->max_rx_queues = 8;
1860                 dev_info->max_tx_queues = 8;
1861                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1862                 dev_info->vmdq_queue_num = 8;
1863                 break;
1864
1865         case e1000_i354:
1866                 dev_info->max_rx_queues = 8;
1867                 dev_info->max_tx_queues = 8;
1868                 break;
1869
1870         case e1000_i210:
1871                 dev_info->max_rx_queues = 4;
1872                 dev_info->max_tx_queues = 4;
1873                 dev_info->max_vmdq_pools = 0;
1874                 break;
1875
1876         case e1000_i211:
1877                 dev_info->max_rx_queues = 2;
1878                 dev_info->max_tx_queues = 2;
1879                 dev_info->max_vmdq_pools = 0;
1880                 break;
1881
1882         default:
1883                 /* Should not happen */
1884                 break;
1885         }
1886         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
1887         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
1888         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
1889
1890         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1891                 .rx_thresh = {
1892                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1893                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1894                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1895                 },
1896                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1897                 .rx_drop_en = 0,
1898         };
1899
1900         dev_info->default_txconf = (struct rte_eth_txconf) {
1901                 .tx_thresh = {
1902                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1903                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1904                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1905                 },
1906                 .txq_flags = 0,
1907         };
1908
1909         dev_info->rx_desc_lim = rx_desc_lim;
1910         dev_info->tx_desc_lim = tx_desc_lim;
1911 }
1912
1913 static void
1914 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1915 {
1916         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1917
1918         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1919         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1920         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1921         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
1922                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1923                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1924                                 DEV_RX_OFFLOAD_TCP_CKSUM;
1925         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
1926                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1927                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1928                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1929                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1930                                 DEV_TX_OFFLOAD_TCP_TSO;
1931         switch (hw->mac.type) {
1932         case e1000_vfadapt:
1933                 dev_info->max_rx_queues = 2;
1934                 dev_info->max_tx_queues = 2;
1935                 break;
1936         case e1000_vfadapt_i350:
1937                 dev_info->max_rx_queues = 1;
1938                 dev_info->max_tx_queues = 1;
1939                 break;
1940         default:
1941                 /* Should not happen */
1942                 break;
1943         }
1944
1945         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1946                 .rx_thresh = {
1947                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1948                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1949                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1950                 },
1951                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1952                 .rx_drop_en = 0,
1953         };
1954
1955         dev_info->default_txconf = (struct rte_eth_txconf) {
1956                 .tx_thresh = {
1957                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1958                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1959                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1960                 },
1961                 .txq_flags = 0,
1962         };
1963
1964         dev_info->rx_desc_lim = rx_desc_lim;
1965         dev_info->tx_desc_lim = tx_desc_lim;
1966 }
1967
1968 /* return 0 means link status changed, -1 means not changed */
1969 static int
1970 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1971 {
1972         struct e1000_hw *hw =
1973                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1974         struct rte_eth_link link, old;
1975         int link_check, count;
1976
1977         link_check = 0;
1978         hw->mac.get_link_status = 1;
1979
1980         /* possible wait-to-complete in up to 9 seconds */
1981         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1982                 /* Read the real link status */
1983                 switch (hw->phy.media_type) {
1984                 case e1000_media_type_copper:
1985                         /* Do the work to read phy */
1986                         e1000_check_for_link(hw);
1987                         link_check = !hw->mac.get_link_status;
1988                         break;
1989
1990                 case e1000_media_type_fiber:
1991                         e1000_check_for_link(hw);
1992                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1993                                       E1000_STATUS_LU);
1994                         break;
1995
1996                 case e1000_media_type_internal_serdes:
1997                         e1000_check_for_link(hw);
1998                         link_check = hw->mac.serdes_has_link;
1999                         break;
2000
2001                 /* VF device is type_unknown */
2002                 case e1000_media_type_unknown:
2003                         eth_igbvf_link_update(hw);
2004                         link_check = !hw->mac.get_link_status;
2005                         break;
2006
2007                 default:
2008                         break;
2009                 }
2010                 if (link_check || wait_to_complete == 0)
2011                         break;
2012                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2013         }
2014         memset(&link, 0, sizeof(link));
2015         rte_igb_dev_atomic_read_link_status(dev, &link);
2016         old = link;
2017
2018         /* Now we check if a transition has happened */
2019         if (link_check) {
2020                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
2021                                           &link.link_duplex);
2022                 link.link_status = 1;
2023         } else if (!link_check) {
2024                 link.link_speed = 0;
2025                 link.link_duplex = 0;
2026                 link.link_status = 0;
2027         }
2028         rte_igb_dev_atomic_write_link_status(dev, &link);
2029
2030         /* not changed */
2031         if (old.link_status == link.link_status)
2032                 return -1;
2033
2034         /* changed */
2035         return 0;
2036 }
2037
2038 /*
2039  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2040  * For ASF and Pass Through versions of f/w this means
2041  * that the driver is loaded.
2042  */
2043 static void
2044 igb_hw_control_acquire(struct e1000_hw *hw)
2045 {
2046         uint32_t ctrl_ext;
2047
2048         /* Let firmware know the driver has taken over */
2049         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2050         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2051 }
2052
2053 /*
2054  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2055  * For ASF and Pass Through versions of f/w this means that the
2056  * driver is no longer loaded.
2057  */
2058 static void
2059 igb_hw_control_release(struct e1000_hw *hw)
2060 {
2061         uint32_t ctrl_ext;
2062
2063         /* Let firmware taken over control of h/w */
2064         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2065         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2066                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2067 }
2068
2069 /*
2070  * Bit of a misnomer, what this really means is
2071  * to enable OS management of the system... aka
2072  * to disable special hardware management features.
2073  */
2074 static void
2075 igb_init_manageability(struct e1000_hw *hw)
2076 {
2077         if (e1000_enable_mng_pass_thru(hw)) {
2078                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2079                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2080
2081                 /* disable hardware interception of ARP */
2082                 manc &= ~(E1000_MANC_ARP_EN);
2083
2084                 /* enable receiving management packets to the host */
2085                 manc |= E1000_MANC_EN_MNG2HOST;
2086                 manc2h |= 1 << 5;  /* Mng Port 623 */
2087                 manc2h |= 1 << 6;  /* Mng Port 664 */
2088                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2089                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2090         }
2091 }
2092
2093 static void
2094 igb_release_manageability(struct e1000_hw *hw)
2095 {
2096         if (e1000_enable_mng_pass_thru(hw)) {
2097                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2098
2099                 manc |= E1000_MANC_ARP_EN;
2100                 manc &= ~E1000_MANC_EN_MNG2HOST;
2101
2102                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2103         }
2104 }
2105
2106 static void
2107 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2108 {
2109         struct e1000_hw *hw =
2110                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2111         uint32_t rctl;
2112
2113         rctl = E1000_READ_REG(hw, E1000_RCTL);
2114         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2115         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2116 }
2117
2118 static void
2119 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2120 {
2121         struct e1000_hw *hw =
2122                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2123         uint32_t rctl;
2124
2125         rctl = E1000_READ_REG(hw, E1000_RCTL);
2126         rctl &= (~E1000_RCTL_UPE);
2127         if (dev->data->all_multicast == 1)
2128                 rctl |= E1000_RCTL_MPE;
2129         else
2130                 rctl &= (~E1000_RCTL_MPE);
2131         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2132 }
2133
2134 static void
2135 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2136 {
2137         struct e1000_hw *hw =
2138                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2139         uint32_t rctl;
2140
2141         rctl = E1000_READ_REG(hw, E1000_RCTL);
2142         rctl |= E1000_RCTL_MPE;
2143         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2144 }
2145
2146 static void
2147 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2148 {
2149         struct e1000_hw *hw =
2150                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2151         uint32_t rctl;
2152
2153         if (dev->data->promiscuous == 1)
2154                 return; /* must remain in all_multicast mode */
2155         rctl = E1000_READ_REG(hw, E1000_RCTL);
2156         rctl &= (~E1000_RCTL_MPE);
2157         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2158 }
2159
2160 static int
2161 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2162 {
2163         struct e1000_hw *hw =
2164                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2165         struct e1000_vfta * shadow_vfta =
2166                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2167         uint32_t vfta;
2168         uint32_t vid_idx;
2169         uint32_t vid_bit;
2170
2171         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2172                               E1000_VFTA_ENTRY_MASK);
2173         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2174         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2175         if (on)
2176                 vfta |= vid_bit;
2177         else
2178                 vfta &= ~vid_bit;
2179         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2180
2181         /* update local VFTA copy */
2182         shadow_vfta->vfta[vid_idx] = vfta;
2183
2184         return 0;
2185 }
2186
2187 static void
2188 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
2189 {
2190         struct e1000_hw *hw =
2191                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2192         uint32_t reg = ETHER_TYPE_VLAN ;
2193
2194         reg |= (tpid << 16);
2195         E1000_WRITE_REG(hw, E1000_VET, reg);
2196 }
2197
2198 static void
2199 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2200 {
2201         struct e1000_hw *hw =
2202                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2203         uint32_t reg;
2204
2205         /* Filter Table Disable */
2206         reg = E1000_READ_REG(hw, E1000_RCTL);
2207         reg &= ~E1000_RCTL_CFIEN;
2208         reg &= ~E1000_RCTL_VFE;
2209         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2210 }
2211
2212 static void
2213 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2214 {
2215         struct e1000_hw *hw =
2216                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2217         struct e1000_vfta * shadow_vfta =
2218                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2219         uint32_t reg;
2220         int i;
2221
2222         /* Filter Table Enable, CFI not used for packet acceptance */
2223         reg = E1000_READ_REG(hw, E1000_RCTL);
2224         reg &= ~E1000_RCTL_CFIEN;
2225         reg |= E1000_RCTL_VFE;
2226         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2227
2228         /* restore VFTA table */
2229         for (i = 0; i < IGB_VFTA_SIZE; i++)
2230                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2231 }
2232
2233 static void
2234 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2235 {
2236         struct e1000_hw *hw =
2237                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2238         uint32_t reg;
2239
2240         /* VLAN Mode Disable */
2241         reg = E1000_READ_REG(hw, E1000_CTRL);
2242         reg &= ~E1000_CTRL_VME;
2243         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2244 }
2245
2246 static void
2247 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2248 {
2249         struct e1000_hw *hw =
2250                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2251         uint32_t reg;
2252
2253         /* VLAN Mode Enable */
2254         reg = E1000_READ_REG(hw, E1000_CTRL);
2255         reg |= E1000_CTRL_VME;
2256         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2257 }
2258
2259 static void
2260 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2261 {
2262         struct e1000_hw *hw =
2263                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2264         uint32_t reg;
2265
2266         /* CTRL_EXT: Extended VLAN */
2267         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2268         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2269         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2270
2271         /* Update maximum packet length */
2272         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2273                 E1000_WRITE_REG(hw, E1000_RLPML,
2274                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2275                                                 VLAN_TAG_SIZE);
2276 }
2277
2278 static void
2279 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2280 {
2281         struct e1000_hw *hw =
2282                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2283         uint32_t reg;
2284
2285         /* CTRL_EXT: Extended VLAN */
2286         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2287         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2288         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2289
2290         /* Update maximum packet length */
2291         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2292                 E1000_WRITE_REG(hw, E1000_RLPML,
2293                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2294                                                 2 * VLAN_TAG_SIZE);
2295 }
2296
2297 static void
2298 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2299 {
2300         if(mask & ETH_VLAN_STRIP_MASK){
2301                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2302                         igb_vlan_hw_strip_enable(dev);
2303                 else
2304                         igb_vlan_hw_strip_disable(dev);
2305         }
2306
2307         if(mask & ETH_VLAN_FILTER_MASK){
2308                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2309                         igb_vlan_hw_filter_enable(dev);
2310                 else
2311                         igb_vlan_hw_filter_disable(dev);
2312         }
2313
2314         if(mask & ETH_VLAN_EXTEND_MASK){
2315                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2316                         igb_vlan_hw_extend_enable(dev);
2317                 else
2318                         igb_vlan_hw_extend_disable(dev);
2319         }
2320 }
2321
2322
2323 /**
2324  * It enables the interrupt mask and then enable the interrupt.
2325  *
2326  * @param dev
2327  *  Pointer to struct rte_eth_dev.
2328  *
2329  * @return
2330  *  - On success, zero.
2331  *  - On failure, a negative value.
2332  */
2333 static int
2334 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2335 {
2336         struct e1000_interrupt *intr =
2337                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2338
2339         intr->mask |= E1000_ICR_LSC;
2340
2341         return 0;
2342 }
2343
2344 /* It clears the interrupt causes and enables the interrupt.
2345  * It will be called once only during nic initialized.
2346  *
2347  * @param dev
2348  *  Pointer to struct rte_eth_dev.
2349  *
2350  * @return
2351  *  - On success, zero.
2352  *  - On failure, a negative value.
2353  */
2354 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2355 {
2356         uint32_t mask, regval;
2357         struct e1000_hw *hw =
2358                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2359         struct rte_eth_dev_info dev_info;
2360
2361         memset(&dev_info, 0, sizeof(dev_info));
2362         eth_igb_infos_get(dev, &dev_info);
2363
2364         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2365         regval = E1000_READ_REG(hw, E1000_EIMS);
2366         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2367
2368         return 0;
2369 }
2370
2371 /*
2372  * It reads ICR and gets interrupt causes, check it and set a bit flag
2373  * to update link status.
2374  *
2375  * @param dev
2376  *  Pointer to struct rte_eth_dev.
2377  *
2378  * @return
2379  *  - On success, zero.
2380  *  - On failure, a negative value.
2381  */
2382 static int
2383 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2384 {
2385         uint32_t icr;
2386         struct e1000_hw *hw =
2387                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2388         struct e1000_interrupt *intr =
2389                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2390
2391         igb_intr_disable(hw);
2392
2393         /* read-on-clear nic registers here */
2394         icr = E1000_READ_REG(hw, E1000_ICR);
2395
2396         intr->flags = 0;
2397         if (icr & E1000_ICR_LSC) {
2398                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2399         }
2400
2401         if (icr & E1000_ICR_VMMB)
2402                 intr->flags |= E1000_FLAG_MAILBOX;
2403
2404         return 0;
2405 }
2406
2407 /*
2408  * It executes link_update after knowing an interrupt is prsent.
2409  *
2410  * @param dev
2411  *  Pointer to struct rte_eth_dev.
2412  *
2413  * @return
2414  *  - On success, zero.
2415  *  - On failure, a negative value.
2416  */
2417 static int
2418 eth_igb_interrupt_action(struct rte_eth_dev *dev)
2419 {
2420         struct e1000_hw *hw =
2421                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2422         struct e1000_interrupt *intr =
2423                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2424         uint32_t tctl, rctl;
2425         struct rte_eth_link link;
2426         int ret;
2427
2428         if (intr->flags & E1000_FLAG_MAILBOX) {
2429                 igb_pf_mbx_process(dev);
2430                 intr->flags &= ~E1000_FLAG_MAILBOX;
2431         }
2432
2433         igb_intr_enable(dev);
2434         rte_intr_enable(&(dev->pci_dev->intr_handle));
2435
2436         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2437                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2438
2439                 /* set get_link_status to check register later */
2440                 hw->mac.get_link_status = 1;
2441                 ret = eth_igb_link_update(dev, 0);
2442
2443                 /* check if link has changed */
2444                 if (ret < 0)
2445                         return 0;
2446
2447                 memset(&link, 0, sizeof(link));
2448                 rte_igb_dev_atomic_read_link_status(dev, &link);
2449                 if (link.link_status) {
2450                         PMD_INIT_LOG(INFO,
2451                                      " Port %d: Link Up - speed %u Mbps - %s",
2452                                      dev->data->port_id,
2453                                      (unsigned)link.link_speed,
2454                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2455                                      "full-duplex" : "half-duplex");
2456                 } else {
2457                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2458                                      dev->data->port_id);
2459                 }
2460
2461                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2462                              dev->pci_dev->addr.domain,
2463                              dev->pci_dev->addr.bus,
2464                              dev->pci_dev->addr.devid,
2465                              dev->pci_dev->addr.function);
2466                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2467                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2468                 if (link.link_status) {
2469                         /* enable Tx/Rx */
2470                         tctl |= E1000_TCTL_EN;
2471                         rctl |= E1000_RCTL_EN;
2472                 } else {
2473                         /* disable Tx/Rx */
2474                         tctl &= ~E1000_TCTL_EN;
2475                         rctl &= ~E1000_RCTL_EN;
2476                 }
2477                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2478                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2479                 E1000_WRITE_FLUSH(hw);
2480                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2481         }
2482
2483         return 0;
2484 }
2485
2486 /**
2487  * Interrupt handler which shall be registered at first.
2488  *
2489  * @param handle
2490  *  Pointer to interrupt handle.
2491  * @param param
2492  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2493  *
2494  * @return
2495  *  void
2496  */
2497 static void
2498 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2499                                                         void *param)
2500 {
2501         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2502
2503         eth_igb_interrupt_get_status(dev);
2504         eth_igb_interrupt_action(dev);
2505 }
2506
2507 static int
2508 eth_igb_led_on(struct rte_eth_dev *dev)
2509 {
2510         struct e1000_hw *hw;
2511
2512         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2513         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2514 }
2515
2516 static int
2517 eth_igb_led_off(struct rte_eth_dev *dev)
2518 {
2519         struct e1000_hw *hw;
2520
2521         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2522         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2523 }
2524
2525 static int
2526 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2527 {
2528         struct e1000_hw *hw;
2529         uint32_t ctrl;
2530         int tx_pause;
2531         int rx_pause;
2532
2533         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2534         fc_conf->pause_time = hw->fc.pause_time;
2535         fc_conf->high_water = hw->fc.high_water;
2536         fc_conf->low_water = hw->fc.low_water;
2537         fc_conf->send_xon = hw->fc.send_xon;
2538         fc_conf->autoneg = hw->mac.autoneg;
2539
2540         /*
2541          * Return rx_pause and tx_pause status according to actual setting of
2542          * the TFCE and RFCE bits in the CTRL register.
2543          */
2544         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2545         if (ctrl & E1000_CTRL_TFCE)
2546                 tx_pause = 1;
2547         else
2548                 tx_pause = 0;
2549
2550         if (ctrl & E1000_CTRL_RFCE)
2551                 rx_pause = 1;
2552         else
2553                 rx_pause = 0;
2554
2555         if (rx_pause && tx_pause)
2556                 fc_conf->mode = RTE_FC_FULL;
2557         else if (rx_pause)
2558                 fc_conf->mode = RTE_FC_RX_PAUSE;
2559         else if (tx_pause)
2560                 fc_conf->mode = RTE_FC_TX_PAUSE;
2561         else
2562                 fc_conf->mode = RTE_FC_NONE;
2563
2564         return 0;
2565 }
2566
2567 static int
2568 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2569 {
2570         struct e1000_hw *hw;
2571         int err;
2572         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2573                 e1000_fc_none,
2574                 e1000_fc_rx_pause,
2575                 e1000_fc_tx_pause,
2576                 e1000_fc_full
2577         };
2578         uint32_t rx_buf_size;
2579         uint32_t max_high_water;
2580         uint32_t rctl;
2581
2582         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2583         if (fc_conf->autoneg != hw->mac.autoneg)
2584                 return -ENOTSUP;
2585         rx_buf_size = igb_get_rx_buffer_size(hw);
2586         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2587
2588         /* At least reserve one Ethernet frame for watermark */
2589         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2590         if ((fc_conf->high_water > max_high_water) ||
2591             (fc_conf->high_water < fc_conf->low_water)) {
2592                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2593                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2594                 return -EINVAL;
2595         }
2596
2597         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2598         hw->fc.pause_time     = fc_conf->pause_time;
2599         hw->fc.high_water     = fc_conf->high_water;
2600         hw->fc.low_water      = fc_conf->low_water;
2601         hw->fc.send_xon       = fc_conf->send_xon;
2602
2603         err = e1000_setup_link_generic(hw);
2604         if (err == E1000_SUCCESS) {
2605
2606                 /* check if we want to forward MAC frames - driver doesn't have native
2607                  * capability to do that, so we'll write the registers ourselves */
2608
2609                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2610
2611                 /* set or clear MFLCN.PMCF bit depending on configuration */
2612                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2613                         rctl |= E1000_RCTL_PMCF;
2614                 else
2615                         rctl &= ~E1000_RCTL_PMCF;
2616
2617                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2618                 E1000_WRITE_FLUSH(hw);
2619
2620                 return 0;
2621         }
2622
2623         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2624         return -EIO;
2625 }
2626
2627 #define E1000_RAH_POOLSEL_SHIFT      (18)
2628 static void
2629 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2630                 uint32_t index, __rte_unused uint32_t pool)
2631 {
2632         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2633         uint32_t rah;
2634
2635         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2636         rah = E1000_READ_REG(hw, E1000_RAH(index));
2637         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2638         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2639 }
2640
2641 static void
2642 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2643 {
2644         uint8_t addr[ETHER_ADDR_LEN];
2645         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2646
2647         memset(addr, 0, sizeof(addr));
2648
2649         e1000_rar_set(hw, addr, index);
2650 }
2651
2652 static void
2653 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2654                                 struct ether_addr *addr)
2655 {
2656         eth_igb_rar_clear(dev, 0);
2657
2658         eth_igb_rar_set(dev, (void *)addr, 0, 0);
2659 }
2660 /*
2661  * Virtual Function operations
2662  */
2663 static void
2664 igbvf_intr_disable(struct e1000_hw *hw)
2665 {
2666         PMD_INIT_FUNC_TRACE();
2667
2668         /* Clear interrupt mask to stop from interrupts being generated */
2669         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2670
2671         E1000_WRITE_FLUSH(hw);
2672 }
2673
2674 static void
2675 igbvf_stop_adapter(struct rte_eth_dev *dev)
2676 {
2677         u32 reg_val;
2678         u16 i;
2679         struct rte_eth_dev_info dev_info;
2680         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2681
2682         memset(&dev_info, 0, sizeof(dev_info));
2683         eth_igbvf_infos_get(dev, &dev_info);
2684
2685         /* Clear interrupt mask to stop from interrupts being generated */
2686         igbvf_intr_disable(hw);
2687
2688         /* Clear any pending interrupts, flush previous writes */
2689         E1000_READ_REG(hw, E1000_EICR);
2690
2691         /* Disable the transmit unit.  Each queue must be disabled. */
2692         for (i = 0; i < dev_info.max_tx_queues; i++)
2693                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2694
2695         /* Disable the receive unit by stopping each queue */
2696         for (i = 0; i < dev_info.max_rx_queues; i++) {
2697                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2698                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2699                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2700                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2701                         ;
2702         }
2703
2704         /* flush all queues disables */
2705         E1000_WRITE_FLUSH(hw);
2706         msec_delay(2);
2707 }
2708
2709 static int eth_igbvf_link_update(struct e1000_hw *hw)
2710 {
2711         struct e1000_mbx_info *mbx = &hw->mbx;
2712         struct e1000_mac_info *mac = &hw->mac;
2713         int ret_val = E1000_SUCCESS;
2714
2715         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2716
2717         /*
2718          * We only want to run this if there has been a rst asserted.
2719          * in this case that could mean a link change, device reset,
2720          * or a virtual function reset
2721          */
2722
2723         /* If we were hit with a reset or timeout drop the link */
2724         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2725                 mac->get_link_status = TRUE;
2726
2727         if (!mac->get_link_status)
2728                 goto out;
2729
2730         /* if link status is down no point in checking to see if pf is up */
2731         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2732                 goto out;
2733
2734         /* if we passed all the tests above then the link is up and we no
2735          * longer need to check for link */
2736         mac->get_link_status = FALSE;
2737
2738 out:
2739         return ret_val;
2740 }
2741
2742
2743 static int
2744 igbvf_dev_configure(struct rte_eth_dev *dev)
2745 {
2746         struct rte_eth_conf* conf = &dev->data->dev_conf;
2747
2748         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2749                      dev->data->port_id);
2750
2751         /*
2752          * VF has no ability to enable/disable HW CRC
2753          * Keep the persistent behavior the same as Host PF
2754          */
2755 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2756         if (!conf->rxmode.hw_strip_crc) {
2757                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
2758                 conf->rxmode.hw_strip_crc = 1;
2759         }
2760 #else
2761         if (conf->rxmode.hw_strip_crc) {
2762                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
2763                 conf->rxmode.hw_strip_crc = 0;
2764         }
2765 #endif
2766
2767         return 0;
2768 }
2769
2770 static int
2771 igbvf_dev_start(struct rte_eth_dev *dev)
2772 {
2773         struct e1000_hw *hw =
2774                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2775         struct e1000_adapter *adapter =
2776                 E1000_DEV_PRIVATE(dev->data->dev_private);
2777         int ret;
2778
2779         PMD_INIT_FUNC_TRACE();
2780
2781         hw->mac.ops.reset_hw(hw);
2782         adapter->stopped = 0;
2783
2784         /* Set all vfta */
2785         igbvf_set_vfta_all(dev,1);
2786
2787         eth_igbvf_tx_init(dev);
2788
2789         /* This can fail when allocating mbufs for descriptor rings */
2790         ret = eth_igbvf_rx_init(dev);
2791         if (ret) {
2792                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2793                 igb_dev_clear_queues(dev);
2794                 return ret;
2795         }
2796
2797         return 0;
2798 }
2799
2800 static void
2801 igbvf_dev_stop(struct rte_eth_dev *dev)
2802 {
2803         PMD_INIT_FUNC_TRACE();
2804
2805         igbvf_stop_adapter(dev);
2806
2807         /*
2808           * Clear what we set, but we still keep shadow_vfta to
2809           * restore after device starts
2810           */
2811         igbvf_set_vfta_all(dev,0);
2812
2813         igb_dev_clear_queues(dev);
2814 }
2815
2816 static void
2817 igbvf_dev_close(struct rte_eth_dev *dev)
2818 {
2819         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2820         struct e1000_adapter *adapter =
2821                 E1000_DEV_PRIVATE(dev->data->dev_private);
2822
2823         PMD_INIT_FUNC_TRACE();
2824
2825         e1000_reset_hw(hw);
2826
2827         igbvf_dev_stop(dev);
2828         adapter->stopped = 1;
2829         igb_dev_free_queues(dev);
2830 }
2831
2832 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2833 {
2834         struct e1000_mbx_info *mbx = &hw->mbx;
2835         uint32_t msgbuf[2];
2836         s32 err;
2837
2838         /* After set vlan, vlan strip will also be enabled in igb driver*/
2839         msgbuf[0] = E1000_VF_SET_VLAN;
2840         msgbuf[1] = vid;
2841         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2842         if (on)
2843                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2844
2845         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
2846         if (err)
2847                 goto mbx_err;
2848
2849         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
2850         if (err)
2851                 goto mbx_err;
2852
2853         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
2854         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
2855                 err = -EINVAL;
2856
2857 mbx_err:
2858         return err;
2859 }
2860
2861 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2862 {
2863         struct e1000_hw *hw =
2864                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2865         struct e1000_vfta * shadow_vfta =
2866                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2867         int i = 0, j = 0, vfta = 0, mask = 1;
2868
2869         for (i = 0; i < IGB_VFTA_SIZE; i++){
2870                 vfta = shadow_vfta->vfta[i];
2871                 if(vfta){
2872                         mask = 1;
2873                         for (j = 0; j < 32; j++){
2874                                 if(vfta & mask)
2875                                         igbvf_set_vfta(hw,
2876                                                 (uint16_t)((i<<5)+j), on);
2877                                 mask<<=1;
2878                         }
2879                 }
2880         }
2881
2882 }
2883
2884 static int
2885 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2886 {
2887         struct e1000_hw *hw =
2888                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2889         struct e1000_vfta * shadow_vfta =
2890                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2891         uint32_t vid_idx = 0;
2892         uint32_t vid_bit = 0;
2893         int ret = 0;
2894
2895         PMD_INIT_FUNC_TRACE();
2896
2897         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2898         ret = igbvf_set_vfta(hw, vlan_id, !!on);
2899         if(ret){
2900                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2901                 return ret;
2902         }
2903         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2904         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2905
2906         /*Save what we set and retore it after device reset*/
2907         if (on)
2908                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2909         else
2910                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2911
2912         return 0;
2913 }
2914
2915 static void
2916 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
2917 {
2918         struct e1000_hw *hw =
2919                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2920
2921         /* index is not used by rar_set() */
2922         hw->mac.ops.rar_set(hw, (void *)addr, 0);
2923 }
2924
2925
2926 static int
2927 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2928                         struct rte_eth_rss_reta_entry64 *reta_conf,
2929                         uint16_t reta_size)
2930 {
2931         uint8_t i, j, mask;
2932         uint32_t reta, r;
2933         uint16_t idx, shift;
2934         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2935
2936         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2937                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2938                         "(%d) doesn't match the number hardware can supported "
2939                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2940                 return -EINVAL;
2941         }
2942
2943         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2944                 idx = i / RTE_RETA_GROUP_SIZE;
2945                 shift = i % RTE_RETA_GROUP_SIZE;
2946                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2947                                                 IGB_4_BIT_MASK);
2948                 if (!mask)
2949                         continue;
2950                 if (mask == IGB_4_BIT_MASK)
2951                         r = 0;
2952                 else
2953                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2954                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
2955                         if (mask & (0x1 << j))
2956                                 reta |= reta_conf[idx].reta[shift + j] <<
2957                                                         (CHAR_BIT * j);
2958                         else
2959                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
2960                 }
2961                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2962         }
2963
2964         return 0;
2965 }
2966
2967 static int
2968 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2969                        struct rte_eth_rss_reta_entry64 *reta_conf,
2970                        uint16_t reta_size)
2971 {
2972         uint8_t i, j, mask;
2973         uint32_t reta;
2974         uint16_t idx, shift;
2975         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2976
2977         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2978                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2979                         "(%d) doesn't match the number hardware can supported "
2980                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2981                 return -EINVAL;
2982         }
2983
2984         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2985                 idx = i / RTE_RETA_GROUP_SIZE;
2986                 shift = i % RTE_RETA_GROUP_SIZE;
2987                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2988                                                 IGB_4_BIT_MASK);
2989                 if (!mask)
2990                         continue;
2991                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2992                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
2993                         if (mask & (0x1 << j))
2994                                 reta_conf[idx].reta[shift + j] =
2995                                         ((reta >> (CHAR_BIT * j)) &
2996                                                 IGB_8_BIT_MASK);
2997                 }
2998         }
2999
3000         return 0;
3001 }
3002
3003 #define MAC_TYPE_FILTER_SUP(type)    do {\
3004         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3005                 (type) != e1000_82576)\
3006                 return -ENOTSUP;\
3007 } while (0)
3008
3009 static int
3010 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3011                         struct rte_eth_syn_filter *filter,
3012                         bool add)
3013 {
3014         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3015         uint32_t synqf, rfctl;
3016
3017         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3018                 return -EINVAL;
3019
3020         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3021
3022         if (add) {
3023                 if (synqf & E1000_SYN_FILTER_ENABLE)
3024                         return -EINVAL;
3025
3026                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3027                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3028
3029                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3030                 if (filter->hig_pri)
3031                         rfctl |= E1000_RFCTL_SYNQFP;
3032                 else
3033                         rfctl &= ~E1000_RFCTL_SYNQFP;
3034
3035                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3036         } else {
3037                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3038                         return -ENOENT;
3039                 synqf = 0;
3040         }
3041
3042         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3043         E1000_WRITE_FLUSH(hw);
3044         return 0;
3045 }
3046
3047 static int
3048 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3049                         struct rte_eth_syn_filter *filter)
3050 {
3051         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3052         uint32_t synqf, rfctl;
3053
3054         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3055         if (synqf & E1000_SYN_FILTER_ENABLE) {
3056                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3057                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3058                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3059                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3060                 return 0;
3061         }
3062
3063         return -ENOENT;
3064 }
3065
3066 static int
3067 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3068                         enum rte_filter_op filter_op,
3069                         void *arg)
3070 {
3071         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3072         int ret;
3073
3074         MAC_TYPE_FILTER_SUP(hw->mac.type);
3075
3076         if (filter_op == RTE_ETH_FILTER_NOP)
3077                 return 0;
3078
3079         if (arg == NULL) {
3080                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3081                             filter_op);
3082                 return -EINVAL;
3083         }
3084
3085         switch (filter_op) {
3086         case RTE_ETH_FILTER_ADD:
3087                 ret = eth_igb_syn_filter_set(dev,
3088                                 (struct rte_eth_syn_filter *)arg,
3089                                 TRUE);
3090                 break;
3091         case RTE_ETH_FILTER_DELETE:
3092                 ret = eth_igb_syn_filter_set(dev,
3093                                 (struct rte_eth_syn_filter *)arg,
3094                                 FALSE);
3095                 break;
3096         case RTE_ETH_FILTER_GET:
3097                 ret = eth_igb_syn_filter_get(dev,
3098                                 (struct rte_eth_syn_filter *)arg);
3099                 break;
3100         default:
3101                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3102                 ret = -EINVAL;
3103                 break;
3104         }
3105
3106         return ret;
3107 }
3108
3109 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3110         if ((type) != e1000_82580 && (type) != e1000_i350)\
3111                 return -ENOSYS; \
3112 } while (0)
3113
3114 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3115 static inline int
3116 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3117                         struct e1000_2tuple_filter_info *filter_info)
3118 {
3119         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3120                 return -EINVAL;
3121         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3122                 return -EINVAL;  /* filter index is out of range. */
3123         if (filter->tcp_flags > TCP_FLAG_ALL)
3124                 return -EINVAL;  /* flags is invalid. */
3125
3126         switch (filter->dst_port_mask) {
3127         case UINT16_MAX:
3128                 filter_info->dst_port_mask = 0;
3129                 filter_info->dst_port = filter->dst_port;
3130                 break;
3131         case 0:
3132                 filter_info->dst_port_mask = 1;
3133                 break;
3134         default:
3135                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3136                 return -EINVAL;
3137         }
3138
3139         switch (filter->proto_mask) {
3140         case UINT8_MAX:
3141                 filter_info->proto_mask = 0;
3142                 filter_info->proto = filter->proto;
3143                 break;
3144         case 0:
3145                 filter_info->proto_mask = 1;
3146                 break;
3147         default:
3148                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3149                 return -EINVAL;
3150         }
3151
3152         filter_info->priority = (uint8_t)filter->priority;
3153         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3154                 filter_info->tcp_flags = filter->tcp_flags;
3155         else
3156                 filter_info->tcp_flags = 0;
3157
3158         return 0;
3159 }
3160
3161 static inline struct e1000_2tuple_filter *
3162 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3163                         struct e1000_2tuple_filter_info *key)
3164 {
3165         struct e1000_2tuple_filter *it;
3166
3167         TAILQ_FOREACH(it, filter_list, entries) {
3168                 if (memcmp(key, &it->filter_info,
3169                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3170                         return it;
3171                 }
3172         }
3173         return NULL;
3174 }
3175
3176 /*
3177  * igb_add_2tuple_filter - add a 2tuple filter
3178  *
3179  * @param
3180  * dev: Pointer to struct rte_eth_dev.
3181  * ntuple_filter: ponter to the filter that will be added.
3182  *
3183  * @return
3184  *    - On success, zero.
3185  *    - On failure, a negative value.
3186  */
3187 static int
3188 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3189                         struct rte_eth_ntuple_filter *ntuple_filter)
3190 {
3191         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3192         struct e1000_filter_info *filter_info =
3193                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3194         struct e1000_2tuple_filter *filter;
3195         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3196         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3197         int i, ret;
3198
3199         filter = rte_zmalloc("e1000_2tuple_filter",
3200                         sizeof(struct e1000_2tuple_filter), 0);
3201         if (filter == NULL)
3202                 return -ENOMEM;
3203
3204         ret = ntuple_filter_to_2tuple(ntuple_filter,
3205                                       &filter->filter_info);
3206         if (ret < 0) {
3207                 rte_free(filter);
3208                 return ret;
3209         }
3210         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3211                                          &filter->filter_info) != NULL) {
3212                 PMD_DRV_LOG(ERR, "filter exists.");
3213                 rte_free(filter);
3214                 return -EEXIST;
3215         }
3216         filter->queue = ntuple_filter->queue;
3217
3218         /*
3219          * look for an unused 2tuple filter index,
3220          * and insert the filter to list.
3221          */
3222         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3223                 if (!(filter_info->twotuple_mask & (1 << i))) {
3224                         filter_info->twotuple_mask |= 1 << i;
3225                         filter->index = i;
3226                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3227                                           filter,
3228                                           entries);
3229                         break;
3230                 }
3231         }
3232         if (i >= E1000_MAX_TTQF_FILTERS) {
3233                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3234                 rte_free(filter);
3235                 return -ENOSYS;
3236         }
3237
3238         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3239         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3240                 imir |= E1000_IMIR_PORT_BP;
3241         else
3242                 imir &= ~E1000_IMIR_PORT_BP;
3243
3244         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3245
3246         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3247         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3248         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3249         if (filter->filter_info.proto_mask == 0)
3250                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3251
3252         /* tcp flags bits setting. */
3253         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3254                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3255                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3256                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3257                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3258                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3259                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3260                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3261                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3262                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3263                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3264                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3265                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3266         } else
3267                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3268         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3269         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3270         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3271         return 0;
3272 }
3273
3274 /*
3275  * igb_remove_2tuple_filter - remove a 2tuple filter
3276  *
3277  * @param
3278  * dev: Pointer to struct rte_eth_dev.
3279  * ntuple_filter: ponter to the filter that will be removed.
3280  *
3281  * @return
3282  *    - On success, zero.
3283  *    - On failure, a negative value.
3284  */
3285 static int
3286 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3287                         struct rte_eth_ntuple_filter *ntuple_filter)
3288 {
3289         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3290         struct e1000_filter_info *filter_info =
3291                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3292         struct e1000_2tuple_filter_info filter_2tuple;
3293         struct e1000_2tuple_filter *filter;
3294         int ret;
3295
3296         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3297         ret = ntuple_filter_to_2tuple(ntuple_filter,
3298                                       &filter_2tuple);
3299         if (ret < 0)
3300                 return ret;
3301
3302         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3303                                          &filter_2tuple);
3304         if (filter == NULL) {
3305                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3306                 return -ENOENT;
3307         }
3308
3309         filter_info->twotuple_mask &= ~(1 << filter->index);
3310         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3311         rte_free(filter);
3312
3313         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3314         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3315         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3316         return 0;
3317 }
3318
3319 static inline struct e1000_flex_filter *
3320 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3321                         struct e1000_flex_filter_info *key)
3322 {
3323         struct e1000_flex_filter *it;
3324
3325         TAILQ_FOREACH(it, filter_list, entries) {
3326                 if (memcmp(key, &it->filter_info,
3327                         sizeof(struct e1000_flex_filter_info)) == 0)
3328                         return it;
3329         }
3330
3331         return NULL;
3332 }
3333
3334 static int
3335 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3336                         struct rte_eth_flex_filter *filter,
3337                         bool add)
3338 {
3339         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3340         struct e1000_filter_info *filter_info =
3341                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3342         struct e1000_flex_filter *flex_filter, *it;
3343         uint32_t wufc, queueing, mask;
3344         uint32_t reg_off;
3345         uint8_t shift, i, j = 0;
3346
3347         flex_filter = rte_zmalloc("e1000_flex_filter",
3348                         sizeof(struct e1000_flex_filter), 0);
3349         if (flex_filter == NULL)
3350                 return -ENOMEM;
3351
3352         flex_filter->filter_info.len = filter->len;
3353         flex_filter->filter_info.priority = filter->priority;
3354         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3355         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3356                 mask = 0;
3357                 /* reverse bits in flex filter's mask*/
3358                 for (shift = 0; shift < CHAR_BIT; shift++) {
3359                         if (filter->mask[i] & (0x01 << shift))
3360                                 mask |= (0x80 >> shift);
3361                 }
3362                 flex_filter->filter_info.mask[i] = mask;
3363         }
3364
3365         wufc = E1000_READ_REG(hw, E1000_WUFC);
3366         if (flex_filter->index < E1000_MAX_FHFT)
3367                 reg_off = E1000_FHFT(flex_filter->index);
3368         else
3369                 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3370
3371         if (add) {
3372                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3373                                 &flex_filter->filter_info) != NULL) {
3374                         PMD_DRV_LOG(ERR, "filter exists.");
3375                         rte_free(flex_filter);
3376                         return -EEXIST;
3377                 }
3378                 flex_filter->queue = filter->queue;
3379                 /*
3380                  * look for an unused flex filter index
3381                  * and insert the filter into the list.
3382                  */
3383                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3384                         if (!(filter_info->flex_mask & (1 << i))) {
3385                                 filter_info->flex_mask |= 1 << i;
3386                                 flex_filter->index = i;
3387                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3388                                         flex_filter,
3389                                         entries);
3390                                 break;
3391                         }
3392                 }
3393                 if (i >= E1000_MAX_FLEX_FILTERS) {
3394                         PMD_DRV_LOG(ERR, "flex filters are full.");
3395                         rte_free(flex_filter);
3396                         return -ENOSYS;
3397                 }
3398
3399                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3400                                 (E1000_WUFC_FLX0 << flex_filter->index));
3401                 queueing = filter->len |
3402                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3403                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3404                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3405                                 queueing);
3406                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3407                         E1000_WRITE_REG(hw, reg_off,
3408                                         flex_filter->filter_info.dwords[j]);
3409                         reg_off += sizeof(uint32_t);
3410                         E1000_WRITE_REG(hw, reg_off,
3411                                         flex_filter->filter_info.dwords[++j]);
3412                         reg_off += sizeof(uint32_t);
3413                         E1000_WRITE_REG(hw, reg_off,
3414                                 (uint32_t)flex_filter->filter_info.mask[i]);
3415                         reg_off += sizeof(uint32_t) * 2;
3416                         ++j;
3417                 }
3418         } else {
3419                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3420                                 &flex_filter->filter_info);
3421                 if (it == NULL) {
3422                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3423                         rte_free(flex_filter);
3424                         return -ENOENT;
3425                 }
3426
3427                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3428                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3429                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3430                         (~(E1000_WUFC_FLX0 << it->index)));
3431
3432                 filter_info->flex_mask &= ~(1 << it->index);
3433                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3434                 rte_free(it);
3435                 rte_free(flex_filter);
3436         }
3437
3438         return 0;
3439 }
3440
3441 static int
3442 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3443                         struct rte_eth_flex_filter *filter)
3444 {
3445         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3446         struct e1000_filter_info *filter_info =
3447                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3448         struct e1000_flex_filter flex_filter, *it;
3449         uint32_t wufc, queueing, wufc_en = 0;
3450
3451         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3452         flex_filter.filter_info.len = filter->len;
3453         flex_filter.filter_info.priority = filter->priority;
3454         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3455         memcpy(flex_filter.filter_info.mask, filter->mask,
3456                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3457
3458         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3459                                 &flex_filter.filter_info);
3460         if (it == NULL) {
3461                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3462                 return -ENOENT;
3463         }
3464
3465         wufc = E1000_READ_REG(hw, E1000_WUFC);
3466         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3467
3468         if ((wufc & wufc_en) == wufc_en) {
3469                 uint32_t reg_off = 0;
3470                 if (it->index < E1000_MAX_FHFT)
3471                         reg_off = E1000_FHFT(it->index);
3472                 else
3473                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3474
3475                 queueing = E1000_READ_REG(hw,
3476                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3477                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3478                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3479                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
3480                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3481                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3482                 return 0;
3483         }
3484         return -ENOENT;
3485 }
3486
3487 static int
3488 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3489                         enum rte_filter_op filter_op,
3490                         void *arg)
3491 {
3492         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3493         struct rte_eth_flex_filter *filter;
3494         int ret = 0;
3495
3496         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3497
3498         if (filter_op == RTE_ETH_FILTER_NOP)
3499                 return ret;
3500
3501         if (arg == NULL) {
3502                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3503                             filter_op);
3504                 return -EINVAL;
3505         }
3506
3507         filter = (struct rte_eth_flex_filter *)arg;
3508         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3509             || filter->len % sizeof(uint64_t) != 0) {
3510                 PMD_DRV_LOG(ERR, "filter's length is out of range");
3511                 return -EINVAL;
3512         }
3513         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3514                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3515                 return -EINVAL;
3516         }
3517
3518         switch (filter_op) {
3519         case RTE_ETH_FILTER_ADD:
3520                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3521                 break;
3522         case RTE_ETH_FILTER_DELETE:
3523                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3524                 break;
3525         case RTE_ETH_FILTER_GET:
3526                 ret = eth_igb_get_flex_filter(dev, filter);
3527                 break;
3528         default:
3529                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3530                 ret = -EINVAL;
3531                 break;
3532         }
3533
3534         return ret;
3535 }
3536
3537 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3538 static inline int
3539 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3540                         struct e1000_5tuple_filter_info *filter_info)
3541 {
3542         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3543                 return -EINVAL;
3544         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3545                 return -EINVAL;  /* filter index is out of range. */
3546         if (filter->tcp_flags > TCP_FLAG_ALL)
3547                 return -EINVAL;  /* flags is invalid. */
3548
3549         switch (filter->dst_ip_mask) {
3550         case UINT32_MAX:
3551                 filter_info->dst_ip_mask = 0;
3552                 filter_info->dst_ip = filter->dst_ip;
3553                 break;
3554         case 0:
3555                 filter_info->dst_ip_mask = 1;
3556                 break;
3557         default:
3558                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3559                 return -EINVAL;
3560         }
3561
3562         switch (filter->src_ip_mask) {
3563         case UINT32_MAX:
3564                 filter_info->src_ip_mask = 0;
3565                 filter_info->src_ip = filter->src_ip;
3566                 break;
3567         case 0:
3568                 filter_info->src_ip_mask = 1;
3569                 break;
3570         default:
3571                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3572                 return -EINVAL;
3573         }
3574
3575         switch (filter->dst_port_mask) {
3576         case UINT16_MAX:
3577                 filter_info->dst_port_mask = 0;
3578                 filter_info->dst_port = filter->dst_port;
3579                 break;
3580         case 0:
3581                 filter_info->dst_port_mask = 1;
3582                 break;
3583         default:
3584                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3585                 return -EINVAL;
3586         }
3587
3588         switch (filter->src_port_mask) {
3589         case UINT16_MAX:
3590                 filter_info->src_port_mask = 0;
3591                 filter_info->src_port = filter->src_port;
3592                 break;
3593         case 0:
3594                 filter_info->src_port_mask = 1;
3595                 break;
3596         default:
3597                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3598                 return -EINVAL;
3599         }
3600
3601         switch (filter->proto_mask) {
3602         case UINT8_MAX:
3603                 filter_info->proto_mask = 0;
3604                 filter_info->proto = filter->proto;
3605                 break;
3606         case 0:
3607                 filter_info->proto_mask = 1;
3608                 break;
3609         default:
3610                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3611                 return -EINVAL;
3612         }
3613
3614         filter_info->priority = (uint8_t)filter->priority;
3615         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3616                 filter_info->tcp_flags = filter->tcp_flags;
3617         else
3618                 filter_info->tcp_flags = 0;
3619
3620         return 0;
3621 }
3622
3623 static inline struct e1000_5tuple_filter *
3624 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
3625                         struct e1000_5tuple_filter_info *key)
3626 {
3627         struct e1000_5tuple_filter *it;
3628
3629         TAILQ_FOREACH(it, filter_list, entries) {
3630                 if (memcmp(key, &it->filter_info,
3631                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
3632                         return it;
3633                 }
3634         }
3635         return NULL;
3636 }
3637
3638 /*
3639  * igb_add_5tuple_filter_82576 - add a 5tuple filter
3640  *
3641  * @param
3642  * dev: Pointer to struct rte_eth_dev.
3643  * ntuple_filter: ponter to the filter that will be added.
3644  *
3645  * @return
3646  *    - On success, zero.
3647  *    - On failure, a negative value.
3648  */
3649 static int
3650 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
3651                         struct rte_eth_ntuple_filter *ntuple_filter)
3652 {
3653         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3654         struct e1000_filter_info *filter_info =
3655                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3656         struct e1000_5tuple_filter *filter;
3657         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
3658         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3659         uint8_t i;
3660         int ret;
3661
3662         filter = rte_zmalloc("e1000_5tuple_filter",
3663                         sizeof(struct e1000_5tuple_filter), 0);
3664         if (filter == NULL)
3665                 return -ENOMEM;
3666
3667         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3668                                             &filter->filter_info);
3669         if (ret < 0) {
3670                 rte_free(filter);
3671                 return ret;
3672         }
3673
3674         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3675                                          &filter->filter_info) != NULL) {
3676                 PMD_DRV_LOG(ERR, "filter exists.");
3677                 rte_free(filter);
3678                 return -EEXIST;
3679         }
3680         filter->queue = ntuple_filter->queue;
3681
3682         /*
3683          * look for an unused 5tuple filter index,
3684          * and insert the filter to list.
3685          */
3686         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
3687                 if (!(filter_info->fivetuple_mask & (1 << i))) {
3688                         filter_info->fivetuple_mask |= 1 << i;
3689                         filter->index = i;
3690                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3691                                           filter,
3692                                           entries);
3693                         break;
3694                 }
3695         }
3696         if (i >= E1000_MAX_FTQF_FILTERS) {
3697                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3698                 rte_free(filter);
3699                 return -ENOSYS;
3700         }
3701
3702         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
3703         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
3704                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
3705         if (filter->filter_info.dst_ip_mask == 0)
3706                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
3707         if (filter->filter_info.src_port_mask == 0)
3708                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
3709         if (filter->filter_info.proto_mask == 0)
3710                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
3711         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
3712                 E1000_FTQF_QUEUE_MASK;
3713         ftqf |= E1000_FTQF_QUEUE_ENABLE;
3714         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
3715         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
3716         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
3717
3718         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
3719         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
3720
3721         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3722         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3723                 imir |= E1000_IMIR_PORT_BP;
3724         else
3725                 imir &= ~E1000_IMIR_PORT_BP;
3726         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3727
3728         /* tcp flags bits setting. */
3729         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3730                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3731                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3732                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3733                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3734                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3735                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3736                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3737                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3738                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3739                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3740                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3741                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3742         } else
3743                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3744         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3745         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3746         return 0;
3747 }
3748
3749 /*
3750  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
3751  *
3752  * @param
3753  * dev: Pointer to struct rte_eth_dev.
3754  * ntuple_filter: ponter to the filter that will be removed.
3755  *
3756  * @return
3757  *    - On success, zero.
3758  *    - On failure, a negative value.
3759  */
3760 static int
3761 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
3762                                 struct rte_eth_ntuple_filter *ntuple_filter)
3763 {
3764         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3765         struct e1000_filter_info *filter_info =
3766                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3767         struct e1000_5tuple_filter_info filter_5tuple;
3768         struct e1000_5tuple_filter *filter;
3769         int ret;
3770
3771         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
3772         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3773                                             &filter_5tuple);
3774         if (ret < 0)
3775                 return ret;
3776
3777         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3778                                          &filter_5tuple);
3779         if (filter == NULL) {
3780                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3781                 return -ENOENT;
3782         }
3783
3784         filter_info->fivetuple_mask &= ~(1 << filter->index);
3785         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3786         rte_free(filter);
3787
3788         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
3789                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
3790         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
3791         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
3792         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
3793         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3794         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3795         return 0;
3796 }
3797
3798 static int
3799 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3800 {
3801         uint32_t rctl;
3802         struct e1000_hw *hw;
3803         struct rte_eth_dev_info dev_info;
3804         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3805                                      VLAN_TAG_SIZE);
3806
3807         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3808
3809 #ifdef RTE_LIBRTE_82571_SUPPORT
3810         /* XXX: not bigger than max_rx_pktlen */
3811         if (hw->mac.type == e1000_82571)
3812                 return -ENOTSUP;
3813 #endif
3814         eth_igb_infos_get(dev, &dev_info);
3815
3816         /* check that mtu is within the allowed range */
3817         if ((mtu < ETHER_MIN_MTU) ||
3818             (frame_size > dev_info.max_rx_pktlen))
3819                 return -EINVAL;
3820
3821         /* refuse mtu that requires the support of scattered packets when this
3822          * feature has not been enabled before. */
3823         if (!dev->data->scattered_rx &&
3824             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3825                 return -EINVAL;
3826
3827         rctl = E1000_READ_REG(hw, E1000_RCTL);
3828
3829         /* switch to jumbo mode if needed */
3830         if (frame_size > ETHER_MAX_LEN) {
3831                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3832                 rctl |= E1000_RCTL_LPE;
3833         } else {
3834                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3835                 rctl &= ~E1000_RCTL_LPE;
3836         }
3837         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3838
3839         /* update max frame size */
3840         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3841
3842         E1000_WRITE_REG(hw, E1000_RLPML,
3843                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
3844
3845         return 0;
3846 }
3847
3848 /*
3849  * igb_add_del_ntuple_filter - add or delete a ntuple filter
3850  *
3851  * @param
3852  * dev: Pointer to struct rte_eth_dev.
3853  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3854  * add: if true, add filter, if false, remove filter
3855  *
3856  * @return
3857  *    - On success, zero.
3858  *    - On failure, a negative value.
3859  */
3860 static int
3861 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
3862                         struct rte_eth_ntuple_filter *ntuple_filter,
3863                         bool add)
3864 {
3865         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3866         int ret;
3867
3868         switch (ntuple_filter->flags) {
3869         case RTE_5TUPLE_FLAGS:
3870         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3871                 if (hw->mac.type != e1000_82576)
3872                         return -ENOTSUP;
3873                 if (add)
3874                         ret = igb_add_5tuple_filter_82576(dev,
3875                                                           ntuple_filter);
3876                 else
3877                         ret = igb_remove_5tuple_filter_82576(dev,
3878                                                              ntuple_filter);
3879                 break;
3880         case RTE_2TUPLE_FLAGS:
3881         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3882                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3883                         return -ENOTSUP;
3884                 if (add)
3885                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
3886                 else
3887                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
3888                 break;
3889         default:
3890                 ret = -EINVAL;
3891                 break;
3892         }
3893
3894         return ret;
3895 }
3896
3897 /*
3898  * igb_get_ntuple_filter - get a ntuple filter
3899  *
3900  * @param
3901  * dev: Pointer to struct rte_eth_dev.
3902  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3903  *
3904  * @return
3905  *    - On success, zero.
3906  *    - On failure, a negative value.
3907  */
3908 static int
3909 igb_get_ntuple_filter(struct rte_eth_dev *dev,
3910                         struct rte_eth_ntuple_filter *ntuple_filter)
3911 {
3912         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3913         struct e1000_filter_info *filter_info =
3914                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3915         struct e1000_5tuple_filter_info filter_5tuple;
3916         struct e1000_2tuple_filter_info filter_2tuple;
3917         struct e1000_5tuple_filter *p_5tuple_filter;
3918         struct e1000_2tuple_filter *p_2tuple_filter;
3919         int ret;
3920
3921         switch (ntuple_filter->flags) {
3922         case RTE_5TUPLE_FLAGS:
3923         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3924                 if (hw->mac.type != e1000_82576)
3925                         return -ENOTSUP;
3926                 memset(&filter_5tuple,
3927                         0,
3928                         sizeof(struct e1000_5tuple_filter_info));
3929                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3930                                                     &filter_5tuple);
3931                 if (ret < 0)
3932                         return ret;
3933                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
3934                                         &filter_info->fivetuple_list,
3935                                         &filter_5tuple);
3936                 if (p_5tuple_filter == NULL) {
3937                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3938                         return -ENOENT;
3939                 }
3940                 ntuple_filter->queue = p_5tuple_filter->queue;
3941                 break;
3942         case RTE_2TUPLE_FLAGS:
3943         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3944                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3945                         return -ENOTSUP;
3946                 memset(&filter_2tuple,
3947                         0,
3948                         sizeof(struct e1000_2tuple_filter_info));
3949                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
3950                 if (ret < 0)
3951                         return ret;
3952                 p_2tuple_filter = igb_2tuple_filter_lookup(
3953                                         &filter_info->twotuple_list,
3954                                         &filter_2tuple);
3955                 if (p_2tuple_filter == NULL) {
3956                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3957                         return -ENOENT;
3958                 }
3959                 ntuple_filter->queue = p_2tuple_filter->queue;
3960                 break;
3961         default:
3962                 ret = -EINVAL;
3963                 break;
3964         }
3965
3966         return 0;
3967 }
3968
3969 /*
3970  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
3971  * @dev: pointer to rte_eth_dev structure
3972  * @filter_op:operation will be taken.
3973  * @arg: a pointer to specific structure corresponding to the filter_op
3974  */
3975 static int
3976 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
3977                                 enum rte_filter_op filter_op,
3978                                 void *arg)
3979 {
3980         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3981         int ret;
3982
3983         MAC_TYPE_FILTER_SUP(hw->mac.type);
3984
3985         if (filter_op == RTE_ETH_FILTER_NOP)
3986                 return 0;
3987
3988         if (arg == NULL) {
3989                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3990                             filter_op);
3991                 return -EINVAL;
3992         }
3993
3994         switch (filter_op) {
3995         case RTE_ETH_FILTER_ADD:
3996                 ret = igb_add_del_ntuple_filter(dev,
3997                         (struct rte_eth_ntuple_filter *)arg,
3998                         TRUE);
3999                 break;
4000         case RTE_ETH_FILTER_DELETE:
4001                 ret = igb_add_del_ntuple_filter(dev,
4002                         (struct rte_eth_ntuple_filter *)arg,
4003                         FALSE);
4004                 break;
4005         case RTE_ETH_FILTER_GET:
4006                 ret = igb_get_ntuple_filter(dev,
4007                         (struct rte_eth_ntuple_filter *)arg);
4008                 break;
4009         default:
4010                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4011                 ret = -EINVAL;
4012                 break;
4013         }
4014         return ret;
4015 }
4016
4017 static inline int
4018 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4019                         uint16_t ethertype)
4020 {
4021         int i;
4022
4023         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4024                 if (filter_info->ethertype_filters[i] == ethertype &&
4025                     (filter_info->ethertype_mask & (1 << i)))
4026                         return i;
4027         }
4028         return -1;
4029 }
4030
4031 static inline int
4032 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4033                         uint16_t ethertype)
4034 {
4035         int i;
4036
4037         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4038                 if (!(filter_info->ethertype_mask & (1 << i))) {
4039                         filter_info->ethertype_mask |= 1 << i;
4040                         filter_info->ethertype_filters[i] = ethertype;
4041                         return i;
4042                 }
4043         }
4044         return -1;
4045 }
4046
4047 static inline int
4048 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4049                         uint8_t idx)
4050 {
4051         if (idx >= E1000_MAX_ETQF_FILTERS)
4052                 return -1;
4053         filter_info->ethertype_mask &= ~(1 << idx);
4054         filter_info->ethertype_filters[idx] = 0;
4055         return idx;
4056 }
4057
4058
4059 static int
4060 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4061                         struct rte_eth_ethertype_filter *filter,
4062                         bool add)
4063 {
4064         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4065         struct e1000_filter_info *filter_info =
4066                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4067         uint32_t etqf = 0;
4068         int ret;
4069
4070         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4071                 filter->ether_type == ETHER_TYPE_IPv6) {
4072                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4073                         " ethertype filter.", filter->ether_type);
4074                 return -EINVAL;
4075         }
4076
4077         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4078                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4079                 return -EINVAL;
4080         }
4081         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4082                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4083                 return -EINVAL;
4084         }
4085
4086         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4087         if (ret >= 0 && add) {
4088                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4089                             filter->ether_type);
4090                 return -EEXIST;
4091         }
4092         if (ret < 0 && !add) {
4093                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4094                             filter->ether_type);
4095                 return -ENOENT;
4096         }
4097
4098         if (add) {
4099                 ret = igb_ethertype_filter_insert(filter_info,
4100                         filter->ether_type);
4101                 if (ret < 0) {
4102                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4103                         return -ENOSYS;
4104                 }
4105
4106                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4107                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4108                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4109         } else {
4110                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4111                 if (ret < 0)
4112                         return -ENOSYS;
4113         }
4114         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4115         E1000_WRITE_FLUSH(hw);
4116
4117         return 0;
4118 }
4119
4120 static int
4121 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4122                         struct rte_eth_ethertype_filter *filter)
4123 {
4124         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4125         struct e1000_filter_info *filter_info =
4126                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4127         uint32_t etqf;
4128         int ret;
4129
4130         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4131         if (ret < 0) {
4132                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4133                             filter->ether_type);
4134                 return -ENOENT;
4135         }
4136
4137         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4138         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4139                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4140                 filter->flags = 0;
4141                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4142                                 E1000_ETQF_QUEUE_SHIFT;
4143                 return 0;
4144         }
4145
4146         return -ENOENT;
4147 }
4148
4149 /*
4150  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4151  * @dev: pointer to rte_eth_dev structure
4152  * @filter_op:operation will be taken.
4153  * @arg: a pointer to specific structure corresponding to the filter_op
4154  */
4155 static int
4156 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4157                                 enum rte_filter_op filter_op,
4158                                 void *arg)
4159 {
4160         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4161         int ret;
4162
4163         MAC_TYPE_FILTER_SUP(hw->mac.type);
4164
4165         if (filter_op == RTE_ETH_FILTER_NOP)
4166                 return 0;
4167
4168         if (arg == NULL) {
4169                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4170                             filter_op);
4171                 return -EINVAL;
4172         }
4173
4174         switch (filter_op) {
4175         case RTE_ETH_FILTER_ADD:
4176                 ret = igb_add_del_ethertype_filter(dev,
4177                         (struct rte_eth_ethertype_filter *)arg,
4178                         TRUE);
4179                 break;
4180         case RTE_ETH_FILTER_DELETE:
4181                 ret = igb_add_del_ethertype_filter(dev,
4182                         (struct rte_eth_ethertype_filter *)arg,
4183                         FALSE);
4184                 break;
4185         case RTE_ETH_FILTER_GET:
4186                 ret = igb_get_ethertype_filter(dev,
4187                         (struct rte_eth_ethertype_filter *)arg);
4188                 break;
4189         default:
4190                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4191                 ret = -EINVAL;
4192                 break;
4193         }
4194         return ret;
4195 }
4196
4197 static int
4198 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4199                      enum rte_filter_type filter_type,
4200                      enum rte_filter_op filter_op,
4201                      void *arg)
4202 {
4203         int ret = -EINVAL;
4204
4205         switch (filter_type) {
4206         case RTE_ETH_FILTER_NTUPLE:
4207                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4208                 break;
4209         case RTE_ETH_FILTER_ETHERTYPE:
4210                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4211                 break;
4212         case RTE_ETH_FILTER_SYN:
4213                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4214                 break;
4215         case RTE_ETH_FILTER_FLEXIBLE:
4216                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4217                 break;
4218         default:
4219                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4220                                                         filter_type);
4221                 break;
4222         }
4223
4224         return ret;
4225 }
4226
4227 static int
4228 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4229                          struct ether_addr *mc_addr_set,
4230                          uint32_t nb_mc_addr)
4231 {
4232         struct e1000_hw *hw;
4233
4234         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4235         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4236         return 0;
4237 }
4238
4239 static uint64_t
4240 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4241 {
4242         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4243         uint64_t systime_cycles;
4244
4245         switch (hw->mac.type) {
4246         case e1000_i210:
4247         case e1000_i211:
4248                 /*
4249                  * Need to read System Time Residue Register to be able
4250                  * to read the other two registers.
4251                  */
4252                 E1000_READ_REG(hw, E1000_SYSTIMR);
4253                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4254                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4255                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4256                                 * NSEC_PER_SEC;
4257                 break;
4258         case e1000_82580:
4259         case e1000_i350:
4260         case e1000_i354:
4261                 /*
4262                  * Need to read System Time Residue Register to be able
4263                  * to read the other two registers.
4264                  */
4265                 E1000_READ_REG(hw, E1000_SYSTIMR);
4266                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4267                 /* Only the 8 LSB are valid. */
4268                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4269                                 & 0xff) << 32;
4270                 break;
4271         default:
4272                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4273                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4274                                 << 32;
4275                 break;
4276         }
4277
4278         return systime_cycles;
4279 }
4280
4281 static uint64_t
4282 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4283 {
4284         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4285         uint64_t rx_tstamp_cycles;
4286
4287         switch (hw->mac.type) {
4288         case e1000_i210:
4289         case e1000_i211:
4290                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4291                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4292                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4293                                 * NSEC_PER_SEC;
4294                 break;
4295         case e1000_82580:
4296         case e1000_i350:
4297         case e1000_i354:
4298                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4299                 /* Only the 8 LSB are valid. */
4300                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4301                                 & 0xff) << 32;
4302                 break;
4303         default:
4304                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4305                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4306                                 << 32;
4307                 break;
4308         }
4309
4310         return rx_tstamp_cycles;
4311 }
4312
4313 static uint64_t
4314 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4315 {
4316         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4317         uint64_t tx_tstamp_cycles;
4318
4319         switch (hw->mac.type) {
4320         case e1000_i210:
4321         case e1000_i211:
4322                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4323                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4324                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4325                                 * NSEC_PER_SEC;
4326                 break;
4327         case e1000_82580:
4328         case e1000_i350:
4329         case e1000_i354:
4330                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4331                 /* Only the 8 LSB are valid. */
4332                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4333                                 & 0xff) << 32;
4334                 break;
4335         default:
4336                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4337                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4338                                 << 32;
4339                 break;
4340         }
4341
4342         return tx_tstamp_cycles;
4343 }
4344
4345 static void
4346 igb_start_timecounters(struct rte_eth_dev *dev)
4347 {
4348         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4349         struct e1000_adapter *adapter =
4350                 (struct e1000_adapter *)dev->data->dev_private;
4351         uint32_t incval = 1;
4352         uint32_t shift = 0;
4353         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4354
4355         switch (hw->mac.type) {
4356         case e1000_82580:
4357         case e1000_i350:
4358         case e1000_i354:
4359                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4360                 mask = (1ULL << 40) - 1;
4361                 /* fall-through */
4362         case e1000_i210:
4363         case e1000_i211:
4364                 /*
4365                  * Start incrementing the register
4366                  * used to timestamp PTP packets.
4367                  */
4368                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4369                 break;
4370         case e1000_82576:
4371                 incval = E1000_INCVALUE_82576;
4372                 shift = IGB_82576_TSYNC_SHIFT;
4373                 E1000_WRITE_REG(hw, E1000_TIMINCA,
4374                                 E1000_INCPERIOD_82576 | incval);
4375                 break;
4376         default:
4377                 /* Not supported */
4378                 return;
4379         }
4380
4381         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4382         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4383         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4384
4385         adapter->systime_tc.cc_mask = mask;
4386         adapter->systime_tc.cc_shift = shift;
4387         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4388
4389         adapter->rx_tstamp_tc.cc_mask = mask;
4390         adapter->rx_tstamp_tc.cc_shift = shift;
4391         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4392
4393         adapter->tx_tstamp_tc.cc_mask = mask;
4394         adapter->tx_tstamp_tc.cc_shift = shift;
4395         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4396 }
4397
4398 static int
4399 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4400 {
4401         struct e1000_adapter *adapter =
4402                         (struct e1000_adapter *)dev->data->dev_private;
4403
4404         adapter->systime_tc.nsec += delta;
4405         adapter->rx_tstamp_tc.nsec += delta;
4406         adapter->tx_tstamp_tc.nsec += delta;
4407
4408         return 0;
4409 }
4410
4411 static int
4412 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4413 {
4414         uint64_t ns;
4415         struct e1000_adapter *adapter =
4416                         (struct e1000_adapter *)dev->data->dev_private;
4417
4418         ns = rte_timespec_to_ns(ts);
4419
4420         /* Set the timecounters to a new value. */
4421         adapter->systime_tc.nsec = ns;
4422         adapter->rx_tstamp_tc.nsec = ns;
4423         adapter->tx_tstamp_tc.nsec = ns;
4424
4425         return 0;
4426 }
4427
4428 static int
4429 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4430 {
4431         uint64_t ns, systime_cycles;
4432         struct e1000_adapter *adapter =
4433                         (struct e1000_adapter *)dev->data->dev_private;
4434
4435         systime_cycles = igb_read_systime_cyclecounter(dev);
4436         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4437         *ts = rte_ns_to_timespec(ns);
4438
4439         return 0;
4440 }
4441
4442 static int
4443 igb_timesync_enable(struct rte_eth_dev *dev)
4444 {
4445         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4446         uint32_t tsync_ctl;
4447         uint32_t tsauxc;
4448
4449         /* Stop the timesync system time. */
4450         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4451         /* Reset the timesync system time value. */
4452         switch (hw->mac.type) {
4453         case e1000_82580:
4454         case e1000_i350:
4455         case e1000_i354:
4456         case e1000_i210:
4457         case e1000_i211:
4458                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4459                 /* fall-through */
4460         case e1000_82576:
4461                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4462                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4463                 break;
4464         default:
4465                 /* Not supported. */
4466                 return -ENOTSUP;
4467         }
4468
4469         /* Enable system time for it isn't on by default. */
4470         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4471         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4472         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4473
4474         igb_start_timecounters(dev);
4475
4476         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4477         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4478                         (ETHER_TYPE_1588 |
4479                          E1000_ETQF_FILTER_ENABLE |
4480                          E1000_ETQF_1588));
4481
4482         /* Enable timestamping of received PTP packets. */
4483         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4484         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4485         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4486
4487         /* Enable Timestamping of transmitted PTP packets. */
4488         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4489         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4490         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4491
4492         return 0;
4493 }
4494
4495 static int
4496 igb_timesync_disable(struct rte_eth_dev *dev)
4497 {
4498         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4499         uint32_t tsync_ctl;
4500
4501         /* Disable timestamping of transmitted PTP packets. */
4502         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4503         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4504         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4505
4506         /* Disable timestamping of received PTP packets. */
4507         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4508         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4509         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4510
4511         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4512         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4513
4514         /* Stop incrementating the System Time registers. */
4515         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4516
4517         return 0;
4518 }
4519
4520 static int
4521 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4522                                struct timespec *timestamp,
4523                                uint32_t flags __rte_unused)
4524 {
4525         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4526         struct e1000_adapter *adapter =
4527                         (struct e1000_adapter *)dev->data->dev_private;
4528         uint32_t tsync_rxctl;
4529         uint64_t rx_tstamp_cycles;
4530         uint64_t ns;
4531
4532         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4533         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4534                 return -EINVAL;
4535
4536         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4537         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4538         *timestamp = rte_ns_to_timespec(ns);
4539
4540         return  0;
4541 }
4542
4543 static int
4544 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4545                                struct timespec *timestamp)
4546 {
4547         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4548         struct e1000_adapter *adapter =
4549                         (struct e1000_adapter *)dev->data->dev_private;
4550         uint32_t tsync_txctl;
4551         uint64_t tx_tstamp_cycles;
4552         uint64_t ns;
4553
4554         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4555         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4556                 return -EINVAL;
4557
4558         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
4559         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4560         *timestamp = rte_ns_to_timespec(ns);
4561
4562         return  0;
4563 }
4564
4565 static int
4566 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4567 {
4568         int count = 0;
4569         int g_ind = 0;
4570         const struct reg_info *reg_group;
4571
4572         while ((reg_group = igb_regs[g_ind++]))
4573                 count += igb_reg_group_count(reg_group);
4574
4575         return count;
4576 }
4577
4578 static int
4579 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4580 {
4581         int count = 0;
4582         int g_ind = 0;
4583         const struct reg_info *reg_group;
4584
4585         while ((reg_group = igbvf_regs[g_ind++]))
4586                 count += igb_reg_group_count(reg_group);
4587
4588         return count;
4589 }
4590
4591 static int
4592 eth_igb_get_regs(struct rte_eth_dev *dev,
4593         struct rte_dev_reg_info *regs)
4594 {
4595         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4596         uint32_t *data = regs->data;
4597         int g_ind = 0;
4598         int count = 0;
4599         const struct reg_info *reg_group;
4600
4601         /* Support only full register dump */
4602         if ((regs->length == 0) ||
4603             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4604                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4605                         hw->device_id;
4606                 while ((reg_group = igb_regs[g_ind++]))
4607                         count += igb_read_regs_group(dev, &data[count],
4608                                                         reg_group);
4609                 return 0;
4610         }
4611
4612         return -ENOTSUP;
4613 }
4614
4615 static int
4616 igbvf_get_regs(struct rte_eth_dev *dev,
4617         struct rte_dev_reg_info *regs)
4618 {
4619         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4620         uint32_t *data = regs->data;
4621         int g_ind = 0;
4622         int count = 0;
4623         const struct reg_info *reg_group;
4624
4625         /* Support only full register dump */
4626         if ((regs->length == 0) ||
4627             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
4628                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4629                         hw->device_id;
4630                 while ((reg_group = igbvf_regs[g_ind++]))
4631                         count += igb_read_regs_group(dev, &data[count],
4632                                                         reg_group);
4633                 return 0;
4634         }
4635
4636         return -ENOTSUP;
4637 }
4638
4639 static int
4640 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
4641 {
4642         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4643
4644         /* Return unit is byte count */
4645         return hw->nvm.word_size * 2;
4646 }
4647
4648 static int
4649 eth_igb_get_eeprom(struct rte_eth_dev *dev,
4650         struct rte_dev_eeprom_info *in_eeprom)
4651 {
4652         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4653         struct e1000_nvm_info *nvm = &hw->nvm;
4654         uint16_t *data = in_eeprom->data;
4655         int first, length;
4656
4657         first = in_eeprom->offset >> 1;
4658         length = in_eeprom->length >> 1;
4659         if ((first >= hw->nvm.word_size) ||
4660             ((first + length) >= hw->nvm.word_size))
4661                 return -EINVAL;
4662
4663         in_eeprom->magic = hw->vendor_id |
4664                 ((uint32_t)hw->device_id << 16);
4665
4666         if ((nvm->ops.read) == NULL)
4667                 return -ENOTSUP;
4668
4669         return nvm->ops.read(hw, first, length, data);
4670 }
4671
4672 static int
4673 eth_igb_set_eeprom(struct rte_eth_dev *dev,
4674         struct rte_dev_eeprom_info *in_eeprom)
4675 {
4676         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4677         struct e1000_nvm_info *nvm = &hw->nvm;
4678         uint16_t *data = in_eeprom->data;
4679         int first, length;
4680
4681         first = in_eeprom->offset >> 1;
4682         length = in_eeprom->length >> 1;
4683         if ((first >= hw->nvm.word_size) ||
4684             ((first + length) >= hw->nvm.word_size))
4685                 return -EINVAL;
4686
4687         in_eeprom->magic = (uint32_t)hw->vendor_id |
4688                 ((uint32_t)hw->device_id << 16);
4689
4690         if ((nvm->ops.write) == NULL)
4691                 return -ENOTSUP;
4692         return nvm->ops.write(hw,  first, length, data);
4693 }
4694
4695 static struct rte_driver pmd_igb_drv = {
4696         .type = PMD_PDEV,
4697         .init = rte_igb_pmd_init,
4698 };
4699
4700 static struct rte_driver pmd_igbvf_drv = {
4701         .type = PMD_PDEV,
4702         .init = rte_igbvf_pmd_init,
4703 };
4704
4705 static int
4706 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4707 {
4708         struct e1000_hw *hw =
4709                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4710         uint32_t mask = 1 << queue_id;
4711
4712         E1000_WRITE_REG(hw, E1000_EIMC, mask);
4713         E1000_WRITE_FLUSH(hw);
4714
4715         return 0;
4716 }
4717
4718 static int
4719 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4720 {
4721         struct e1000_hw *hw =
4722                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4723         uint32_t mask = 1 << queue_id;
4724         uint32_t regval;
4725
4726         regval = E1000_READ_REG(hw, E1000_EIMS);
4727         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
4728         E1000_WRITE_FLUSH(hw);
4729
4730         rte_intr_enable(&dev->pci_dev->intr_handle);
4731
4732         return 0;
4733 }
4734
4735 static void
4736 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
4737                    uint8_t index, uint8_t offset)
4738 {
4739         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
4740
4741         /* clear bits */
4742         val &= ~((uint32_t)0xFF << offset);
4743
4744         /* write vector and valid bit */
4745         val |= (msix_vector | E1000_IVAR_VALID) << offset;
4746
4747         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
4748 }
4749
4750 static void
4751 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
4752                            uint8_t queue, uint8_t msix_vector)
4753 {
4754         uint32_t tmp = 0;
4755
4756         if (hw->mac.type == e1000_82575) {
4757                 if (direction == 0)
4758                         tmp = E1000_EICR_RX_QUEUE0 << queue;
4759                 else if (direction == 1)
4760                         tmp = E1000_EICR_TX_QUEUE0 << queue;
4761                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
4762         } else if (hw->mac.type == e1000_82576) {
4763                 if ((direction == 0) || (direction == 1))
4764                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
4765                                            ((queue & 0x8) << 1) +
4766                                            8 * direction);
4767         } else if ((hw->mac.type == e1000_82580) ||
4768                         (hw->mac.type == e1000_i350) ||
4769                         (hw->mac.type == e1000_i354) ||
4770                         (hw->mac.type == e1000_i210) ||
4771                         (hw->mac.type == e1000_i211)) {
4772                 if ((direction == 0) || (direction == 1))
4773                         eth_igb_write_ivar(hw, msix_vector,
4774                                            queue >> 1,
4775                                            ((queue & 0x1) << 4) +
4776                                            8 * direction);
4777         }
4778 }
4779
4780 /* Sets up the hardware to generate MSI-X interrupts properly
4781  * @hw
4782  *  board private structure
4783  */
4784 static void
4785 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
4786 {
4787         int queue_id;
4788         uint32_t tmpval, regval, intr_mask;
4789         struct e1000_hw *hw =
4790                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4791         uint32_t vec = E1000_MISC_VEC_ID;
4792         uint32_t base = E1000_MISC_VEC_ID;
4793         uint32_t misc_shift = 0;
4794
4795         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4796
4797         /* won't configure msix register if no mapping is done
4798          * between intr vector and event fd
4799          */
4800         if (!rte_intr_dp_is_en(intr_handle))
4801                 return;
4802
4803         if (rte_intr_allow_others(intr_handle)) {
4804                 vec = base = E1000_RX_VEC_START;
4805                 misc_shift = 1;
4806         }
4807
4808         /* set interrupt vector for other causes */
4809         if (hw->mac.type == e1000_82575) {
4810                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
4811                 /* enable MSI-X PBA support */
4812                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
4813
4814                 /* Auto-Mask interrupts upon ICR read */
4815                 tmpval |= E1000_CTRL_EXT_EIAME;
4816                 tmpval |= E1000_CTRL_EXT_IRCA;
4817
4818                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
4819
4820                 /* enable msix_other interrupt */
4821                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
4822                 regval = E1000_READ_REG(hw, E1000_EIAC);
4823                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
4824                 regval = E1000_READ_REG(hw, E1000_EIAM);
4825                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
4826         } else if ((hw->mac.type == e1000_82576) ||
4827                         (hw->mac.type == e1000_82580) ||
4828                         (hw->mac.type == e1000_i350) ||
4829                         (hw->mac.type == e1000_i354) ||
4830                         (hw->mac.type == e1000_i210) ||
4831                         (hw->mac.type == e1000_i211)) {
4832                 /* turn on MSI-X capability first */
4833                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
4834                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
4835                                         E1000_GPIE_NSICR);
4836                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
4837                         misc_shift;
4838                 regval = E1000_READ_REG(hw, E1000_EIAC);
4839                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
4840
4841                 /* enable msix_other interrupt */
4842                 regval = E1000_READ_REG(hw, E1000_EIMS);
4843                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
4844                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
4845                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
4846         }
4847
4848         /* use EIAM to auto-mask when MSI-X interrupt
4849          * is asserted, this saves a register write for every interrupt
4850          */
4851         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
4852                 misc_shift;
4853         regval = E1000_READ_REG(hw, E1000_EIAM);
4854         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
4855
4856         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
4857                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
4858                 intr_handle->intr_vec[queue_id] = vec;
4859                 if (vec < base + intr_handle->nb_efd - 1)
4860                         vec++;
4861         }
4862
4863         E1000_WRITE_FLUSH(hw);
4864 }
4865
4866 PMD_REGISTER_DRIVER(pmd_igb_drv);
4867 PMD_REGISTER_DRIVER(pmd_igbvf_drv);