drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58 #include "igb_regs.h"
  59
  60 /*
  61  * Default values for port configuration
  62  */
  63 #define IGB_DEFAULT_RX_FREE_THRESH  32
  64
  65 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  66 #define IGB_DEFAULT_RX_HTHRESH      8
  67 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  68
  69 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  70 #define IGB_DEFAULT_TX_HTHRESH      1
  71 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  72
  73 #define IGB_HKEY_MAX_INDEX 10
  74
  75 /* Bit shift and mask */
  76 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  77 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  78 #define IGB_8_BIT_WIDTH  CHAR_BIT
  79 #define IGB_8_BIT_MASK   UINT8_MAX
  80
  81 /* Additional timesync values. */
  82 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  83 #define E1000_ETQF_FILTER_1588       3
  84 #define IGB_82576_TSYNC_SHIFT        16
  85 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  86 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  87 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  88
  89 static int  eth_igb_configure(struct rte_eth_dev *dev);
  90 static int  eth_igb_start(struct rte_eth_dev *dev);
  91 static void eth_igb_stop(struct rte_eth_dev *dev);
  92 static void eth_igb_close(struct rte_eth_dev *dev);
  93 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  94 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  95 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  96 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  97 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  98                                 int wait_to_complete);
  99 static void eth_igb_stats_get(struct rte_eth_dev *dev,
 100                                 struct rte_eth_stats *rte_stats);
 101 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 102                               struct rte_eth_xstats *xstats, unsigned n);
 103 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 104 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 105 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 106                               struct rte_eth_dev_info *dev_info);
 107 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 108 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 109                                 struct rte_eth_dev_info *dev_info);
 110 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 111                                 struct rte_eth_fc_conf *fc_conf);
 112 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 113                                 struct rte_eth_fc_conf *fc_conf);
 114 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 115 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 116 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 117 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
 118 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 119                                                         void *param);
 120 static int  igb_hardware_init(struct e1000_hw *hw);
 121 static void igb_hw_control_acquire(struct e1000_hw *hw);
 122 static void igb_hw_control_release(struct e1000_hw *hw);
 123 static void igb_init_manageability(struct e1000_hw *hw);
 124 static void igb_release_manageability(struct e1000_hw *hw);
 125
 126 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 127
 128 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 129                 uint16_t vlan_id, int on);
 130 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 131                                  enum rte_vlan_type vlan_type,
 132                                  uint16_t tpid_id);
 133 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 134
 135 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 136 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 137 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 138 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 139 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 140 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 141
 142 static int eth_igb_led_on(struct rte_eth_dev *dev);
 143 static int eth_igb_led_off(struct rte_eth_dev *dev);
 144
 145 static void igb_intr_disable(struct e1000_hw *hw);
 146 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 147 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 148                 struct ether_addr *mac_addr,
 149                 uint32_t index, uint32_t pool);
 150 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 151 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 152                 struct ether_addr *addr);
 153
 154 static void igbvf_intr_disable(struct e1000_hw *hw);
 155 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 156 static int igbvf_dev_start(struct rte_eth_dev *dev);
 157 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 158 static void igbvf_dev_close(struct rte_eth_dev *dev);
 159 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 160 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 161 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 162 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 163 static int eth_igbvf_link_update(struct e1000_hw *hw);
 164 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
 165                                 struct rte_eth_stats *rte_stats);
 166 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 167                                 struct rte_eth_xstats *xstats, unsigned n);
 168 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 169 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 170                 uint16_t vlan_id, int on);
 171 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 172 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 173 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 174                 struct ether_addr *addr);
 175 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 176 static int igbvf_get_regs(struct rte_eth_dev *dev,
 177                 struct rte_dev_reg_info *regs);
 178
 179 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 180                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 181                                    uint16_t reta_size);
 182 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 183                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 184                                   uint16_t reta_size);
 185
 186 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 187                         struct rte_eth_syn_filter *filter,
 188                         bool add);
 189 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 190                         struct rte_eth_syn_filter *filter);
 191 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 192                         enum rte_filter_op filter_op,
 193                         void *arg);
 194 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 195                         struct rte_eth_ntuple_filter *ntuple_filter);
 196 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 197                         struct rte_eth_ntuple_filter *ntuple_filter);
 198 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 199                         struct rte_eth_flex_filter *filter,
 200                         bool add);
 201 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 202                         struct rte_eth_flex_filter *filter);
 203 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 204                         enum rte_filter_op filter_op,
 205                         void *arg);
 206 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 207                         struct rte_eth_ntuple_filter *ntuple_filter);
 208 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 209                         struct rte_eth_ntuple_filter *ntuple_filter);
 210 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 211                         struct rte_eth_ntuple_filter *filter,
 212                         bool add);
 213 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 214                         struct rte_eth_ntuple_filter *filter);
 215 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 216                                 enum rte_filter_op filter_op,
 217                                 void *arg);
 218 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 219                         struct rte_eth_ethertype_filter *filter,
 220                         bool add);
 221 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 222                                 enum rte_filter_op filter_op,
 223                                 void *arg);
 224 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 225                         struct rte_eth_ethertype_filter *filter);
 226 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 227                      enum rte_filter_type filter_type,
 228                      enum rte_filter_op filter_op,
 229                      void *arg);
 230 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 231 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 232                 struct rte_dev_reg_info *regs);
 233 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 234 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 235                 struct rte_dev_eeprom_info *eeprom);
 236 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 237                 struct rte_dev_eeprom_info *eeprom);
 238 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 239                                     struct ether_addr *mc_addr_set,
 240                                     uint32_t nb_mc_addr);
 241 static int igb_timesync_enable(struct rte_eth_dev *dev);
 242 static int igb_timesync_disable(struct rte_eth_dev *dev);
 243 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 244                                           struct timespec *timestamp,
 245                                           uint32_t flags);
 246 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 247                                           struct timespec *timestamp);
 248 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 249 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 250                                   struct timespec *timestamp);
 251 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 252                                    const struct timespec *timestamp);
 253 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 254                                         uint16_t queue_id);
 255 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 256                                          uint16_t queue_id);
 257 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 258                                        uint8_t queue, uint8_t msix_vector);
 259 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 260                                uint8_t index, uint8_t offset);
 261 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 262
 263 /*
 264  * Define VF Stats MACRO for Non "cleared on read" register
 265  */
 266 #define UPDATE_VF_STAT(reg, last, cur)            \
 267 {                                                 \
 268         u32 latest = E1000_READ_REG(hw, reg);     \
 269         cur += (latest - last) & UINT_MAX;        \
 270         last = latest;                            \
 271 }
 272
 273 #define IGB_FC_PAUSE_TIME 0x0680
 274 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 275 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 276
 277 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 278
 279 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 280
 281 /*
 282  * The set of PCI devices this driver supports
 283  */
 284 static const struct rte_pci_id pci_id_igb_map[] = {
 285
 286 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 287 #include "rte_pci_dev_ids.h"
 288
 289 {0},
 290 };
 291
 292 /*
 293  * The set of PCI devices this driver supports (for 82576&I350 VF)
 294  */
 295 static const struct rte_pci_id pci_id_igbvf_map[] = {
 296
 297 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 298 #include "rte_pci_dev_ids.h"
 299
 300 {0},
 301 };
 302
 303 static const struct rte_eth_desc_lim rx_desc_lim = {
 304         .nb_max = E1000_MAX_RING_DESC,
 305         .nb_min = E1000_MIN_RING_DESC,
 306         .nb_align = IGB_RXD_ALIGN,
 307 };
 308
 309 static const struct rte_eth_desc_lim tx_desc_lim = {
 310         .nb_max = E1000_MAX_RING_DESC,
 311         .nb_min = E1000_MIN_RING_DESC,
 312         .nb_align = IGB_RXD_ALIGN,
 313 };
 314
 315 static const struct eth_dev_ops eth_igb_ops = {
 316         .dev_configure        = eth_igb_configure,
 317         .dev_start            = eth_igb_start,
 318         .dev_stop             = eth_igb_stop,
 319         .dev_close            = eth_igb_close,
 320         .promiscuous_enable   = eth_igb_promiscuous_enable,
 321         .promiscuous_disable  = eth_igb_promiscuous_disable,
 322         .allmulticast_enable  = eth_igb_allmulticast_enable,
 323         .allmulticast_disable = eth_igb_allmulticast_disable,
 324         .link_update          = eth_igb_link_update,
 325         .stats_get            = eth_igb_stats_get,
 326         .xstats_get           = eth_igb_xstats_get,
 327         .stats_reset          = eth_igb_stats_reset,
 328         .xstats_reset         = eth_igb_xstats_reset,
 329         .dev_infos_get        = eth_igb_infos_get,
 330         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 331         .mtu_set              = eth_igb_mtu_set,
 332         .vlan_filter_set      = eth_igb_vlan_filter_set,
 333         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 334         .vlan_offload_set     = eth_igb_vlan_offload_set,
 335         .rx_queue_setup       = eth_igb_rx_queue_setup,
 336         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 337         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 338         .rx_queue_release     = eth_igb_rx_queue_release,
 339         .rx_queue_count       = eth_igb_rx_queue_count,
 340         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 341         .tx_queue_setup       = eth_igb_tx_queue_setup,
 342         .tx_queue_release     = eth_igb_tx_queue_release,
 343         .dev_led_on           = eth_igb_led_on,
 344         .dev_led_off          = eth_igb_led_off,
 345         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 346         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 347         .mac_addr_add         = eth_igb_rar_set,
 348         .mac_addr_remove      = eth_igb_rar_clear,
 349         .mac_addr_set         = eth_igb_default_mac_addr_set,
 350         .reta_update          = eth_igb_rss_reta_update,
 351         .reta_query           = eth_igb_rss_reta_query,
 352         .rss_hash_update      = eth_igb_rss_hash_update,
 353         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 354         .filter_ctrl          = eth_igb_filter_ctrl,
 355         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 356         .rxq_info_get         = igb_rxq_info_get,
 357         .txq_info_get         = igb_txq_info_get,
 358         .timesync_enable      = igb_timesync_enable,
 359         .timesync_disable     = igb_timesync_disable,
 360         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 361         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 362         .get_reg_length       = eth_igb_get_reg_length,
 363         .get_reg              = eth_igb_get_regs,
 364         .get_eeprom_length    = eth_igb_get_eeprom_length,
 365         .get_eeprom           = eth_igb_get_eeprom,
 366         .set_eeprom           = eth_igb_set_eeprom,
 367         .timesync_adjust_time = igb_timesync_adjust_time,
 368         .timesync_read_time   = igb_timesync_read_time,
 369         .timesync_write_time  = igb_timesync_write_time,
 370 };
 371
 372 /*
 373  * dev_ops for virtual function, bare necessities for basic vf
 374  * operation have been implemented
 375  */
 376 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 377         .dev_configure        = igbvf_dev_configure,
 378         .dev_start            = igbvf_dev_start,
 379         .dev_stop             = igbvf_dev_stop,
 380         .dev_close            = igbvf_dev_close,
 381         .promiscuous_enable   = igbvf_promiscuous_enable,
 382         .promiscuous_disable  = igbvf_promiscuous_disable,
 383         .allmulticast_enable  = igbvf_allmulticast_enable,
 384         .allmulticast_disable = igbvf_allmulticast_disable,
 385         .link_update          = eth_igb_link_update,
 386         .stats_get            = eth_igbvf_stats_get,
 387         .xstats_get           = eth_igbvf_xstats_get,
 388         .stats_reset          = eth_igbvf_stats_reset,
 389         .xstats_reset         = eth_igbvf_stats_reset,
 390         .vlan_filter_set      = igbvf_vlan_filter_set,
 391         .dev_infos_get        = eth_igbvf_infos_get,
 392         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 393         .rx_queue_setup       = eth_igb_rx_queue_setup,
 394         .rx_queue_release     = eth_igb_rx_queue_release,
 395         .tx_queue_setup       = eth_igb_tx_queue_setup,
 396         .tx_queue_release     = eth_igb_tx_queue_release,
 397         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 398         .rxq_info_get         = igb_rxq_info_get,
 399         .txq_info_get         = igb_txq_info_get,
 400         .mac_addr_set         = igbvf_default_mac_addr_set,
 401         .get_reg_length       = igbvf_get_reg_length,
 402         .get_reg              = igbvf_get_regs,
 403 };
 404
 405 /* store statistics names and its offset in stats structure */
 406 struct rte_igb_xstats_name_off {
 407         char name[RTE_ETH_XSTATS_NAME_SIZE];
 408         unsigned offset;
 409 };
 410
 411 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 412         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 413         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 414         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 415         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 416         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 417         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 418         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 419                 ecol)},
 420         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 421         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 422         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 423         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 424         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 425         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 426         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 427         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 428         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 429         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 430         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 431                 fcruc)},
 432         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 433         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 434         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 435         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 436         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 437                 prc1023)},
 438         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 439                 prc1522)},
 440         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 441         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 442         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 443         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 444         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 445         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 446         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 447         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 448         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 449         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 450         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 451         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 452         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 453         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 454         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 455         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 456         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 457         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 458                 ptc1023)},
 459         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 460                 ptc1522)},
 461         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 462         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 463         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 464         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 465         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 466         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 467         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 468
 469         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 470 };
 471
 472 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 473                 sizeof(rte_igb_stats_strings[0]))
 474
 475 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 476         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 477         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 478         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 479         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 480         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 481 };
 482
 483 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 484                 sizeof(rte_igbvf_stats_strings[0]))
 485
 486 /**
 487  * Atomically reads the link status information from global
 488  * structure rte_eth_dev.
 489  *
 490  * @param dev
 491  *   - Pointer to the structure rte_eth_dev to read from.
 492  *   - Pointer to the buffer to be saved with the link status.
 493  *
 494  * @return
 495  *   - On success, zero.
 496  *   - On failure, negative value.
 497  */
 498 static inline int
 499 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 500                                 struct rte_eth_link *link)
 501 {
 502         struct rte_eth_link *dst = link;
 503         struct rte_eth_link *src = &(dev->data->dev_link);
 504
 505         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 506                                         *(uint64_t *)src) == 0)
 507                 return -1;
 508
 509         return 0;
 510 }
 511
 512 /**
 513  * Atomically writes the link status information into global
 514  * structure rte_eth_dev.
 515  *
 516  * @param dev
 517  *   - Pointer to the structure rte_eth_dev to read from.
 518  *   - Pointer to the buffer to be saved with the link status.
 519  *
 520  * @return
 521  *   - On success, zero.
 522  *   - On failure, negative value.
 523  */
 524 static inline int
 525 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 526                                 struct rte_eth_link *link)
 527 {
 528         struct rte_eth_link *dst = &(dev->data->dev_link);
 529         struct rte_eth_link *src = link;
 530
 531         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 532                                         *(uint64_t *)src) == 0)
 533                 return -1;
 534
 535         return 0;
 536 }
 537
 538 static inline void
 539 igb_intr_enable(struct rte_eth_dev *dev)
 540 {
 541         struct e1000_interrupt *intr =
 542                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 543         struct e1000_hw *hw =
 544                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 545
 546         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 547         E1000_WRITE_FLUSH(hw);
 548 }
 549
 550 static void
 551 igb_intr_disable(struct e1000_hw *hw)
 552 {
 553         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 554         E1000_WRITE_FLUSH(hw);
 555 }
 556
 557 static inline int32_t
 558 igb_pf_reset_hw(struct e1000_hw *hw)
 559 {
 560         uint32_t ctrl_ext;
 561         int32_t status;
 562
 563         status = e1000_reset_hw(hw);
 564
 565         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 566         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 567         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 568         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 569         E1000_WRITE_FLUSH(hw);
 570
 571         return status;
 572 }
 573
 574 static void
 575 igb_identify_hardware(struct rte_eth_dev *dev)
 576 {
 577         struct e1000_hw *hw =
 578                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 579
 580         hw->vendor_id = dev->pci_dev->id.vendor_id;
 581         hw->device_id = dev->pci_dev->id.device_id;
 582         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 583         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 584
 585         e1000_set_mac_type(hw);
 586
 587         /* need to check if it is a vf device below */
 588 }
 589
 590 static int
 591 igb_reset_swfw_lock(struct e1000_hw *hw)
 592 {
 593         int ret_val;
 594
 595         /*
 596          * Do mac ops initialization manually here, since we will need
 597          * some function pointers set by this call.
 598          */
 599         ret_val = e1000_init_mac_params(hw);
 600         if (ret_val)
 601                 return ret_val;
 602
 603         /*
 604          * SMBI lock should not fail in this early stage. If this is the case,
 605          * it is due to an improper exit of the application.
 606          * So force the release of the faulty lock.
 607          */
 608         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 609                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 610         }
 611         e1000_put_hw_semaphore_generic(hw);
 612
 613         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 614                 uint16_t mask;
 615
 616                 /*
 617                  * Phy lock should not fail in this early stage. If this is the case,
 618                  * it is due to an improper exit of the application.
 619                  * So force the release of the faulty lock.
 620                  */
 621                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 622                 if (hw->bus.func > E1000_FUNC_1)
 623                         mask <<= 2;
 624                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 625                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 626                                     hw->bus.func);
 627                 }
 628                 hw->mac.ops.release_swfw_sync(hw, mask);
 629
 630                 /*
 631                  * This one is more tricky since it is common to all ports; but
 632                  * swfw_sync retries last long enough (1s) to be almost sure that if
 633                  * lock can not be taken it is due to an improper lock of the
 634                  * semaphore.
 635                  */
 636                 mask = E1000_SWFW_EEP_SM;
 637                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 638                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 639                 }
 640                 hw->mac.ops.release_swfw_sync(hw, mask);
 641         }
 642
 643         return E1000_SUCCESS;
 644 }
 645
 646 static int
 647 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 648 {
 649         int error = 0;
 650         struct rte_pci_device *pci_dev;
 651         struct e1000_hw *hw =
 652                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 653         struct e1000_vfta * shadow_vfta =
 654                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 655         struct e1000_filter_info *filter_info =
 656                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 657         struct e1000_adapter *adapter =
 658                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 659
 660         uint32_t ctrl_ext;
 661
 662         pci_dev = eth_dev->pci_dev;
 663
 664         eth_dev->dev_ops = &eth_igb_ops;
 665         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 666         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 667
 668         /* for secondary processes, we don't initialise any further as primary
 669          * has already done this work. Only check we don't need a different
 670          * RX function */
 671         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 672                 if (eth_dev->data->scattered_rx)
 673                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 674                 return 0;
 675         }
 676
 677         rte_eth_copy_pci_info(eth_dev, pci_dev);
 678
 679         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 680
 681         igb_identify_hardware(eth_dev);
 682         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 683                 error = -EIO;
 684                 goto err_late;
 685         }
 686
 687         e1000_get_bus_info(hw);
 688
 689         /* Reset any pending lock */
 690         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 691                 error = -EIO;
 692                 goto err_late;
 693         }
 694
 695         /* Finish initialization */
 696         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 697                 error = -EIO;
 698                 goto err_late;
 699         }
 700
 701         hw->mac.autoneg = 1;
 702         hw->phy.autoneg_wait_to_complete = 0;
 703         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 704
 705         /* Copper options */
 706         if (hw->phy.media_type == e1000_media_type_copper) {
 707                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 708                 hw->phy.disable_polarity_correction = 0;
 709                 hw->phy.ms_type = e1000_ms_hw_default;
 710         }
 711
 712         /*
 713          * Start from a known state, this is important in reading the nvm
 714          * and mac from that.
 715          */
 716         igb_pf_reset_hw(hw);
 717
 718         /* Make sure we have a good EEPROM before we read from it */
 719         if (e1000_validate_nvm_checksum(hw) < 0) {
 720                 /*
 721                  * Some PCI-E parts fail the first check due to
 722                  * the link being in sleep state, call it again,
 723                  * if it fails a second time its a real issue.
 724                  */
 725                 if (e1000_validate_nvm_checksum(hw) < 0) {
 726                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 727                         error = -EIO;
 728                         goto err_late;
 729                 }
 730         }
 731
 732         /* Read the permanent MAC address out of the EEPROM */
 733         if (e1000_read_mac_addr(hw) != 0) {
 734                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 735                 error = -EIO;
 736                 goto err_late;
 737         }
 738
 739         /* Allocate memory for storing MAC addresses */
 740         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 741                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 742         if (eth_dev->data->mac_addrs == NULL) {
 743                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 744                                                 "store MAC addresses",
 745                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 746                 error = -ENOMEM;
 747                 goto err_late;
 748         }
 749
 750         /* Copy the permanent MAC address */
 751         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 752
 753         /* initialize the vfta */
 754         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 755
 756         /* Now initialize the hardware */
 757         if (igb_hardware_init(hw) != 0) {
 758                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 759                 rte_free(eth_dev->data->mac_addrs);
 760                 eth_dev->data->mac_addrs = NULL;
 761                 error = -ENODEV;
 762                 goto err_late;
 763         }
 764         hw->mac.get_link_status = 1;
 765         adapter->stopped = 0;
 766
 767         /* Indicate SOL/IDER usage */
 768         if (e1000_check_reset_block(hw) < 0) {
 769                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 770                                         "SOL/IDER session");
 771         }
 772
 773         /* initialize PF if max_vfs not zero */
 774         igb_pf_host_init(eth_dev);
 775
 776         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 777         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 778         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 779         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 780         E1000_WRITE_FLUSH(hw);
 781
 782         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 783                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 784                      pci_dev->id.device_id);
 785
 786         rte_intr_callback_register(&pci_dev->intr_handle,
 787                                    eth_igb_interrupt_handler,
 788                                    (void *)eth_dev);
 789
 790         /* enable uio/vfio intr/eventfd mapping */
 791         rte_intr_enable(&pci_dev->intr_handle);
 792
 793         /* enable support intr */
 794         igb_intr_enable(eth_dev);
 795
 796         TAILQ_INIT(&filter_info->flex_list);
 797         filter_info->flex_mask = 0;
 798         TAILQ_INIT(&filter_info->twotuple_list);
 799         filter_info->twotuple_mask = 0;
 800         TAILQ_INIT(&filter_info->fivetuple_list);
 801         filter_info->fivetuple_mask = 0;
 802
 803         return 0;
 804
 805 err_late:
 806         igb_hw_control_release(hw);
 807
 808         return error;
 809 }
 810
 811 static int
 812 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 813 {
 814         struct rte_pci_device *pci_dev;
 815         struct e1000_hw *hw;
 816         struct e1000_adapter *adapter =
 817                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 818
 819         PMD_INIT_FUNC_TRACE();
 820
 821         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 822                 return -EPERM;
 823
 824         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 825         pci_dev = eth_dev->pci_dev;
 826
 827         if (adapter->stopped == 0)
 828                 eth_igb_close(eth_dev);
 829
 830         eth_dev->dev_ops = NULL;
 831         eth_dev->rx_pkt_burst = NULL;
 832         eth_dev->tx_pkt_burst = NULL;
 833
 834         /* Reset any pending lock */
 835         igb_reset_swfw_lock(hw);
 836
 837         rte_free(eth_dev->data->mac_addrs);
 838         eth_dev->data->mac_addrs = NULL;
 839
 840         /* uninitialize PF if max_vfs not zero */
 841         igb_pf_host_uninit(eth_dev);
 842
 843         /* disable uio intr before callback unregister */
 844         rte_intr_disable(&(pci_dev->intr_handle));
 845         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 846                 eth_igb_interrupt_handler, (void *)eth_dev);
 847
 848         return 0;
 849 }
 850
 851 /*
 852  * Virtual Function device init
 853  */
 854 static int
 855 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 856 {
 857         struct rte_pci_device *pci_dev;
 858         struct e1000_adapter *adapter =
 859                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 860         struct e1000_hw *hw =
 861                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 862         int diag;
 863         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
 864
 865         PMD_INIT_FUNC_TRACE();
 866
 867         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 868         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 869         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 870
 871         /* for secondary processes, we don't initialise any further as primary
 872          * has already done this work. Only check we don't need a different
 873          * RX function */
 874         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 875                 if (eth_dev->data->scattered_rx)
 876                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 877                 return 0;
 878         }
 879
 880         pci_dev = eth_dev->pci_dev;
 881
 882         rte_eth_copy_pci_info(eth_dev, pci_dev);
 883
 884         hw->device_id = pci_dev->id.device_id;
 885         hw->vendor_id = pci_dev->id.vendor_id;
 886         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 887         adapter->stopped = 0;
 888
 889         /* Initialize the shared code (base driver) */
 890         diag = e1000_setup_init_funcs(hw, TRUE);
 891         if (diag != 0) {
 892                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 893                         diag);
 894                 return -EIO;
 895         }
 896
 897         /* init_mailbox_params */
 898         hw->mbx.ops.init_params(hw);
 899
 900         /* Disable the interrupts for VF */
 901         igbvf_intr_disable(hw);
 902
 903         diag = hw->mac.ops.reset_hw(hw);
 904
 905         /* Allocate memory for storing MAC addresses */
 906         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 907                 hw->mac.rar_entry_count, 0);
 908         if (eth_dev->data->mac_addrs == NULL) {
 909                 PMD_INIT_LOG(ERR,
 910                         "Failed to allocate %d bytes needed to store MAC "
 911                         "addresses",
 912                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 913                 return -ENOMEM;
 914         }
 915
 916         /* Generate a random MAC address, if none was assigned by PF. */
 917         if (is_zero_ether_addr(perm_addr)) {
 918                 eth_random_addr(perm_addr->addr_bytes);
 919                 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
 920                 if (diag) {
 921                         rte_free(eth_dev->data->mac_addrs);
 922                         eth_dev->data->mac_addrs = NULL;
 923                         return diag;
 924                 }
 925                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
 926                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
 927                              "%02x:%02x:%02x:%02x:%02x:%02x",
 928                              perm_addr->addr_bytes[0],
 929                              perm_addr->addr_bytes[1],
 930                              perm_addr->addr_bytes[2],
 931                              perm_addr->addr_bytes[3],
 932                              perm_addr->addr_bytes[4],
 933                              perm_addr->addr_bytes[5]);
 934         }
 935
 936         /* Copy the permanent MAC address */
 937         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 938                         &eth_dev->data->mac_addrs[0]);
 939
 940         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
 941                      "mac.type=%s",
 942                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 943                      pci_dev->id.device_id, "igb_mac_82576_vf");
 944
 945         return 0;
 946 }
 947
 948 static int
 949 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
 950 {
 951         struct e1000_adapter *adapter =
 952                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 953
 954         PMD_INIT_FUNC_TRACE();
 955
 956         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 957                 return -EPERM;
 958
 959         if (adapter->stopped == 0)
 960                 igbvf_dev_close(eth_dev);
 961
 962         eth_dev->dev_ops = NULL;
 963         eth_dev->rx_pkt_burst = NULL;
 964         eth_dev->tx_pkt_burst = NULL;
 965
 966         rte_free(eth_dev->data->mac_addrs);
 967         eth_dev->data->mac_addrs = NULL;
 968
 969         return 0;
 970 }
 971
 972 static struct eth_driver rte_igb_pmd = {
 973         .pci_drv = {
 974                 .name = "rte_igb_pmd",
 975                 .id_table = pci_id_igb_map,
 976                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 977                         RTE_PCI_DRV_DETACHABLE,
 978         },
 979         .eth_dev_init = eth_igb_dev_init,
 980         .eth_dev_uninit = eth_igb_dev_uninit,
 981         .dev_private_size = sizeof(struct e1000_adapter),
 982 };
 983
 984 /*
 985  * virtual function driver struct
 986  */
 987 static struct eth_driver rte_igbvf_pmd = {
 988         .pci_drv = {
 989                 .name = "rte_igbvf_pmd",
 990                 .id_table = pci_id_igbvf_map,
 991                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
 992         },
 993         .eth_dev_init = eth_igbvf_dev_init,
 994         .eth_dev_uninit = eth_igbvf_dev_uninit,
 995         .dev_private_size = sizeof(struct e1000_adapter),
 996 };
 997
 998 static int
 999 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1000 {
1001         rte_eth_driver_register(&rte_igb_pmd);
1002         return 0;
1003 }
1004
1005 static void
1006 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1007 {
1008         struct e1000_hw *hw =
1009                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1010         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1011         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1012         rctl |= E1000_RCTL_VFE;
1013         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1014 }
1015
1016 /*
1017  * VF Driver initialization routine.
1018  * Invoked one at EAL init time.
1019  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
1020  */
1021 static int
1022 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1023 {
1024         PMD_INIT_FUNC_TRACE();
1025
1026         rte_eth_driver_register(&rte_igbvf_pmd);
1027         return 0;
1028 }
1029
1030 static int
1031 igb_check_mq_mode(struct rte_eth_dev *dev)
1032 {
1033         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1034         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1035         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1036         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1037
1038         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1039             tx_mq_mode == ETH_MQ_TX_DCB ||
1040             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1041                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1042                 return -EINVAL;
1043         }
1044         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1045                 /* Check multi-queue mode.
1046                  * To no break software we accept ETH_MQ_RX_NONE as this might
1047                  * be used to turn off VLAN filter.
1048                  */
1049
1050                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1051                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1052                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1053                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1054                 } else {
1055                         /* Only support one queue on VFs.
1056                          * RSS together with SRIOV is not supported.
1057                          */
1058                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1059                                         " wrong mq_mode rx %d.",
1060                                         rx_mq_mode);
1061                         return -EINVAL;
1062                 }
1063                 /* TX mode is not used here, so mode might be ignored.*/
1064                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1065                         /* SRIOV only works in VMDq enable mode */
1066                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1067                                         " TX mode %d is not supported. "
1068                                         " Driver will behave as %d mode.",
1069                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1070                 }
1071
1072                 /* check valid queue number */
1073                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1074                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1075                                         " only support one queue on VFs.");
1076                         return -EINVAL;
1077                 }
1078         } else {
1079                 /* To no break software that set invalid mode, only display
1080                  * warning if invalid mode is used.
1081                  */
1082                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1083                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1084                     rx_mq_mode != ETH_MQ_RX_RSS) {
1085                         /* RSS together with VMDq not supported*/
1086                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1087                                      rx_mq_mode);
1088                         return -EINVAL;
1089                 }
1090
1091                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1092                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1093                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1094                                         " Due to txmode is meaningless in this"
1095                                         " driver, just ignore.",
1096                                         tx_mq_mode);
1097                 }
1098         }
1099         return 0;
1100 }
1101
1102 static int
1103 eth_igb_configure(struct rte_eth_dev *dev)
1104 {
1105         struct e1000_interrupt *intr =
1106                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1107         int ret;
1108
1109         PMD_INIT_FUNC_TRACE();
1110
1111         /* multipe queue mode checking */
1112         ret  = igb_check_mq_mode(dev);
1113         if (ret != 0) {
1114                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1115                             ret);
1116                 return ret;
1117         }
1118
1119         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1120         PMD_INIT_FUNC_TRACE();
1121
1122         return 0;
1123 }
1124
1125 static int
1126 eth_igb_start(struct rte_eth_dev *dev)
1127 {
1128         struct e1000_hw *hw =
1129                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1130         struct e1000_adapter *adapter =
1131                 E1000_DEV_PRIVATE(dev->data->dev_private);
1132         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1133         int ret, mask;
1134         uint32_t intr_vector = 0;
1135         uint32_t ctrl_ext;
1136
1137         PMD_INIT_FUNC_TRACE();
1138
1139         /* disable uio/vfio intr/eventfd mapping */
1140         rte_intr_disable(intr_handle);
1141
1142         /* Power up the phy. Needed to make the link go Up */
1143         e1000_power_up_phy(hw);
1144
1145         /*
1146          * Packet Buffer Allocation (PBA)
1147          * Writing PBA sets the receive portion of the buffer
1148          * the remainder is used for the transmit buffer.
1149          */
1150         if (hw->mac.type == e1000_82575) {
1151                 uint32_t pba;
1152
1153                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1154                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1155         }
1156
1157         /* Put the address into the Receive Address Array */
1158         e1000_rar_set(hw, hw->mac.addr, 0);
1159
1160         /* Initialize the hardware */
1161         if (igb_hardware_init(hw)) {
1162                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1163                 return -EIO;
1164         }
1165         adapter->stopped = 0;
1166
1167         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1168
1169         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1170         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1171         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1172         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1173         E1000_WRITE_FLUSH(hw);
1174
1175         /* configure PF module if SRIOV enabled */
1176         igb_pf_host_configure(dev);
1177
1178         /* check and configure queue intr-vector mapping */
1179         if ((rte_intr_cap_multiple(intr_handle) ||
1180              !RTE_ETH_DEV_SRIOV(dev).active) &&
1181             dev->data->dev_conf.intr_conf.rxq != 0) {
1182                 intr_vector = dev->data->nb_rx_queues;
1183                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1184                         return -1;
1185         }
1186
1187         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1188                 intr_handle->intr_vec =
1189                         rte_zmalloc("intr_vec",
1190                                     dev->data->nb_rx_queues * sizeof(int), 0);
1191                 if (intr_handle->intr_vec == NULL) {
1192                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1193                                      " intr_vec\n", dev->data->nb_rx_queues);
1194                         return -ENOMEM;
1195                 }
1196         }
1197
1198         /* confiugre msix for rx interrupt */
1199         eth_igb_configure_msix_intr(dev);
1200
1201         /* Configure for OS presence */
1202         igb_init_manageability(hw);
1203
1204         eth_igb_tx_init(dev);
1205
1206         /* This can fail when allocating mbufs for descriptor rings */
1207         ret = eth_igb_rx_init(dev);
1208         if (ret) {
1209                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1210                 igb_dev_clear_queues(dev);
1211                 return ret;
1212         }
1213
1214         e1000_clear_hw_cntrs_base_generic(hw);
1215
1216         /*
1217          * VLAN Offload Settings
1218          */
1219         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1220                         ETH_VLAN_EXTEND_MASK;
1221         eth_igb_vlan_offload_set(dev, mask);
1222
1223         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1224                 /* Enable VLAN filter since VMDq always use VLAN filter */
1225                 igb_vmdq_vlan_hw_filter_enable(dev);
1226         }
1227
1228         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1229                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1230                 (hw->mac.type == e1000_i211)) {
1231                 /* Configure EITR with the maximum possible value (0xFFFF) */
1232                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1233         }
1234
1235         /* Setup link speed and duplex */
1236         switch (dev->data->dev_conf.link_speed) {
1237         case ETH_LINK_SPEED_AUTONEG:
1238                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1239                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1240                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1241                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
1242                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1243                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
1244                 else
1245                         goto error_invalid_config;
1246                 break;
1247         case ETH_SPEED_NUM_10M:
1248                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1249                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
1250                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1251                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
1252                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1253                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
1254                 else
1255                         goto error_invalid_config;
1256                 break;
1257         case ETH_SPEED_NUM_100M:
1258                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1259                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
1260                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1261                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
1262                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1263                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
1264                 else
1265                         goto error_invalid_config;
1266                 break;
1267         case ETH_SPEED_NUM_1G:
1268                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
1269                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
1270                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
1271                 else
1272                         goto error_invalid_config;
1273                 break;
1274         case ETH_SPEED_NUM_10G:
1275         default:
1276                 goto error_invalid_config;
1277         }
1278         e1000_setup_link(hw);
1279
1280         if (rte_intr_allow_others(intr_handle)) {
1281                 /* check if lsc interrupt is enabled */
1282                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1283                         eth_igb_lsc_interrupt_setup(dev);
1284         } else {
1285                 rte_intr_callback_unregister(intr_handle,
1286                                              eth_igb_interrupt_handler,
1287                                              (void *)dev);
1288                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1289                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1290                                      " no intr multiplex\n");
1291         }
1292
1293         /* check if rxq interrupt is enabled */
1294         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1295             rte_intr_dp_is_en(intr_handle))
1296                 eth_igb_rxq_interrupt_setup(dev);
1297
1298         /* enable uio/vfio intr/eventfd mapping */
1299         rte_intr_enable(intr_handle);
1300
1301         /* resume enabled intr since hw reset */
1302         igb_intr_enable(dev);
1303
1304         PMD_INIT_LOG(DEBUG, "<<");
1305
1306         return 0;
1307
1308 error_invalid_config:
1309         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
1310                      dev->data->dev_conf.link_speed,
1311                      dev->data->dev_conf.link_duplex, dev->data->port_id);
1312         igb_dev_clear_queues(dev);
1313         return -EINVAL;
1314 }
1315
1316 /*********************************************************************
1317  *
1318  *  This routine disables all traffic on the adapter by issuing a
1319  *  global reset on the MAC.
1320  *
1321  **********************************************************************/
1322 static void
1323 eth_igb_stop(struct rte_eth_dev *dev)
1324 {
1325         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1326         struct e1000_filter_info *filter_info =
1327                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1328         struct rte_eth_link link;
1329         struct e1000_flex_filter *p_flex;
1330         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1331         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1332         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1333
1334         igb_intr_disable(hw);
1335
1336         /* disable intr eventfd mapping */
1337         rte_intr_disable(intr_handle);
1338
1339         igb_pf_reset_hw(hw);
1340         E1000_WRITE_REG(hw, E1000_WUC, 0);
1341
1342         /* Set bit for Go Link disconnect */
1343         if (hw->mac.type >= e1000_82580) {
1344                 uint32_t phpm_reg;
1345
1346                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1347                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1348                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1349         }
1350
1351         /* Power down the phy. Needed to make the link go Down */
1352         if (hw->phy.media_type == e1000_media_type_copper)
1353                 e1000_power_down_phy(hw);
1354         else
1355                 e1000_shutdown_fiber_serdes_link(hw);
1356
1357         igb_dev_clear_queues(dev);
1358
1359         /* clear the recorded link status */
1360         memset(&link, 0, sizeof(link));
1361         rte_igb_dev_atomic_write_link_status(dev, &link);
1362
1363         /* Remove all flex filters of the device */
1364         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1365                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1366                 rte_free(p_flex);
1367         }
1368         filter_info->flex_mask = 0;
1369
1370         /* Remove all ntuple filters of the device */
1371         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1372              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1373                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1374                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1375                              p_5tuple, entries);
1376                 rte_free(p_5tuple);
1377         }
1378         filter_info->fivetuple_mask = 0;
1379         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1380              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1381                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1382                 TAILQ_REMOVE(&filter_info->twotuple_list,
1383                              p_2tuple, entries);
1384                 rte_free(p_2tuple);
1385         }
1386         filter_info->twotuple_mask = 0;
1387
1388         if (!rte_intr_allow_others(intr_handle))
1389                 /* resume to the default handler */
1390                 rte_intr_callback_register(intr_handle,
1391                                            eth_igb_interrupt_handler,
1392                                            (void *)dev);
1393
1394         /* Clean datapath event and queue/vec mapping */
1395         rte_intr_efd_disable(intr_handle);
1396         if (intr_handle->intr_vec != NULL) {
1397                 rte_free(intr_handle->intr_vec);
1398                 intr_handle->intr_vec = NULL;
1399         }
1400 }
1401
1402 static void
1403 eth_igb_close(struct rte_eth_dev *dev)
1404 {
1405         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1406         struct e1000_adapter *adapter =
1407                 E1000_DEV_PRIVATE(dev->data->dev_private);
1408         struct rte_eth_link link;
1409         struct rte_pci_device *pci_dev;
1410
1411         eth_igb_stop(dev);
1412         adapter->stopped = 1;
1413
1414         e1000_phy_hw_reset(hw);
1415         igb_release_manageability(hw);
1416         igb_hw_control_release(hw);
1417
1418         /* Clear bit for Go Link disconnect */
1419         if (hw->mac.type >= e1000_82580) {
1420                 uint32_t phpm_reg;
1421
1422                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1423                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1424                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1425         }
1426
1427         igb_dev_free_queues(dev);
1428
1429         pci_dev = dev->pci_dev;
1430         if (pci_dev->intr_handle.intr_vec) {
1431                 rte_free(pci_dev->intr_handle.intr_vec);
1432                 pci_dev->intr_handle.intr_vec = NULL;
1433         }
1434
1435         memset(&link, 0, sizeof(link));
1436         rte_igb_dev_atomic_write_link_status(dev, &link);
1437 }
1438
1439 static int
1440 igb_get_rx_buffer_size(struct e1000_hw *hw)
1441 {
1442         uint32_t rx_buf_size;
1443         if (hw->mac.type == e1000_82576) {
1444                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1445         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1446                 /* PBS needs to be translated according to a lookup table */
1447                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1448                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1449                 rx_buf_size = (rx_buf_size << 10);
1450         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1451                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1452         } else {
1453                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1454         }
1455
1456         return rx_buf_size;
1457 }
1458
1459 /*********************************************************************
1460  *
1461  *  Initialize the hardware
1462  *
1463  **********************************************************************/
1464 static int
1465 igb_hardware_init(struct e1000_hw *hw)
1466 {
1467         uint32_t rx_buf_size;
1468         int diag;
1469
1470         /* Let the firmware know the OS is in control */
1471         igb_hw_control_acquire(hw);
1472
1473         /*
1474          * These parameters control the automatic generation (Tx) and
1475          * response (Rx) to Ethernet PAUSE frames.
1476          * - High water mark should allow for at least two standard size (1518)
1477          *   frames to be received after sending an XOFF.
1478          * - Low water mark works best when it is very near the high water mark.
1479          *   This allows the receiver to restart by sending XON when it has
1480          *   drained a bit. Here we use an arbitrary value of 1500 which will
1481          *   restart after one full frame is pulled from the buffer. There
1482          *   could be several smaller frames in the buffer and if so they will
1483          *   not trigger the XON until their total number reduces the buffer
1484          *   by 1500.
1485          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1486          */
1487         rx_buf_size = igb_get_rx_buffer_size(hw);
1488
1489         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1490         hw->fc.low_water = hw->fc.high_water - 1500;
1491         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1492         hw->fc.send_xon = 1;
1493
1494         /* Set Flow control, use the tunable location if sane */
1495         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1496                 hw->fc.requested_mode = igb_fc_setting;
1497         else
1498                 hw->fc.requested_mode = e1000_fc_none;
1499
1500         /* Issue a global reset */
1501         igb_pf_reset_hw(hw);
1502         E1000_WRITE_REG(hw, E1000_WUC, 0);
1503
1504         diag = e1000_init_hw(hw);
1505         if (diag < 0)
1506                 return diag;
1507
1508         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1509         e1000_get_phy_info(hw);
1510         e1000_check_for_link(hw);
1511
1512         return 0;
1513 }
1514
1515 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1516 static void
1517 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1518 {
1519         int pause_frames;
1520
1521         uint64_t old_gprc  = stats->gprc;
1522         uint64_t old_gptc  = stats->gptc;
1523         uint64_t old_tpr   = stats->tpr;
1524         uint64_t old_tpt   = stats->tpt;
1525         uint64_t old_rpthc = stats->rpthc;
1526         uint64_t old_hgptc = stats->hgptc;
1527
1528         if(hw->phy.media_type == e1000_media_type_copper ||
1529             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1530                 stats->symerrs +=
1531                     E1000_READ_REG(hw,E1000_SYMERRS);
1532                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1533         }
1534
1535         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1536         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1537         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1538         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1539
1540         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1541         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1542         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1543         stats->dc += E1000_READ_REG(hw, E1000_DC);
1544         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1545         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1546         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1547         /*
1548         ** For watchdog management we need to know if we have been
1549         ** paused during the last interval, so capture that here.
1550         */
1551         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1552         stats->xoffrxc += pause_frames;
1553         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1554         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1555         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1556         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1557         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1558         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1559         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1560         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1561         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1562         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1563         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1564         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1565
1566         /* For the 64-bit byte counters the low dword must be read first. */
1567         /* Both registers clear on the read of the high dword */
1568
1569         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1570         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1571         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1572         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1573         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1574         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1575         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1576
1577         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1578         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1579         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1580         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1581         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1582
1583         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1584         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1585
1586         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1587         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1588         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1589         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1590         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1591         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1592
1593         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1594         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1595         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1596         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1597         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1598         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1599         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1600         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1601
1602         /* Interrupt Counts */
1603
1604         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1605         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1606         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1607         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1608         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1609         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1610         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1611         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1612         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1613
1614         /* Host to Card Statistics */
1615
1616         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1617         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1618         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1619         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1620         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1621         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1622         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1623         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1624         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1625         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1626         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1627         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1628         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1629         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1630         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1631         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1632
1633         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1634         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1635         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1636         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1637         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1638         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1639 }
1640
1641 static void
1642 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1643 {
1644         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1645         struct e1000_hw_stats *stats =
1646                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1647
1648         igb_read_stats_registers(hw, stats);
1649
1650         if (rte_stats == NULL)
1651                 return;
1652
1653         /* Rx Errors */
1654         rte_stats->imissed = stats->mpc;
1655         rte_stats->ierrors = stats->crcerrs +
1656                              stats->rlec + stats->ruc + stats->roc +
1657                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1658
1659         /* Tx Errors */
1660         rte_stats->oerrors = stats->ecol + stats->latecol;
1661
1662         rte_stats->ipackets = stats->gprc;
1663         rte_stats->opackets = stats->gptc;
1664         rte_stats->ibytes   = stats->gorc;
1665         rte_stats->obytes   = stats->gotc;
1666 }
1667
1668 static void
1669 eth_igb_stats_reset(struct rte_eth_dev *dev)
1670 {
1671         struct e1000_hw_stats *hw_stats =
1672                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1673
1674         /* HW registers are cleared on read */
1675         eth_igb_stats_get(dev, NULL);
1676
1677         /* Reset software totals */
1678         memset(hw_stats, 0, sizeof(*hw_stats));
1679 }
1680
1681 static void
1682 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1683 {
1684         struct e1000_hw_stats *stats =
1685                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1686
1687         /* HW registers are cleared on read */
1688         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1689
1690         /* Reset software totals */
1691         memset(stats, 0, sizeof(*stats));
1692 }
1693
1694 static int
1695 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1696                    unsigned n)
1697 {
1698         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1699         struct e1000_hw_stats *hw_stats =
1700                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1701         unsigned i;
1702
1703         if (n < IGB_NB_XSTATS)
1704                 return IGB_NB_XSTATS;
1705
1706         igb_read_stats_registers(hw, hw_stats);
1707
1708         /* If this is a reset xstats is NULL, and we have cleared the
1709          * registers by reading them.
1710          */
1711         if (!xstats)
1712                 return 0;
1713
1714         /* Extended stats */
1715         for (i = 0; i < IGB_NB_XSTATS; i++) {
1716                 snprintf(xstats[i].name, sizeof(xstats[i].name),
1717                          "%s", rte_igb_stats_strings[i].name);
1718                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1719                         rte_igb_stats_strings[i].offset);
1720         }
1721
1722         return IGB_NB_XSTATS;
1723 }
1724
1725 static void
1726 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1727 {
1728         /* Good Rx packets, include VF loopback */
1729         UPDATE_VF_STAT(E1000_VFGPRC,
1730             hw_stats->last_gprc, hw_stats->gprc);
1731
1732         /* Good Rx octets, include VF loopback */
1733         UPDATE_VF_STAT(E1000_VFGORC,
1734             hw_stats->last_gorc, hw_stats->gorc);
1735
1736         /* Good Tx packets, include VF loopback */
1737         UPDATE_VF_STAT(E1000_VFGPTC,
1738             hw_stats->last_gptc, hw_stats->gptc);
1739
1740         /* Good Tx octets, include VF loopback */
1741         UPDATE_VF_STAT(E1000_VFGOTC,
1742             hw_stats->last_gotc, hw_stats->gotc);
1743
1744         /* Rx Multicst packets */
1745         UPDATE_VF_STAT(E1000_VFMPRC,
1746             hw_stats->last_mprc, hw_stats->mprc);
1747
1748         /* Good Rx loopback packets */
1749         UPDATE_VF_STAT(E1000_VFGPRLBC,
1750             hw_stats->last_gprlbc, hw_stats->gprlbc);
1751
1752         /* Good Rx loopback octets */
1753         UPDATE_VF_STAT(E1000_VFGORLBC,
1754             hw_stats->last_gorlbc, hw_stats->gorlbc);
1755
1756         /* Good Tx loopback packets */
1757         UPDATE_VF_STAT(E1000_VFGPTLBC,
1758             hw_stats->last_gptlbc, hw_stats->gptlbc);
1759
1760         /* Good Tx loopback octets */
1761         UPDATE_VF_STAT(E1000_VFGOTLBC,
1762             hw_stats->last_gotlbc, hw_stats->gotlbc);
1763 }
1764
1765 static int
1766 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1767                      unsigned n)
1768 {
1769         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1770         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1771                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1772         unsigned i;
1773
1774         if (n < IGBVF_NB_XSTATS)
1775                 return IGBVF_NB_XSTATS;
1776
1777         igbvf_read_stats_registers(hw, hw_stats);
1778
1779         if (!xstats)
1780                 return 0;
1781
1782         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1783                 snprintf(xstats[i].name, sizeof(xstats[i].name), "%s",
1784                          rte_igbvf_stats_strings[i].name);
1785                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1786                         rte_igbvf_stats_strings[i].offset);
1787         }
1788
1789         return IGBVF_NB_XSTATS;
1790 }
1791
1792 static void
1793 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1794 {
1795         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1796         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1797                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1798
1799         igbvf_read_stats_registers(hw, hw_stats);
1800
1801         if (rte_stats == NULL)
1802                 return;
1803
1804         rte_stats->ipackets = hw_stats->gprc;
1805         rte_stats->ibytes = hw_stats->gorc;
1806         rte_stats->opackets = hw_stats->gptc;
1807         rte_stats->obytes = hw_stats->gotc;
1808         rte_stats->imcasts = hw_stats->mprc;
1809         rte_stats->ilbpackets = hw_stats->gprlbc;
1810         rte_stats->ilbbytes = hw_stats->gorlbc;
1811         rte_stats->olbpackets = hw_stats->gptlbc;
1812         rte_stats->olbbytes = hw_stats->gotlbc;
1813 }
1814
1815 static void
1816 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1817 {
1818         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1819                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1820
1821         /* Sync HW register to the last stats */
1822         eth_igbvf_stats_get(dev, NULL);
1823
1824         /* reset HW current stats*/
1825         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1826                offsetof(struct e1000_vf_stats, gprc));
1827 }
1828
1829 static void
1830 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1831 {
1832         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1833
1834         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1835         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1836         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1837         dev_info->rx_offload_capa =
1838                 DEV_RX_OFFLOAD_VLAN_STRIP |
1839                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1840                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1841                 DEV_RX_OFFLOAD_TCP_CKSUM;
1842         dev_info->tx_offload_capa =
1843                 DEV_TX_OFFLOAD_VLAN_INSERT |
1844                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1845                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1846                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1847                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1848                 DEV_TX_OFFLOAD_TCP_TSO;
1849
1850         switch (hw->mac.type) {
1851         case e1000_82575:
1852                 dev_info->max_rx_queues = 4;
1853                 dev_info->max_tx_queues = 4;
1854                 dev_info->max_vmdq_pools = 0;
1855                 break;
1856
1857         case e1000_82576:
1858                 dev_info->max_rx_queues = 16;
1859                 dev_info->max_tx_queues = 16;
1860                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1861                 dev_info->vmdq_queue_num = 16;
1862                 break;
1863
1864         case e1000_82580:
1865                 dev_info->max_rx_queues = 8;
1866                 dev_info->max_tx_queues = 8;
1867                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1868                 dev_info->vmdq_queue_num = 8;
1869                 break;
1870
1871         case e1000_i350:
1872                 dev_info->max_rx_queues = 8;
1873                 dev_info->max_tx_queues = 8;
1874                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1875                 dev_info->vmdq_queue_num = 8;
1876                 break;
1877
1878         case e1000_i354:
1879                 dev_info->max_rx_queues = 8;
1880                 dev_info->max_tx_queues = 8;
1881                 break;
1882
1883         case e1000_i210:
1884                 dev_info->max_rx_queues = 4;
1885                 dev_info->max_tx_queues = 4;
1886                 dev_info->max_vmdq_pools = 0;
1887                 break;
1888
1889         case e1000_i211:
1890                 dev_info->max_rx_queues = 2;
1891                 dev_info->max_tx_queues = 2;
1892                 dev_info->max_vmdq_pools = 0;
1893                 break;
1894
1895         default:
1896                 /* Should not happen */
1897                 break;
1898         }
1899         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
1900         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
1901         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
1902
1903         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1904                 .rx_thresh = {
1905                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1906                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1907                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1908                 },
1909                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1910                 .rx_drop_en = 0,
1911         };
1912
1913         dev_info->default_txconf = (struct rte_eth_txconf) {
1914                 .tx_thresh = {
1915                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1916                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1917                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1918                 },
1919                 .txq_flags = 0,
1920         };
1921
1922         dev_info->rx_desc_lim = rx_desc_lim;
1923         dev_info->tx_desc_lim = tx_desc_lim;
1924
1925         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1926                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1927                         ETH_LINK_SPEED_1G;
1928 }
1929
1930 static const uint32_t *
1931 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
1932 {
1933         static const uint32_t ptypes[] = {
1934                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
1935                 RTE_PTYPE_L2_ETHER,
1936                 RTE_PTYPE_L3_IPV4,
1937                 RTE_PTYPE_L3_IPV4_EXT,
1938                 RTE_PTYPE_L3_IPV6,
1939                 RTE_PTYPE_L3_IPV6_EXT,
1940                 RTE_PTYPE_L4_TCP,
1941                 RTE_PTYPE_L4_UDP,
1942                 RTE_PTYPE_L4_SCTP,
1943                 RTE_PTYPE_TUNNEL_IP,
1944                 RTE_PTYPE_INNER_L3_IPV6,
1945                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1946                 RTE_PTYPE_INNER_L4_TCP,
1947                 RTE_PTYPE_INNER_L4_UDP,
1948                 RTE_PTYPE_UNKNOWN
1949         };
1950
1951         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
1952             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
1953                 return ptypes;
1954         return NULL;
1955 }
1956
1957 static void
1958 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1959 {
1960         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1961
1962         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1963         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1964         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1965         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
1966                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1967                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1968                                 DEV_RX_OFFLOAD_TCP_CKSUM;
1969         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
1970                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1971                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1972                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1973                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1974                                 DEV_TX_OFFLOAD_TCP_TSO;
1975         switch (hw->mac.type) {
1976         case e1000_vfadapt:
1977                 dev_info->max_rx_queues = 2;
1978                 dev_info->max_tx_queues = 2;
1979                 break;
1980         case e1000_vfadapt_i350:
1981                 dev_info->max_rx_queues = 1;
1982                 dev_info->max_tx_queues = 1;
1983                 break;
1984         default:
1985                 /* Should not happen */
1986                 break;
1987         }
1988
1989         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1990                 .rx_thresh = {
1991                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1992                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1993                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1994                 },
1995                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1996                 .rx_drop_en = 0,
1997         };
1998
1999         dev_info->default_txconf = (struct rte_eth_txconf) {
2000                 .tx_thresh = {
2001                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2002                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2003                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2004                 },
2005                 .txq_flags = 0,
2006         };
2007
2008         dev_info->rx_desc_lim = rx_desc_lim;
2009         dev_info->tx_desc_lim = tx_desc_lim;
2010 }
2011
2012 /* return 0 means link status changed, -1 means not changed */
2013 static int
2014 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2015 {
2016         struct e1000_hw *hw =
2017                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2018         struct rte_eth_link link, old;
2019         int link_check, count;
2020
2021         link_check = 0;
2022         hw->mac.get_link_status = 1;
2023
2024         /* possible wait-to-complete in up to 9 seconds */
2025         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2026                 /* Read the real link status */
2027                 switch (hw->phy.media_type) {
2028                 case e1000_media_type_copper:
2029                         /* Do the work to read phy */
2030                         e1000_check_for_link(hw);
2031                         link_check = !hw->mac.get_link_status;
2032                         break;
2033
2034                 case e1000_media_type_fiber:
2035                         e1000_check_for_link(hw);
2036                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2037                                       E1000_STATUS_LU);
2038                         break;
2039
2040                 case e1000_media_type_internal_serdes:
2041                         e1000_check_for_link(hw);
2042                         link_check = hw->mac.serdes_has_link;
2043                         break;
2044
2045                 /* VF device is type_unknown */
2046                 case e1000_media_type_unknown:
2047                         eth_igbvf_link_update(hw);
2048                         link_check = !hw->mac.get_link_status;
2049                         break;
2050
2051                 default:
2052                         break;
2053                 }
2054                 if (link_check || wait_to_complete == 0)
2055                         break;
2056                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2057         }
2058         memset(&link, 0, sizeof(link));
2059         rte_igb_dev_atomic_read_link_status(dev, &link);
2060         old = link;
2061
2062         /* Now we check if a transition has happened */
2063         if (link_check) {
2064                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
2065                                           &link.link_duplex);
2066                 link.link_status = ETH_LINK_UP;
2067         } else if (!link_check) {
2068                 link.link_speed = 0;
2069                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2070                 link.link_status = ETH_LINK_DOWN;
2071         }
2072         rte_igb_dev_atomic_write_link_status(dev, &link);
2073
2074         /* not changed */
2075         if (old.link_status == link.link_status)
2076                 return -1;
2077
2078         /* changed */
2079         return 0;
2080 }
2081
2082 /*
2083  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2084  * For ASF and Pass Through versions of f/w this means
2085  * that the driver is loaded.
2086  */
2087 static void
2088 igb_hw_control_acquire(struct e1000_hw *hw)
2089 {
2090         uint32_t ctrl_ext;
2091
2092         /* Let firmware know the driver has taken over */
2093         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2094         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2095 }
2096
2097 /*
2098  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2099  * For ASF and Pass Through versions of f/w this means that the
2100  * driver is no longer loaded.
2101  */
2102 static void
2103 igb_hw_control_release(struct e1000_hw *hw)
2104 {
2105         uint32_t ctrl_ext;
2106
2107         /* Let firmware taken over control of h/w */
2108         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2109         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2110                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2111 }
2112
2113 /*
2114  * Bit of a misnomer, what this really means is
2115  * to enable OS management of the system... aka
2116  * to disable special hardware management features.
2117  */
2118 static void
2119 igb_init_manageability(struct e1000_hw *hw)
2120 {
2121         if (e1000_enable_mng_pass_thru(hw)) {
2122                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2123                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2124
2125                 /* disable hardware interception of ARP */
2126                 manc &= ~(E1000_MANC_ARP_EN);
2127
2128                 /* enable receiving management packets to the host */
2129                 manc |= E1000_MANC_EN_MNG2HOST;
2130                 manc2h |= 1 << 5;  /* Mng Port 623 */
2131                 manc2h |= 1 << 6;  /* Mng Port 664 */
2132                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2133                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2134         }
2135 }
2136
2137 static void
2138 igb_release_manageability(struct e1000_hw *hw)
2139 {
2140         if (e1000_enable_mng_pass_thru(hw)) {
2141                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2142
2143                 manc |= E1000_MANC_ARP_EN;
2144                 manc &= ~E1000_MANC_EN_MNG2HOST;
2145
2146                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2147         }
2148 }
2149
2150 static void
2151 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2152 {
2153         struct e1000_hw *hw =
2154                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2155         uint32_t rctl;
2156
2157         rctl = E1000_READ_REG(hw, E1000_RCTL);
2158         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2159         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2160 }
2161
2162 static void
2163 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2164 {
2165         struct e1000_hw *hw =
2166                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2167         uint32_t rctl;
2168
2169         rctl = E1000_READ_REG(hw, E1000_RCTL);
2170         rctl &= (~E1000_RCTL_UPE);
2171         if (dev->data->all_multicast == 1)
2172                 rctl |= E1000_RCTL_MPE;
2173         else
2174                 rctl &= (~E1000_RCTL_MPE);
2175         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2176 }
2177
2178 static void
2179 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2180 {
2181         struct e1000_hw *hw =
2182                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2183         uint32_t rctl;
2184
2185         rctl = E1000_READ_REG(hw, E1000_RCTL);
2186         rctl |= E1000_RCTL_MPE;
2187         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2188 }
2189
2190 static void
2191 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2192 {
2193         struct e1000_hw *hw =
2194                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2195         uint32_t rctl;
2196
2197         if (dev->data->promiscuous == 1)
2198                 return; /* must remain in all_multicast mode */
2199         rctl = E1000_READ_REG(hw, E1000_RCTL);
2200         rctl &= (~E1000_RCTL_MPE);
2201         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2202 }
2203
2204 static int
2205 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2206 {
2207         struct e1000_hw *hw =
2208                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2209         struct e1000_vfta * shadow_vfta =
2210                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2211         uint32_t vfta;
2212         uint32_t vid_idx;
2213         uint32_t vid_bit;
2214
2215         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2216                               E1000_VFTA_ENTRY_MASK);
2217         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2218         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2219         if (on)
2220                 vfta |= vid_bit;
2221         else
2222                 vfta &= ~vid_bit;
2223         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2224
2225         /* update local VFTA copy */
2226         shadow_vfta->vfta[vid_idx] = vfta;
2227
2228         return 0;
2229 }
2230
2231 static int
2232 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2233                       enum rte_vlan_type vlan_type,
2234                       uint16_t tpid)
2235 {
2236         struct e1000_hw *hw =
2237                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2238         uint32_t reg = ETHER_TYPE_VLAN;
2239         int ret = 0;
2240
2241         switch (vlan_type) {
2242         case ETH_VLAN_TYPE_INNER:
2243                 reg |= (tpid << 16);
2244                 E1000_WRITE_REG(hw, E1000_VET, reg);
2245                 break;
2246         default:
2247                 ret = -EINVAL;
2248                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d\n", vlan_type);
2249                 break;
2250         }
2251
2252         return ret;
2253 }
2254
2255 static void
2256 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2257 {
2258         struct e1000_hw *hw =
2259                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2260         uint32_t reg;
2261
2262         /* Filter Table Disable */
2263         reg = E1000_READ_REG(hw, E1000_RCTL);
2264         reg &= ~E1000_RCTL_CFIEN;
2265         reg &= ~E1000_RCTL_VFE;
2266         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2267 }
2268
2269 static void
2270 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2271 {
2272         struct e1000_hw *hw =
2273                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2274         struct e1000_vfta * shadow_vfta =
2275                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2276         uint32_t reg;
2277         int i;
2278
2279         /* Filter Table Enable, CFI not used for packet acceptance */
2280         reg = E1000_READ_REG(hw, E1000_RCTL);
2281         reg &= ~E1000_RCTL_CFIEN;
2282         reg |= E1000_RCTL_VFE;
2283         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2284
2285         /* restore VFTA table */
2286         for (i = 0; i < IGB_VFTA_SIZE; i++)
2287                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2288 }
2289
2290 static void
2291 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2292 {
2293         struct e1000_hw *hw =
2294                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2295         uint32_t reg;
2296
2297         /* VLAN Mode Disable */
2298         reg = E1000_READ_REG(hw, E1000_CTRL);
2299         reg &= ~E1000_CTRL_VME;
2300         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2301 }
2302
2303 static void
2304 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2305 {
2306         struct e1000_hw *hw =
2307                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2308         uint32_t reg;
2309
2310         /* VLAN Mode Enable */
2311         reg = E1000_READ_REG(hw, E1000_CTRL);
2312         reg |= E1000_CTRL_VME;
2313         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2314 }
2315
2316 static void
2317 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2318 {
2319         struct e1000_hw *hw =
2320                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2321         uint32_t reg;
2322
2323         /* CTRL_EXT: Extended VLAN */
2324         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2325         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2326         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2327
2328         /* Update maximum packet length */
2329         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2330                 E1000_WRITE_REG(hw, E1000_RLPML,
2331                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2332                                                 VLAN_TAG_SIZE);
2333 }
2334
2335 static void
2336 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2337 {
2338         struct e1000_hw *hw =
2339                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2340         uint32_t reg;
2341
2342         /* CTRL_EXT: Extended VLAN */
2343         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2344         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2345         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2346
2347         /* Update maximum packet length */
2348         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2349                 E1000_WRITE_REG(hw, E1000_RLPML,
2350                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2351                                                 2 * VLAN_TAG_SIZE);
2352 }
2353
2354 static void
2355 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2356 {
2357         if(mask & ETH_VLAN_STRIP_MASK){
2358                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2359                         igb_vlan_hw_strip_enable(dev);
2360                 else
2361                         igb_vlan_hw_strip_disable(dev);
2362         }
2363
2364         if(mask & ETH_VLAN_FILTER_MASK){
2365                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2366                         igb_vlan_hw_filter_enable(dev);
2367                 else
2368                         igb_vlan_hw_filter_disable(dev);
2369         }
2370
2371         if(mask & ETH_VLAN_EXTEND_MASK){
2372                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2373                         igb_vlan_hw_extend_enable(dev);
2374                 else
2375                         igb_vlan_hw_extend_disable(dev);
2376         }
2377 }
2378
2379
2380 /**
2381  * It enables the interrupt mask and then enable the interrupt.
2382  *
2383  * @param dev
2384  *  Pointer to struct rte_eth_dev.
2385  *
2386  * @return
2387  *  - On success, zero.
2388  *  - On failure, a negative value.
2389  */
2390 static int
2391 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2392 {
2393         struct e1000_interrupt *intr =
2394                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2395
2396         intr->mask |= E1000_ICR_LSC;
2397
2398         return 0;
2399 }
2400
2401 /* It clears the interrupt causes and enables the interrupt.
2402  * It will be called once only during nic initialized.
2403  *
2404  * @param dev
2405  *  Pointer to struct rte_eth_dev.
2406  *
2407  * @return
2408  *  - On success, zero.
2409  *  - On failure, a negative value.
2410  */
2411 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2412 {
2413         uint32_t mask, regval;
2414         struct e1000_hw *hw =
2415                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2416         struct rte_eth_dev_info dev_info;
2417
2418         memset(&dev_info, 0, sizeof(dev_info));
2419         eth_igb_infos_get(dev, &dev_info);
2420
2421         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2422         regval = E1000_READ_REG(hw, E1000_EIMS);
2423         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2424
2425         return 0;
2426 }
2427
2428 /*
2429  * It reads ICR and gets interrupt causes, check it and set a bit flag
2430  * to update link status.
2431  *
2432  * @param dev
2433  *  Pointer to struct rte_eth_dev.
2434  *
2435  * @return
2436  *  - On success, zero.
2437  *  - On failure, a negative value.
2438  */
2439 static int
2440 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2441 {
2442         uint32_t icr;
2443         struct e1000_hw *hw =
2444                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2445         struct e1000_interrupt *intr =
2446                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2447
2448         igb_intr_disable(hw);
2449
2450         /* read-on-clear nic registers here */
2451         icr = E1000_READ_REG(hw, E1000_ICR);
2452
2453         intr->flags = 0;
2454         if (icr & E1000_ICR_LSC) {
2455                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2456         }
2457
2458         if (icr & E1000_ICR_VMMB)
2459                 intr->flags |= E1000_FLAG_MAILBOX;
2460
2461         return 0;
2462 }
2463
2464 /*
2465  * It executes link_update after knowing an interrupt is prsent.
2466  *
2467  * @param dev
2468  *  Pointer to struct rte_eth_dev.
2469  *
2470  * @return
2471  *  - On success, zero.
2472  *  - On failure, a negative value.
2473  */
2474 static int
2475 eth_igb_interrupt_action(struct rte_eth_dev *dev)
2476 {
2477         struct e1000_hw *hw =
2478                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2479         struct e1000_interrupt *intr =
2480                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2481         uint32_t tctl, rctl;
2482         struct rte_eth_link link;
2483         int ret;
2484
2485         if (intr->flags & E1000_FLAG_MAILBOX) {
2486                 igb_pf_mbx_process(dev);
2487                 intr->flags &= ~E1000_FLAG_MAILBOX;
2488         }
2489
2490         igb_intr_enable(dev);
2491         rte_intr_enable(&(dev->pci_dev->intr_handle));
2492
2493         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2494                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2495
2496                 /* set get_link_status to check register later */
2497                 hw->mac.get_link_status = 1;
2498                 ret = eth_igb_link_update(dev, 0);
2499
2500                 /* check if link has changed */
2501                 if (ret < 0)
2502                         return 0;
2503
2504                 memset(&link, 0, sizeof(link));
2505                 rte_igb_dev_atomic_read_link_status(dev, &link);
2506                 if (link.link_status) {
2507                         PMD_INIT_LOG(INFO,
2508                                      " Port %d: Link Up - speed %u Mbps - %s",
2509                                      dev->data->port_id,
2510                                      (unsigned)link.link_speed,
2511                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2512                                      "full-duplex" : "half-duplex");
2513                 } else {
2514                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2515                                      dev->data->port_id);
2516                 }
2517
2518                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2519                              dev->pci_dev->addr.domain,
2520                              dev->pci_dev->addr.bus,
2521                              dev->pci_dev->addr.devid,
2522                              dev->pci_dev->addr.function);
2523                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2524                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2525                 if (link.link_status) {
2526                         /* enable Tx/Rx */
2527                         tctl |= E1000_TCTL_EN;
2528                         rctl |= E1000_RCTL_EN;
2529                 } else {
2530                         /* disable Tx/Rx */
2531                         tctl &= ~E1000_TCTL_EN;
2532                         rctl &= ~E1000_RCTL_EN;
2533                 }
2534                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2535                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2536                 E1000_WRITE_FLUSH(hw);
2537                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2538         }
2539
2540         return 0;
2541 }
2542
2543 /**
2544  * Interrupt handler which shall be registered at first.
2545  *
2546  * @param handle
2547  *  Pointer to interrupt handle.
2548  * @param param
2549  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2550  *
2551  * @return
2552  *  void
2553  */
2554 static void
2555 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2556                                                         void *param)
2557 {
2558         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2559
2560         eth_igb_interrupt_get_status(dev);
2561         eth_igb_interrupt_action(dev);
2562 }
2563
2564 static int
2565 eth_igb_led_on(struct rte_eth_dev *dev)
2566 {
2567         struct e1000_hw *hw;
2568
2569         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2570         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2571 }
2572
2573 static int
2574 eth_igb_led_off(struct rte_eth_dev *dev)
2575 {
2576         struct e1000_hw *hw;
2577
2578         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2579         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2580 }
2581
2582 static int
2583 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2584 {
2585         struct e1000_hw *hw;
2586         uint32_t ctrl;
2587         int tx_pause;
2588         int rx_pause;
2589
2590         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2591         fc_conf->pause_time = hw->fc.pause_time;
2592         fc_conf->high_water = hw->fc.high_water;
2593         fc_conf->low_water = hw->fc.low_water;
2594         fc_conf->send_xon = hw->fc.send_xon;
2595         fc_conf->autoneg = hw->mac.autoneg;
2596
2597         /*
2598          * Return rx_pause and tx_pause status according to actual setting of
2599          * the TFCE and RFCE bits in the CTRL register.
2600          */
2601         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2602         if (ctrl & E1000_CTRL_TFCE)
2603                 tx_pause = 1;
2604         else
2605                 tx_pause = 0;
2606
2607         if (ctrl & E1000_CTRL_RFCE)
2608                 rx_pause = 1;
2609         else
2610                 rx_pause = 0;
2611
2612         if (rx_pause && tx_pause)
2613                 fc_conf->mode = RTE_FC_FULL;
2614         else if (rx_pause)
2615                 fc_conf->mode = RTE_FC_RX_PAUSE;
2616         else if (tx_pause)
2617                 fc_conf->mode = RTE_FC_TX_PAUSE;
2618         else
2619                 fc_conf->mode = RTE_FC_NONE;
2620
2621         return 0;
2622 }
2623
2624 static int
2625 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2626 {
2627         struct e1000_hw *hw;
2628         int err;
2629         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2630                 e1000_fc_none,
2631                 e1000_fc_rx_pause,
2632                 e1000_fc_tx_pause,
2633                 e1000_fc_full
2634         };
2635         uint32_t rx_buf_size;
2636         uint32_t max_high_water;
2637         uint32_t rctl;
2638
2639         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2640         if (fc_conf->autoneg != hw->mac.autoneg)
2641                 return -ENOTSUP;
2642         rx_buf_size = igb_get_rx_buffer_size(hw);
2643         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2644
2645         /* At least reserve one Ethernet frame for watermark */
2646         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2647         if ((fc_conf->high_water > max_high_water) ||
2648             (fc_conf->high_water < fc_conf->low_water)) {
2649                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2650                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2651                 return -EINVAL;
2652         }
2653
2654         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2655         hw->fc.pause_time     = fc_conf->pause_time;
2656         hw->fc.high_water     = fc_conf->high_water;
2657         hw->fc.low_water      = fc_conf->low_water;
2658         hw->fc.send_xon       = fc_conf->send_xon;
2659
2660         err = e1000_setup_link_generic(hw);
2661         if (err == E1000_SUCCESS) {
2662
2663                 /* check if we want to forward MAC frames - driver doesn't have native
2664                  * capability to do that, so we'll write the registers ourselves */
2665
2666                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2667
2668                 /* set or clear MFLCN.PMCF bit depending on configuration */
2669                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2670                         rctl |= E1000_RCTL_PMCF;
2671                 else
2672                         rctl &= ~E1000_RCTL_PMCF;
2673
2674                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2675                 E1000_WRITE_FLUSH(hw);
2676
2677                 return 0;
2678         }
2679
2680         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2681         return -EIO;
2682 }
2683
2684 #define E1000_RAH_POOLSEL_SHIFT      (18)
2685 static void
2686 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2687                 uint32_t index, __rte_unused uint32_t pool)
2688 {
2689         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2690         uint32_t rah;
2691
2692         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2693         rah = E1000_READ_REG(hw, E1000_RAH(index));
2694         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2695         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2696 }
2697
2698 static void
2699 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2700 {
2701         uint8_t addr[ETHER_ADDR_LEN];
2702         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2703
2704         memset(addr, 0, sizeof(addr));
2705
2706         e1000_rar_set(hw, addr, index);
2707 }
2708
2709 static void
2710 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2711                                 struct ether_addr *addr)
2712 {
2713         eth_igb_rar_clear(dev, 0);
2714
2715         eth_igb_rar_set(dev, (void *)addr, 0, 0);
2716 }
2717 /*
2718  * Virtual Function operations
2719  */
2720 static void
2721 igbvf_intr_disable(struct e1000_hw *hw)
2722 {
2723         PMD_INIT_FUNC_TRACE();
2724
2725         /* Clear interrupt mask to stop from interrupts being generated */
2726         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2727
2728         E1000_WRITE_FLUSH(hw);
2729 }
2730
2731 static void
2732 igbvf_stop_adapter(struct rte_eth_dev *dev)
2733 {
2734         u32 reg_val;
2735         u16 i;
2736         struct rte_eth_dev_info dev_info;
2737         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2738
2739         memset(&dev_info, 0, sizeof(dev_info));
2740         eth_igbvf_infos_get(dev, &dev_info);
2741
2742         /* Clear interrupt mask to stop from interrupts being generated */
2743         igbvf_intr_disable(hw);
2744
2745         /* Clear any pending interrupts, flush previous writes */
2746         E1000_READ_REG(hw, E1000_EICR);
2747
2748         /* Disable the transmit unit.  Each queue must be disabled. */
2749         for (i = 0; i < dev_info.max_tx_queues; i++)
2750                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2751
2752         /* Disable the receive unit by stopping each queue */
2753         for (i = 0; i < dev_info.max_rx_queues; i++) {
2754                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2755                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2756                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2757                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2758                         ;
2759         }
2760
2761         /* flush all queues disables */
2762         E1000_WRITE_FLUSH(hw);
2763         msec_delay(2);
2764 }
2765
2766 static int eth_igbvf_link_update(struct e1000_hw *hw)
2767 {
2768         struct e1000_mbx_info *mbx = &hw->mbx;
2769         struct e1000_mac_info *mac = &hw->mac;
2770         int ret_val = E1000_SUCCESS;
2771
2772         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2773
2774         /*
2775          * We only want to run this if there has been a rst asserted.
2776          * in this case that could mean a link change, device reset,
2777          * or a virtual function reset
2778          */
2779
2780         /* If we were hit with a reset or timeout drop the link */
2781         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2782                 mac->get_link_status = TRUE;
2783
2784         if (!mac->get_link_status)
2785                 goto out;
2786
2787         /* if link status is down no point in checking to see if pf is up */
2788         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2789                 goto out;
2790
2791         /* if we passed all the tests above then the link is up and we no
2792          * longer need to check for link */
2793         mac->get_link_status = FALSE;
2794
2795 out:
2796         return ret_val;
2797 }
2798
2799
2800 static int
2801 igbvf_dev_configure(struct rte_eth_dev *dev)
2802 {
2803         struct rte_eth_conf* conf = &dev->data->dev_conf;
2804
2805         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2806                      dev->data->port_id);
2807
2808         /*
2809          * VF has no ability to enable/disable HW CRC
2810          * Keep the persistent behavior the same as Host PF
2811          */
2812 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2813         if (!conf->rxmode.hw_strip_crc) {
2814                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
2815                 conf->rxmode.hw_strip_crc = 1;
2816         }
2817 #else
2818         if (conf->rxmode.hw_strip_crc) {
2819                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
2820                 conf->rxmode.hw_strip_crc = 0;
2821         }
2822 #endif
2823
2824         return 0;
2825 }
2826
2827 static int
2828 igbvf_dev_start(struct rte_eth_dev *dev)
2829 {
2830         struct e1000_hw *hw =
2831                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2832         struct e1000_adapter *adapter =
2833                 E1000_DEV_PRIVATE(dev->data->dev_private);
2834         int ret;
2835
2836         PMD_INIT_FUNC_TRACE();
2837
2838         hw->mac.ops.reset_hw(hw);
2839         adapter->stopped = 0;
2840
2841         /* Set all vfta */
2842         igbvf_set_vfta_all(dev,1);
2843
2844         eth_igbvf_tx_init(dev);
2845
2846         /* This can fail when allocating mbufs for descriptor rings */
2847         ret = eth_igbvf_rx_init(dev);
2848         if (ret) {
2849                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2850                 igb_dev_clear_queues(dev);
2851                 return ret;
2852         }
2853
2854         return 0;
2855 }
2856
2857 static void
2858 igbvf_dev_stop(struct rte_eth_dev *dev)
2859 {
2860         PMD_INIT_FUNC_TRACE();
2861
2862         igbvf_stop_adapter(dev);
2863
2864         /*
2865           * Clear what we set, but we still keep shadow_vfta to
2866           * restore after device starts
2867           */
2868         igbvf_set_vfta_all(dev,0);
2869
2870         igb_dev_clear_queues(dev);
2871 }
2872
2873 static void
2874 igbvf_dev_close(struct rte_eth_dev *dev)
2875 {
2876         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2877         struct e1000_adapter *adapter =
2878                 E1000_DEV_PRIVATE(dev->data->dev_private);
2879         struct ether_addr addr;
2880
2881         PMD_INIT_FUNC_TRACE();
2882
2883         e1000_reset_hw(hw);
2884
2885         igbvf_dev_stop(dev);
2886         adapter->stopped = 1;
2887         igb_dev_free_queues(dev);
2888
2889         /**
2890          * reprogram the RAR with a zero mac address,
2891          * to ensure that the VF traffic goes to the PF
2892          * after stop, close and detach of the VF.
2893          **/
2894
2895         memset(&addr, 0, sizeof(addr));
2896         igbvf_default_mac_addr_set(dev, &addr);
2897 }
2898
2899 static void
2900 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
2901 {
2902         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2903
2904         /* Set both unicast and multicast promisc */
2905         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
2906 }
2907
2908 static void
2909 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
2910 {
2911         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2912
2913         /* If in allmulticast mode leave multicast promisc */
2914         if (dev->data->all_multicast == 1)
2915                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
2916         else
2917                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
2918 }
2919
2920 static void
2921 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
2922 {
2923         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2924
2925         /* In promiscuous mode multicast promisc already set */
2926         if (dev->data->promiscuous == 0)
2927                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
2928 }
2929
2930 static void
2931 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
2932 {
2933         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2934
2935         /* In promiscuous mode leave multicast promisc enabled */
2936         if (dev->data->promiscuous == 0)
2937                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
2938 }
2939
2940 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2941 {
2942         struct e1000_mbx_info *mbx = &hw->mbx;
2943         uint32_t msgbuf[2];
2944         s32 err;
2945
2946         /* After set vlan, vlan strip will also be enabled in igb driver*/
2947         msgbuf[0] = E1000_VF_SET_VLAN;
2948         msgbuf[1] = vid;
2949         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2950         if (on)
2951                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2952
2953         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
2954         if (err)
2955                 goto mbx_err;
2956
2957         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
2958         if (err)
2959                 goto mbx_err;
2960
2961         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
2962         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
2963                 err = -EINVAL;
2964
2965 mbx_err:
2966         return err;
2967 }
2968
2969 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2970 {
2971         struct e1000_hw *hw =
2972                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2973         struct e1000_vfta * shadow_vfta =
2974                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2975         int i = 0, j = 0, vfta = 0, mask = 1;
2976
2977         for (i = 0; i < IGB_VFTA_SIZE; i++){
2978                 vfta = shadow_vfta->vfta[i];
2979                 if(vfta){
2980                         mask = 1;
2981                         for (j = 0; j < 32; j++){
2982                                 if(vfta & mask)
2983                                         igbvf_set_vfta(hw,
2984                                                 (uint16_t)((i<<5)+j), on);
2985                                 mask<<=1;
2986                         }
2987                 }
2988         }
2989
2990 }
2991
2992 static int
2993 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2994 {
2995         struct e1000_hw *hw =
2996                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2997         struct e1000_vfta * shadow_vfta =
2998                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2999         uint32_t vid_idx = 0;
3000         uint32_t vid_bit = 0;
3001         int ret = 0;
3002
3003         PMD_INIT_FUNC_TRACE();
3004
3005         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3006         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3007         if(ret){
3008                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3009                 return ret;
3010         }
3011         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3012         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3013
3014         /*Save what we set and retore it after device reset*/
3015         if (on)
3016                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3017         else
3018                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3019
3020         return 0;
3021 }
3022
3023 static void
3024 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3025 {
3026         struct e1000_hw *hw =
3027                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3028
3029         /* index is not used by rar_set() */
3030         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3031 }
3032
3033
3034 static int
3035 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3036                         struct rte_eth_rss_reta_entry64 *reta_conf,
3037                         uint16_t reta_size)
3038 {
3039         uint8_t i, j, mask;
3040         uint32_t reta, r;
3041         uint16_t idx, shift;
3042         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3043
3044         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3045                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3046                         "(%d) doesn't match the number hardware can supported "
3047                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3048                 return -EINVAL;
3049         }
3050
3051         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3052                 idx = i / RTE_RETA_GROUP_SIZE;
3053                 shift = i % RTE_RETA_GROUP_SIZE;
3054                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3055                                                 IGB_4_BIT_MASK);
3056                 if (!mask)
3057                         continue;
3058                 if (mask == IGB_4_BIT_MASK)
3059                         r = 0;
3060                 else
3061                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3062                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3063                         if (mask & (0x1 << j))
3064                                 reta |= reta_conf[idx].reta[shift + j] <<
3065                                                         (CHAR_BIT * j);
3066                         else
3067                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3068                 }
3069                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3070         }
3071
3072         return 0;
3073 }
3074
3075 static int
3076 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3077                        struct rte_eth_rss_reta_entry64 *reta_conf,
3078                        uint16_t reta_size)
3079 {
3080         uint8_t i, j, mask;
3081         uint32_t reta;
3082         uint16_t idx, shift;
3083         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3084
3085         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3086                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3087                         "(%d) doesn't match the number hardware can supported "
3088                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3089                 return -EINVAL;
3090         }
3091
3092         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3093                 idx = i / RTE_RETA_GROUP_SIZE;
3094                 shift = i % RTE_RETA_GROUP_SIZE;
3095                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3096                                                 IGB_4_BIT_MASK);
3097                 if (!mask)
3098                         continue;
3099                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3100                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3101                         if (mask & (0x1 << j))
3102                                 reta_conf[idx].reta[shift + j] =
3103                                         ((reta >> (CHAR_BIT * j)) &
3104                                                 IGB_8_BIT_MASK);
3105                 }
3106         }
3107
3108         return 0;
3109 }
3110
3111 #define MAC_TYPE_FILTER_SUP(type)    do {\
3112         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3113                 (type) != e1000_82576)\
3114                 return -ENOTSUP;\
3115 } while (0)
3116
3117 static int
3118 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3119                         struct rte_eth_syn_filter *filter,
3120                         bool add)
3121 {
3122         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3123         uint32_t synqf, rfctl;
3124
3125         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3126                 return -EINVAL;
3127
3128         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3129
3130         if (add) {
3131                 if (synqf & E1000_SYN_FILTER_ENABLE)
3132                         return -EINVAL;
3133
3134                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3135                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3136
3137                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3138                 if (filter->hig_pri)
3139                         rfctl |= E1000_RFCTL_SYNQFP;
3140                 else
3141                         rfctl &= ~E1000_RFCTL_SYNQFP;
3142
3143                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3144         } else {
3145                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3146                         return -ENOENT;
3147                 synqf = 0;
3148         }
3149
3150         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3151         E1000_WRITE_FLUSH(hw);
3152         return 0;
3153 }
3154
3155 static int
3156 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3157                         struct rte_eth_syn_filter *filter)
3158 {
3159         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3160         uint32_t synqf, rfctl;
3161
3162         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3163         if (synqf & E1000_SYN_FILTER_ENABLE) {
3164                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3165                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3166                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3167                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3168                 return 0;
3169         }
3170
3171         return -ENOENT;
3172 }
3173
3174 static int
3175 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3176                         enum rte_filter_op filter_op,
3177                         void *arg)
3178 {
3179         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3180         int ret;
3181
3182         MAC_TYPE_FILTER_SUP(hw->mac.type);
3183
3184         if (filter_op == RTE_ETH_FILTER_NOP)
3185                 return 0;
3186
3187         if (arg == NULL) {
3188                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3189                             filter_op);
3190                 return -EINVAL;
3191         }
3192
3193         switch (filter_op) {
3194         case RTE_ETH_FILTER_ADD:
3195                 ret = eth_igb_syn_filter_set(dev,
3196                                 (struct rte_eth_syn_filter *)arg,
3197                                 TRUE);
3198                 break;
3199         case RTE_ETH_FILTER_DELETE:
3200                 ret = eth_igb_syn_filter_set(dev,
3201                                 (struct rte_eth_syn_filter *)arg,
3202                                 FALSE);
3203                 break;
3204         case RTE_ETH_FILTER_GET:
3205                 ret = eth_igb_syn_filter_get(dev,
3206                                 (struct rte_eth_syn_filter *)arg);
3207                 break;
3208         default:
3209                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3210                 ret = -EINVAL;
3211                 break;
3212         }
3213
3214         return ret;
3215 }
3216
3217 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3218         if ((type) != e1000_82580 && (type) != e1000_i350)\
3219                 return -ENOSYS; \
3220 } while (0)
3221
3222 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3223 static inline int
3224 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3225                         struct e1000_2tuple_filter_info *filter_info)
3226 {
3227         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3228                 return -EINVAL;
3229         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3230                 return -EINVAL;  /* filter index is out of range. */
3231         if (filter->tcp_flags > TCP_FLAG_ALL)
3232                 return -EINVAL;  /* flags is invalid. */
3233
3234         switch (filter->dst_port_mask) {
3235         case UINT16_MAX:
3236                 filter_info->dst_port_mask = 0;
3237                 filter_info->dst_port = filter->dst_port;
3238                 break;
3239         case 0:
3240                 filter_info->dst_port_mask = 1;
3241                 break;
3242         default:
3243                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3244                 return -EINVAL;
3245         }
3246
3247         switch (filter->proto_mask) {
3248         case UINT8_MAX:
3249                 filter_info->proto_mask = 0;
3250                 filter_info->proto = filter->proto;
3251                 break;
3252         case 0:
3253                 filter_info->proto_mask = 1;
3254                 break;
3255         default:
3256                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3257                 return -EINVAL;
3258         }
3259
3260         filter_info->priority = (uint8_t)filter->priority;
3261         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3262                 filter_info->tcp_flags = filter->tcp_flags;
3263         else
3264                 filter_info->tcp_flags = 0;
3265
3266         return 0;
3267 }
3268
3269 static inline struct e1000_2tuple_filter *
3270 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3271                         struct e1000_2tuple_filter_info *key)
3272 {
3273         struct e1000_2tuple_filter *it;
3274
3275         TAILQ_FOREACH(it, filter_list, entries) {
3276                 if (memcmp(key, &it->filter_info,
3277                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3278                         return it;
3279                 }
3280         }
3281         return NULL;
3282 }
3283
3284 /*
3285  * igb_add_2tuple_filter - add a 2tuple filter
3286  *
3287  * @param
3288  * dev: Pointer to struct rte_eth_dev.
3289  * ntuple_filter: ponter to the filter that will be added.
3290  *
3291  * @return
3292  *    - On success, zero.
3293  *    - On failure, a negative value.
3294  */
3295 static int
3296 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3297                         struct rte_eth_ntuple_filter *ntuple_filter)
3298 {
3299         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3300         struct e1000_filter_info *filter_info =
3301                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3302         struct e1000_2tuple_filter *filter;
3303         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3304         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3305         int i, ret;
3306
3307         filter = rte_zmalloc("e1000_2tuple_filter",
3308                         sizeof(struct e1000_2tuple_filter), 0);
3309         if (filter == NULL)
3310                 return -ENOMEM;
3311
3312         ret = ntuple_filter_to_2tuple(ntuple_filter,
3313                                       &filter->filter_info);
3314         if (ret < 0) {
3315                 rte_free(filter);
3316                 return ret;
3317         }
3318         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3319                                          &filter->filter_info) != NULL) {
3320                 PMD_DRV_LOG(ERR, "filter exists.");
3321                 rte_free(filter);
3322                 return -EEXIST;
3323         }
3324         filter->queue = ntuple_filter->queue;
3325
3326         /*
3327          * look for an unused 2tuple filter index,
3328          * and insert the filter to list.
3329          */
3330         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3331                 if (!(filter_info->twotuple_mask & (1 << i))) {
3332                         filter_info->twotuple_mask |= 1 << i;
3333                         filter->index = i;
3334                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3335                                           filter,
3336                                           entries);
3337                         break;
3338                 }
3339         }
3340         if (i >= E1000_MAX_TTQF_FILTERS) {
3341                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3342                 rte_free(filter);
3343                 return -ENOSYS;
3344         }
3345
3346         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3347         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3348                 imir |= E1000_IMIR_PORT_BP;
3349         else
3350                 imir &= ~E1000_IMIR_PORT_BP;
3351
3352         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3353
3354         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3355         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3356         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3357         if (filter->filter_info.proto_mask == 0)
3358                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3359
3360         /* tcp flags bits setting. */
3361         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3362                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3363                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3364                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3365                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3366                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3367                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3368                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3369                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3370                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3371                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3372                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3373                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3374         } else
3375                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3376         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3377         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3378         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3379         return 0;
3380 }
3381
3382 /*
3383  * igb_remove_2tuple_filter - remove a 2tuple filter
3384  *
3385  * @param
3386  * dev: Pointer to struct rte_eth_dev.
3387  * ntuple_filter: ponter to the filter that will be removed.
3388  *
3389  * @return
3390  *    - On success, zero.
3391  *    - On failure, a negative value.
3392  */
3393 static int
3394 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3395                         struct rte_eth_ntuple_filter *ntuple_filter)
3396 {
3397         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3398         struct e1000_filter_info *filter_info =
3399                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3400         struct e1000_2tuple_filter_info filter_2tuple;
3401         struct e1000_2tuple_filter *filter;
3402         int ret;
3403
3404         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3405         ret = ntuple_filter_to_2tuple(ntuple_filter,
3406                                       &filter_2tuple);
3407         if (ret < 0)
3408                 return ret;
3409
3410         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3411                                          &filter_2tuple);
3412         if (filter == NULL) {
3413                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3414                 return -ENOENT;
3415         }
3416
3417         filter_info->twotuple_mask &= ~(1 << filter->index);
3418         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3419         rte_free(filter);
3420
3421         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3422         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3423         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3424         return 0;
3425 }
3426
3427 static inline struct e1000_flex_filter *
3428 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3429                         struct e1000_flex_filter_info *key)
3430 {
3431         struct e1000_flex_filter *it;
3432
3433         TAILQ_FOREACH(it, filter_list, entries) {
3434                 if (memcmp(key, &it->filter_info,
3435                         sizeof(struct e1000_flex_filter_info)) == 0)
3436                         return it;
3437         }
3438
3439         return NULL;
3440 }
3441
3442 static int
3443 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3444                         struct rte_eth_flex_filter *filter,
3445                         bool add)
3446 {
3447         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3448         struct e1000_filter_info *filter_info =
3449                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3450         struct e1000_flex_filter *flex_filter, *it;
3451         uint32_t wufc, queueing, mask;
3452         uint32_t reg_off;
3453         uint8_t shift, i, j = 0;
3454
3455         flex_filter = rte_zmalloc("e1000_flex_filter",
3456                         sizeof(struct e1000_flex_filter), 0);
3457         if (flex_filter == NULL)
3458                 return -ENOMEM;
3459
3460         flex_filter->filter_info.len = filter->len;
3461         flex_filter->filter_info.priority = filter->priority;
3462         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3463         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3464                 mask = 0;
3465                 /* reverse bits in flex filter's mask*/
3466                 for (shift = 0; shift < CHAR_BIT; shift++) {
3467                         if (filter->mask[i] & (0x01 << shift))
3468                                 mask |= (0x80 >> shift);
3469                 }
3470                 flex_filter->filter_info.mask[i] = mask;
3471         }
3472
3473         wufc = E1000_READ_REG(hw, E1000_WUFC);
3474         if (flex_filter->index < E1000_MAX_FHFT)
3475                 reg_off = E1000_FHFT(flex_filter->index);
3476         else
3477                 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3478
3479         if (add) {
3480                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3481                                 &flex_filter->filter_info) != NULL) {
3482                         PMD_DRV_LOG(ERR, "filter exists.");
3483                         rte_free(flex_filter);
3484                         return -EEXIST;
3485                 }
3486                 flex_filter->queue = filter->queue;
3487                 /*
3488                  * look for an unused flex filter index
3489                  * and insert the filter into the list.
3490                  */
3491                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3492                         if (!(filter_info->flex_mask & (1 << i))) {
3493                                 filter_info->flex_mask |= 1 << i;
3494                                 flex_filter->index = i;
3495                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3496                                         flex_filter,
3497                                         entries);
3498                                 break;
3499                         }
3500                 }
3501                 if (i >= E1000_MAX_FLEX_FILTERS) {
3502                         PMD_DRV_LOG(ERR, "flex filters are full.");
3503                         rte_free(flex_filter);
3504                         return -ENOSYS;
3505                 }
3506
3507                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3508                                 (E1000_WUFC_FLX0 << flex_filter->index));
3509                 queueing = filter->len |
3510                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3511                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3512                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3513                                 queueing);
3514                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3515                         E1000_WRITE_REG(hw, reg_off,
3516                                         flex_filter->filter_info.dwords[j]);
3517                         reg_off += sizeof(uint32_t);
3518                         E1000_WRITE_REG(hw, reg_off,
3519                                         flex_filter->filter_info.dwords[++j]);
3520                         reg_off += sizeof(uint32_t);
3521                         E1000_WRITE_REG(hw, reg_off,
3522                                 (uint32_t)flex_filter->filter_info.mask[i]);
3523                         reg_off += sizeof(uint32_t) * 2;
3524                         ++j;
3525                 }
3526         } else {
3527                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3528                                 &flex_filter->filter_info);
3529                 if (it == NULL) {
3530                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3531                         rte_free(flex_filter);
3532                         return -ENOENT;
3533                 }
3534
3535                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3536                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3537                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3538                         (~(E1000_WUFC_FLX0 << it->index)));
3539
3540                 filter_info->flex_mask &= ~(1 << it->index);
3541                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3542                 rte_free(it);
3543                 rte_free(flex_filter);
3544         }
3545
3546         return 0;
3547 }
3548
3549 static int
3550 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3551                         struct rte_eth_flex_filter *filter)
3552 {
3553         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3554         struct e1000_filter_info *filter_info =
3555                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3556         struct e1000_flex_filter flex_filter, *it;
3557         uint32_t wufc, queueing, wufc_en = 0;
3558
3559         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3560         flex_filter.filter_info.len = filter->len;
3561         flex_filter.filter_info.priority = filter->priority;
3562         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3563         memcpy(flex_filter.filter_info.mask, filter->mask,
3564                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3565
3566         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3567                                 &flex_filter.filter_info);
3568         if (it == NULL) {
3569                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3570                 return -ENOENT;
3571         }
3572
3573         wufc = E1000_READ_REG(hw, E1000_WUFC);
3574         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3575
3576         if ((wufc & wufc_en) == wufc_en) {
3577                 uint32_t reg_off = 0;
3578                 if (it->index < E1000_MAX_FHFT)
3579                         reg_off = E1000_FHFT(it->index);
3580                 else
3581                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3582
3583                 queueing = E1000_READ_REG(hw,
3584                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3585                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3586                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3587                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
3588                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3589                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3590                 return 0;
3591         }
3592         return -ENOENT;
3593 }
3594
3595 static int
3596 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3597                         enum rte_filter_op filter_op,
3598                         void *arg)
3599 {
3600         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3601         struct rte_eth_flex_filter *filter;
3602         int ret = 0;
3603
3604         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3605
3606         if (filter_op == RTE_ETH_FILTER_NOP)
3607                 return ret;
3608
3609         if (arg == NULL) {
3610                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3611                             filter_op);
3612                 return -EINVAL;
3613         }
3614
3615         filter = (struct rte_eth_flex_filter *)arg;
3616         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3617             || filter->len % sizeof(uint64_t) != 0) {
3618                 PMD_DRV_LOG(ERR, "filter's length is out of range");
3619                 return -EINVAL;
3620         }
3621         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3622                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3623                 return -EINVAL;
3624         }
3625
3626         switch (filter_op) {
3627         case RTE_ETH_FILTER_ADD:
3628                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3629                 break;
3630         case RTE_ETH_FILTER_DELETE:
3631                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3632                 break;
3633         case RTE_ETH_FILTER_GET:
3634                 ret = eth_igb_get_flex_filter(dev, filter);
3635                 break;
3636         default:
3637                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3638                 ret = -EINVAL;
3639                 break;
3640         }
3641
3642         return ret;
3643 }
3644
3645 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3646 static inline int
3647 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3648                         struct e1000_5tuple_filter_info *filter_info)
3649 {
3650         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3651                 return -EINVAL;
3652         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3653                 return -EINVAL;  /* filter index is out of range. */
3654         if (filter->tcp_flags > TCP_FLAG_ALL)
3655                 return -EINVAL;  /* flags is invalid. */
3656
3657         switch (filter->dst_ip_mask) {
3658         case UINT32_MAX:
3659                 filter_info->dst_ip_mask = 0;
3660                 filter_info->dst_ip = filter->dst_ip;
3661                 break;
3662         case 0:
3663                 filter_info->dst_ip_mask = 1;
3664                 break;
3665         default:
3666                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3667                 return -EINVAL;
3668         }
3669
3670         switch (filter->src_ip_mask) {
3671         case UINT32_MAX:
3672                 filter_info->src_ip_mask = 0;
3673                 filter_info->src_ip = filter->src_ip;
3674                 break;
3675         case 0:
3676                 filter_info->src_ip_mask = 1;
3677                 break;
3678         default:
3679                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3680                 return -EINVAL;
3681         }
3682
3683         switch (filter->dst_port_mask) {
3684         case UINT16_MAX:
3685                 filter_info->dst_port_mask = 0;
3686                 filter_info->dst_port = filter->dst_port;
3687                 break;
3688         case 0:
3689                 filter_info->dst_port_mask = 1;
3690                 break;
3691         default:
3692                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3693                 return -EINVAL;
3694         }
3695
3696         switch (filter->src_port_mask) {
3697         case UINT16_MAX:
3698                 filter_info->src_port_mask = 0;
3699                 filter_info->src_port = filter->src_port;
3700                 break;
3701         case 0:
3702                 filter_info->src_port_mask = 1;
3703                 break;
3704         default:
3705                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3706                 return -EINVAL;
3707         }
3708
3709         switch (filter->proto_mask) {
3710         case UINT8_MAX:
3711                 filter_info->proto_mask = 0;
3712                 filter_info->proto = filter->proto;
3713                 break;
3714         case 0:
3715                 filter_info->proto_mask = 1;
3716                 break;
3717         default:
3718                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3719                 return -EINVAL;
3720         }
3721
3722         filter_info->priority = (uint8_t)filter->priority;
3723         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3724                 filter_info->tcp_flags = filter->tcp_flags;
3725         else
3726                 filter_info->tcp_flags = 0;
3727
3728         return 0;
3729 }
3730
3731 static inline struct e1000_5tuple_filter *
3732 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
3733                         struct e1000_5tuple_filter_info *key)
3734 {
3735         struct e1000_5tuple_filter *it;
3736
3737         TAILQ_FOREACH(it, filter_list, entries) {
3738                 if (memcmp(key, &it->filter_info,
3739                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
3740                         return it;
3741                 }
3742         }
3743         return NULL;
3744 }
3745
3746 /*
3747  * igb_add_5tuple_filter_82576 - add a 5tuple filter
3748  *
3749  * @param
3750  * dev: Pointer to struct rte_eth_dev.
3751  * ntuple_filter: ponter to the filter that will be added.
3752  *
3753  * @return
3754  *    - On success, zero.
3755  *    - On failure, a negative value.
3756  */
3757 static int
3758 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
3759                         struct rte_eth_ntuple_filter *ntuple_filter)
3760 {
3761         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3762         struct e1000_filter_info *filter_info =
3763                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3764         struct e1000_5tuple_filter *filter;
3765         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
3766         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3767         uint8_t i;
3768         int ret;
3769
3770         filter = rte_zmalloc("e1000_5tuple_filter",
3771                         sizeof(struct e1000_5tuple_filter), 0);
3772         if (filter == NULL)
3773                 return -ENOMEM;
3774
3775         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3776                                             &filter->filter_info);
3777         if (ret < 0) {
3778                 rte_free(filter);
3779                 return ret;
3780         }
3781
3782         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3783                                          &filter->filter_info) != NULL) {
3784                 PMD_DRV_LOG(ERR, "filter exists.");
3785                 rte_free(filter);
3786                 return -EEXIST;
3787         }
3788         filter->queue = ntuple_filter->queue;
3789
3790         /*
3791          * look for an unused 5tuple filter index,
3792          * and insert the filter to list.
3793          */
3794         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
3795                 if (!(filter_info->fivetuple_mask & (1 << i))) {
3796                         filter_info->fivetuple_mask |= 1 << i;
3797                         filter->index = i;
3798                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3799                                           filter,
3800                                           entries);
3801                         break;
3802                 }
3803         }
3804         if (i >= E1000_MAX_FTQF_FILTERS) {
3805                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3806                 rte_free(filter);
3807                 return -ENOSYS;
3808         }
3809
3810         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
3811         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
3812                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
3813         if (filter->filter_info.dst_ip_mask == 0)
3814                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
3815         if (filter->filter_info.src_port_mask == 0)
3816                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
3817         if (filter->filter_info.proto_mask == 0)
3818                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
3819         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
3820                 E1000_FTQF_QUEUE_MASK;
3821         ftqf |= E1000_FTQF_QUEUE_ENABLE;
3822         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
3823         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
3824         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
3825
3826         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
3827         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
3828
3829         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3830         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3831                 imir |= E1000_IMIR_PORT_BP;
3832         else
3833                 imir &= ~E1000_IMIR_PORT_BP;
3834         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3835
3836         /* tcp flags bits setting. */
3837         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3838                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3839                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3840                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3841                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3842                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3843                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3844                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3845                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3846                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3847                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3848                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3849                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3850         } else
3851                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3852         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3853         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3854         return 0;
3855 }
3856
3857 /*
3858  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
3859  *
3860  * @param
3861  * dev: Pointer to struct rte_eth_dev.
3862  * ntuple_filter: ponter to the filter that will be removed.
3863  *
3864  * @return
3865  *    - On success, zero.
3866  *    - On failure, a negative value.
3867  */
3868 static int
3869 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
3870                                 struct rte_eth_ntuple_filter *ntuple_filter)
3871 {
3872         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3873         struct e1000_filter_info *filter_info =
3874                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3875         struct e1000_5tuple_filter_info filter_5tuple;
3876         struct e1000_5tuple_filter *filter;
3877         int ret;
3878
3879         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
3880         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3881                                             &filter_5tuple);
3882         if (ret < 0)
3883                 return ret;
3884
3885         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3886                                          &filter_5tuple);
3887         if (filter == NULL) {
3888                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3889                 return -ENOENT;
3890         }
3891
3892         filter_info->fivetuple_mask &= ~(1 << filter->index);
3893         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3894         rte_free(filter);
3895
3896         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
3897                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
3898         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
3899         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
3900         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
3901         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3902         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3903         return 0;
3904 }
3905
3906 static int
3907 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3908 {
3909         uint32_t rctl;
3910         struct e1000_hw *hw;
3911         struct rte_eth_dev_info dev_info;
3912         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3913                                      VLAN_TAG_SIZE);
3914
3915         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3916
3917 #ifdef RTE_LIBRTE_82571_SUPPORT
3918         /* XXX: not bigger than max_rx_pktlen */
3919         if (hw->mac.type == e1000_82571)
3920                 return -ENOTSUP;
3921 #endif
3922         eth_igb_infos_get(dev, &dev_info);
3923
3924         /* check that mtu is within the allowed range */
3925         if ((mtu < ETHER_MIN_MTU) ||
3926             (frame_size > dev_info.max_rx_pktlen))
3927                 return -EINVAL;
3928
3929         /* refuse mtu that requires the support of scattered packets when this
3930          * feature has not been enabled before. */
3931         if (!dev->data->scattered_rx &&
3932             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3933                 return -EINVAL;
3934
3935         rctl = E1000_READ_REG(hw, E1000_RCTL);
3936
3937         /* switch to jumbo mode if needed */
3938         if (frame_size > ETHER_MAX_LEN) {
3939                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3940                 rctl |= E1000_RCTL_LPE;
3941         } else {
3942                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3943                 rctl &= ~E1000_RCTL_LPE;
3944         }
3945         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3946
3947         /* update max frame size */
3948         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3949
3950         E1000_WRITE_REG(hw, E1000_RLPML,
3951                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
3952
3953         return 0;
3954 }
3955
3956 /*
3957  * igb_add_del_ntuple_filter - add or delete a ntuple filter
3958  *
3959  * @param
3960  * dev: Pointer to struct rte_eth_dev.
3961  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3962  * add: if true, add filter, if false, remove filter
3963  *
3964  * @return
3965  *    - On success, zero.
3966  *    - On failure, a negative value.
3967  */
3968 static int
3969 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
3970                         struct rte_eth_ntuple_filter *ntuple_filter,
3971                         bool add)
3972 {
3973         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3974         int ret;
3975
3976         switch (ntuple_filter->flags) {
3977         case RTE_5TUPLE_FLAGS:
3978         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3979                 if (hw->mac.type != e1000_82576)
3980                         return -ENOTSUP;
3981                 if (add)
3982                         ret = igb_add_5tuple_filter_82576(dev,
3983                                                           ntuple_filter);
3984                 else
3985                         ret = igb_remove_5tuple_filter_82576(dev,
3986                                                              ntuple_filter);
3987                 break;
3988         case RTE_2TUPLE_FLAGS:
3989         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3990                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3991                         return -ENOTSUP;
3992                 if (add)
3993                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
3994                 else
3995                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
3996                 break;
3997         default:
3998                 ret = -EINVAL;
3999                 break;
4000         }
4001
4002         return ret;
4003 }
4004
4005 /*
4006  * igb_get_ntuple_filter - get a ntuple filter
4007  *
4008  * @param
4009  * dev: Pointer to struct rte_eth_dev.
4010  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4011  *
4012  * @return
4013  *    - On success, zero.
4014  *    - On failure, a negative value.
4015  */
4016 static int
4017 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4018                         struct rte_eth_ntuple_filter *ntuple_filter)
4019 {
4020         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4021         struct e1000_filter_info *filter_info =
4022                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4023         struct e1000_5tuple_filter_info filter_5tuple;
4024         struct e1000_2tuple_filter_info filter_2tuple;
4025         struct e1000_5tuple_filter *p_5tuple_filter;
4026         struct e1000_2tuple_filter *p_2tuple_filter;
4027         int ret;
4028
4029         switch (ntuple_filter->flags) {
4030         case RTE_5TUPLE_FLAGS:
4031         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4032                 if (hw->mac.type != e1000_82576)
4033                         return -ENOTSUP;
4034                 memset(&filter_5tuple,
4035                         0,
4036                         sizeof(struct e1000_5tuple_filter_info));
4037                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4038                                                     &filter_5tuple);
4039                 if (ret < 0)
4040                         return ret;
4041                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4042                                         &filter_info->fivetuple_list,
4043                                         &filter_5tuple);
4044                 if (p_5tuple_filter == NULL) {
4045                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4046                         return -ENOENT;
4047                 }
4048                 ntuple_filter->queue = p_5tuple_filter->queue;
4049                 break;
4050         case RTE_2TUPLE_FLAGS:
4051         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4052                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4053                         return -ENOTSUP;
4054                 memset(&filter_2tuple,
4055                         0,
4056                         sizeof(struct e1000_2tuple_filter_info));
4057                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4058                 if (ret < 0)
4059                         return ret;
4060                 p_2tuple_filter = igb_2tuple_filter_lookup(
4061                                         &filter_info->twotuple_list,
4062                                         &filter_2tuple);
4063                 if (p_2tuple_filter == NULL) {
4064                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4065                         return -ENOENT;
4066                 }
4067                 ntuple_filter->queue = p_2tuple_filter->queue;
4068                 break;
4069         default:
4070                 ret = -EINVAL;
4071                 break;
4072         }
4073
4074         return 0;
4075 }
4076
4077 /*
4078  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4079  * @dev: pointer to rte_eth_dev structure
4080  * @filter_op:operation will be taken.
4081  * @arg: a pointer to specific structure corresponding to the filter_op
4082  */
4083 static int
4084 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4085                                 enum rte_filter_op filter_op,
4086                                 void *arg)
4087 {
4088         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4089         int ret;
4090
4091         MAC_TYPE_FILTER_SUP(hw->mac.type);
4092
4093         if (filter_op == RTE_ETH_FILTER_NOP)
4094                 return 0;
4095
4096         if (arg == NULL) {
4097                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4098                             filter_op);
4099                 return -EINVAL;
4100         }
4101
4102         switch (filter_op) {
4103         case RTE_ETH_FILTER_ADD:
4104                 ret = igb_add_del_ntuple_filter(dev,
4105                         (struct rte_eth_ntuple_filter *)arg,
4106                         TRUE);
4107                 break;
4108         case RTE_ETH_FILTER_DELETE:
4109                 ret = igb_add_del_ntuple_filter(dev,
4110                         (struct rte_eth_ntuple_filter *)arg,
4111                         FALSE);
4112                 break;
4113         case RTE_ETH_FILTER_GET:
4114                 ret = igb_get_ntuple_filter(dev,
4115                         (struct rte_eth_ntuple_filter *)arg);
4116                 break;
4117         default:
4118                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4119                 ret = -EINVAL;
4120                 break;
4121         }
4122         return ret;
4123 }
4124
4125 static inline int
4126 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4127                         uint16_t ethertype)
4128 {
4129         int i;
4130
4131         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4132                 if (filter_info->ethertype_filters[i] == ethertype &&
4133                     (filter_info->ethertype_mask & (1 << i)))
4134                         return i;
4135         }
4136         return -1;
4137 }
4138
4139 static inline int
4140 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4141                         uint16_t ethertype)
4142 {
4143         int i;
4144
4145         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4146                 if (!(filter_info->ethertype_mask & (1 << i))) {
4147                         filter_info->ethertype_mask |= 1 << i;
4148                         filter_info->ethertype_filters[i] = ethertype;
4149                         return i;
4150                 }
4151         }
4152         return -1;
4153 }
4154
4155 static inline int
4156 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4157                         uint8_t idx)
4158 {
4159         if (idx >= E1000_MAX_ETQF_FILTERS)
4160                 return -1;
4161         filter_info->ethertype_mask &= ~(1 << idx);
4162         filter_info->ethertype_filters[idx] = 0;
4163         return idx;
4164 }
4165
4166
4167 static int
4168 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4169                         struct rte_eth_ethertype_filter *filter,
4170                         bool add)
4171 {
4172         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4173         struct e1000_filter_info *filter_info =
4174                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4175         uint32_t etqf = 0;
4176         int ret;
4177
4178         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4179                 filter->ether_type == ETHER_TYPE_IPv6) {
4180                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4181                         " ethertype filter.", filter->ether_type);
4182                 return -EINVAL;
4183         }
4184
4185         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4186                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4187                 return -EINVAL;
4188         }
4189         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4190                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4191                 return -EINVAL;
4192         }
4193
4194         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4195         if (ret >= 0 && add) {
4196                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4197                             filter->ether_type);
4198                 return -EEXIST;
4199         }
4200         if (ret < 0 && !add) {
4201                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4202                             filter->ether_type);
4203                 return -ENOENT;
4204         }
4205
4206         if (add) {
4207                 ret = igb_ethertype_filter_insert(filter_info,
4208                         filter->ether_type);
4209                 if (ret < 0) {
4210                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4211                         return -ENOSYS;
4212                 }
4213
4214                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4215                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4216                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4217         } else {
4218                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4219                 if (ret < 0)
4220                         return -ENOSYS;
4221         }
4222         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4223         E1000_WRITE_FLUSH(hw);
4224
4225         return 0;
4226 }
4227
4228 static int
4229 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4230                         struct rte_eth_ethertype_filter *filter)
4231 {
4232         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4233         struct e1000_filter_info *filter_info =
4234                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4235         uint32_t etqf;
4236         int ret;
4237
4238         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4239         if (ret < 0) {
4240                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4241                             filter->ether_type);
4242                 return -ENOENT;
4243         }
4244
4245         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4246         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4247                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4248                 filter->flags = 0;
4249                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4250                                 E1000_ETQF_QUEUE_SHIFT;
4251                 return 0;
4252         }
4253
4254         return -ENOENT;
4255 }
4256
4257 /*
4258  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4259  * @dev: pointer to rte_eth_dev structure
4260  * @filter_op:operation will be taken.
4261  * @arg: a pointer to specific structure corresponding to the filter_op
4262  */
4263 static int
4264 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4265                                 enum rte_filter_op filter_op,
4266                                 void *arg)
4267 {
4268         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4269         int ret;
4270
4271         MAC_TYPE_FILTER_SUP(hw->mac.type);
4272
4273         if (filter_op == RTE_ETH_FILTER_NOP)
4274                 return 0;
4275
4276         if (arg == NULL) {
4277                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4278                             filter_op);
4279                 return -EINVAL;
4280         }
4281
4282         switch (filter_op) {
4283         case RTE_ETH_FILTER_ADD:
4284                 ret = igb_add_del_ethertype_filter(dev,
4285                         (struct rte_eth_ethertype_filter *)arg,
4286                         TRUE);
4287                 break;
4288         case RTE_ETH_FILTER_DELETE:
4289                 ret = igb_add_del_ethertype_filter(dev,
4290                         (struct rte_eth_ethertype_filter *)arg,
4291                         FALSE);
4292                 break;
4293         case RTE_ETH_FILTER_GET:
4294                 ret = igb_get_ethertype_filter(dev,
4295                         (struct rte_eth_ethertype_filter *)arg);
4296                 break;
4297         default:
4298                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4299                 ret = -EINVAL;
4300                 break;
4301         }
4302         return ret;
4303 }
4304
4305 static int
4306 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4307                      enum rte_filter_type filter_type,
4308                      enum rte_filter_op filter_op,
4309                      void *arg)
4310 {
4311         int ret = -EINVAL;
4312
4313         switch (filter_type) {
4314         case RTE_ETH_FILTER_NTUPLE:
4315                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4316                 break;
4317         case RTE_ETH_FILTER_ETHERTYPE:
4318                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4319                 break;
4320         case RTE_ETH_FILTER_SYN:
4321                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4322                 break;
4323         case RTE_ETH_FILTER_FLEXIBLE:
4324                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4325                 break;
4326         default:
4327                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4328                                                         filter_type);
4329                 break;
4330         }
4331
4332         return ret;
4333 }
4334
4335 static int
4336 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4337                          struct ether_addr *mc_addr_set,
4338                          uint32_t nb_mc_addr)
4339 {
4340         struct e1000_hw *hw;
4341
4342         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4343         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4344         return 0;
4345 }
4346
4347 static uint64_t
4348 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4349 {
4350         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4351         uint64_t systime_cycles;
4352
4353         switch (hw->mac.type) {
4354         case e1000_i210:
4355         case e1000_i211:
4356                 /*
4357                  * Need to read System Time Residue Register to be able
4358                  * to read the other two registers.
4359                  */
4360                 E1000_READ_REG(hw, E1000_SYSTIMR);
4361                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4362                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4363                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4364                                 * NSEC_PER_SEC;
4365                 break;
4366         case e1000_82580:
4367         case e1000_i350:
4368         case e1000_i354:
4369                 /*
4370                  * Need to read System Time Residue Register to be able
4371                  * to read the other two registers.
4372                  */
4373                 E1000_READ_REG(hw, E1000_SYSTIMR);
4374                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4375                 /* Only the 8 LSB are valid. */
4376                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4377                                 & 0xff) << 32;
4378                 break;
4379         default:
4380                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4381                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4382                                 << 32;
4383                 break;
4384         }
4385
4386         return systime_cycles;
4387 }
4388
4389 static uint64_t
4390 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4391 {
4392         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4393         uint64_t rx_tstamp_cycles;
4394
4395         switch (hw->mac.type) {
4396         case e1000_i210:
4397         case e1000_i211:
4398                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4399                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4400                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4401                                 * NSEC_PER_SEC;
4402                 break;
4403         case e1000_82580:
4404         case e1000_i350:
4405         case e1000_i354:
4406                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4407                 /* Only the 8 LSB are valid. */
4408                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4409                                 & 0xff) << 32;
4410                 break;
4411         default:
4412                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4413                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4414                                 << 32;
4415                 break;
4416         }
4417
4418         return rx_tstamp_cycles;
4419 }
4420
4421 static uint64_t
4422 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4423 {
4424         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4425         uint64_t tx_tstamp_cycles;
4426
4427         switch (hw->mac.type) {
4428         case e1000_i210:
4429         case e1000_i211:
4430                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4431                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4432                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4433                                 * NSEC_PER_SEC;
4434                 break;
4435         case e1000_82580:
4436         case e1000_i350:
4437         case e1000_i354:
4438                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4439                 /* Only the 8 LSB are valid. */
4440                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4441                                 & 0xff) << 32;
4442                 break;
4443         default:
4444                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4445                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4446                                 << 32;
4447                 break;
4448         }
4449
4450         return tx_tstamp_cycles;
4451 }
4452
4453 static void
4454 igb_start_timecounters(struct rte_eth_dev *dev)
4455 {
4456         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4457         struct e1000_adapter *adapter =
4458                 (struct e1000_adapter *)dev->data->dev_private;
4459         uint32_t incval = 1;
4460         uint32_t shift = 0;
4461         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4462
4463         switch (hw->mac.type) {
4464         case e1000_82580:
4465         case e1000_i350:
4466         case e1000_i354:
4467                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4468                 mask = (1ULL << 40) - 1;
4469                 /* fall-through */
4470         case e1000_i210:
4471         case e1000_i211:
4472                 /*
4473                  * Start incrementing the register
4474                  * used to timestamp PTP packets.
4475                  */
4476                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4477                 break;
4478         case e1000_82576:
4479                 incval = E1000_INCVALUE_82576;
4480                 shift = IGB_82576_TSYNC_SHIFT;
4481                 E1000_WRITE_REG(hw, E1000_TIMINCA,
4482                                 E1000_INCPERIOD_82576 | incval);
4483                 break;
4484         default:
4485                 /* Not supported */
4486                 return;
4487         }
4488
4489         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4490         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4491         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4492
4493         adapter->systime_tc.cc_mask = mask;
4494         adapter->systime_tc.cc_shift = shift;
4495         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4496
4497         adapter->rx_tstamp_tc.cc_mask = mask;
4498         adapter->rx_tstamp_tc.cc_shift = shift;
4499         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4500
4501         adapter->tx_tstamp_tc.cc_mask = mask;
4502         adapter->tx_tstamp_tc.cc_shift = shift;
4503         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4504 }
4505
4506 static int
4507 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4508 {
4509         struct e1000_adapter *adapter =
4510                         (struct e1000_adapter *)dev->data->dev_private;
4511
4512         adapter->systime_tc.nsec += delta;
4513         adapter->rx_tstamp_tc.nsec += delta;
4514         adapter->tx_tstamp_tc.nsec += delta;
4515
4516         return 0;
4517 }
4518
4519 static int
4520 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4521 {
4522         uint64_t ns;
4523         struct e1000_adapter *adapter =
4524                         (struct e1000_adapter *)dev->data->dev_private;
4525
4526         ns = rte_timespec_to_ns(ts);
4527
4528         /* Set the timecounters to a new value. */
4529         adapter->systime_tc.nsec = ns;
4530         adapter->rx_tstamp_tc.nsec = ns;
4531         adapter->tx_tstamp_tc.nsec = ns;
4532
4533         return 0;
4534 }
4535
4536 static int
4537 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4538 {
4539         uint64_t ns, systime_cycles;
4540         struct e1000_adapter *adapter =
4541                         (struct e1000_adapter *)dev->data->dev_private;
4542
4543         systime_cycles = igb_read_systime_cyclecounter(dev);
4544         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4545         *ts = rte_ns_to_timespec(ns);
4546
4547         return 0;
4548 }
4549
4550 static int
4551 igb_timesync_enable(struct rte_eth_dev *dev)
4552 {
4553         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4554         uint32_t tsync_ctl;
4555         uint32_t tsauxc;
4556
4557         /* Stop the timesync system time. */
4558         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4559         /* Reset the timesync system time value. */
4560         switch (hw->mac.type) {
4561         case e1000_82580:
4562         case e1000_i350:
4563         case e1000_i354:
4564         case e1000_i210:
4565         case e1000_i211:
4566                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4567                 /* fall-through */
4568         case e1000_82576:
4569                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4570                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4571                 break;
4572         default:
4573                 /* Not supported. */
4574                 return -ENOTSUP;
4575         }
4576
4577         /* Enable system time for it isn't on by default. */
4578         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4579         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4580         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4581
4582         igb_start_timecounters(dev);
4583
4584         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4585         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4586                         (ETHER_TYPE_1588 |
4587                          E1000_ETQF_FILTER_ENABLE |
4588                          E1000_ETQF_1588));
4589
4590         /* Enable timestamping of received PTP packets. */
4591         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4592         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4593         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4594
4595         /* Enable Timestamping of transmitted PTP packets. */
4596         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4597         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4598         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4599
4600         return 0;
4601 }
4602
4603 static int
4604 igb_timesync_disable(struct rte_eth_dev *dev)
4605 {
4606         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4607         uint32_t tsync_ctl;
4608
4609         /* Disable timestamping of transmitted PTP packets. */
4610         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4611         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4612         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4613
4614         /* Disable timestamping of received PTP packets. */
4615         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4616         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4617         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4618
4619         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4620         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4621
4622         /* Stop incrementating the System Time registers. */
4623         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4624
4625         return 0;
4626 }
4627
4628 static int
4629 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4630                                struct timespec *timestamp,
4631                                uint32_t flags __rte_unused)
4632 {
4633         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4634         struct e1000_adapter *adapter =
4635                         (struct e1000_adapter *)dev->data->dev_private;
4636         uint32_t tsync_rxctl;
4637         uint64_t rx_tstamp_cycles;
4638         uint64_t ns;
4639
4640         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4641         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4642                 return -EINVAL;
4643
4644         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4645         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4646         *timestamp = rte_ns_to_timespec(ns);
4647
4648         return  0;
4649 }
4650
4651 static int
4652 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4653                                struct timespec *timestamp)
4654 {
4655         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4656         struct e1000_adapter *adapter =
4657                         (struct e1000_adapter *)dev->data->dev_private;
4658         uint32_t tsync_txctl;
4659         uint64_t tx_tstamp_cycles;
4660         uint64_t ns;
4661
4662         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4663         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4664                 return -EINVAL;
4665
4666         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
4667         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4668         *timestamp = rte_ns_to_timespec(ns);
4669
4670         return  0;
4671 }
4672
4673 static int
4674 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4675 {
4676         int count = 0;
4677         int g_ind = 0;
4678         const struct reg_info *reg_group;
4679
4680         while ((reg_group = igb_regs[g_ind++]))
4681                 count += igb_reg_group_count(reg_group);
4682
4683         return count;
4684 }
4685
4686 static int
4687 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4688 {
4689         int count = 0;
4690         int g_ind = 0;
4691         const struct reg_info *reg_group;
4692
4693         while ((reg_group = igbvf_regs[g_ind++]))
4694                 count += igb_reg_group_count(reg_group);
4695
4696         return count;
4697 }
4698
4699 static int
4700 eth_igb_get_regs(struct rte_eth_dev *dev,
4701         struct rte_dev_reg_info *regs)
4702 {
4703         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4704         uint32_t *data = regs->data;
4705         int g_ind = 0;
4706         int count = 0;
4707         const struct reg_info *reg_group;
4708
4709         /* Support only full register dump */
4710         if ((regs->length == 0) ||
4711             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4712                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4713                         hw->device_id;
4714                 while ((reg_group = igb_regs[g_ind++]))
4715                         count += igb_read_regs_group(dev, &data[count],
4716                                                         reg_group);
4717                 return 0;
4718         }
4719
4720         return -ENOTSUP;
4721 }
4722
4723 static int
4724 igbvf_get_regs(struct rte_eth_dev *dev,
4725         struct rte_dev_reg_info *regs)
4726 {
4727         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4728         uint32_t *data = regs->data;
4729         int g_ind = 0;
4730         int count = 0;
4731         const struct reg_info *reg_group;
4732
4733         /* Support only full register dump */
4734         if ((regs->length == 0) ||
4735             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
4736                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4737                         hw->device_id;
4738                 while ((reg_group = igbvf_regs[g_ind++]))
4739                         count += igb_read_regs_group(dev, &data[count],
4740                                                         reg_group);
4741                 return 0;
4742         }
4743
4744         return -ENOTSUP;
4745 }
4746
4747 static int
4748 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
4749 {
4750         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4751
4752         /* Return unit is byte count */
4753         return hw->nvm.word_size * 2;
4754 }
4755
4756 static int
4757 eth_igb_get_eeprom(struct rte_eth_dev *dev,
4758         struct rte_dev_eeprom_info *in_eeprom)
4759 {
4760         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4761         struct e1000_nvm_info *nvm = &hw->nvm;
4762         uint16_t *data = in_eeprom->data;
4763         int first, length;
4764
4765         first = in_eeprom->offset >> 1;
4766         length = in_eeprom->length >> 1;
4767         if ((first >= hw->nvm.word_size) ||
4768             ((first + length) >= hw->nvm.word_size))
4769                 return -EINVAL;
4770
4771         in_eeprom->magic = hw->vendor_id |
4772                 ((uint32_t)hw->device_id << 16);
4773
4774         if ((nvm->ops.read) == NULL)
4775                 return -ENOTSUP;
4776
4777         return nvm->ops.read(hw, first, length, data);
4778 }
4779
4780 static int
4781 eth_igb_set_eeprom(struct rte_eth_dev *dev,
4782         struct rte_dev_eeprom_info *in_eeprom)
4783 {
4784         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4785         struct e1000_nvm_info *nvm = &hw->nvm;
4786         uint16_t *data = in_eeprom->data;
4787         int first, length;
4788
4789         first = in_eeprom->offset >> 1;
4790         length = in_eeprom->length >> 1;
4791         if ((first >= hw->nvm.word_size) ||
4792             ((first + length) >= hw->nvm.word_size))
4793                 return -EINVAL;
4794
4795         in_eeprom->magic = (uint32_t)hw->vendor_id |
4796                 ((uint32_t)hw->device_id << 16);
4797
4798         if ((nvm->ops.write) == NULL)
4799                 return -ENOTSUP;
4800         return nvm->ops.write(hw,  first, length, data);
4801 }
4802
4803 static struct rte_driver pmd_igb_drv = {
4804         .type = PMD_PDEV,
4805         .init = rte_igb_pmd_init,
4806 };
4807
4808 static struct rte_driver pmd_igbvf_drv = {
4809         .type = PMD_PDEV,
4810         .init = rte_igbvf_pmd_init,
4811 };
4812
4813 static int
4814 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4815 {
4816         struct e1000_hw *hw =
4817                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4818         uint32_t mask = 1 << queue_id;
4819
4820         E1000_WRITE_REG(hw, E1000_EIMC, mask);
4821         E1000_WRITE_FLUSH(hw);
4822
4823         return 0;
4824 }
4825
4826 static int
4827 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4828 {
4829         struct e1000_hw *hw =
4830                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4831         uint32_t mask = 1 << queue_id;
4832         uint32_t regval;
4833
4834         regval = E1000_READ_REG(hw, E1000_EIMS);
4835         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
4836         E1000_WRITE_FLUSH(hw);
4837
4838         rte_intr_enable(&dev->pci_dev->intr_handle);
4839
4840         return 0;
4841 }
4842
4843 static void
4844 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
4845                    uint8_t index, uint8_t offset)
4846 {
4847         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
4848
4849         /* clear bits */
4850         val &= ~((uint32_t)0xFF << offset);
4851
4852         /* write vector and valid bit */
4853         val |= (msix_vector | E1000_IVAR_VALID) << offset;
4854
4855         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
4856 }
4857
4858 static void
4859 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
4860                            uint8_t queue, uint8_t msix_vector)
4861 {
4862         uint32_t tmp = 0;
4863
4864         if (hw->mac.type == e1000_82575) {
4865                 if (direction == 0)
4866                         tmp = E1000_EICR_RX_QUEUE0 << queue;
4867                 else if (direction == 1)
4868                         tmp = E1000_EICR_TX_QUEUE0 << queue;
4869                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
4870         } else if (hw->mac.type == e1000_82576) {
4871                 if ((direction == 0) || (direction == 1))
4872                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
4873                                            ((queue & 0x8) << 1) +
4874                                            8 * direction);
4875         } else if ((hw->mac.type == e1000_82580) ||
4876                         (hw->mac.type == e1000_i350) ||
4877                         (hw->mac.type == e1000_i354) ||
4878                         (hw->mac.type == e1000_i210) ||
4879                         (hw->mac.type == e1000_i211)) {
4880                 if ((direction == 0) || (direction == 1))
4881                         eth_igb_write_ivar(hw, msix_vector,
4882                                            queue >> 1,
4883                                            ((queue & 0x1) << 4) +
4884                                            8 * direction);
4885         }
4886 }
4887
4888 /* Sets up the hardware to generate MSI-X interrupts properly
4889  * @hw
4890  *  board private structure
4891  */
4892 static void
4893 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
4894 {
4895         int queue_id;
4896         uint32_t tmpval, regval, intr_mask;
4897         struct e1000_hw *hw =
4898                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4899         uint32_t vec = E1000_MISC_VEC_ID;
4900         uint32_t base = E1000_MISC_VEC_ID;
4901         uint32_t misc_shift = 0;
4902
4903         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4904
4905         /* won't configure msix register if no mapping is done
4906          * between intr vector and event fd
4907          */
4908         if (!rte_intr_dp_is_en(intr_handle))
4909                 return;
4910
4911         if (rte_intr_allow_others(intr_handle)) {
4912                 vec = base = E1000_RX_VEC_START;
4913                 misc_shift = 1;
4914         }
4915
4916         /* set interrupt vector for other causes */
4917         if (hw->mac.type == e1000_82575) {
4918                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
4919                 /* enable MSI-X PBA support */
4920                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
4921
4922                 /* Auto-Mask interrupts upon ICR read */
4923                 tmpval |= E1000_CTRL_EXT_EIAME;
4924                 tmpval |= E1000_CTRL_EXT_IRCA;
4925
4926                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
4927
4928                 /* enable msix_other interrupt */
4929                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
4930                 regval = E1000_READ_REG(hw, E1000_EIAC);
4931                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
4932                 regval = E1000_READ_REG(hw, E1000_EIAM);
4933                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
4934         } else if ((hw->mac.type == e1000_82576) ||
4935                         (hw->mac.type == e1000_82580) ||
4936                         (hw->mac.type == e1000_i350) ||
4937                         (hw->mac.type == e1000_i354) ||
4938                         (hw->mac.type == e1000_i210) ||
4939                         (hw->mac.type == e1000_i211)) {
4940                 /* turn on MSI-X capability first */
4941                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
4942                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
4943                                         E1000_GPIE_NSICR);
4944                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
4945                         misc_shift;
4946                 regval = E1000_READ_REG(hw, E1000_EIAC);
4947                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
4948
4949                 /* enable msix_other interrupt */
4950                 regval = E1000_READ_REG(hw, E1000_EIMS);
4951                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
4952                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
4953                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
4954         }
4955
4956         /* use EIAM to auto-mask when MSI-X interrupt
4957          * is asserted, this saves a register write for every interrupt
4958          */
4959         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
4960                 misc_shift;
4961         regval = E1000_READ_REG(hw, E1000_EIAM);
4962         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
4963
4964         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
4965                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
4966                 intr_handle->intr_vec[queue_id] = vec;
4967                 if (vec < base + intr_handle->nb_efd - 1)
4968                         vec++;
4969         }
4970
4971         E1000_WRITE_FLUSH(hw);
4972 }
4973
4974 PMD_REGISTER_DRIVER(pmd_igb_drv);
4975 PMD_REGISTER_DRIVER(pmd_igbvf_drv);