1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
11 #include <rte_string_fns.h>
12 #include <rte_common.h>
13 #include <rte_interrupts.h>
14 #include <rte_byteorder.h>
16 #include <rte_debug.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
22 #include <rte_memory.h>
24 #include <rte_malloc.h>
27 #include "e1000_logs.h"
28 #include "base/e1000_api.h"
29 #include "e1000_ethdev.h"
33 * Default values for port configuration
35 #define IGB_DEFAULT_RX_FREE_THRESH 32
37 #define IGB_DEFAULT_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
38 #define IGB_DEFAULT_RX_HTHRESH 8
39 #define IGB_DEFAULT_RX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 4)
41 #define IGB_DEFAULT_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
42 #define IGB_DEFAULT_TX_HTHRESH 1
43 #define IGB_DEFAULT_TX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 16)
45 /* Bit shift and mask */
46 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
47 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
48 #define IGB_8_BIT_WIDTH CHAR_BIT
49 #define IGB_8_BIT_MASK UINT8_MAX
51 /* Additional timesync values. */
52 #define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL
53 #define E1000_ETQF_FILTER_1588 3
54 #define IGB_82576_TSYNC_SHIFT 16
55 #define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
56 #define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
57 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
59 #define E1000_VTIVAR_MISC 0x01740
60 #define E1000_VTIVAR_MISC_MASK 0xFF
61 #define E1000_VTIVAR_VALID 0x80
62 #define E1000_VTIVAR_MISC_MAILBOX 0
63 #define E1000_VTIVAR_MISC_INTR_MASK 0x3
65 /* External VLAN Enable bit mask */
66 #define E1000_CTRL_EXT_EXT_VLAN (1 << 26)
68 /* External VLAN Ether Type bit mask and shift */
69 #define E1000_VET_VET_EXT 0xFFFF0000
70 #define E1000_VET_VET_EXT_SHIFT 16
72 /* MSI-X other interrupt vector */
73 #define IGB_MSIX_OTHER_INTR_VEC 0
75 static int eth_igb_configure(struct rte_eth_dev *dev);
76 static int eth_igb_start(struct rte_eth_dev *dev);
77 static void eth_igb_stop(struct rte_eth_dev *dev);
78 static int eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
79 static int eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
80 static void eth_igb_close(struct rte_eth_dev *dev);
81 static int eth_igb_reset(struct rte_eth_dev *dev);
82 static int eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
83 static int eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
84 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
85 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
86 static int eth_igb_link_update(struct rte_eth_dev *dev,
87 int wait_to_complete);
88 static int eth_igb_stats_get(struct rte_eth_dev *dev,
89 struct rte_eth_stats *rte_stats);
90 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
91 struct rte_eth_xstat *xstats, unsigned n);
92 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
94 uint64_t *values, unsigned int n);
95 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
96 struct rte_eth_xstat_name *xstats_names,
98 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
99 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
101 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
102 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
103 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
104 char *fw_version, size_t fw_size);
105 static int eth_igb_infos_get(struct rte_eth_dev *dev,
106 struct rte_eth_dev_info *dev_info);
107 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
108 static int eth_igbvf_infos_get(struct rte_eth_dev *dev,
109 struct rte_eth_dev_info *dev_info);
110 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
111 struct rte_eth_fc_conf *fc_conf);
112 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
113 struct rte_eth_fc_conf *fc_conf);
114 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
115 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
116 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
117 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
118 struct rte_intr_handle *handle);
119 static void eth_igb_interrupt_handler(void *param);
120 static int igb_hardware_init(struct e1000_hw *hw);
121 static void igb_hw_control_acquire(struct e1000_hw *hw);
122 static void igb_hw_control_release(struct e1000_hw *hw);
123 static void igb_init_manageability(struct e1000_hw *hw);
124 static void igb_release_manageability(struct e1000_hw *hw);
126 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
128 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
129 uint16_t vlan_id, int on);
130 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
131 enum rte_vlan_type vlan_type,
133 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
135 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
136 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
137 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
138 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
139 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
140 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
142 static int eth_igb_led_on(struct rte_eth_dev *dev);
143 static int eth_igb_led_off(struct rte_eth_dev *dev);
145 static void igb_intr_disable(struct rte_eth_dev *dev);
146 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
147 static int eth_igb_rar_set(struct rte_eth_dev *dev,
148 struct rte_ether_addr *mac_addr,
149 uint32_t index, uint32_t pool);
150 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
151 static int eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
152 struct rte_ether_addr *addr);
154 static void igbvf_intr_disable(struct e1000_hw *hw);
155 static int igbvf_dev_configure(struct rte_eth_dev *dev);
156 static int igbvf_dev_start(struct rte_eth_dev *dev);
157 static void igbvf_dev_stop(struct rte_eth_dev *dev);
158 static void igbvf_dev_close(struct rte_eth_dev *dev);
159 static int igbvf_promiscuous_enable(struct rte_eth_dev *dev);
160 static int igbvf_promiscuous_disable(struct rte_eth_dev *dev);
161 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
162 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
163 static int eth_igbvf_link_update(struct e1000_hw *hw);
164 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
165 struct rte_eth_stats *rte_stats);
166 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
167 struct rte_eth_xstat *xstats, unsigned n);
168 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
169 struct rte_eth_xstat_name *xstats_names,
171 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
172 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
173 uint16_t vlan_id, int on);
174 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
175 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
176 static int igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
177 struct rte_ether_addr *addr);
178 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
179 static int igbvf_get_regs(struct rte_eth_dev *dev,
180 struct rte_dev_reg_info *regs);
182 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
183 struct rte_eth_rss_reta_entry64 *reta_conf,
185 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
186 struct rte_eth_rss_reta_entry64 *reta_conf,
189 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
190 struct rte_eth_syn_filter *filter);
191 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
192 enum rte_filter_op filter_op,
194 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
195 struct rte_eth_ntuple_filter *ntuple_filter);
196 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
197 struct rte_eth_ntuple_filter *ntuple_filter);
198 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
199 struct rte_eth_flex_filter *filter);
200 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
201 enum rte_filter_op filter_op,
203 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
204 struct rte_eth_ntuple_filter *ntuple_filter);
205 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
206 struct rte_eth_ntuple_filter *ntuple_filter);
207 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
208 struct rte_eth_ntuple_filter *filter);
209 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
210 enum rte_filter_op filter_op,
212 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
213 enum rte_filter_op filter_op,
215 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
216 struct rte_eth_ethertype_filter *filter);
217 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
218 enum rte_filter_type filter_type,
219 enum rte_filter_op filter_op,
221 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
222 static int eth_igb_get_regs(struct rte_eth_dev *dev,
223 struct rte_dev_reg_info *regs);
224 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
225 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
226 struct rte_dev_eeprom_info *eeprom);
227 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
228 struct rte_dev_eeprom_info *eeprom);
229 static int eth_igb_get_module_info(struct rte_eth_dev *dev,
230 struct rte_eth_dev_module_info *modinfo);
231 static int eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
232 struct rte_dev_eeprom_info *info);
233 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
234 struct rte_ether_addr *mc_addr_set,
235 uint32_t nb_mc_addr);
236 static int igb_timesync_enable(struct rte_eth_dev *dev);
237 static int igb_timesync_disable(struct rte_eth_dev *dev);
238 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
239 struct timespec *timestamp,
241 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
242 struct timespec *timestamp);
243 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
244 static int igb_timesync_read_time(struct rte_eth_dev *dev,
245 struct timespec *timestamp);
246 static int igb_timesync_write_time(struct rte_eth_dev *dev,
247 const struct timespec *timestamp);
248 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
250 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
252 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
253 uint8_t queue, uint8_t msix_vector);
254 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
255 uint8_t index, uint8_t offset);
256 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
257 static void eth_igbvf_interrupt_handler(void *param);
258 static void igbvf_mbx_process(struct rte_eth_dev *dev);
259 static int igb_filter_restore(struct rte_eth_dev *dev);
262 * Define VF Stats MACRO for Non "cleared on read" register
264 #define UPDATE_VF_STAT(reg, last, cur) \
266 u32 latest = E1000_READ_REG(hw, reg); \
267 cur += (latest - last) & UINT_MAX; \
271 #define IGB_FC_PAUSE_TIME 0x0680
272 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
273 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
275 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
277 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
280 * The set of PCI devices this driver supports
282 static const struct rte_pci_id pci_id_igb_map[] = {
283 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
284 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
285 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
286 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
287 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
288 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
289 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
290 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
292 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
293 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
294 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
296 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
297 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
298 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
299 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
300 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
301 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
303 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
304 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
305 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
306 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
307 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
308 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
309 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
310 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
311 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
312 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
313 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
314 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
315 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
316 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
317 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
318 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
319 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
320 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
321 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
322 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
323 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
324 { .vendor_id = 0, /* sentinel */ },
328 * The set of PCI devices this driver supports (for 82576&I350 VF)
330 static const struct rte_pci_id pci_id_igbvf_map[] = {
331 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
332 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
333 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
334 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
335 { .vendor_id = 0, /* sentinel */ },
338 static const struct rte_eth_desc_lim rx_desc_lim = {
339 .nb_max = E1000_MAX_RING_DESC,
340 .nb_min = E1000_MIN_RING_DESC,
341 .nb_align = IGB_RXD_ALIGN,
344 static const struct rte_eth_desc_lim tx_desc_lim = {
345 .nb_max = E1000_MAX_RING_DESC,
346 .nb_min = E1000_MIN_RING_DESC,
347 .nb_align = IGB_RXD_ALIGN,
348 .nb_seg_max = IGB_TX_MAX_SEG,
349 .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
352 static const struct eth_dev_ops eth_igb_ops = {
353 .dev_configure = eth_igb_configure,
354 .dev_start = eth_igb_start,
355 .dev_stop = eth_igb_stop,
356 .dev_set_link_up = eth_igb_dev_set_link_up,
357 .dev_set_link_down = eth_igb_dev_set_link_down,
358 .dev_close = eth_igb_close,
359 .dev_reset = eth_igb_reset,
360 .promiscuous_enable = eth_igb_promiscuous_enable,
361 .promiscuous_disable = eth_igb_promiscuous_disable,
362 .allmulticast_enable = eth_igb_allmulticast_enable,
363 .allmulticast_disable = eth_igb_allmulticast_disable,
364 .link_update = eth_igb_link_update,
365 .stats_get = eth_igb_stats_get,
366 .xstats_get = eth_igb_xstats_get,
367 .xstats_get_by_id = eth_igb_xstats_get_by_id,
368 .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
369 .xstats_get_names = eth_igb_xstats_get_names,
370 .stats_reset = eth_igb_stats_reset,
371 .xstats_reset = eth_igb_xstats_reset,
372 .fw_version_get = eth_igb_fw_version_get,
373 .dev_infos_get = eth_igb_infos_get,
374 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
375 .mtu_set = eth_igb_mtu_set,
376 .vlan_filter_set = eth_igb_vlan_filter_set,
377 .vlan_tpid_set = eth_igb_vlan_tpid_set,
378 .vlan_offload_set = eth_igb_vlan_offload_set,
379 .rx_queue_setup = eth_igb_rx_queue_setup,
380 .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
381 .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
382 .rx_queue_release = eth_igb_rx_queue_release,
383 .rx_queue_count = eth_igb_rx_queue_count,
384 .rx_descriptor_done = eth_igb_rx_descriptor_done,
385 .rx_descriptor_status = eth_igb_rx_descriptor_status,
386 .tx_descriptor_status = eth_igb_tx_descriptor_status,
387 .tx_queue_setup = eth_igb_tx_queue_setup,
388 .tx_queue_release = eth_igb_tx_queue_release,
389 .tx_done_cleanup = eth_igb_tx_done_cleanup,
390 .dev_led_on = eth_igb_led_on,
391 .dev_led_off = eth_igb_led_off,
392 .flow_ctrl_get = eth_igb_flow_ctrl_get,
393 .flow_ctrl_set = eth_igb_flow_ctrl_set,
394 .mac_addr_add = eth_igb_rar_set,
395 .mac_addr_remove = eth_igb_rar_clear,
396 .mac_addr_set = eth_igb_default_mac_addr_set,
397 .reta_update = eth_igb_rss_reta_update,
398 .reta_query = eth_igb_rss_reta_query,
399 .rss_hash_update = eth_igb_rss_hash_update,
400 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
401 .filter_ctrl = eth_igb_filter_ctrl,
402 .set_mc_addr_list = eth_igb_set_mc_addr_list,
403 .rxq_info_get = igb_rxq_info_get,
404 .txq_info_get = igb_txq_info_get,
405 .timesync_enable = igb_timesync_enable,
406 .timesync_disable = igb_timesync_disable,
407 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
408 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
409 .get_reg = eth_igb_get_regs,
410 .get_eeprom_length = eth_igb_get_eeprom_length,
411 .get_eeprom = eth_igb_get_eeprom,
412 .set_eeprom = eth_igb_set_eeprom,
413 .get_module_info = eth_igb_get_module_info,
414 .get_module_eeprom = eth_igb_get_module_eeprom,
415 .timesync_adjust_time = igb_timesync_adjust_time,
416 .timesync_read_time = igb_timesync_read_time,
417 .timesync_write_time = igb_timesync_write_time,
421 * dev_ops for virtual function, bare necessities for basic vf
422 * operation have been implemented
424 static const struct eth_dev_ops igbvf_eth_dev_ops = {
425 .dev_configure = igbvf_dev_configure,
426 .dev_start = igbvf_dev_start,
427 .dev_stop = igbvf_dev_stop,
428 .dev_close = igbvf_dev_close,
429 .promiscuous_enable = igbvf_promiscuous_enable,
430 .promiscuous_disable = igbvf_promiscuous_disable,
431 .allmulticast_enable = igbvf_allmulticast_enable,
432 .allmulticast_disable = igbvf_allmulticast_disable,
433 .link_update = eth_igb_link_update,
434 .stats_get = eth_igbvf_stats_get,
435 .xstats_get = eth_igbvf_xstats_get,
436 .xstats_get_names = eth_igbvf_xstats_get_names,
437 .stats_reset = eth_igbvf_stats_reset,
438 .xstats_reset = eth_igbvf_stats_reset,
439 .vlan_filter_set = igbvf_vlan_filter_set,
440 .dev_infos_get = eth_igbvf_infos_get,
441 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
442 .rx_queue_setup = eth_igb_rx_queue_setup,
443 .rx_queue_release = eth_igb_rx_queue_release,
444 .rx_descriptor_done = eth_igb_rx_descriptor_done,
445 .rx_descriptor_status = eth_igb_rx_descriptor_status,
446 .tx_descriptor_status = eth_igb_tx_descriptor_status,
447 .tx_queue_setup = eth_igb_tx_queue_setup,
448 .tx_queue_release = eth_igb_tx_queue_release,
449 .set_mc_addr_list = eth_igb_set_mc_addr_list,
450 .rxq_info_get = igb_rxq_info_get,
451 .txq_info_get = igb_txq_info_get,
452 .mac_addr_set = igbvf_default_mac_addr_set,
453 .get_reg = igbvf_get_regs,
456 /* store statistics names and its offset in stats structure */
457 struct rte_igb_xstats_name_off {
458 char name[RTE_ETH_XSTATS_NAME_SIZE];
462 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
463 {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
464 {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
465 {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
466 {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
467 {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
468 {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
469 {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
471 {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
472 {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
473 {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
474 {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
475 {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
476 {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
477 {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
478 {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
479 {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
480 {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
481 {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
483 {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
484 {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
485 {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
486 {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
487 {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
489 {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
491 {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
492 {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
493 {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
494 {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
495 {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
496 {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
497 {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
498 {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
499 {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
500 {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
501 {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
502 {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
503 {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
504 {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
505 {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
506 {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
507 {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
508 {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
510 {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
512 {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
513 {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
514 {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
515 {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
516 {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
517 {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
518 {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
520 {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
523 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
524 sizeof(rte_igb_stats_strings[0]))
526 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
527 {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
528 {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
529 {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
530 {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
531 {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
534 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
535 sizeof(rte_igbvf_stats_strings[0]))
539 igb_intr_enable(struct rte_eth_dev *dev)
541 struct e1000_interrupt *intr =
542 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
543 struct e1000_hw *hw =
544 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
545 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
546 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
548 if (rte_intr_allow_others(intr_handle) &&
549 dev->data->dev_conf.intr_conf.lsc != 0) {
550 E1000_WRITE_REG(hw, E1000_EIMS, 1 << IGB_MSIX_OTHER_INTR_VEC);
553 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
554 E1000_WRITE_FLUSH(hw);
558 igb_intr_disable(struct rte_eth_dev *dev)
560 struct e1000_hw *hw =
561 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
562 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
563 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
565 if (rte_intr_allow_others(intr_handle) &&
566 dev->data->dev_conf.intr_conf.lsc != 0) {
567 E1000_WRITE_REG(hw, E1000_EIMC, 1 << IGB_MSIX_OTHER_INTR_VEC);
570 E1000_WRITE_REG(hw, E1000_IMC, ~0);
571 E1000_WRITE_FLUSH(hw);
575 igbvf_intr_enable(struct rte_eth_dev *dev)
577 struct e1000_hw *hw =
578 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
580 /* only for mailbox */
581 E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
582 E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
583 E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
584 E1000_WRITE_FLUSH(hw);
587 /* only for mailbox now. If RX/TX needed, should extend this function. */
589 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
594 tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
595 tmp |= E1000_VTIVAR_VALID;
596 E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
600 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
602 struct e1000_hw *hw =
603 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
605 /* Configure VF other cause ivar */
606 igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
609 static inline int32_t
610 igb_pf_reset_hw(struct e1000_hw *hw)
615 status = e1000_reset_hw(hw);
617 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
618 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
619 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
620 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
621 E1000_WRITE_FLUSH(hw);
627 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
629 struct e1000_hw *hw =
630 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
633 hw->vendor_id = pci_dev->id.vendor_id;
634 hw->device_id = pci_dev->id.device_id;
635 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
636 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
638 e1000_set_mac_type(hw);
640 /* need to check if it is a vf device below */
644 igb_reset_swfw_lock(struct e1000_hw *hw)
649 * Do mac ops initialization manually here, since we will need
650 * some function pointers set by this call.
652 ret_val = e1000_init_mac_params(hw);
657 * SMBI lock should not fail in this early stage. If this is the case,
658 * it is due to an improper exit of the application.
659 * So force the release of the faulty lock.
661 if (e1000_get_hw_semaphore_generic(hw) < 0) {
662 PMD_DRV_LOG(DEBUG, "SMBI lock released");
664 e1000_put_hw_semaphore_generic(hw);
666 if (hw->mac.ops.acquire_swfw_sync != NULL) {
670 * Phy lock should not fail in this early stage. If this is the case,
671 * it is due to an improper exit of the application.
672 * So force the release of the faulty lock.
674 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
675 if (hw->bus.func > E1000_FUNC_1)
677 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
678 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
681 hw->mac.ops.release_swfw_sync(hw, mask);
684 * This one is more tricky since it is common to all ports; but
685 * swfw_sync retries last long enough (1s) to be almost sure that if
686 * lock can not be taken it is due to an improper lock of the
689 mask = E1000_SWFW_EEP_SM;
690 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
691 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
693 hw->mac.ops.release_swfw_sync(hw, mask);
696 return E1000_SUCCESS;
699 /* Remove all ntuple filters of the device */
700 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
702 struct e1000_filter_info *filter_info =
703 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
704 struct e1000_5tuple_filter *p_5tuple;
705 struct e1000_2tuple_filter *p_2tuple;
707 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
708 TAILQ_REMOVE(&filter_info->fivetuple_list,
712 filter_info->fivetuple_mask = 0;
713 while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
714 TAILQ_REMOVE(&filter_info->twotuple_list,
718 filter_info->twotuple_mask = 0;
723 /* Remove all flex filters of the device */
724 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
726 struct e1000_filter_info *filter_info =
727 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
728 struct e1000_flex_filter *p_flex;
730 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
731 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
734 filter_info->flex_mask = 0;
740 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
743 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
744 struct e1000_hw *hw =
745 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
746 struct e1000_vfta * shadow_vfta =
747 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
748 struct e1000_filter_info *filter_info =
749 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
750 struct e1000_adapter *adapter =
751 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
755 eth_dev->dev_ops = ð_igb_ops;
756 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
757 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
758 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
760 /* for secondary processes, we don't initialise any further as primary
761 * has already done this work. Only check we don't need a different
763 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
764 if (eth_dev->data->scattered_rx)
765 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
769 rte_eth_copy_pci_info(eth_dev, pci_dev);
771 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
773 igb_identify_hardware(eth_dev, pci_dev);
774 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
779 e1000_get_bus_info(hw);
781 /* Reset any pending lock */
782 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
787 /* Finish initialization */
788 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
794 hw->phy.autoneg_wait_to_complete = 0;
795 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
798 if (hw->phy.media_type == e1000_media_type_copper) {
799 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
800 hw->phy.disable_polarity_correction = 0;
801 hw->phy.ms_type = e1000_ms_hw_default;
805 * Start from a known state, this is important in reading the nvm
810 /* Make sure we have a good EEPROM before we read from it */
811 if (e1000_validate_nvm_checksum(hw) < 0) {
813 * Some PCI-E parts fail the first check due to
814 * the link being in sleep state, call it again,
815 * if it fails a second time its a real issue.
817 if (e1000_validate_nvm_checksum(hw) < 0) {
818 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
824 /* Read the permanent MAC address out of the EEPROM */
825 if (e1000_read_mac_addr(hw) != 0) {
826 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
831 /* Allocate memory for storing MAC addresses */
832 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
833 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
834 if (eth_dev->data->mac_addrs == NULL) {
835 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
836 "store MAC addresses",
837 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
842 /* Copy the permanent MAC address */
843 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
844 ð_dev->data->mac_addrs[0]);
846 /* initialize the vfta */
847 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
849 /* Now initialize the hardware */
850 if (igb_hardware_init(hw) != 0) {
851 PMD_INIT_LOG(ERR, "Hardware initialization failed");
852 rte_free(eth_dev->data->mac_addrs);
853 eth_dev->data->mac_addrs = NULL;
857 hw->mac.get_link_status = 1;
858 adapter->stopped = 0;
860 /* Indicate SOL/IDER usage */
861 if (e1000_check_reset_block(hw) < 0) {
862 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
866 /* initialize PF if max_vfs not zero */
867 igb_pf_host_init(eth_dev);
869 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
870 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
871 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
872 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
873 E1000_WRITE_FLUSH(hw);
875 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
876 eth_dev->data->port_id, pci_dev->id.vendor_id,
877 pci_dev->id.device_id);
879 rte_intr_callback_register(&pci_dev->intr_handle,
880 eth_igb_interrupt_handler,
883 /* enable uio/vfio intr/eventfd mapping */
884 rte_intr_enable(&pci_dev->intr_handle);
886 /* enable support intr */
887 igb_intr_enable(eth_dev);
889 /* initialize filter info */
890 memset(filter_info, 0,
891 sizeof(struct e1000_filter_info));
893 TAILQ_INIT(&filter_info->flex_list);
894 TAILQ_INIT(&filter_info->twotuple_list);
895 TAILQ_INIT(&filter_info->fivetuple_list);
897 TAILQ_INIT(&igb_filter_ntuple_list);
898 TAILQ_INIT(&igb_filter_ethertype_list);
899 TAILQ_INIT(&igb_filter_syn_list);
900 TAILQ_INIT(&igb_filter_flex_list);
901 TAILQ_INIT(&igb_filter_rss_list);
902 TAILQ_INIT(&igb_flow_list);
907 igb_hw_control_release(hw);
913 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
915 struct rte_pci_device *pci_dev;
916 struct rte_intr_handle *intr_handle;
918 struct e1000_adapter *adapter =
919 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
920 struct e1000_filter_info *filter_info =
921 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
923 PMD_INIT_FUNC_TRACE();
925 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
928 hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
929 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
930 intr_handle = &pci_dev->intr_handle;
932 if (adapter->stopped == 0)
933 eth_igb_close(eth_dev);
935 eth_dev->dev_ops = NULL;
936 eth_dev->rx_pkt_burst = NULL;
937 eth_dev->tx_pkt_burst = NULL;
939 /* Reset any pending lock */
940 igb_reset_swfw_lock(hw);
942 /* uninitialize PF if max_vfs not zero */
943 igb_pf_host_uninit(eth_dev);
945 /* disable uio intr before callback unregister */
946 rte_intr_disable(intr_handle);
947 rte_intr_callback_unregister(intr_handle,
948 eth_igb_interrupt_handler, eth_dev);
950 /* clear the SYN filter info */
951 filter_info->syn_info = 0;
953 /* clear the ethertype filters info */
954 filter_info->ethertype_mask = 0;
955 memset(filter_info->ethertype_filters, 0,
956 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
958 /* clear the rss filter info */
959 memset(&filter_info->rss_info, 0,
960 sizeof(struct igb_rte_flow_rss_conf));
962 /* remove all ntuple filters of the device */
963 igb_ntuple_filter_uninit(eth_dev);
965 /* remove all flex filters of the device */
966 igb_flex_filter_uninit(eth_dev);
968 /* clear all the filters list */
969 igb_filterlist_flush(eth_dev);
975 * Virtual Function device init
978 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
980 struct rte_pci_device *pci_dev;
981 struct rte_intr_handle *intr_handle;
982 struct e1000_adapter *adapter =
983 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
984 struct e1000_hw *hw =
985 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
987 struct rte_ether_addr *perm_addr =
988 (struct rte_ether_addr *)hw->mac.perm_addr;
990 PMD_INIT_FUNC_TRACE();
992 eth_dev->dev_ops = &igbvf_eth_dev_ops;
993 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
994 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
995 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
997 /* for secondary processes, we don't initialise any further as primary
998 * has already done this work. Only check we don't need a different
1000 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1001 if (eth_dev->data->scattered_rx)
1002 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
1006 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1007 rte_eth_copy_pci_info(eth_dev, pci_dev);
1009 hw->device_id = pci_dev->id.device_id;
1010 hw->vendor_id = pci_dev->id.vendor_id;
1011 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1012 adapter->stopped = 0;
1014 /* Initialize the shared code (base driver) */
1015 diag = e1000_setup_init_funcs(hw, TRUE);
1017 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
1022 /* init_mailbox_params */
1023 hw->mbx.ops.init_params(hw);
1025 /* Disable the interrupts for VF */
1026 igbvf_intr_disable(hw);
1028 diag = hw->mac.ops.reset_hw(hw);
1030 /* Allocate memory for storing MAC addresses */
1031 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", RTE_ETHER_ADDR_LEN *
1032 hw->mac.rar_entry_count, 0);
1033 if (eth_dev->data->mac_addrs == NULL) {
1035 "Failed to allocate %d bytes needed to store MAC "
1037 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1041 /* Generate a random MAC address, if none was assigned by PF. */
1042 if (rte_is_zero_ether_addr(perm_addr)) {
1043 rte_eth_random_addr(perm_addr->addr_bytes);
1044 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1045 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1046 "%02x:%02x:%02x:%02x:%02x:%02x",
1047 perm_addr->addr_bytes[0],
1048 perm_addr->addr_bytes[1],
1049 perm_addr->addr_bytes[2],
1050 perm_addr->addr_bytes[3],
1051 perm_addr->addr_bytes[4],
1052 perm_addr->addr_bytes[5]);
1055 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1057 rte_free(eth_dev->data->mac_addrs);
1058 eth_dev->data->mac_addrs = NULL;
1061 /* Copy the permanent MAC address */
1062 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1063 ð_dev->data->mac_addrs[0]);
1065 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1067 eth_dev->data->port_id, pci_dev->id.vendor_id,
1068 pci_dev->id.device_id, "igb_mac_82576_vf");
1070 intr_handle = &pci_dev->intr_handle;
1071 rte_intr_callback_register(intr_handle,
1072 eth_igbvf_interrupt_handler, eth_dev);
1078 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1080 struct e1000_adapter *adapter =
1081 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1082 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1084 PMD_INIT_FUNC_TRACE();
1086 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1089 if (adapter->stopped == 0)
1090 igbvf_dev_close(eth_dev);
1092 eth_dev->dev_ops = NULL;
1093 eth_dev->rx_pkt_burst = NULL;
1094 eth_dev->tx_pkt_burst = NULL;
1096 /* disable uio intr before callback unregister */
1097 rte_intr_disable(&pci_dev->intr_handle);
1098 rte_intr_callback_unregister(&pci_dev->intr_handle,
1099 eth_igbvf_interrupt_handler,
1105 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1106 struct rte_pci_device *pci_dev)
1108 return rte_eth_dev_pci_generic_probe(pci_dev,
1109 sizeof(struct e1000_adapter), eth_igb_dev_init);
1112 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1114 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1117 static struct rte_pci_driver rte_igb_pmd = {
1118 .id_table = pci_id_igb_map,
1119 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1120 .probe = eth_igb_pci_probe,
1121 .remove = eth_igb_pci_remove,
1125 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1126 struct rte_pci_device *pci_dev)
1128 return rte_eth_dev_pci_generic_probe(pci_dev,
1129 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1132 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1134 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1138 * virtual function driver struct
1140 static struct rte_pci_driver rte_igbvf_pmd = {
1141 .id_table = pci_id_igbvf_map,
1142 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1143 .probe = eth_igbvf_pci_probe,
1144 .remove = eth_igbvf_pci_remove,
1148 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1150 struct e1000_hw *hw =
1151 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1152 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1153 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1154 rctl |= E1000_RCTL_VFE;
1155 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1159 igb_check_mq_mode(struct rte_eth_dev *dev)
1161 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1162 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1163 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1164 uint16_t nb_tx_q = dev->data->nb_tx_queues;
1166 if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1167 tx_mq_mode == ETH_MQ_TX_DCB ||
1168 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1169 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1172 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1173 /* Check multi-queue mode.
1174 * To no break software we accept ETH_MQ_RX_NONE as this might
1175 * be used to turn off VLAN filter.
1178 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1179 rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1180 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1181 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1183 /* Only support one queue on VFs.
1184 * RSS together with SRIOV is not supported.
1186 PMD_INIT_LOG(ERR, "SRIOV is active,"
1187 " wrong mq_mode rx %d.",
1191 /* TX mode is not used here, so mode might be ignored.*/
1192 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1193 /* SRIOV only works in VMDq enable mode */
1194 PMD_INIT_LOG(WARNING, "SRIOV is active,"
1195 " TX mode %d is not supported. "
1196 " Driver will behave as %d mode.",
1197 tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1200 /* check valid queue number */
1201 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1202 PMD_INIT_LOG(ERR, "SRIOV is active,"
1203 " only support one queue on VFs.");
1207 /* To no break software that set invalid mode, only display
1208 * warning if invalid mode is used.
1210 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1211 rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1212 rx_mq_mode != ETH_MQ_RX_RSS) {
1213 /* RSS together with VMDq not supported*/
1214 PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1219 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1220 tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1221 PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1222 " Due to txmode is meaningless in this"
1223 " driver, just ignore.",
1231 eth_igb_configure(struct rte_eth_dev *dev)
1233 struct e1000_interrupt *intr =
1234 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1237 PMD_INIT_FUNC_TRACE();
1239 /* multipe queue mode checking */
1240 ret = igb_check_mq_mode(dev);
1242 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1247 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1248 PMD_INIT_FUNC_TRACE();
1254 eth_igb_rxtx_control(struct rte_eth_dev *dev,
1257 struct e1000_hw *hw =
1258 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1259 uint32_t tctl, rctl;
1261 tctl = E1000_READ_REG(hw, E1000_TCTL);
1262 rctl = E1000_READ_REG(hw, E1000_RCTL);
1266 tctl |= E1000_TCTL_EN;
1267 rctl |= E1000_RCTL_EN;
1270 tctl &= ~E1000_TCTL_EN;
1271 rctl &= ~E1000_RCTL_EN;
1273 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1274 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1275 E1000_WRITE_FLUSH(hw);
1279 eth_igb_start(struct rte_eth_dev *dev)
1281 struct e1000_hw *hw =
1282 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1283 struct e1000_adapter *adapter =
1284 E1000_DEV_PRIVATE(dev->data->dev_private);
1285 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1286 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1288 uint32_t intr_vector = 0;
1294 PMD_INIT_FUNC_TRACE();
1296 /* disable uio/vfio intr/eventfd mapping */
1297 rte_intr_disable(intr_handle);
1299 /* Power up the phy. Needed to make the link go Up */
1300 eth_igb_dev_set_link_up(dev);
1303 * Packet Buffer Allocation (PBA)
1304 * Writing PBA sets the receive portion of the buffer
1305 * the remainder is used for the transmit buffer.
1307 if (hw->mac.type == e1000_82575) {
1310 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1311 E1000_WRITE_REG(hw, E1000_PBA, pba);
1314 /* Put the address into the Receive Address Array */
1315 e1000_rar_set(hw, hw->mac.addr, 0);
1317 /* Initialize the hardware */
1318 if (igb_hardware_init(hw)) {
1319 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1322 adapter->stopped = 0;
1324 E1000_WRITE_REG(hw, E1000_VET,
1325 RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1327 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1328 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1329 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1330 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1331 E1000_WRITE_FLUSH(hw);
1333 /* configure PF module if SRIOV enabled */
1334 igb_pf_host_configure(dev);
1336 /* check and configure queue intr-vector mapping */
1337 if ((rte_intr_cap_multiple(intr_handle) ||
1338 !RTE_ETH_DEV_SRIOV(dev).active) &&
1339 dev->data->dev_conf.intr_conf.rxq != 0) {
1340 intr_vector = dev->data->nb_rx_queues;
1341 if (rte_intr_efd_enable(intr_handle, intr_vector))
1345 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1346 intr_handle->intr_vec =
1347 rte_zmalloc("intr_vec",
1348 dev->data->nb_rx_queues * sizeof(int), 0);
1349 if (intr_handle->intr_vec == NULL) {
1350 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1351 " intr_vec", dev->data->nb_rx_queues);
1356 /* confiugre msix for rx interrupt */
1357 eth_igb_configure_msix_intr(dev);
1359 /* Configure for OS presence */
1360 igb_init_manageability(hw);
1362 eth_igb_tx_init(dev);
1364 /* This can fail when allocating mbufs for descriptor rings */
1365 ret = eth_igb_rx_init(dev);
1367 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1368 igb_dev_clear_queues(dev);
1372 e1000_clear_hw_cntrs_base_generic(hw);
1375 * VLAN Offload Settings
1377 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1378 ETH_VLAN_EXTEND_MASK;
1379 ret = eth_igb_vlan_offload_set(dev, mask);
1381 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1382 igb_dev_clear_queues(dev);
1386 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1387 /* Enable VLAN filter since VMDq always use VLAN filter */
1388 igb_vmdq_vlan_hw_filter_enable(dev);
1391 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1392 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1393 (hw->mac.type == e1000_i211)) {
1394 /* Configure EITR with the maximum possible value (0xFFFF) */
1395 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1398 /* Setup link speed and duplex */
1399 speeds = &dev->data->dev_conf.link_speeds;
1400 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1401 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1402 hw->mac.autoneg = 1;
1405 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1408 hw->phy.autoneg_advertised = 0;
1410 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1411 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1412 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1414 goto error_invalid_config;
1416 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1417 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1420 if (*speeds & ETH_LINK_SPEED_10M) {
1421 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1424 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1425 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1428 if (*speeds & ETH_LINK_SPEED_100M) {
1429 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1432 if (*speeds & ETH_LINK_SPEED_1G) {
1433 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1436 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1437 goto error_invalid_config;
1439 /* Set/reset the mac.autoneg based on the link speed,
1443 hw->mac.autoneg = 0;
1444 hw->mac.forced_speed_duplex =
1445 hw->phy.autoneg_advertised;
1447 hw->mac.autoneg = 1;
1451 e1000_setup_link(hw);
1453 if (rte_intr_allow_others(intr_handle)) {
1454 /* check if lsc interrupt is enabled */
1455 if (dev->data->dev_conf.intr_conf.lsc != 0)
1456 eth_igb_lsc_interrupt_setup(dev, TRUE);
1458 eth_igb_lsc_interrupt_setup(dev, FALSE);
1460 rte_intr_callback_unregister(intr_handle,
1461 eth_igb_interrupt_handler,
1463 if (dev->data->dev_conf.intr_conf.lsc != 0)
1464 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1465 " no intr multiplex");
1468 /* check if rxq interrupt is enabled */
1469 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1470 rte_intr_dp_is_en(intr_handle))
1471 eth_igb_rxq_interrupt_setup(dev);
1473 /* enable uio/vfio intr/eventfd mapping */
1474 rte_intr_enable(intr_handle);
1476 /* resume enabled intr since hw reset */
1477 igb_intr_enable(dev);
1479 /* restore all types filter */
1480 igb_filter_restore(dev);
1482 eth_igb_rxtx_control(dev, true);
1483 eth_igb_link_update(dev, 0);
1485 PMD_INIT_LOG(DEBUG, "<<");
1489 error_invalid_config:
1490 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1491 dev->data->dev_conf.link_speeds, dev->data->port_id);
1492 igb_dev_clear_queues(dev);
1496 /*********************************************************************
1498 * This routine disables all traffic on the adapter by issuing a
1499 * global reset on the MAC.
1501 **********************************************************************/
1503 eth_igb_stop(struct rte_eth_dev *dev)
1505 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1506 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1507 struct rte_eth_link link;
1508 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1510 eth_igb_rxtx_control(dev, false);
1512 igb_intr_disable(dev);
1514 /* disable intr eventfd mapping */
1515 rte_intr_disable(intr_handle);
1517 igb_pf_reset_hw(hw);
1518 E1000_WRITE_REG(hw, E1000_WUC, 0);
1520 /* Set bit for Go Link disconnect */
1521 if (hw->mac.type >= e1000_82580) {
1524 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1525 phpm_reg |= E1000_82580_PM_GO_LINKD;
1526 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1529 /* Power down the phy. Needed to make the link go Down */
1530 eth_igb_dev_set_link_down(dev);
1532 igb_dev_clear_queues(dev);
1534 /* clear the recorded link status */
1535 memset(&link, 0, sizeof(link));
1536 rte_eth_linkstatus_set(dev, &link);
1538 if (!rte_intr_allow_others(intr_handle))
1539 /* resume to the default handler */
1540 rte_intr_callback_register(intr_handle,
1541 eth_igb_interrupt_handler,
1544 /* Clean datapath event and queue/vec mapping */
1545 rte_intr_efd_disable(intr_handle);
1546 if (intr_handle->intr_vec != NULL) {
1547 rte_free(intr_handle->intr_vec);
1548 intr_handle->intr_vec = NULL;
1553 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1555 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1557 if (hw->phy.media_type == e1000_media_type_copper)
1558 e1000_power_up_phy(hw);
1560 e1000_power_up_fiber_serdes_link(hw);
1566 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1568 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1570 if (hw->phy.media_type == e1000_media_type_copper)
1571 e1000_power_down_phy(hw);
1573 e1000_shutdown_fiber_serdes_link(hw);
1579 eth_igb_close(struct rte_eth_dev *dev)
1581 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1582 struct e1000_adapter *adapter =
1583 E1000_DEV_PRIVATE(dev->data->dev_private);
1584 struct rte_eth_link link;
1585 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1586 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1589 adapter->stopped = 1;
1591 e1000_phy_hw_reset(hw);
1592 igb_release_manageability(hw);
1593 igb_hw_control_release(hw);
1595 /* Clear bit for Go Link disconnect */
1596 if (hw->mac.type >= e1000_82580) {
1599 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1600 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1601 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1604 igb_dev_free_queues(dev);
1606 if (intr_handle->intr_vec) {
1607 rte_free(intr_handle->intr_vec);
1608 intr_handle->intr_vec = NULL;
1611 memset(&link, 0, sizeof(link));
1612 rte_eth_linkstatus_set(dev, &link);
1619 eth_igb_reset(struct rte_eth_dev *dev)
1623 /* When a DPDK PMD PF begin to reset PF port, it should notify all
1624 * its VF to make them align with it. The detailed notification
1625 * mechanism is PMD specific and is currently not implemented.
1626 * To avoid unexpected behavior in VF, currently reset of PF with
1627 * SR-IOV activation is not supported. It might be supported later.
1629 if (dev->data->sriov.active)
1632 ret = eth_igb_dev_uninit(dev);
1636 ret = eth_igb_dev_init(dev);
1643 igb_get_rx_buffer_size(struct e1000_hw *hw)
1645 uint32_t rx_buf_size;
1646 if (hw->mac.type == e1000_82576) {
1647 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1648 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1649 /* PBS needs to be translated according to a lookup table */
1650 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1651 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1652 rx_buf_size = (rx_buf_size << 10);
1653 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1654 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1656 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1662 /*********************************************************************
1664 * Initialize the hardware
1666 **********************************************************************/
1668 igb_hardware_init(struct e1000_hw *hw)
1670 uint32_t rx_buf_size;
1673 /* Let the firmware know the OS is in control */
1674 igb_hw_control_acquire(hw);
1677 * These parameters control the automatic generation (Tx) and
1678 * response (Rx) to Ethernet PAUSE frames.
1679 * - High water mark should allow for at least two standard size (1518)
1680 * frames to be received after sending an XOFF.
1681 * - Low water mark works best when it is very near the high water mark.
1682 * This allows the receiver to restart by sending XON when it has
1683 * drained a bit. Here we use an arbitrary value of 1500 which will
1684 * restart after one full frame is pulled from the buffer. There
1685 * could be several smaller frames in the buffer and if so they will
1686 * not trigger the XON until their total number reduces the buffer
1688 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1690 rx_buf_size = igb_get_rx_buffer_size(hw);
1692 hw->fc.high_water = rx_buf_size - (RTE_ETHER_MAX_LEN * 2);
1693 hw->fc.low_water = hw->fc.high_water - 1500;
1694 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1695 hw->fc.send_xon = 1;
1697 /* Set Flow control, use the tunable location if sane */
1698 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1699 hw->fc.requested_mode = igb_fc_setting;
1701 hw->fc.requested_mode = e1000_fc_none;
1703 /* Issue a global reset */
1704 igb_pf_reset_hw(hw);
1705 E1000_WRITE_REG(hw, E1000_WUC, 0);
1707 diag = e1000_init_hw(hw);
1711 E1000_WRITE_REG(hw, E1000_VET,
1712 RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1713 e1000_get_phy_info(hw);
1714 e1000_check_for_link(hw);
1719 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1721 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1725 uint64_t old_gprc = stats->gprc;
1726 uint64_t old_gptc = stats->gptc;
1727 uint64_t old_tpr = stats->tpr;
1728 uint64_t old_tpt = stats->tpt;
1729 uint64_t old_rpthc = stats->rpthc;
1730 uint64_t old_hgptc = stats->hgptc;
1732 if(hw->phy.media_type == e1000_media_type_copper ||
1733 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1735 E1000_READ_REG(hw,E1000_SYMERRS);
1736 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1739 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1740 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1741 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1742 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1744 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1745 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1746 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1747 stats->dc += E1000_READ_REG(hw, E1000_DC);
1748 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1749 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1750 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1752 ** For watchdog management we need to know if we have been
1753 ** paused during the last interval, so capture that here.
1755 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1756 stats->xoffrxc += pause_frames;
1757 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1758 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1759 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1760 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1761 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1762 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1763 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1764 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1765 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1766 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1767 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1768 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1770 /* For the 64-bit byte counters the low dword must be read first. */
1771 /* Both registers clear on the read of the high dword */
1773 /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1774 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1775 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1776 stats->gorc -= (stats->gprc - old_gprc) * RTE_ETHER_CRC_LEN;
1777 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1778 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1779 stats->gotc -= (stats->gptc - old_gptc) * RTE_ETHER_CRC_LEN;
1781 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1782 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1783 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1784 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1785 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1787 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1788 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1790 stats->tor += E1000_READ_REG(hw, E1000_TORL);
1791 stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1792 stats->tor -= (stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
1793 stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1794 stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1795 stats->tot -= (stats->tpt - old_tpt) * RTE_ETHER_CRC_LEN;
1797 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1798 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1799 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1800 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1801 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1802 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1803 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1804 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1806 /* Interrupt Counts */
1808 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1809 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1810 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1811 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1812 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1813 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1814 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1815 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1816 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1818 /* Host to Card Statistics */
1820 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1821 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1822 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1823 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1824 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1825 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1826 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1827 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1828 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1829 stats->hgorc -= (stats->rpthc - old_rpthc) * RTE_ETHER_CRC_LEN;
1830 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1831 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1832 stats->hgotc -= (stats->hgptc - old_hgptc) * RTE_ETHER_CRC_LEN;
1833 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1834 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1835 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1837 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1838 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1839 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1840 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1841 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1842 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1846 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1848 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1849 struct e1000_hw_stats *stats =
1850 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1852 igb_read_stats_registers(hw, stats);
1854 if (rte_stats == NULL)
1858 rte_stats->imissed = stats->mpc;
1859 rte_stats->ierrors = stats->crcerrs +
1860 stats->rlec + stats->ruc + stats->roc +
1861 stats->rxerrc + stats->algnerrc + stats->cexterr;
1864 rte_stats->oerrors = stats->ecol + stats->latecol;
1866 rte_stats->ipackets = stats->gprc;
1867 rte_stats->opackets = stats->gptc;
1868 rte_stats->ibytes = stats->gorc;
1869 rte_stats->obytes = stats->gotc;
1874 eth_igb_stats_reset(struct rte_eth_dev *dev)
1876 struct e1000_hw_stats *hw_stats =
1877 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1879 /* HW registers are cleared on read */
1880 eth_igb_stats_get(dev, NULL);
1882 /* Reset software totals */
1883 memset(hw_stats, 0, sizeof(*hw_stats));
1887 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1889 struct e1000_hw_stats *stats =
1890 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1892 /* HW registers are cleared on read */
1893 eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1895 /* Reset software totals */
1896 memset(stats, 0, sizeof(*stats));
1899 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1900 struct rte_eth_xstat_name *xstats_names,
1901 __rte_unused unsigned int size)
1905 if (xstats_names == NULL)
1906 return IGB_NB_XSTATS;
1908 /* Note: limit checked in rte_eth_xstats_names() */
1910 for (i = 0; i < IGB_NB_XSTATS; i++) {
1911 strlcpy(xstats_names[i].name, rte_igb_stats_strings[i].name,
1912 sizeof(xstats_names[i].name));
1915 return IGB_NB_XSTATS;
1918 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1919 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1925 if (xstats_names == NULL)
1926 return IGB_NB_XSTATS;
1928 for (i = 0; i < IGB_NB_XSTATS; i++)
1929 strlcpy(xstats_names[i].name,
1930 rte_igb_stats_strings[i].name,
1931 sizeof(xstats_names[i].name));
1933 return IGB_NB_XSTATS;
1936 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1938 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1941 for (i = 0; i < limit; i++) {
1942 if (ids[i] >= IGB_NB_XSTATS) {
1943 PMD_INIT_LOG(ERR, "id value isn't valid");
1946 strcpy(xstats_names[i].name,
1947 xstats_names_copy[ids[i]].name);
1954 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1957 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1958 struct e1000_hw_stats *hw_stats =
1959 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1962 if (n < IGB_NB_XSTATS)
1963 return IGB_NB_XSTATS;
1965 igb_read_stats_registers(hw, hw_stats);
1967 /* If this is a reset xstats is NULL, and we have cleared the
1968 * registers by reading them.
1973 /* Extended stats */
1974 for (i = 0; i < IGB_NB_XSTATS; i++) {
1976 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1977 rte_igb_stats_strings[i].offset);
1980 return IGB_NB_XSTATS;
1984 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1985 uint64_t *values, unsigned int n)
1990 struct e1000_hw *hw =
1991 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1992 struct e1000_hw_stats *hw_stats =
1993 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1995 if (n < IGB_NB_XSTATS)
1996 return IGB_NB_XSTATS;
1998 igb_read_stats_registers(hw, hw_stats);
2000 /* If this is a reset xstats is NULL, and we have cleared the
2001 * registers by reading them.
2006 /* Extended stats */
2007 for (i = 0; i < IGB_NB_XSTATS; i++)
2008 values[i] = *(uint64_t *)(((char *)hw_stats) +
2009 rte_igb_stats_strings[i].offset);
2011 return IGB_NB_XSTATS;
2014 uint64_t values_copy[IGB_NB_XSTATS];
2016 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
2019 for (i = 0; i < n; i++) {
2020 if (ids[i] >= IGB_NB_XSTATS) {
2021 PMD_INIT_LOG(ERR, "id value isn't valid");
2024 values[i] = values_copy[ids[i]];
2031 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2033 /* Good Rx packets, include VF loopback */
2034 UPDATE_VF_STAT(E1000_VFGPRC,
2035 hw_stats->last_gprc, hw_stats->gprc);
2037 /* Good Rx octets, include VF loopback */
2038 UPDATE_VF_STAT(E1000_VFGORC,
2039 hw_stats->last_gorc, hw_stats->gorc);
2041 /* Good Tx packets, include VF loopback */
2042 UPDATE_VF_STAT(E1000_VFGPTC,
2043 hw_stats->last_gptc, hw_stats->gptc);
2045 /* Good Tx octets, include VF loopback */
2046 UPDATE_VF_STAT(E1000_VFGOTC,
2047 hw_stats->last_gotc, hw_stats->gotc);
2049 /* Rx Multicst packets */
2050 UPDATE_VF_STAT(E1000_VFMPRC,
2051 hw_stats->last_mprc, hw_stats->mprc);
2053 /* Good Rx loopback packets */
2054 UPDATE_VF_STAT(E1000_VFGPRLBC,
2055 hw_stats->last_gprlbc, hw_stats->gprlbc);
2057 /* Good Rx loopback octets */
2058 UPDATE_VF_STAT(E1000_VFGORLBC,
2059 hw_stats->last_gorlbc, hw_stats->gorlbc);
2061 /* Good Tx loopback packets */
2062 UPDATE_VF_STAT(E1000_VFGPTLBC,
2063 hw_stats->last_gptlbc, hw_stats->gptlbc);
2065 /* Good Tx loopback octets */
2066 UPDATE_VF_STAT(E1000_VFGOTLBC,
2067 hw_stats->last_gotlbc, hw_stats->gotlbc);
2070 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2071 struct rte_eth_xstat_name *xstats_names,
2072 __rte_unused unsigned limit)
2076 if (xstats_names != NULL)
2077 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2078 strlcpy(xstats_names[i].name,
2079 rte_igbvf_stats_strings[i].name,
2080 sizeof(xstats_names[i].name));
2082 return IGBVF_NB_XSTATS;
2086 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2089 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2090 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2091 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2094 if (n < IGBVF_NB_XSTATS)
2095 return IGBVF_NB_XSTATS;
2097 igbvf_read_stats_registers(hw, hw_stats);
2102 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2104 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2105 rte_igbvf_stats_strings[i].offset);
2108 return IGBVF_NB_XSTATS;
2112 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2114 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2115 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2116 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2118 igbvf_read_stats_registers(hw, hw_stats);
2120 if (rte_stats == NULL)
2123 rte_stats->ipackets = hw_stats->gprc;
2124 rte_stats->ibytes = hw_stats->gorc;
2125 rte_stats->opackets = hw_stats->gptc;
2126 rte_stats->obytes = hw_stats->gotc;
2131 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2133 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2134 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2136 /* Sync HW register to the last stats */
2137 eth_igbvf_stats_get(dev, NULL);
2139 /* reset HW current stats*/
2140 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2141 offsetof(struct e1000_vf_stats, gprc));
2145 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2148 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2149 struct e1000_fw_version fw;
2152 e1000_get_fw_version(hw, &fw);
2154 switch (hw->mac.type) {
2157 if (!(e1000_get_flash_presence_i210(hw))) {
2158 ret = snprintf(fw_version, fw_size,
2160 fw.invm_major, fw.invm_minor,
2166 /* if option rom is valid, display its version too */
2168 ret = snprintf(fw_version, fw_size,
2169 "%d.%d, 0x%08x, %d.%d.%d",
2170 fw.eep_major, fw.eep_minor, fw.etrack_id,
2171 fw.or_major, fw.or_build, fw.or_patch);
2174 if (fw.etrack_id != 0X0000) {
2175 ret = snprintf(fw_version, fw_size,
2177 fw.eep_major, fw.eep_minor,
2180 ret = snprintf(fw_version, fw_size,
2182 fw.eep_major, fw.eep_minor,
2189 ret += 1; /* add the size of '\0' */
2190 if (fw_size < (u32)ret)
2197 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2199 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2201 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2202 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2203 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2204 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2205 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2206 dev_info->rx_queue_offload_capa;
2207 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2208 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2209 dev_info->tx_queue_offload_capa;
2211 switch (hw->mac.type) {
2213 dev_info->max_rx_queues = 4;
2214 dev_info->max_tx_queues = 4;
2215 dev_info->max_vmdq_pools = 0;
2219 dev_info->max_rx_queues = 16;
2220 dev_info->max_tx_queues = 16;
2221 dev_info->max_vmdq_pools = ETH_8_POOLS;
2222 dev_info->vmdq_queue_num = 16;
2226 dev_info->max_rx_queues = 8;
2227 dev_info->max_tx_queues = 8;
2228 dev_info->max_vmdq_pools = ETH_8_POOLS;
2229 dev_info->vmdq_queue_num = 8;
2233 dev_info->max_rx_queues = 8;
2234 dev_info->max_tx_queues = 8;
2235 dev_info->max_vmdq_pools = ETH_8_POOLS;
2236 dev_info->vmdq_queue_num = 8;
2240 dev_info->max_rx_queues = 8;
2241 dev_info->max_tx_queues = 8;
2245 dev_info->max_rx_queues = 4;
2246 dev_info->max_tx_queues = 4;
2247 dev_info->max_vmdq_pools = 0;
2251 dev_info->max_rx_queues = 2;
2252 dev_info->max_tx_queues = 2;
2253 dev_info->max_vmdq_pools = 0;
2257 /* Should not happen */
2260 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2261 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2262 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2264 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2266 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2267 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2268 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2270 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2275 dev_info->default_txconf = (struct rte_eth_txconf) {
2277 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2278 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2279 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2284 dev_info->rx_desc_lim = rx_desc_lim;
2285 dev_info->tx_desc_lim = tx_desc_lim;
2287 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2288 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2291 dev_info->max_mtu = dev_info->max_rx_pktlen - E1000_ETH_OVERHEAD;
2292 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2297 static const uint32_t *
2298 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2300 static const uint32_t ptypes[] = {
2301 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2304 RTE_PTYPE_L3_IPV4_EXT,
2306 RTE_PTYPE_L3_IPV6_EXT,
2310 RTE_PTYPE_TUNNEL_IP,
2311 RTE_PTYPE_INNER_L3_IPV6,
2312 RTE_PTYPE_INNER_L3_IPV6_EXT,
2313 RTE_PTYPE_INNER_L4_TCP,
2314 RTE_PTYPE_INNER_L4_UDP,
2318 if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2319 dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2325 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2327 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2329 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2330 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2331 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2332 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2333 DEV_TX_OFFLOAD_IPV4_CKSUM |
2334 DEV_TX_OFFLOAD_UDP_CKSUM |
2335 DEV_TX_OFFLOAD_TCP_CKSUM |
2336 DEV_TX_OFFLOAD_SCTP_CKSUM |
2337 DEV_TX_OFFLOAD_TCP_TSO;
2338 switch (hw->mac.type) {
2340 dev_info->max_rx_queues = 2;
2341 dev_info->max_tx_queues = 2;
2343 case e1000_vfadapt_i350:
2344 dev_info->max_rx_queues = 1;
2345 dev_info->max_tx_queues = 1;
2348 /* Should not happen */
2352 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2353 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2354 dev_info->rx_queue_offload_capa;
2355 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2356 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2357 dev_info->tx_queue_offload_capa;
2359 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2361 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2362 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2363 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2365 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2370 dev_info->default_txconf = (struct rte_eth_txconf) {
2372 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2373 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2374 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2379 dev_info->rx_desc_lim = rx_desc_lim;
2380 dev_info->tx_desc_lim = tx_desc_lim;
2385 /* return 0 means link status changed, -1 means not changed */
2387 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2389 struct e1000_hw *hw =
2390 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2391 struct rte_eth_link link;
2392 int link_check, count;
2395 hw->mac.get_link_status = 1;
2397 /* possible wait-to-complete in up to 9 seconds */
2398 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2399 /* Read the real link status */
2400 switch (hw->phy.media_type) {
2401 case e1000_media_type_copper:
2402 /* Do the work to read phy */
2403 e1000_check_for_link(hw);
2404 link_check = !hw->mac.get_link_status;
2407 case e1000_media_type_fiber:
2408 e1000_check_for_link(hw);
2409 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2413 case e1000_media_type_internal_serdes:
2414 e1000_check_for_link(hw);
2415 link_check = hw->mac.serdes_has_link;
2418 /* VF device is type_unknown */
2419 case e1000_media_type_unknown:
2420 eth_igbvf_link_update(hw);
2421 link_check = !hw->mac.get_link_status;
2427 if (link_check || wait_to_complete == 0)
2429 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2431 memset(&link, 0, sizeof(link));
2433 /* Now we check if a transition has happened */
2435 uint16_t duplex, speed;
2436 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2437 link.link_duplex = (duplex == FULL_DUPLEX) ?
2438 ETH_LINK_FULL_DUPLEX :
2439 ETH_LINK_HALF_DUPLEX;
2440 link.link_speed = speed;
2441 link.link_status = ETH_LINK_UP;
2442 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2443 ETH_LINK_SPEED_FIXED);
2444 } else if (!link_check) {
2445 link.link_speed = 0;
2446 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2447 link.link_status = ETH_LINK_DOWN;
2448 link.link_autoneg = ETH_LINK_FIXED;
2451 return rte_eth_linkstatus_set(dev, &link);
2455 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2456 * For ASF and Pass Through versions of f/w this means
2457 * that the driver is loaded.
2460 igb_hw_control_acquire(struct e1000_hw *hw)
2464 /* Let firmware know the driver has taken over */
2465 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2466 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2470 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2471 * For ASF and Pass Through versions of f/w this means that the
2472 * driver is no longer loaded.
2475 igb_hw_control_release(struct e1000_hw *hw)
2479 /* Let firmware taken over control of h/w */
2480 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2481 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2482 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2486 * Bit of a misnomer, what this really means is
2487 * to enable OS management of the system... aka
2488 * to disable special hardware management features.
2491 igb_init_manageability(struct e1000_hw *hw)
2493 if (e1000_enable_mng_pass_thru(hw)) {
2494 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2495 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2497 /* disable hardware interception of ARP */
2498 manc &= ~(E1000_MANC_ARP_EN);
2500 /* enable receiving management packets to the host */
2501 manc |= E1000_MANC_EN_MNG2HOST;
2502 manc2h |= 1 << 5; /* Mng Port 623 */
2503 manc2h |= 1 << 6; /* Mng Port 664 */
2504 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2505 E1000_WRITE_REG(hw, E1000_MANC, manc);
2510 igb_release_manageability(struct e1000_hw *hw)
2512 if (e1000_enable_mng_pass_thru(hw)) {
2513 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2515 manc |= E1000_MANC_ARP_EN;
2516 manc &= ~E1000_MANC_EN_MNG2HOST;
2518 E1000_WRITE_REG(hw, E1000_MANC, manc);
2523 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2525 struct e1000_hw *hw =
2526 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2529 rctl = E1000_READ_REG(hw, E1000_RCTL);
2530 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2531 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2537 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2539 struct e1000_hw *hw =
2540 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2543 rctl = E1000_READ_REG(hw, E1000_RCTL);
2544 rctl &= (~E1000_RCTL_UPE);
2545 if (dev->data->all_multicast == 1)
2546 rctl |= E1000_RCTL_MPE;
2548 rctl &= (~E1000_RCTL_MPE);
2549 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2555 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2557 struct e1000_hw *hw =
2558 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2561 rctl = E1000_READ_REG(hw, E1000_RCTL);
2562 rctl |= E1000_RCTL_MPE;
2563 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2567 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2569 struct e1000_hw *hw =
2570 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2573 if (dev->data->promiscuous == 1)
2574 return; /* must remain in all_multicast mode */
2575 rctl = E1000_READ_REG(hw, E1000_RCTL);
2576 rctl &= (~E1000_RCTL_MPE);
2577 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2581 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2583 struct e1000_hw *hw =
2584 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2585 struct e1000_vfta * shadow_vfta =
2586 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2591 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2592 E1000_VFTA_ENTRY_MASK);
2593 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2594 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2599 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2601 /* update local VFTA copy */
2602 shadow_vfta->vfta[vid_idx] = vfta;
2608 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2609 enum rte_vlan_type vlan_type,
2612 struct e1000_hw *hw =
2613 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2616 qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2617 qinq &= E1000_CTRL_EXT_EXT_VLAN;
2619 /* only outer TPID of double VLAN can be configured*/
2620 if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2621 reg = E1000_READ_REG(hw, E1000_VET);
2622 reg = (reg & (~E1000_VET_VET_EXT)) |
2623 ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2624 E1000_WRITE_REG(hw, E1000_VET, reg);
2629 /* all other TPID values are read-only*/
2630 PMD_DRV_LOG(ERR, "Not supported");
2636 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2638 struct e1000_hw *hw =
2639 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2642 /* Filter Table Disable */
2643 reg = E1000_READ_REG(hw, E1000_RCTL);
2644 reg &= ~E1000_RCTL_CFIEN;
2645 reg &= ~E1000_RCTL_VFE;
2646 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2650 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2652 struct e1000_hw *hw =
2653 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2654 struct e1000_vfta * shadow_vfta =
2655 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2659 /* Filter Table Enable, CFI not used for packet acceptance */
2660 reg = E1000_READ_REG(hw, E1000_RCTL);
2661 reg &= ~E1000_RCTL_CFIEN;
2662 reg |= E1000_RCTL_VFE;
2663 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2665 /* restore VFTA table */
2666 for (i = 0; i < IGB_VFTA_SIZE; i++)
2667 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2671 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2673 struct e1000_hw *hw =
2674 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2677 /* VLAN Mode Disable */
2678 reg = E1000_READ_REG(hw, E1000_CTRL);
2679 reg &= ~E1000_CTRL_VME;
2680 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2684 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2686 struct e1000_hw *hw =
2687 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2690 /* VLAN Mode Enable */
2691 reg = E1000_READ_REG(hw, E1000_CTRL);
2692 reg |= E1000_CTRL_VME;
2693 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2697 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2699 struct e1000_hw *hw =
2700 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2703 /* CTRL_EXT: Extended VLAN */
2704 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2705 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2706 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2708 /* Update maximum packet length */
2709 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2710 E1000_WRITE_REG(hw, E1000_RLPML,
2711 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2716 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2718 struct e1000_hw *hw =
2719 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2722 /* CTRL_EXT: Extended VLAN */
2723 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2724 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2725 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2727 /* Update maximum packet length */
2728 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2729 E1000_WRITE_REG(hw, E1000_RLPML,
2730 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2735 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2737 struct rte_eth_rxmode *rxmode;
2739 rxmode = &dev->data->dev_conf.rxmode;
2740 if(mask & ETH_VLAN_STRIP_MASK){
2741 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2742 igb_vlan_hw_strip_enable(dev);
2744 igb_vlan_hw_strip_disable(dev);
2747 if(mask & ETH_VLAN_FILTER_MASK){
2748 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2749 igb_vlan_hw_filter_enable(dev);
2751 igb_vlan_hw_filter_disable(dev);
2754 if(mask & ETH_VLAN_EXTEND_MASK){
2755 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2756 igb_vlan_hw_extend_enable(dev);
2758 igb_vlan_hw_extend_disable(dev);
2766 * It enables the interrupt mask and then enable the interrupt.
2769 * Pointer to struct rte_eth_dev.
2774 * - On success, zero.
2775 * - On failure, a negative value.
2778 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2780 struct e1000_interrupt *intr =
2781 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2784 intr->mask |= E1000_ICR_LSC;
2786 intr->mask &= ~E1000_ICR_LSC;
2791 /* It clears the interrupt causes and enables the interrupt.
2792 * It will be called once only during nic initialized.
2795 * Pointer to struct rte_eth_dev.
2798 * - On success, zero.
2799 * - On failure, a negative value.
2801 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2803 uint32_t mask, regval;
2805 struct e1000_hw *hw =
2806 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2807 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2808 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2809 int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0;
2810 struct rte_eth_dev_info dev_info;
2812 memset(&dev_info, 0, sizeof(dev_info));
2813 ret = eth_igb_infos_get(dev, &dev_info);
2817 mask = (0xFFFFFFFF >> (32 - dev_info.max_rx_queues)) << misc_shift;
2818 regval = E1000_READ_REG(hw, E1000_EIMS);
2819 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2825 * It reads ICR and gets interrupt causes, check it and set a bit flag
2826 * to update link status.
2829 * Pointer to struct rte_eth_dev.
2832 * - On success, zero.
2833 * - On failure, a negative value.
2836 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2839 struct e1000_hw *hw =
2840 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2841 struct e1000_interrupt *intr =
2842 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2844 igb_intr_disable(dev);
2846 /* read-on-clear nic registers here */
2847 icr = E1000_READ_REG(hw, E1000_ICR);
2850 if (icr & E1000_ICR_LSC) {
2851 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2854 if (icr & E1000_ICR_VMMB)
2855 intr->flags |= E1000_FLAG_MAILBOX;
2861 * It executes link_update after knowing an interrupt is prsent.
2864 * Pointer to struct rte_eth_dev.
2867 * - On success, zero.
2868 * - On failure, a negative value.
2871 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2872 struct rte_intr_handle *intr_handle)
2874 struct e1000_hw *hw =
2875 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2876 struct e1000_interrupt *intr =
2877 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2878 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2879 struct rte_eth_link link;
2882 if (intr->flags & E1000_FLAG_MAILBOX) {
2883 igb_pf_mbx_process(dev);
2884 intr->flags &= ~E1000_FLAG_MAILBOX;
2887 igb_intr_enable(dev);
2888 rte_intr_ack(intr_handle);
2890 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2891 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2893 /* set get_link_status to check register later */
2894 hw->mac.get_link_status = 1;
2895 ret = eth_igb_link_update(dev, 0);
2897 /* check if link has changed */
2901 rte_eth_linkstatus_get(dev, &link);
2902 if (link.link_status) {
2904 " Port %d: Link Up - speed %u Mbps - %s",
2906 (unsigned)link.link_speed,
2907 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2908 "full-duplex" : "half-duplex");
2910 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2911 dev->data->port_id);
2914 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2915 pci_dev->addr.domain,
2917 pci_dev->addr.devid,
2918 pci_dev->addr.function);
2919 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2927 * Interrupt handler which shall be registered at first.
2930 * Pointer to interrupt handle.
2932 * The address of parameter (struct rte_eth_dev *) regsitered before.
2938 eth_igb_interrupt_handler(void *param)
2940 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2942 eth_igb_interrupt_get_status(dev);
2943 eth_igb_interrupt_action(dev, dev->intr_handle);
2947 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2950 struct e1000_hw *hw =
2951 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2952 struct e1000_interrupt *intr =
2953 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2955 igbvf_intr_disable(hw);
2957 /* read-on-clear nic registers here */
2958 eicr = E1000_READ_REG(hw, E1000_EICR);
2961 if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2962 intr->flags |= E1000_FLAG_MAILBOX;
2967 void igbvf_mbx_process(struct rte_eth_dev *dev)
2969 struct e1000_hw *hw =
2970 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2971 struct e1000_mbx_info *mbx = &hw->mbx;
2974 /* peek the message first */
2975 in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2977 /* PF reset VF event */
2978 if (in_msg == E1000_PF_CONTROL_MSG) {
2979 /* dummy mbx read to ack pf */
2980 if (mbx->ops.read(hw, &in_msg, 1, 0))
2982 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2988 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2990 struct e1000_interrupt *intr =
2991 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2993 if (intr->flags & E1000_FLAG_MAILBOX) {
2994 igbvf_mbx_process(dev);
2995 intr->flags &= ~E1000_FLAG_MAILBOX;
2998 igbvf_intr_enable(dev);
2999 rte_intr_ack(intr_handle);
3005 eth_igbvf_interrupt_handler(void *param)
3007 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3009 eth_igbvf_interrupt_get_status(dev);
3010 eth_igbvf_interrupt_action(dev, dev->intr_handle);
3014 eth_igb_led_on(struct rte_eth_dev *dev)
3016 struct e1000_hw *hw;
3018 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3019 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3023 eth_igb_led_off(struct rte_eth_dev *dev)
3025 struct e1000_hw *hw;
3027 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3028 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3032 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3034 struct e1000_hw *hw;
3039 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3040 fc_conf->pause_time = hw->fc.pause_time;
3041 fc_conf->high_water = hw->fc.high_water;
3042 fc_conf->low_water = hw->fc.low_water;
3043 fc_conf->send_xon = hw->fc.send_xon;
3044 fc_conf->autoneg = hw->mac.autoneg;
3047 * Return rx_pause and tx_pause status according to actual setting of
3048 * the TFCE and RFCE bits in the CTRL register.
3050 ctrl = E1000_READ_REG(hw, E1000_CTRL);
3051 if (ctrl & E1000_CTRL_TFCE)
3056 if (ctrl & E1000_CTRL_RFCE)
3061 if (rx_pause && tx_pause)
3062 fc_conf->mode = RTE_FC_FULL;
3064 fc_conf->mode = RTE_FC_RX_PAUSE;
3066 fc_conf->mode = RTE_FC_TX_PAUSE;
3068 fc_conf->mode = RTE_FC_NONE;
3074 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3076 struct e1000_hw *hw;
3078 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3084 uint32_t rx_buf_size;
3085 uint32_t max_high_water;
3088 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3089 if (fc_conf->autoneg != hw->mac.autoneg)
3091 rx_buf_size = igb_get_rx_buffer_size(hw);
3092 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3094 /* At least reserve one Ethernet frame for watermark */
3095 max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
3096 if ((fc_conf->high_water > max_high_water) ||
3097 (fc_conf->high_water < fc_conf->low_water)) {
3098 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3099 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
3103 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3104 hw->fc.pause_time = fc_conf->pause_time;
3105 hw->fc.high_water = fc_conf->high_water;
3106 hw->fc.low_water = fc_conf->low_water;
3107 hw->fc.send_xon = fc_conf->send_xon;
3109 err = e1000_setup_link_generic(hw);
3110 if (err == E1000_SUCCESS) {
3112 /* check if we want to forward MAC frames - driver doesn't have native
3113 * capability to do that, so we'll write the registers ourselves */
3115 rctl = E1000_READ_REG(hw, E1000_RCTL);
3117 /* set or clear MFLCN.PMCF bit depending on configuration */
3118 if (fc_conf->mac_ctrl_frame_fwd != 0)
3119 rctl |= E1000_RCTL_PMCF;
3121 rctl &= ~E1000_RCTL_PMCF;
3123 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3124 E1000_WRITE_FLUSH(hw);
3129 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3133 #define E1000_RAH_POOLSEL_SHIFT (18)
3135 eth_igb_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3136 uint32_t index, uint32_t pool)
3138 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3141 e1000_rar_set(hw, mac_addr->addr_bytes, index);
3142 rah = E1000_READ_REG(hw, E1000_RAH(index));
3143 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3144 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3149 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3151 uint8_t addr[RTE_ETHER_ADDR_LEN];
3152 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3154 memset(addr, 0, sizeof(addr));
3156 e1000_rar_set(hw, addr, index);
3160 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3161 struct rte_ether_addr *addr)
3163 eth_igb_rar_clear(dev, 0);
3164 eth_igb_rar_set(dev, (void *)addr, 0, 0);
3169 * Virtual Function operations
3172 igbvf_intr_disable(struct e1000_hw *hw)
3174 PMD_INIT_FUNC_TRACE();
3176 /* Clear interrupt mask to stop from interrupts being generated */
3177 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3179 E1000_WRITE_FLUSH(hw);
3183 igbvf_stop_adapter(struct rte_eth_dev *dev)
3187 struct rte_eth_dev_info dev_info;
3188 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3191 memset(&dev_info, 0, sizeof(dev_info));
3192 ret = eth_igbvf_infos_get(dev, &dev_info);
3196 /* Clear interrupt mask to stop from interrupts being generated */
3197 igbvf_intr_disable(hw);
3199 /* Clear any pending interrupts, flush previous writes */
3200 E1000_READ_REG(hw, E1000_EICR);
3202 /* Disable the transmit unit. Each queue must be disabled. */
3203 for (i = 0; i < dev_info.max_tx_queues; i++)
3204 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3206 /* Disable the receive unit by stopping each queue */
3207 for (i = 0; i < dev_info.max_rx_queues; i++) {
3208 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3209 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3210 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3211 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3215 /* flush all queues disables */
3216 E1000_WRITE_FLUSH(hw);
3220 static int eth_igbvf_link_update(struct e1000_hw *hw)
3222 struct e1000_mbx_info *mbx = &hw->mbx;
3223 struct e1000_mac_info *mac = &hw->mac;
3224 int ret_val = E1000_SUCCESS;
3226 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3229 * We only want to run this if there has been a rst asserted.
3230 * in this case that could mean a link change, device reset,
3231 * or a virtual function reset
3234 /* If we were hit with a reset or timeout drop the link */
3235 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3236 mac->get_link_status = TRUE;
3238 if (!mac->get_link_status)
3241 /* if link status is down no point in checking to see if pf is up */
3242 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3245 /* if we passed all the tests above then the link is up and we no
3246 * longer need to check for link */
3247 mac->get_link_status = FALSE;
3255 igbvf_dev_configure(struct rte_eth_dev *dev)
3257 struct rte_eth_conf* conf = &dev->data->dev_conf;
3259 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3260 dev->data->port_id);
3263 * VF has no ability to enable/disable HW CRC
3264 * Keep the persistent behavior the same as Host PF
3266 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3267 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
3268 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3269 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
3272 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
3273 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3274 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
3282 igbvf_dev_start(struct rte_eth_dev *dev)
3284 struct e1000_hw *hw =
3285 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3286 struct e1000_adapter *adapter =
3287 E1000_DEV_PRIVATE(dev->data->dev_private);
3288 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3289 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3291 uint32_t intr_vector = 0;
3293 PMD_INIT_FUNC_TRACE();
3295 hw->mac.ops.reset_hw(hw);
3296 adapter->stopped = 0;
3299 igbvf_set_vfta_all(dev,1);
3301 eth_igbvf_tx_init(dev);
3303 /* This can fail when allocating mbufs for descriptor rings */
3304 ret = eth_igbvf_rx_init(dev);
3306 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3307 igb_dev_clear_queues(dev);
3311 /* check and configure queue intr-vector mapping */
3312 if (rte_intr_cap_multiple(intr_handle) &&
3313 dev->data->dev_conf.intr_conf.rxq) {
3314 intr_vector = dev->data->nb_rx_queues;
3315 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3320 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3321 intr_handle->intr_vec =
3322 rte_zmalloc("intr_vec",
3323 dev->data->nb_rx_queues * sizeof(int), 0);
3324 if (!intr_handle->intr_vec) {
3325 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3326 " intr_vec", dev->data->nb_rx_queues);
3331 eth_igbvf_configure_msix_intr(dev);
3333 /* enable uio/vfio intr/eventfd mapping */
3334 rte_intr_enable(intr_handle);
3336 /* resume enabled intr since hw reset */
3337 igbvf_intr_enable(dev);
3343 igbvf_dev_stop(struct rte_eth_dev *dev)
3345 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3346 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3348 PMD_INIT_FUNC_TRACE();
3350 igbvf_stop_adapter(dev);
3353 * Clear what we set, but we still keep shadow_vfta to
3354 * restore after device starts
3356 igbvf_set_vfta_all(dev,0);
3358 igb_dev_clear_queues(dev);
3360 /* disable intr eventfd mapping */
3361 rte_intr_disable(intr_handle);
3363 /* Clean datapath event and queue/vec mapping */
3364 rte_intr_efd_disable(intr_handle);
3365 if (intr_handle->intr_vec) {
3366 rte_free(intr_handle->intr_vec);
3367 intr_handle->intr_vec = NULL;
3372 igbvf_dev_close(struct rte_eth_dev *dev)
3374 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3375 struct e1000_adapter *adapter =
3376 E1000_DEV_PRIVATE(dev->data->dev_private);
3377 struct rte_ether_addr addr;
3379 PMD_INIT_FUNC_TRACE();
3383 igbvf_dev_stop(dev);
3384 adapter->stopped = 1;
3385 igb_dev_free_queues(dev);
3388 * reprogram the RAR with a zero mac address,
3389 * to ensure that the VF traffic goes to the PF
3390 * after stop, close and detach of the VF.
3393 memset(&addr, 0, sizeof(addr));
3394 igbvf_default_mac_addr_set(dev, &addr);
3398 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3400 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3402 /* Set both unicast and multicast promisc */
3403 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3409 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3411 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3413 /* If in allmulticast mode leave multicast promisc */
3414 if (dev->data->all_multicast == 1)
3415 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3417 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3423 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3425 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3427 /* In promiscuous mode multicast promisc already set */
3428 if (dev->data->promiscuous == 0)
3429 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3433 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3435 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3437 /* In promiscuous mode leave multicast promisc enabled */
3438 if (dev->data->promiscuous == 0)
3439 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3442 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3444 struct e1000_mbx_info *mbx = &hw->mbx;
3448 /* After set vlan, vlan strip will also be enabled in igb driver*/
3449 msgbuf[0] = E1000_VF_SET_VLAN;
3451 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3453 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3455 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3459 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3463 msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3464 if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3471 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3473 struct e1000_hw *hw =
3474 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3475 struct e1000_vfta * shadow_vfta =
3476 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3477 int i = 0, j = 0, vfta = 0, mask = 1;
3479 for (i = 0; i < IGB_VFTA_SIZE; i++){
3480 vfta = shadow_vfta->vfta[i];
3483 for (j = 0; j < 32; j++){
3486 (uint16_t)((i<<5)+j), on);
3495 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3497 struct e1000_hw *hw =
3498 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3499 struct e1000_vfta * shadow_vfta =
3500 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3501 uint32_t vid_idx = 0;
3502 uint32_t vid_bit = 0;
3505 PMD_INIT_FUNC_TRACE();
3507 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3508 ret = igbvf_set_vfta(hw, vlan_id, !!on);
3510 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3513 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3514 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3516 /*Save what we set and retore it after device reset*/
3518 shadow_vfta->vfta[vid_idx] |= vid_bit;
3520 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3526 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3528 struct e1000_hw *hw =
3529 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3531 /* index is not used by rar_set() */
3532 hw->mac.ops.rar_set(hw, (void *)addr, 0);
3538 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3539 struct rte_eth_rss_reta_entry64 *reta_conf,
3544 uint16_t idx, shift;
3545 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3547 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3548 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3549 "(%d) doesn't match the number hardware can supported "
3550 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3554 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3555 idx = i / RTE_RETA_GROUP_SIZE;
3556 shift = i % RTE_RETA_GROUP_SIZE;
3557 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3561 if (mask == IGB_4_BIT_MASK)
3564 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3565 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3566 if (mask & (0x1 << j))
3567 reta |= reta_conf[idx].reta[shift + j] <<
3570 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3572 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3579 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3580 struct rte_eth_rss_reta_entry64 *reta_conf,
3585 uint16_t idx, shift;
3586 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3588 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3589 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3590 "(%d) doesn't match the number hardware can supported "
3591 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3595 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3596 idx = i / RTE_RETA_GROUP_SIZE;
3597 shift = i % RTE_RETA_GROUP_SIZE;
3598 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3602 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3603 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3604 if (mask & (0x1 << j))
3605 reta_conf[idx].reta[shift + j] =
3606 ((reta >> (CHAR_BIT * j)) &
3615 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3616 struct rte_eth_syn_filter *filter,
3619 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3620 struct e1000_filter_info *filter_info =
3621 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3622 uint32_t synqf, rfctl;
3624 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3627 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3630 if (synqf & E1000_SYN_FILTER_ENABLE)
3633 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3634 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3636 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3637 if (filter->hig_pri)
3638 rfctl |= E1000_RFCTL_SYNQFP;
3640 rfctl &= ~E1000_RFCTL_SYNQFP;
3642 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3644 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3649 filter_info->syn_info = synqf;
3650 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3651 E1000_WRITE_FLUSH(hw);
3656 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3657 struct rte_eth_syn_filter *filter)
3659 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3660 uint32_t synqf, rfctl;
3662 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3663 if (synqf & E1000_SYN_FILTER_ENABLE) {
3664 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3665 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3666 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3667 E1000_SYN_FILTER_QUEUE_SHIFT);
3675 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3676 enum rte_filter_op filter_op,
3679 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3682 MAC_TYPE_FILTER_SUP(hw->mac.type);
3684 if (filter_op == RTE_ETH_FILTER_NOP)
3688 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3693 switch (filter_op) {
3694 case RTE_ETH_FILTER_ADD:
3695 ret = eth_igb_syn_filter_set(dev,
3696 (struct rte_eth_syn_filter *)arg,
3699 case RTE_ETH_FILTER_DELETE:
3700 ret = eth_igb_syn_filter_set(dev,
3701 (struct rte_eth_syn_filter *)arg,
3704 case RTE_ETH_FILTER_GET:
3705 ret = eth_igb_syn_filter_get(dev,
3706 (struct rte_eth_syn_filter *)arg);
3709 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3717 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3719 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3720 struct e1000_2tuple_filter_info *filter_info)
3722 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3724 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3725 return -EINVAL; /* filter index is out of range. */
3726 if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
3727 return -EINVAL; /* flags is invalid. */
3729 switch (filter->dst_port_mask) {
3731 filter_info->dst_port_mask = 0;
3732 filter_info->dst_port = filter->dst_port;
3735 filter_info->dst_port_mask = 1;
3738 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3742 switch (filter->proto_mask) {
3744 filter_info->proto_mask = 0;
3745 filter_info->proto = filter->proto;
3748 filter_info->proto_mask = 1;
3751 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3755 filter_info->priority = (uint8_t)filter->priority;
3756 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3757 filter_info->tcp_flags = filter->tcp_flags;
3759 filter_info->tcp_flags = 0;
3764 static inline struct e1000_2tuple_filter *
3765 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3766 struct e1000_2tuple_filter_info *key)
3768 struct e1000_2tuple_filter *it;
3770 TAILQ_FOREACH(it, filter_list, entries) {
3771 if (memcmp(key, &it->filter_info,
3772 sizeof(struct e1000_2tuple_filter_info)) == 0) {
3779 /* inject a igb 2tuple filter to HW */
3781 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3782 struct e1000_2tuple_filter *filter)
3784 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3785 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3786 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3790 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3791 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3792 imir |= E1000_IMIR_PORT_BP;
3794 imir &= ~E1000_IMIR_PORT_BP;
3796 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3798 ttqf |= E1000_TTQF_QUEUE_ENABLE;
3799 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3800 ttqf |= (uint32_t)(filter->filter_info.proto &
3801 E1000_TTQF_PROTOCOL_MASK);
3802 if (filter->filter_info.proto_mask == 0)
3803 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3805 /* tcp flags bits setting. */
3806 if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
3807 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
3808 imir_ext |= E1000_IMIREXT_CTRL_URG;
3809 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
3810 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3811 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
3812 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3813 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
3814 imir_ext |= E1000_IMIREXT_CTRL_RST;
3815 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
3816 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3817 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
3818 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3820 imir_ext |= E1000_IMIREXT_CTRL_BP;
3822 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3823 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3824 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3828 * igb_add_2tuple_filter - add a 2tuple filter
3831 * dev: Pointer to struct rte_eth_dev.
3832 * ntuple_filter: ponter to the filter that will be added.
3835 * - On success, zero.
3836 * - On failure, a negative value.
3839 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3840 struct rte_eth_ntuple_filter *ntuple_filter)
3842 struct e1000_filter_info *filter_info =
3843 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3844 struct e1000_2tuple_filter *filter;
3847 filter = rte_zmalloc("e1000_2tuple_filter",
3848 sizeof(struct e1000_2tuple_filter), 0);
3852 ret = ntuple_filter_to_2tuple(ntuple_filter,
3853 &filter->filter_info);
3858 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3859 &filter->filter_info) != NULL) {
3860 PMD_DRV_LOG(ERR, "filter exists.");
3864 filter->queue = ntuple_filter->queue;
3867 * look for an unused 2tuple filter index,
3868 * and insert the filter to list.
3870 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3871 if (!(filter_info->twotuple_mask & (1 << i))) {
3872 filter_info->twotuple_mask |= 1 << i;
3874 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3880 if (i >= E1000_MAX_TTQF_FILTERS) {
3881 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3886 igb_inject_2uple_filter(dev, filter);
3891 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3892 struct e1000_2tuple_filter *filter)
3894 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3895 struct e1000_filter_info *filter_info =
3896 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3898 filter_info->twotuple_mask &= ~(1 << filter->index);
3899 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3902 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3903 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3904 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3909 * igb_remove_2tuple_filter - remove a 2tuple filter
3912 * dev: Pointer to struct rte_eth_dev.
3913 * ntuple_filter: ponter to the filter that will be removed.
3916 * - On success, zero.
3917 * - On failure, a negative value.
3920 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3921 struct rte_eth_ntuple_filter *ntuple_filter)
3923 struct e1000_filter_info *filter_info =
3924 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3925 struct e1000_2tuple_filter_info filter_2tuple;
3926 struct e1000_2tuple_filter *filter;
3929 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3930 ret = ntuple_filter_to_2tuple(ntuple_filter,
3935 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3937 if (filter == NULL) {
3938 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3942 igb_delete_2tuple_filter(dev, filter);
3947 /* inject a igb flex filter to HW */
3949 igb_inject_flex_filter(struct rte_eth_dev *dev,
3950 struct e1000_flex_filter *filter)
3952 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3953 uint32_t wufc, queueing;
3957 wufc = E1000_READ_REG(hw, E1000_WUFC);
3958 if (filter->index < E1000_MAX_FHFT)
3959 reg_off = E1000_FHFT(filter->index);
3961 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3963 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3964 (E1000_WUFC_FLX0 << filter->index));
3965 queueing = filter->filter_info.len |
3966 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3967 (filter->filter_info.priority <<
3968 E1000_FHFT_QUEUEING_PRIO_SHIFT);
3969 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3972 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3973 E1000_WRITE_REG(hw, reg_off,
3974 filter->filter_info.dwords[j]);
3975 reg_off += sizeof(uint32_t);
3976 E1000_WRITE_REG(hw, reg_off,
3977 filter->filter_info.dwords[++j]);
3978 reg_off += sizeof(uint32_t);
3979 E1000_WRITE_REG(hw, reg_off,
3980 (uint32_t)filter->filter_info.mask[i]);
3981 reg_off += sizeof(uint32_t) * 2;
3986 static inline struct e1000_flex_filter *
3987 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3988 struct e1000_flex_filter_info *key)
3990 struct e1000_flex_filter *it;
3992 TAILQ_FOREACH(it, filter_list, entries) {
3993 if (memcmp(key, &it->filter_info,
3994 sizeof(struct e1000_flex_filter_info)) == 0)
4001 /* remove a flex byte filter
4003 * dev: Pointer to struct rte_eth_dev.
4004 * filter: the pointer of the filter will be removed.
4007 igb_remove_flex_filter(struct rte_eth_dev *dev,
4008 struct e1000_flex_filter *filter)
4010 struct e1000_filter_info *filter_info =
4011 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4012 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4016 wufc = E1000_READ_REG(hw, E1000_WUFC);
4017 if (filter->index < E1000_MAX_FHFT)
4018 reg_off = E1000_FHFT(filter->index);
4020 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
4022 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
4023 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
4025 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
4026 (~(E1000_WUFC_FLX0 << filter->index)));
4028 filter_info->flex_mask &= ~(1 << filter->index);
4029 TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
4034 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
4035 struct rte_eth_flex_filter *filter,
4038 struct e1000_filter_info *filter_info =
4039 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4040 struct e1000_flex_filter *flex_filter, *it;
4044 flex_filter = rte_zmalloc("e1000_flex_filter",
4045 sizeof(struct e1000_flex_filter), 0);
4046 if (flex_filter == NULL)
4049 flex_filter->filter_info.len = filter->len;
4050 flex_filter->filter_info.priority = filter->priority;
4051 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4052 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4054 /* reverse bits in flex filter's mask*/
4055 for (shift = 0; shift < CHAR_BIT; shift++) {
4056 if (filter->mask[i] & (0x01 << shift))
4057 mask |= (0x80 >> shift);
4059 flex_filter->filter_info.mask[i] = mask;
4062 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4063 &flex_filter->filter_info);
4064 if (it == NULL && !add) {
4065 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4066 rte_free(flex_filter);
4069 if (it != NULL && add) {
4070 PMD_DRV_LOG(ERR, "filter exists.");
4071 rte_free(flex_filter);
4076 flex_filter->queue = filter->queue;
4078 * look for an unused flex filter index
4079 * and insert the filter into the list.
4081 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4082 if (!(filter_info->flex_mask & (1 << i))) {
4083 filter_info->flex_mask |= 1 << i;
4084 flex_filter->index = i;
4085 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4091 if (i >= E1000_MAX_FLEX_FILTERS) {
4092 PMD_DRV_LOG(ERR, "flex filters are full.");
4093 rte_free(flex_filter);
4097 igb_inject_flex_filter(dev, flex_filter);
4100 igb_remove_flex_filter(dev, it);
4101 rte_free(flex_filter);
4108 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4109 struct rte_eth_flex_filter *filter)
4111 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4112 struct e1000_filter_info *filter_info =
4113 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4114 struct e1000_flex_filter flex_filter, *it;
4115 uint32_t wufc, queueing, wufc_en = 0;
4117 memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4118 flex_filter.filter_info.len = filter->len;
4119 flex_filter.filter_info.priority = filter->priority;
4120 memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4121 memcpy(flex_filter.filter_info.mask, filter->mask,
4122 RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT);
4124 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4125 &flex_filter.filter_info);
4127 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4131 wufc = E1000_READ_REG(hw, E1000_WUFC);
4132 wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4134 if ((wufc & wufc_en) == wufc_en) {
4135 uint32_t reg_off = 0;
4136 if (it->index < E1000_MAX_FHFT)
4137 reg_off = E1000_FHFT(it->index);
4139 reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4141 queueing = E1000_READ_REG(hw,
4142 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4143 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4144 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4145 E1000_FHFT_QUEUEING_PRIO_SHIFT;
4146 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4147 E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4154 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4155 enum rte_filter_op filter_op,
4158 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4159 struct rte_eth_flex_filter *filter;
4162 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4164 if (filter_op == RTE_ETH_FILTER_NOP)
4168 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4173 filter = (struct rte_eth_flex_filter *)arg;
4174 if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4175 || filter->len % sizeof(uint64_t) != 0) {
4176 PMD_DRV_LOG(ERR, "filter's length is out of range");
4179 if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4180 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4184 switch (filter_op) {
4185 case RTE_ETH_FILTER_ADD:
4186 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4188 case RTE_ETH_FILTER_DELETE:
4189 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4191 case RTE_ETH_FILTER_GET:
4192 ret = eth_igb_get_flex_filter(dev, filter);
4195 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4203 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4205 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4206 struct e1000_5tuple_filter_info *filter_info)
4208 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4210 if (filter->priority > E1000_2TUPLE_MAX_PRI)
4211 return -EINVAL; /* filter index is out of range. */
4212 if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
4213 return -EINVAL; /* flags is invalid. */
4215 switch (filter->dst_ip_mask) {
4217 filter_info->dst_ip_mask = 0;
4218 filter_info->dst_ip = filter->dst_ip;
4221 filter_info->dst_ip_mask = 1;
4224 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4228 switch (filter->src_ip_mask) {
4230 filter_info->src_ip_mask = 0;
4231 filter_info->src_ip = filter->src_ip;
4234 filter_info->src_ip_mask = 1;
4237 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4241 switch (filter->dst_port_mask) {
4243 filter_info->dst_port_mask = 0;
4244 filter_info->dst_port = filter->dst_port;
4247 filter_info->dst_port_mask = 1;
4250 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4254 switch (filter->src_port_mask) {
4256 filter_info->src_port_mask = 0;
4257 filter_info->src_port = filter->src_port;
4260 filter_info->src_port_mask = 1;
4263 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4267 switch (filter->proto_mask) {
4269 filter_info->proto_mask = 0;
4270 filter_info->proto = filter->proto;
4273 filter_info->proto_mask = 1;
4276 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4280 filter_info->priority = (uint8_t)filter->priority;
4281 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4282 filter_info->tcp_flags = filter->tcp_flags;
4284 filter_info->tcp_flags = 0;
4289 static inline struct e1000_5tuple_filter *
4290 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4291 struct e1000_5tuple_filter_info *key)
4293 struct e1000_5tuple_filter *it;
4295 TAILQ_FOREACH(it, filter_list, entries) {
4296 if (memcmp(key, &it->filter_info,
4297 sizeof(struct e1000_5tuple_filter_info)) == 0) {
4304 /* inject a igb 5-tuple filter to HW */
4306 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4307 struct e1000_5tuple_filter *filter)
4309 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4310 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4311 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4315 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4316 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4317 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4318 if (filter->filter_info.dst_ip_mask == 0)
4319 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4320 if (filter->filter_info.src_port_mask == 0)
4321 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4322 if (filter->filter_info.proto_mask == 0)
4323 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4324 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4325 E1000_FTQF_QUEUE_MASK;
4326 ftqf |= E1000_FTQF_QUEUE_ENABLE;
4327 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4328 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4329 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4331 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4332 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4334 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4335 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4336 imir |= E1000_IMIR_PORT_BP;
4338 imir &= ~E1000_IMIR_PORT_BP;
4339 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4341 /* tcp flags bits setting. */
4342 if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
4343 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
4344 imir_ext |= E1000_IMIREXT_CTRL_URG;
4345 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
4346 imir_ext |= E1000_IMIREXT_CTRL_ACK;
4347 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
4348 imir_ext |= E1000_IMIREXT_CTRL_PSH;
4349 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
4350 imir_ext |= E1000_IMIREXT_CTRL_RST;
4351 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
4352 imir_ext |= E1000_IMIREXT_CTRL_SYN;
4353 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
4354 imir_ext |= E1000_IMIREXT_CTRL_FIN;
4356 imir_ext |= E1000_IMIREXT_CTRL_BP;
4358 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4359 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4363 * igb_add_5tuple_filter_82576 - add a 5tuple filter
4366 * dev: Pointer to struct rte_eth_dev.
4367 * ntuple_filter: ponter to the filter that will be added.
4370 * - On success, zero.
4371 * - On failure, a negative value.
4374 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4375 struct rte_eth_ntuple_filter *ntuple_filter)
4377 struct e1000_filter_info *filter_info =
4378 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4379 struct e1000_5tuple_filter *filter;
4383 filter = rte_zmalloc("e1000_5tuple_filter",
4384 sizeof(struct e1000_5tuple_filter), 0);
4388 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4389 &filter->filter_info);
4395 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4396 &filter->filter_info) != NULL) {
4397 PMD_DRV_LOG(ERR, "filter exists.");
4401 filter->queue = ntuple_filter->queue;
4404 * look for an unused 5tuple filter index,
4405 * and insert the filter to list.
4407 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4408 if (!(filter_info->fivetuple_mask & (1 << i))) {
4409 filter_info->fivetuple_mask |= 1 << i;
4411 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4417 if (i >= E1000_MAX_FTQF_FILTERS) {
4418 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4423 igb_inject_5tuple_filter_82576(dev, filter);
4428 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4429 struct e1000_5tuple_filter *filter)
4431 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4432 struct e1000_filter_info *filter_info =
4433 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4435 filter_info->fivetuple_mask &= ~(1 << filter->index);
4436 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4439 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4440 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4441 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4442 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4443 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4444 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4445 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4450 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4453 * dev: Pointer to struct rte_eth_dev.
4454 * ntuple_filter: ponter to the filter that will be removed.
4457 * - On success, zero.
4458 * - On failure, a negative value.
4461 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4462 struct rte_eth_ntuple_filter *ntuple_filter)
4464 struct e1000_filter_info *filter_info =
4465 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4466 struct e1000_5tuple_filter_info filter_5tuple;
4467 struct e1000_5tuple_filter *filter;
4470 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4471 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4476 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4478 if (filter == NULL) {
4479 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4483 igb_delete_5tuple_filter_82576(dev, filter);
4489 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4492 struct e1000_hw *hw;
4493 struct rte_eth_dev_info dev_info;
4494 uint32_t frame_size = mtu + E1000_ETH_OVERHEAD;
4497 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4499 #ifdef RTE_LIBRTE_82571_SUPPORT
4500 /* XXX: not bigger than max_rx_pktlen */
4501 if (hw->mac.type == e1000_82571)
4504 ret = eth_igb_infos_get(dev, &dev_info);
4508 /* check that mtu is within the allowed range */
4509 if (mtu < RTE_ETHER_MIN_MTU ||
4510 frame_size > dev_info.max_rx_pktlen)
4513 /* refuse mtu that requires the support of scattered packets when this
4514 * feature has not been enabled before. */
4515 if (!dev->data->scattered_rx &&
4516 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4519 rctl = E1000_READ_REG(hw, E1000_RCTL);
4521 /* switch to jumbo mode if needed */
4522 if (frame_size > RTE_ETHER_MAX_LEN) {
4523 dev->data->dev_conf.rxmode.offloads |=
4524 DEV_RX_OFFLOAD_JUMBO_FRAME;
4525 rctl |= E1000_RCTL_LPE;
4527 dev->data->dev_conf.rxmode.offloads &=
4528 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4529 rctl &= ~E1000_RCTL_LPE;
4531 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4533 /* update max frame size */
4534 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4536 E1000_WRITE_REG(hw, E1000_RLPML,
4537 dev->data->dev_conf.rxmode.max_rx_pkt_len);
4543 * igb_add_del_ntuple_filter - add or delete a ntuple filter
4546 * dev: Pointer to struct rte_eth_dev.
4547 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4548 * add: if true, add filter, if false, remove filter
4551 * - On success, zero.
4552 * - On failure, a negative value.
4555 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4556 struct rte_eth_ntuple_filter *ntuple_filter,
4559 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4562 switch (ntuple_filter->flags) {
4563 case RTE_5TUPLE_FLAGS:
4564 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4565 if (hw->mac.type != e1000_82576)
4568 ret = igb_add_5tuple_filter_82576(dev,
4571 ret = igb_remove_5tuple_filter_82576(dev,
4574 case RTE_2TUPLE_FLAGS:
4575 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4576 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4577 hw->mac.type != e1000_i210 &&
4578 hw->mac.type != e1000_i211)
4581 ret = igb_add_2tuple_filter(dev, ntuple_filter);
4583 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4594 * igb_get_ntuple_filter - get a ntuple filter
4597 * dev: Pointer to struct rte_eth_dev.
4598 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4601 * - On success, zero.
4602 * - On failure, a negative value.
4605 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4606 struct rte_eth_ntuple_filter *ntuple_filter)
4608 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4609 struct e1000_filter_info *filter_info =
4610 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4611 struct e1000_5tuple_filter_info filter_5tuple;
4612 struct e1000_2tuple_filter_info filter_2tuple;
4613 struct e1000_5tuple_filter *p_5tuple_filter;
4614 struct e1000_2tuple_filter *p_2tuple_filter;
4617 switch (ntuple_filter->flags) {
4618 case RTE_5TUPLE_FLAGS:
4619 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4620 if (hw->mac.type != e1000_82576)
4622 memset(&filter_5tuple,
4624 sizeof(struct e1000_5tuple_filter_info));
4625 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4629 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4630 &filter_info->fivetuple_list,
4632 if (p_5tuple_filter == NULL) {
4633 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4636 ntuple_filter->queue = p_5tuple_filter->queue;
4638 case RTE_2TUPLE_FLAGS:
4639 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4640 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4642 memset(&filter_2tuple,
4644 sizeof(struct e1000_2tuple_filter_info));
4645 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4648 p_2tuple_filter = igb_2tuple_filter_lookup(
4649 &filter_info->twotuple_list,
4651 if (p_2tuple_filter == NULL) {
4652 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4655 ntuple_filter->queue = p_2tuple_filter->queue;
4666 * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4667 * @dev: pointer to rte_eth_dev structure
4668 * @filter_op:operation will be taken.
4669 * @arg: a pointer to specific structure corresponding to the filter_op
4672 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4673 enum rte_filter_op filter_op,
4676 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4679 MAC_TYPE_FILTER_SUP(hw->mac.type);
4681 if (filter_op == RTE_ETH_FILTER_NOP)
4685 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4690 switch (filter_op) {
4691 case RTE_ETH_FILTER_ADD:
4692 ret = igb_add_del_ntuple_filter(dev,
4693 (struct rte_eth_ntuple_filter *)arg,
4696 case RTE_ETH_FILTER_DELETE:
4697 ret = igb_add_del_ntuple_filter(dev,
4698 (struct rte_eth_ntuple_filter *)arg,
4701 case RTE_ETH_FILTER_GET:
4702 ret = igb_get_ntuple_filter(dev,
4703 (struct rte_eth_ntuple_filter *)arg);
4706 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4714 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4719 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4720 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4721 (filter_info->ethertype_mask & (1 << i)))
4728 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4729 uint16_t ethertype, uint32_t etqf)
4733 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4734 if (!(filter_info->ethertype_mask & (1 << i))) {
4735 filter_info->ethertype_mask |= 1 << i;
4736 filter_info->ethertype_filters[i].ethertype = ethertype;
4737 filter_info->ethertype_filters[i].etqf = etqf;
4745 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4748 if (idx >= E1000_MAX_ETQF_FILTERS)
4750 filter_info->ethertype_mask &= ~(1 << idx);
4751 filter_info->ethertype_filters[idx].ethertype = 0;
4752 filter_info->ethertype_filters[idx].etqf = 0;
4758 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4759 struct rte_eth_ethertype_filter *filter,
4762 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4763 struct e1000_filter_info *filter_info =
4764 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4768 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
4769 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
4770 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4771 " ethertype filter.", filter->ether_type);
4775 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4776 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4779 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4780 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4784 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4785 if (ret >= 0 && add) {
4786 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4787 filter->ether_type);
4790 if (ret < 0 && !add) {
4791 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4792 filter->ether_type);
4797 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4798 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4799 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4800 ret = igb_ethertype_filter_insert(filter_info,
4801 filter->ether_type, etqf);
4803 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4807 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4811 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4812 E1000_WRITE_FLUSH(hw);
4818 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4819 struct rte_eth_ethertype_filter *filter)
4821 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4822 struct e1000_filter_info *filter_info =
4823 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4827 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4829 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4830 filter->ether_type);
4834 etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4835 if (etqf & E1000_ETQF_FILTER_ENABLE) {
4836 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4838 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4839 E1000_ETQF_QUEUE_SHIFT;
4847 * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4848 * @dev: pointer to rte_eth_dev structure
4849 * @filter_op:operation will be taken.
4850 * @arg: a pointer to specific structure corresponding to the filter_op
4853 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4854 enum rte_filter_op filter_op,
4857 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4860 MAC_TYPE_FILTER_SUP(hw->mac.type);
4862 if (filter_op == RTE_ETH_FILTER_NOP)
4866 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4871 switch (filter_op) {
4872 case RTE_ETH_FILTER_ADD:
4873 ret = igb_add_del_ethertype_filter(dev,
4874 (struct rte_eth_ethertype_filter *)arg,
4877 case RTE_ETH_FILTER_DELETE:
4878 ret = igb_add_del_ethertype_filter(dev,
4879 (struct rte_eth_ethertype_filter *)arg,
4882 case RTE_ETH_FILTER_GET:
4883 ret = igb_get_ethertype_filter(dev,
4884 (struct rte_eth_ethertype_filter *)arg);
4887 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4895 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4896 enum rte_filter_type filter_type,
4897 enum rte_filter_op filter_op,
4902 switch (filter_type) {
4903 case RTE_ETH_FILTER_NTUPLE:
4904 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4906 case RTE_ETH_FILTER_ETHERTYPE:
4907 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4909 case RTE_ETH_FILTER_SYN:
4910 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4912 case RTE_ETH_FILTER_FLEXIBLE:
4913 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4915 case RTE_ETH_FILTER_GENERIC:
4916 if (filter_op != RTE_ETH_FILTER_GET)
4918 *(const void **)arg = &igb_flow_ops;
4921 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4930 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4931 struct rte_ether_addr *mc_addr_set,
4932 uint32_t nb_mc_addr)
4934 struct e1000_hw *hw;
4936 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4937 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4942 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4944 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4945 uint64_t systime_cycles;
4947 switch (hw->mac.type) {
4951 * Need to read System Time Residue Register to be able
4952 * to read the other two registers.
4954 E1000_READ_REG(hw, E1000_SYSTIMR);
4955 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4956 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4957 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4964 * Need to read System Time Residue Register to be able
4965 * to read the other two registers.
4967 E1000_READ_REG(hw, E1000_SYSTIMR);
4968 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4969 /* Only the 8 LSB are valid. */
4970 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4974 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4975 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4980 return systime_cycles;
4984 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4986 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4987 uint64_t rx_tstamp_cycles;
4989 switch (hw->mac.type) {
4992 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4993 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4994 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
5000 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
5001 /* Only the 8 LSB are valid. */
5002 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
5006 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
5007 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
5012 return rx_tstamp_cycles;
5016 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5018 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5019 uint64_t tx_tstamp_cycles;
5021 switch (hw->mac.type) {
5024 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5025 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5026 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5032 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5033 /* Only the 8 LSB are valid. */
5034 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
5038 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5039 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5044 return tx_tstamp_cycles;
5048 igb_start_timecounters(struct rte_eth_dev *dev)
5050 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5051 struct e1000_adapter *adapter = dev->data->dev_private;
5052 uint32_t incval = 1;
5054 uint64_t mask = E1000_CYCLECOUNTER_MASK;
5056 switch (hw->mac.type) {
5060 /* 32 LSB bits + 8 MSB bits = 40 bits */
5061 mask = (1ULL << 40) - 1;
5066 * Start incrementing the register
5067 * used to timestamp PTP packets.
5069 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
5072 incval = E1000_INCVALUE_82576;
5073 shift = IGB_82576_TSYNC_SHIFT;
5074 E1000_WRITE_REG(hw, E1000_TIMINCA,
5075 E1000_INCPERIOD_82576 | incval);
5082 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5083 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5084 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5086 adapter->systime_tc.cc_mask = mask;
5087 adapter->systime_tc.cc_shift = shift;
5088 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5090 adapter->rx_tstamp_tc.cc_mask = mask;
5091 adapter->rx_tstamp_tc.cc_shift = shift;
5092 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5094 adapter->tx_tstamp_tc.cc_mask = mask;
5095 adapter->tx_tstamp_tc.cc_shift = shift;
5096 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5100 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5102 struct e1000_adapter *adapter = dev->data->dev_private;
5104 adapter->systime_tc.nsec += delta;
5105 adapter->rx_tstamp_tc.nsec += delta;
5106 adapter->tx_tstamp_tc.nsec += delta;
5112 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5115 struct e1000_adapter *adapter = dev->data->dev_private;
5117 ns = rte_timespec_to_ns(ts);
5119 /* Set the timecounters to a new value. */
5120 adapter->systime_tc.nsec = ns;
5121 adapter->rx_tstamp_tc.nsec = ns;
5122 adapter->tx_tstamp_tc.nsec = ns;
5128 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5130 uint64_t ns, systime_cycles;
5131 struct e1000_adapter *adapter = dev->data->dev_private;
5133 systime_cycles = igb_read_systime_cyclecounter(dev);
5134 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5135 *ts = rte_ns_to_timespec(ns);
5141 igb_timesync_enable(struct rte_eth_dev *dev)
5143 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5147 /* Stop the timesync system time. */
5148 E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5149 /* Reset the timesync system time value. */
5150 switch (hw->mac.type) {
5156 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5159 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5160 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5163 /* Not supported. */
5167 /* Enable system time for it isn't on by default. */
5168 tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5169 tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5170 E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5172 igb_start_timecounters(dev);
5174 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5175 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5176 (RTE_ETHER_TYPE_1588 |
5177 E1000_ETQF_FILTER_ENABLE |
5180 /* Enable timestamping of received PTP packets. */
5181 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5182 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5183 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5185 /* Enable Timestamping of transmitted PTP packets. */
5186 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5187 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5188 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5194 igb_timesync_disable(struct rte_eth_dev *dev)
5196 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5199 /* Disable timestamping of transmitted PTP packets. */
5200 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5201 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5202 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5204 /* Disable timestamping of received PTP packets. */
5205 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5206 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5207 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5209 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5210 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5212 /* Stop incrementating the System Time registers. */
5213 E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5219 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5220 struct timespec *timestamp,
5221 uint32_t flags __rte_unused)
5223 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5224 struct e1000_adapter *adapter = dev->data->dev_private;
5225 uint32_t tsync_rxctl;
5226 uint64_t rx_tstamp_cycles;
5229 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5230 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5233 rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5234 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5235 *timestamp = rte_ns_to_timespec(ns);
5241 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5242 struct timespec *timestamp)
5244 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5245 struct e1000_adapter *adapter = dev->data->dev_private;
5246 uint32_t tsync_txctl;
5247 uint64_t tx_tstamp_cycles;
5250 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5251 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5254 tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5255 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5256 *timestamp = rte_ns_to_timespec(ns);
5262 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5266 const struct reg_info *reg_group;
5268 while ((reg_group = igb_regs[g_ind++]))
5269 count += igb_reg_group_count(reg_group);
5275 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5279 const struct reg_info *reg_group;
5281 while ((reg_group = igbvf_regs[g_ind++]))
5282 count += igb_reg_group_count(reg_group);
5288 eth_igb_get_regs(struct rte_eth_dev *dev,
5289 struct rte_dev_reg_info *regs)
5291 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5292 uint32_t *data = regs->data;
5295 const struct reg_info *reg_group;
5298 regs->length = eth_igb_get_reg_length(dev);
5299 regs->width = sizeof(uint32_t);
5303 /* Support only full register dump */
5304 if ((regs->length == 0) ||
5305 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5306 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5308 while ((reg_group = igb_regs[g_ind++]))
5309 count += igb_read_regs_group(dev, &data[count],
5318 igbvf_get_regs(struct rte_eth_dev *dev,
5319 struct rte_dev_reg_info *regs)
5321 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5322 uint32_t *data = regs->data;
5325 const struct reg_info *reg_group;
5328 regs->length = igbvf_get_reg_length(dev);
5329 regs->width = sizeof(uint32_t);
5333 /* Support only full register dump */
5334 if ((regs->length == 0) ||
5335 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5336 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5338 while ((reg_group = igbvf_regs[g_ind++]))
5339 count += igb_read_regs_group(dev, &data[count],
5348 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5350 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5352 /* Return unit is byte count */
5353 return hw->nvm.word_size * 2;
5357 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5358 struct rte_dev_eeprom_info *in_eeprom)
5360 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5361 struct e1000_nvm_info *nvm = &hw->nvm;
5362 uint16_t *data = in_eeprom->data;
5365 first = in_eeprom->offset >> 1;
5366 length = in_eeprom->length >> 1;
5367 if ((first >= hw->nvm.word_size) ||
5368 ((first + length) >= hw->nvm.word_size))
5371 in_eeprom->magic = hw->vendor_id |
5372 ((uint32_t)hw->device_id << 16);
5374 if ((nvm->ops.read) == NULL)
5377 return nvm->ops.read(hw, first, length, data);
5381 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5382 struct rte_dev_eeprom_info *in_eeprom)
5384 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5385 struct e1000_nvm_info *nvm = &hw->nvm;
5386 uint16_t *data = in_eeprom->data;
5389 first = in_eeprom->offset >> 1;
5390 length = in_eeprom->length >> 1;
5391 if ((first >= hw->nvm.word_size) ||
5392 ((first + length) >= hw->nvm.word_size))
5395 in_eeprom->magic = (uint32_t)hw->vendor_id |
5396 ((uint32_t)hw->device_id << 16);
5398 if ((nvm->ops.write) == NULL)
5400 return nvm->ops.write(hw, first, length, data);
5404 eth_igb_get_module_info(struct rte_eth_dev *dev,
5405 struct rte_eth_dev_module_info *modinfo)
5407 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5409 uint32_t status = 0;
5410 uint16_t sff8472_rev, addr_mode;
5411 bool page_swap = false;
5413 if (hw->phy.media_type == e1000_media_type_copper ||
5414 hw->phy.media_type == e1000_media_type_unknown)
5417 /* Check whether we support SFF-8472 or not */
5418 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
5422 /* addressing mode is not supported */
5423 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
5427 /* addressing mode is not supported */
5428 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
5430 "Address change required to access page 0xA2, "
5431 "but not supported. Please report the module "
5432 "type to the driver maintainers.\n");
5436 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
5437 /* We have an SFP, but it does not support SFF-8472 */
5438 modinfo->type = RTE_ETH_MODULE_SFF_8079;
5439 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
5441 /* We have an SFP which supports a revision of SFF-8472 */
5442 modinfo->type = RTE_ETH_MODULE_SFF_8472;
5443 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
5450 eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
5451 struct rte_dev_eeprom_info *info)
5453 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5455 uint32_t status = 0;
5456 uint16_t dataword[RTE_ETH_MODULE_SFF_8472_LEN / 2 + 1];
5457 u16 first_word, last_word;
5460 if (info->length == 0)
5463 first_word = info->offset >> 1;
5464 last_word = (info->offset + info->length - 1) >> 1;
5466 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
5467 for (i = 0; i < last_word - first_word + 1; i++) {
5468 status = e1000_read_phy_reg_i2c(hw, (first_word + i) * 2,
5471 /* Error occurred while reading module */
5475 dataword[i] = rte_be_to_cpu_16(dataword[i]);
5478 memcpy(info->data, (u8 *)dataword + (info->offset & 1), info->length);
5484 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5486 struct e1000_hw *hw =
5487 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5488 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5489 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5490 uint32_t vec = E1000_MISC_VEC_ID;
5492 if (rte_intr_allow_others(intr_handle))
5493 vec = E1000_RX_VEC_START;
5495 uint32_t mask = 1 << (queue_id + vec);
5497 E1000_WRITE_REG(hw, E1000_EIMC, mask);
5498 E1000_WRITE_FLUSH(hw);
5504 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5506 struct e1000_hw *hw =
5507 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5508 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5509 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5510 uint32_t vec = E1000_MISC_VEC_ID;
5512 if (rte_intr_allow_others(intr_handle))
5513 vec = E1000_RX_VEC_START;
5515 uint32_t mask = 1 << (queue_id + vec);
5518 regval = E1000_READ_REG(hw, E1000_EIMS);
5519 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5520 E1000_WRITE_FLUSH(hw);
5522 rte_intr_ack(intr_handle);
5528 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
5529 uint8_t index, uint8_t offset)
5531 uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5534 val &= ~((uint32_t)0xFF << offset);
5536 /* write vector and valid bit */
5537 val |= (msix_vector | E1000_IVAR_VALID) << offset;
5539 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5543 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5544 uint8_t queue, uint8_t msix_vector)
5548 if (hw->mac.type == e1000_82575) {
5550 tmp = E1000_EICR_RX_QUEUE0 << queue;
5551 else if (direction == 1)
5552 tmp = E1000_EICR_TX_QUEUE0 << queue;
5553 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5554 } else if (hw->mac.type == e1000_82576) {
5555 if ((direction == 0) || (direction == 1))
5556 eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5557 ((queue & 0x8) << 1) +
5559 } else if ((hw->mac.type == e1000_82580) ||
5560 (hw->mac.type == e1000_i350) ||
5561 (hw->mac.type == e1000_i354) ||
5562 (hw->mac.type == e1000_i210) ||
5563 (hw->mac.type == e1000_i211)) {
5564 if ((direction == 0) || (direction == 1))
5565 eth_igb_write_ivar(hw, msix_vector,
5567 ((queue & 0x1) << 4) +
5572 /* Sets up the hardware to generate MSI-X interrupts properly
5574 * board private structure
5577 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5580 uint32_t tmpval, regval, intr_mask;
5581 struct e1000_hw *hw =
5582 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5583 uint32_t vec = E1000_MISC_VEC_ID;
5584 uint32_t base = E1000_MISC_VEC_ID;
5585 uint32_t misc_shift = 0;
5586 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5587 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5589 /* won't configure msix register if no mapping is done
5590 * between intr vector and event fd
5592 if (!rte_intr_dp_is_en(intr_handle))
5595 if (rte_intr_allow_others(intr_handle)) {
5596 vec = base = E1000_RX_VEC_START;
5600 /* set interrupt vector for other causes */
5601 if (hw->mac.type == e1000_82575) {
5602 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5603 /* enable MSI-X PBA support */
5604 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5606 /* Auto-Mask interrupts upon ICR read */
5607 tmpval |= E1000_CTRL_EXT_EIAME;
5608 tmpval |= E1000_CTRL_EXT_IRCA;
5610 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5612 /* enable msix_other interrupt */
5613 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5614 regval = E1000_READ_REG(hw, E1000_EIAC);
5615 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5616 regval = E1000_READ_REG(hw, E1000_EIAM);
5617 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5618 } else if ((hw->mac.type == e1000_82576) ||
5619 (hw->mac.type == e1000_82580) ||
5620 (hw->mac.type == e1000_i350) ||
5621 (hw->mac.type == e1000_i354) ||
5622 (hw->mac.type == e1000_i210) ||
5623 (hw->mac.type == e1000_i211)) {
5624 /* turn on MSI-X capability first */
5625 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5626 E1000_GPIE_PBA | E1000_GPIE_EIAME |
5628 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5631 if (dev->data->dev_conf.intr_conf.lsc != 0)
5632 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5634 regval = E1000_READ_REG(hw, E1000_EIAC);
5635 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5637 /* enable msix_other interrupt */
5638 regval = E1000_READ_REG(hw, E1000_EIMS);
5639 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5640 tmpval = (IGB_MSIX_OTHER_INTR_VEC | E1000_IVAR_VALID) << 8;
5641 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5644 /* use EIAM to auto-mask when MSI-X interrupt
5645 * is asserted, this saves a register write for every interrupt
5647 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5650 if (dev->data->dev_conf.intr_conf.lsc != 0)
5651 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5653 regval = E1000_READ_REG(hw, E1000_EIAM);
5654 E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5656 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5657 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5658 intr_handle->intr_vec[queue_id] = vec;
5659 if (vec < base + intr_handle->nb_efd - 1)
5663 E1000_WRITE_FLUSH(hw);
5666 /* restore n-tuple filter */
5668 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5670 struct e1000_filter_info *filter_info =
5671 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5672 struct e1000_5tuple_filter *p_5tuple;
5673 struct e1000_2tuple_filter *p_2tuple;
5675 TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5676 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5679 TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5680 igb_inject_2uple_filter(dev, p_2tuple);
5684 /* restore SYN filter */
5686 igb_syn_filter_restore(struct rte_eth_dev *dev)
5688 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5689 struct e1000_filter_info *filter_info =
5690 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5693 synqf = filter_info->syn_info;
5695 if (synqf & E1000_SYN_FILTER_ENABLE) {
5696 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5697 E1000_WRITE_FLUSH(hw);
5701 /* restore ethernet type filter */
5703 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5705 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5706 struct e1000_filter_info *filter_info =
5707 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5710 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5711 if (filter_info->ethertype_mask & (1 << i)) {
5712 E1000_WRITE_REG(hw, E1000_ETQF(i),
5713 filter_info->ethertype_filters[i].etqf);
5714 E1000_WRITE_FLUSH(hw);
5719 /* restore flex byte filter */
5721 igb_flex_filter_restore(struct rte_eth_dev *dev)
5723 struct e1000_filter_info *filter_info =
5724 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5725 struct e1000_flex_filter *flex_filter;
5727 TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5728 igb_inject_flex_filter(dev, flex_filter);
5732 /* restore rss filter */
5734 igb_rss_filter_restore(struct rte_eth_dev *dev)
5736 struct e1000_filter_info *filter_info =
5737 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5739 if (filter_info->rss_info.conf.queue_num)
5740 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5743 /* restore all types filter */
5745 igb_filter_restore(struct rte_eth_dev *dev)
5747 igb_ntuple_filter_restore(dev);
5748 igb_ethertype_filter_restore(dev);
5749 igb_syn_filter_restore(dev);
5750 igb_flex_filter_restore(dev);
5751 igb_rss_filter_restore(dev);
5756 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5757 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5758 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5759 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5760 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5761 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");
5763 /* see e1000_logs.c */
5764 RTE_INIT(e1000_init_log)
5766 e1000_igb_init_log();